drivers/scsi/aic7xxx/aic79xx_pci.c

   1 /*
   2  * Product specific probe and attach routines for:
   3  *      aic7901 and aic7902 SCSI controllers
   4  *
   5  * Copyright (c) 1994-2001 Justin T. Gibbs.
   6  * Copyright (c) 2000-2002 Adaptec Inc.
   7  * All rights reserved.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions, and the following disclaimer,
  14  *    without modification.
  15  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  16  *    substantially similar to the "NO WARRANTY" disclaimer below
  17  *    ("Disclaimer") and any redistribution must be conditioned upon
  18  *    including a substantially similar Disclaimer requirement for further
  19  *    binary redistribution.
  20  * 3. Neither the names of the above-listed copyright holders nor the names
  21  *    of any contributors may be used to endorse or promote products derived
  22  *    from this software without specific prior written permission.
  23  *
  24  * Alternatively, this software may be distributed under the terms of the
  25  * GNU General Public License ("GPL") version 2 as published by the Free
  26  * Software Foundation.
  27  *
  28  * NO WARRANTY
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  34  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  35  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  36  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  37  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  38  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  39  * POSSIBILITY OF SUCH DAMAGES.
  40  *
  41  * $Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#77 $
  42  *
  43  * $FreeBSD$
  44  */
  45
  46 #ifdef __linux__
  47 #include "aic79xx_osm.h"
  48 #include "aic79xx_inline.h"
  49 #else
  50 #include <dev/aic7xxx/aic79xx_osm.h>
  51 #include <dev/aic7xxx/aic79xx_inline.h>
  52 #endif
  53
  54 static __inline uint64_t
  55 ahd_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor)
  56 {
  57         uint64_t id;
  58
  59         id = subvendor
  60            | (subdevice << 16)
  61            | ((uint64_t)vendor << 32)
  62            | ((uint64_t)device << 48);
  63
  64         return (id);
  65 }
  66
  67 #define ID_ALL_MASK                     0xFFFFFFFFFFFFFFFFull
  68 #define ID_ALL_IROC_MASK                0xFFFFFF7FFFFFFFFFull
  69 #define ID_DEV_VENDOR_MASK              0xFFFFFFFF00000000ull
  70 #define ID_9005_GENERIC_MASK            0xFFF0FFFF00000000ull
  71 #define ID_9005_GENERIC_IROC_MASK       0xFFF0FF7F00000000ull
  72
  73 #define ID_AIC7901                      0x800F9005FFFF9005ull
  74 #define ID_AHA_29320A                   0x8000900500609005ull
  75 #define ID_AHA_29320ALP                 0x8017900500449005ull
  76
  77 #define ID_AIC7901A                     0x801E9005FFFF9005ull
  78 #define ID_AHA_29320                    0x8012900500429005ull
  79 #define ID_AHA_29320B                   0x8013900500439005ull
  80 #define ID_AHA_29320LP                  0x8014900500449005ull
  81
  82 #define ID_AIC7902                      0x801F9005FFFF9005ull
  83 #define ID_AIC7902_B                    0x801D9005FFFF9005ull
  84 #define ID_AHA_39320                    0x8010900500409005ull
  85 #define ID_AHA_39320_B                  0x8015900500409005ull
  86 #define ID_AHA_39320A                   0x8016900500409005ull
  87 #define ID_AHA_39320D                   0x8011900500419005ull
  88 #define ID_AHA_39320D_B                 0x801C900500419005ull
  89 #define ID_AHA_39320D_HP                0x8011900500AC0E11ull
  90 #define ID_AHA_39320D_B_HP              0x801C900500AC0E11ull
  91 #define ID_AIC7902_PCI_REV_A4           0x3
  92 #define ID_AIC7902_PCI_REV_B0           0x10
  93 #define SUBID_HP                        0x0E11
  94
  95 #define DEVID_9005_TYPE(id) ((id) & 0xF)
  96 #define         DEVID_9005_TYPE_HBA             0x0     /* Standard Card */
  97 #define         DEVID_9005_TYPE_HBA_2EXT        0x1     /* 2 External Ports */
  98 #define         DEVID_9005_TYPE_IROC            0x8     /* Raid(0,1,10) Card */
  99 #define         DEVID_9005_TYPE_MB              0xF     /* On Motherboard */
 100
 101 #define DEVID_9005_MFUNC(id) ((id) & 0x10)
 102
 103 #define DEVID_9005_PACKETIZED(id) ((id) & 0x8000)
 104
 105 #define SUBID_9005_TYPE(id) ((id) & 0xF)
 106 #define         SUBID_9005_TYPE_HBA             0x0     /* Standard Card */
 107 #define         SUBID_9005_TYPE_MB              0xF     /* On Motherboard */
 108
 109 #define SUBID_9005_AUTOTERM(id) (((id) & 0x10) == 0)
 110
 111 #define SUBID_9005_LEGACYCONN_FUNC(id) ((id) & 0x20)
 112
 113 #define SUBID_9005_SEEPTYPE(id) ((id) & 0x0C0) >> 6)
 114 #define         SUBID_9005_SEEPTYPE_NONE        0x0
 115 #define         SUBID_9005_SEEPTYPE_4K          0x1
 116
 117 static ahd_device_setup_t ahd_aic7901_setup;
 118 static ahd_device_setup_t ahd_aic7901A_setup;
 119 static ahd_device_setup_t ahd_aic7902_setup;
 120 static ahd_device_setup_t ahd_aic790X_setup;
 121
 122 struct ahd_pci_identity ahd_pci_ident_table [] =
 123 {
 124         /* aic7901 based controllers */
 125         {
 126                 ID_AHA_29320A,
 127                 ID_ALL_MASK,
 128                 "Adaptec 29320A Ultra320 SCSI adapter",
 129                 ahd_aic7901_setup
 130         },
 131         {
 132                 ID_AHA_29320ALP,
 133                 ID_ALL_MASK,
 134                 "Adaptec 29320ALP Ultra320 SCSI adapter",
 135                 ahd_aic7901_setup
 136         },
 137         /* aic7901A based controllers */
 138         {
 139                 ID_AHA_29320,
 140                 ID_ALL_MASK,
 141                 "Adaptec 29320 Ultra320 SCSI adapter",
 142                 ahd_aic7901A_setup
 143         },
 144         {
 145                 ID_AHA_29320B,
 146                 ID_ALL_MASK,
 147                 "Adaptec 29320B Ultra320 SCSI adapter",
 148                 ahd_aic7901A_setup
 149         },
 150         {
 151                 ID_AHA_29320LP,
 152                 ID_ALL_MASK,
 153                 "Adaptec 29320LP Ultra320 SCSI adapter",
 154                 ahd_aic7901A_setup
 155         },
 156         /* aic7902 based controllers */
 157         {
 158                 ID_AHA_39320,
 159                 ID_ALL_MASK,
 160                 "Adaptec 39320 Ultra320 SCSI adapter",
 161                 ahd_aic7902_setup
 162         },
 163         {
 164                 ID_AHA_39320_B,
 165                 ID_ALL_MASK,
 166                 "Adaptec 39320 Ultra320 SCSI adapter",
 167                 ahd_aic7902_setup
 168         },
 169         {
 170                 ID_AHA_39320A,
 171                 ID_ALL_MASK,
 172                 "Adaptec 39320A Ultra320 SCSI adapter",
 173                 ahd_aic7902_setup
 174         },
 175         {
 176                 ID_AHA_39320D,
 177                 ID_ALL_MASK,
 178                 "Adaptec 39320D Ultra320 SCSI adapter",
 179                 ahd_aic7902_setup
 180         },
 181         {
 182                 ID_AHA_39320D_HP,
 183                 ID_ALL_MASK,
 184                 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter",
 185                 ahd_aic7902_setup
 186         },
 187         {
 188                 ID_AHA_39320D_B,
 189                 ID_ALL_MASK,
 190                 "Adaptec 39320D Ultra320 SCSI adapter",
 191                 ahd_aic7902_setup
 192         },
 193         {
 194                 ID_AHA_39320D_B_HP,
 195                 ID_ALL_MASK,
 196                 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter",
 197                 ahd_aic7902_setup
 198         },
 199         {
 200                 ID_AHA_29320,
 201                 ID_ALL_MASK,
 202                 "Adaptec 29320 Ultra320 SCSI adapter",
 203                 ahd_aic7902_setup
 204         },
 205         {
 206                 ID_AHA_29320B,
 207                 ID_ALL_MASK,
 208                 "Adaptec 29320B Ultra320 SCSI adapter",
 209                 ahd_aic7902_setup
 210         },
 211         /* Generic chip probes for devices we don't know 'exactly' */
 212         {
 213                 ID_AIC7901 & ID_DEV_VENDOR_MASK,
 214                 ID_DEV_VENDOR_MASK,
 215                 "Adaptec AIC7901 Ultra320 SCSI adapter",
 216                 ahd_aic7901_setup
 217         },
 218         {
 219                 ID_AIC7901A & ID_DEV_VENDOR_MASK,
 220                 ID_DEV_VENDOR_MASK,
 221                 "Adaptec AIC7901A Ultra320 SCSI adapter",
 222                 ahd_aic7901A_setup
 223         },
 224         {
 225                 ID_AIC7902 & ID_9005_GENERIC_MASK,
 226                 ID_9005_GENERIC_MASK,
 227                 "Adaptec AIC7902 Ultra320 SCSI adapter",
 228                 ahd_aic7902_setup
 229         }
 230 };
 231
 232 const u_int ahd_num_pci_devs = NUM_ELEMENTS(ahd_pci_ident_table);
 233
 234 #define DEVCONFIG               0x40
 235 #define         PCIXINITPAT     0x0000E000ul
 236 #define                 PCIXINIT_PCI33_66       0x0000E000ul
 237 #define                 PCIXINIT_PCIX50_66      0x0000C000ul
 238 #define                 PCIXINIT_PCIX66_100     0x0000A000ul
 239 #define                 PCIXINIT_PCIX100_133    0x00008000ul
 240 #define PCI_BUS_MODES_INDEX(devconfig)  \
 241         (((devconfig) & PCIXINITPAT) >> 13)
 242 static const char *pci_bus_modes[] =
 243 {
 244         "PCI bus mode unknown",
 245         "PCI bus mode unknown",
 246         "PCI bus mode unknown",
 247         "PCI bus mode unknown",
 248         "PCI-X 101-133Mhz",
 249         "PCI-X 67-100Mhz",
 250         "PCI-X 50-66Mhz",
 251         "PCI 33 or 66Mhz"
 252 };
 253
 254 #define         TESTMODE        0x00000800ul
 255 #define         IRDY_RST        0x00000200ul
 256 #define         FRAME_RST       0x00000100ul
 257 #define         PCI64BIT        0x00000080ul
 258 #define         MRDCEN          0x00000040ul
 259 #define         ENDIANSEL       0x00000020ul
 260 #define         MIXQWENDIANEN   0x00000008ul
 261 #define         DACEN           0x00000004ul
 262 #define         STPWLEVEL       0x00000002ul
 263 #define         QWENDIANSEL     0x00000001ul
 264
 265 #define DEVCONFIG1              0x44
 266 #define         PREQDIS         0x01
 267
 268 #define CSIZE_LATTIME           0x0c
 269 #define         CACHESIZE       0x000000fful
 270 #define         LATTIME         0x0000ff00ul
 271
 272 static int      ahd_check_extport(struct ahd_softc *ahd);
 273 static void     ahd_configure_termination(struct ahd_softc *ahd,
 274                                           u_int adapter_control);
 275 static void     ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat);
 276
 277 struct ahd_pci_identity *
 278 ahd_find_pci_device(ahd_dev_softc_t pci)
 279 {
 280         uint64_t  full_id;
 281         uint16_t  device;
 282         uint16_t  vendor;
 283         uint16_t  subdevice;
 284         uint16_t  subvendor;
 285         struct    ahd_pci_identity *entry;
 286         u_int     i;
 287
 288         vendor = ahd_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2);
 289         device = ahd_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2);
 290         subvendor = ahd_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2);
 291         subdevice = ahd_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2);
 292         full_id = ahd_compose_id(device,
 293                                  vendor,
 294                                  subdevice,
 295                                  subvendor);
 296
 297         for (i = 0; i < ahd_num_pci_devs; i++) {
 298                 entry = &ahd_pci_ident_table[i];
 299                 if (entry->full_id == (full_id & entry->id_mask)) {
 300                         /* Honor exclusion entries. */
 301                         if (entry->name == NULL)
 302                                 return (NULL);
 303                         return (entry);
 304                 }
 305         }
 306         return (NULL);
 307 }
 308
 309 int
 310 ahd_pci_config(struct ahd_softc *ahd, struct ahd_pci_identity *entry)
 311 {
 312         struct scb_data *shared_scb_data;
 313         u_long           l;
 314         u_int            command;
 315         uint32_t         devconfig;
 316         uint16_t         subvendor;
 317         int              error;
 318
 319         shared_scb_data = NULL;
 320         ahd->description = entry->name;
 321         /*
 322          * Record if this is an HP board.
 323          */
 324         subvendor = ahd_pci_read_config(ahd->dev_softc,
 325                                         PCIR_SUBVEND_0, /*bytes*/2);
 326         if (subvendor == SUBID_HP)
 327                 ahd->flags |= AHD_HP_BOARD;
 328
 329         error = entry->setup(ahd);
 330         if (error != 0)
 331                 return (error);
 332
 333         devconfig = ahd_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4);
 334         if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) {
 335                 ahd->chip |= AHD_PCI;
 336                 /* Disable PCIX workarounds when running in PCI mode. */
 337                 ahd->bugs &= ~AHD_PCIX_BUG_MASK;
 338         } else {
 339                 ahd->chip |= AHD_PCIX;
 340         }
 341         ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)];
 342
 343         ahd_power_state_change(ahd, AHD_POWER_STATE_D0);
 344
 345         error = ahd_pci_map_registers(ahd);
 346         if (error != 0)
 347                 return (error);
 348
 349         /*
 350          * If we need to support high memory, enable dual
 351          * address cycles.  This bit must be set to enable
 352          * high address bit generation even if we are on a
 353          * 64bit bus (PCI64BIT set in devconfig).
 354          */
 355         if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) {
 356                 uint32_t devconfig;
 357
 358                 if (bootverbose)
 359                         printf("%s: Enabling 39Bit Addressing\n",
 360                                ahd_name(ahd));
 361                 devconfig = ahd_pci_read_config(ahd->dev_softc,
 362                                                 DEVCONFIG, /*bytes*/4);
 363                 devconfig |= DACEN;
 364                 ahd_pci_write_config(ahd->dev_softc, DEVCONFIG,
 365                                      devconfig, /*bytes*/4);
 366         }
 367
 368         /* Ensure busmastering is enabled */
 369         command = ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2);
 370         command |= PCIM_CMD_BUSMASTEREN;
 371         ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, command, /*bytes*/2);
 372
 373         error = ahd_softc_init(ahd);
 374         if (error != 0)
 375                 return (error);
 376
 377         ahd->bus_intr = ahd_pci_intr;
 378
 379         error = ahd_reset(ahd, /*reinit*/FALSE);
 380         if (error != 0)
 381                 return (ENXIO);
 382
 383         ahd->pci_cachesize =
 384             ahd_pci_read_config(ahd->dev_softc, CSIZE_LATTIME,
 385                                 /*bytes*/1) & CACHESIZE;
 386         ahd->pci_cachesize *= 4;
 387
 388         ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
 389         /* See if we have a SEEPROM and perform auto-term */
 390         error = ahd_check_extport(ahd);
 391         if (error != 0)
 392                 return (error);
 393
 394         /* Core initialization */
 395         error = ahd_init(ahd);
 396         if (error != 0)
 397                 return (error);
 398
 399         /*
 400          * Allow interrupts now that we are completely setup.
 401          */
 402         error = ahd_pci_map_int(ahd);
 403         if (error != 0)
 404                 return (error);
 405
 406         ahd_list_lock(&l);
 407         /*
 408          * Link this softc in with all other ahd instances.
 409          */
 410         ahd_softc_insert(ahd);
 411         ahd_list_unlock(&l);
 412         return (0);
 413 }
 414
 415 /*
 416  * Perform some simple tests that should catch situations where
 417  * our registers are invalidly mapped.
 418  */
 419 int
 420 ahd_pci_test_register_access(struct ahd_softc *ahd)
 421 {
 422         uint32_t cmd;
 423         u_int    targpcistat;
 424         u_int    pci_status1;
 425         int      error;
 426         uint8_t  hcntrl;
 427
 428         error = EIO;
 429
 430         /*
 431          * Enable PCI error interrupt status, but suppress NMIs
 432          * generated by SERR raised due to target aborts.
 433          */
 434         cmd = ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2);
 435         ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND,
 436                              cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2);
 437
 438         /*
 439          * First a simple test to see if any
 440          * registers can be read.  Reading
 441          * HCNTRL has no side effects and has
 442          * at least one bit that is guaranteed to
 443          * be zero so it is a good register to
 444          * use for this test.
 445          */
 446         hcntrl = ahd_inb(ahd, HCNTRL);
 447         if (hcntrl == 0xFF)
 448                 goto fail;
 449
 450         /*
 451          * Next create a situation where write combining
 452          * or read prefetching could be initiated by the
 453          * CPU or host bridge.  Our device does not support
 454          * either, so look for data corruption and/or flaged
 455          * PCI errors.  First pause without causing another
 456          * chip reset.
 457          */
 458         hcntrl &= ~CHIPRST;
 459         ahd_outb(ahd, HCNTRL, hcntrl|PAUSE);
 460         while (ahd_is_paused(ahd) == 0)
 461                 ;
 462
 463         /* Clear any PCI errors that occurred before our driver attached. */
 464         ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
 465         targpcistat = ahd_inb(ahd, TARGPCISTAT);
 466         ahd_outb(ahd, TARGPCISTAT, targpcistat);
 467         pci_status1 = ahd_pci_read_config(ahd->dev_softc,
 468                                           PCIR_STATUS + 1, /*bytes*/1);
 469         ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
 470                              pci_status1, /*bytes*/1);
 471         ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
 472         ahd_outb(ahd, CLRINT, CLRPCIINT);
 473
 474         ahd_outb(ahd, SEQCTL0, PERRORDIS);
 475         ahd_outl(ahd, SRAM_BASE, 0x5aa555aa);
 476         if (ahd_inl(ahd, SRAM_BASE) != 0x5aa555aa)
 477                 goto fail;
 478
 479         if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) {
 480                 u_int targpcistat;
 481
 482                 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
 483                 targpcistat = ahd_inb(ahd, TARGPCISTAT);
 484                 if ((targpcistat & STA) != 0)
 485                         goto fail;
 486         }
 487
 488         error = 0;
 489
 490 fail:
 491         if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) {
 492
 493                 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
 494                 targpcistat = ahd_inb(ahd, TARGPCISTAT);
 495
 496                 /* Silently clear any latched errors. */
 497                 ahd_outb(ahd, TARGPCISTAT, targpcistat);
 498                 pci_status1 = ahd_pci_read_config(ahd->dev_softc,
 499                                                   PCIR_STATUS + 1, /*bytes*/1);
 500                 ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
 501                                      pci_status1, /*bytes*/1);
 502                 ahd_outb(ahd, CLRINT, CLRPCIINT);
 503         }
 504         ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS);
 505         ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2);
 506         return (error);
 507 }
 508
 509 /*
 510  * Check the external port logic for a serial eeprom
 511  * and termination/cable detection contrls.
 512  */
 513 static int
 514 ahd_check_extport(struct ahd_softc *ahd)
 515 {
 516         struct  vpd_config vpd;
 517         struct  seeprom_config *sc;
 518         u_int   adapter_control;
 519         int     have_seeprom;
 520         int     error;
 521
 522         sc = ahd->seep_config;
 523         have_seeprom = ahd_acquire_seeprom(ahd);
 524         if (have_seeprom) {
 525                 u_int start_addr;
 526
 527                 /*
 528                  * Fetch VPD for this function and parse it.
 529                  */
 530                 if (bootverbose)
 531                         printf("%s: Reading VPD from SEEPROM...",
 532                                ahd_name(ahd));
 533
 534                 /* Address is always in units of 16bit words */
 535                 start_addr = ((2 * sizeof(*sc))
 536                             + (sizeof(vpd) * (ahd->channel - 'A'))) / 2;
 537
 538                 error = ahd_read_seeprom(ahd, (uint16_t *)&vpd,
 539                                          start_addr, sizeof(vpd)/2,
 540                                          /*bytestream*/TRUE);
 541                 if (error == 0)
 542                         error = ahd_parse_vpddata(ahd, &vpd);
 543                 if (bootverbose)
 544                         printf("%s: VPD parsing %s\n",
 545                                ahd_name(ahd),
 546                                error == 0 ? "successful" : "failed");
 547
 548                 if (bootverbose)
 549                         printf("%s: Reading SEEPROM...", ahd_name(ahd));
 550
 551                 /* Address is always in units of 16bit words */
 552                 start_addr = (sizeof(*sc) / 2) * (ahd->channel - 'A');
 553
 554                 error = ahd_read_seeprom(ahd, (uint16_t *)sc,
 555                                          start_addr, sizeof(*sc)/2,
 556                                          /*bytestream*/FALSE);
 557
 558                 if (error != 0) {
 559                         printf("Unable to read SEEPROM\n");
 560                         have_seeprom = 0;
 561                 } else {
 562                         have_seeprom = ahd_verify_cksum(sc);
 563
 564                         if (bootverbose) {
 565                                 if (have_seeprom == 0)
 566                                         printf ("checksum error\n");
 567                                 else
 568                                         printf ("done.\n");
 569                         }
 570                 }
 571                 ahd_release_seeprom(ahd);
 572         }
 573
 574         if (!have_seeprom) {
 575                 u_int     nvram_scb;
 576
 577                 /*
 578                  * Pull scratch ram settings and treat them as
 579                  * if they are the contents of an seeprom if
 580                  * the 'ADPT', 'BIOS', or 'ASPI' signature is found
 581                  * in SCB 0xFF.  We manually compose the data as 16bit
 582                  * values to avoid endian issues.
 583                  */
 584                 ahd_set_scbptr(ahd, 0xFF);
 585                 nvram_scb = ahd_inb_scbram(ahd, SCB_BASE + NVRAM_SCB_OFFSET);
 586                 if (nvram_scb != 0xFF
 587                  && ((ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A'
 588                    && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'D'
 589                    && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P'
 590                    && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'T')
 591                   || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'B'
 592                    && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'I'
 593                    && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'O'
 594                    && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'S')
 595                   || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A'
 596                    && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'S'
 597                    && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P'
 598                    && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'I'))) {
 599                         uint16_t *sc_data;
 600                         int       i;
 601
 602                         ahd_set_scbptr(ahd, nvram_scb);
 603                         sc_data = (uint16_t *)sc;
 604                         for (i = 0; i < 64; i += 2)
 605                                 *sc_data++ = ahd_inw_scbram(ahd, SCB_BASE+i);
 606                         have_seeprom = ahd_verify_cksum(sc);
 607                         if (have_seeprom)
 608                                 ahd->flags |= AHD_SCB_CONFIG_USED;
 609                 }
 610         }
 611
 612 #if AHD_DEBUG
 613         if (have_seeprom != 0
 614          && (ahd_debug & AHD_DUMP_SEEPROM) != 0) {
 615                 uint16_t *sc_data;
 616                 int       i;
 617
 618                 printf("%s: Seeprom Contents:", ahd_name(ahd));
 619                 sc_data = (uint16_t *)sc;
 620                 for (i = 0; i < (sizeof(*sc)); i += 2)
 621                         printf("\n\t0x%.4x", sc_data[i]);
 622                 printf("\n");
 623         }
 624 #endif
 625
 626         if (!have_seeprom) {
 627                 if (bootverbose)
 628                         printf("%s: No SEEPROM available.\n", ahd_name(ahd));
 629                 ahd->flags |= AHD_USEDEFAULTS;
 630                 error = ahd_default_config(ahd);
 631                 adapter_control = CFAUTOTERM|CFSEAUTOTERM;
 632                 free(ahd->seep_config, M_DEVBUF);
 633                 ahd->seep_config = NULL;
 634         } else {
 635                 error = ahd_parse_cfgdata(ahd, sc);
 636                 adapter_control = sc->adapter_control;
 637         }
 638         if (error != 0)
 639                 return (error);
 640
 641         ahd_configure_termination(ahd, adapter_control);
 642
 643         return (0);
 644 }
 645
 646 static void
 647 ahd_configure_termination(struct ahd_softc *ahd, u_int adapter_control)
 648 {
 649         int      error;
 650         u_int    sxfrctl1;
 651         uint8_t  termctl;
 652         uint32_t devconfig;
 653
 654         devconfig = ahd_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4);
 655         devconfig &= ~STPWLEVEL;
 656         if ((ahd->flags & AHD_STPWLEVEL_A) != 0)
 657                 devconfig |= STPWLEVEL;
 658         if (bootverbose)
 659                 printf("%s: STPWLEVEL is %s\n",
 660                        ahd_name(ahd), (devconfig & STPWLEVEL) ? "on" : "off");
 661         ahd_pci_write_config(ahd->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
 662
 663         /* Make sure current sensing is off. */
 664         if ((ahd->flags & AHD_CURRENT_SENSING) != 0) {
 665                 (void)ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0);
 666         }
 667
 668         /*
 669          * Read to sense.  Write to set.
 670          */
 671         error = ahd_read_flexport(ahd, FLXADDR_TERMCTL, &termctl);
 672         if ((adapter_control & CFAUTOTERM) == 0) {
 673                 if (bootverbose)
 674                         printf("%s: Manual Primary Termination\n",
 675                                ahd_name(ahd));
 676                 termctl &= ~(FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH);
 677                 if ((adapter_control & CFSTERM) != 0)
 678                         termctl |= FLX_TERMCTL_ENPRILOW;
 679                 if ((adapter_control & CFWSTERM) != 0)
 680                         termctl |= FLX_TERMCTL_ENPRIHIGH;
 681         } else if (error != 0) {
 682                 printf("%s: Primary Auto-Term Sensing failed! "
 683                        "Using Defaults.\n", ahd_name(ahd));
 684                 termctl = FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH;
 685         }
 686
 687         if ((adapter_control & CFSEAUTOTERM) == 0) {
 688                 if (bootverbose)
 689                         printf("%s: Manual Secondary Termination\n",
 690                                ahd_name(ahd));
 691                 termctl &= ~(FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH);
 692                 if ((adapter_control & CFSELOWTERM) != 0)
 693                         termctl |= FLX_TERMCTL_ENSECLOW;
 694                 if ((adapter_control & CFSEHIGHTERM) != 0)
 695                         termctl |= FLX_TERMCTL_ENSECHIGH;
 696         } else if (error != 0) {
 697                 printf("%s: Secondary Auto-Term Sensing failed! "
 698                        "Using Defaults.\n", ahd_name(ahd));
 699                 termctl |= FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH;
 700         }
 701
 702         /*
 703          * Now set the termination based on what we found.
 704          */
 705         sxfrctl1 = ahd_inb(ahd, SXFRCTL1) & ~STPWEN;
 706         if ((termctl & FLX_TERMCTL_ENPRILOW) != 0) {
 707                 ahd->flags |= AHD_TERM_ENB_A;
 708                 sxfrctl1 |= STPWEN;
 709         }
 710         /* Must set the latch once in order to be effective. */
 711         ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN);
 712         ahd_outb(ahd, SXFRCTL1, sxfrctl1);
 713
 714         error = ahd_write_flexport(ahd, FLXADDR_TERMCTL, termctl);
 715         if (error != 0) {
 716                 printf("%s: Unable to set termination settings!\n",
 717                        ahd_name(ahd));
 718         } else if (bootverbose) {
 719                 printf("%s: Primary High byte termination %sabled\n",
 720                        ahd_name(ahd),
 721                        (termctl & FLX_TERMCTL_ENPRIHIGH) ? "En" : "Dis");
 722
 723                 printf("%s: Primary Low byte termination %sabled\n",
 724                        ahd_name(ahd),
 725                        (termctl & FLX_TERMCTL_ENPRILOW) ? "En" : "Dis");
 726
 727                 printf("%s: Secondary High byte termination %sabled\n",
 728                        ahd_name(ahd),
 729                        (termctl & FLX_TERMCTL_ENSECHIGH) ? "En" : "Dis");
 730
 731                 printf("%s: Secondary Low byte termination %sabled\n",
 732                        ahd_name(ahd),
 733                        (termctl & FLX_TERMCTL_ENSECLOW) ? "En" : "Dis");
 734         }
 735         return;
 736 }
 737
 738 #define DPE     0x80
 739 #define SSE     0x40
 740 #define RMA     0x20
 741 #define RTA     0x10
 742 #define STA     0x08
 743 #define DPR     0x01
 744
 745 static const char *split_status_source[] =
 746 {
 747         "DFF0",
 748         "DFF1",
 749         "OVLY",
 750         "CMC",
 751 };
 752
 753 static const char *pci_status_source[] =
 754 {
 755         "DFF0",
 756         "DFF1",
 757         "SG",
 758         "CMC",
 759         "OVLY",
 760         "NONE",
 761         "MSI",
 762         "TARG"
 763 };
 764
 765 static const char *split_status_strings[] =
 766 {
 767         "%s: Received split response in %s.\n",
 768         "%s: Received split completion error message in %s\n",
 769         "%s: Receive overrun in %s\n",
 770         "%s: Count not complete in %s\n",
 771         "%s: Split completion data bucket in %s\n",
 772         "%s: Split completion address error in %s\n",
 773         "%s: Split completion byte count error in %s\n",
 774         "%s: Signaled Target-abort to early terminate a split in %s\n"
 775 };
 776
 777 static const char *pci_status_strings[] =
 778 {
 779         "%s: Data Parity Error has been reported via PERR# in %s\n",
 780         "%s: Target initial wait state error in %s\n",
 781         "%s: Split completion read data parity error in %s\n",
 782         "%s: Split completion address attribute parity error in %s\n",
 783         "%s: Received a Target Abort in %s\n",
 784         "%s: Received a Master Abort in %s\n",
 785         "%s: Signal System Error Detected in %s\n",
 786         "%s: Address or Write Phase Parity Error Detected in %s.\n"
 787 };
 788
 789 void
 790 ahd_pci_intr(struct ahd_softc *ahd)
 791 {
 792         uint8_t         pci_status[8];
 793         ahd_mode_state  saved_modes;
 794         u_int           pci_status1;
 795         u_int           intstat;
 796         u_int           i;
 797         u_int           reg;
 798
 799         intstat = ahd_inb(ahd, INTSTAT);
 800
 801         if ((intstat & SPLTINT) != 0)
 802                 ahd_pci_split_intr(ahd, intstat);
 803
 804         if ((intstat & PCIINT) == 0)
 805                 return;
 806
 807         printf("%s: PCI error Interrupt\n", ahd_name(ahd));
 808         saved_modes = ahd_save_modes(ahd);
 809         ahd_dump_card_state(ahd);
 810         ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
 811         for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) {
 812
 813                 if (i == 5)
 814                         continue;
 815                 pci_status[i] = ahd_inb(ahd, reg);
 816                 /* Clear latched errors.  So our interrupt deasserts. */
 817                 ahd_outb(ahd, reg, pci_status[i]);
 818         }
 819
 820         for (i = 0; i < 8; i++) {
 821                 u_int bit;
 822
 823                 if (i == 5)
 824                         continue;
 825
 826                 for (bit = 0; bit < 8; bit++) {
 827
 828                         if ((pci_status[i] & (0x1 << bit)) != 0) {
 829                                 static const char *s;
 830
 831                                 s = pci_status_strings[bit];
 832                                 if (i == 7/*TARG*/ && bit == 3)
 833                                         s = "%s: Signaled Target Abort\n";
 834                                 printf(s, ahd_name(ahd), pci_status_source[i]);
 835                         }
 836                 }
 837         }
 838         pci_status1 = ahd_pci_read_config(ahd->dev_softc,
 839                                           PCIR_STATUS + 1, /*bytes*/1);
 840         ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
 841                              pci_status1, /*bytes*/1);
 842         ahd_restore_modes(ahd, saved_modes);
 843         ahd_outb(ahd, CLRINT, CLRPCIINT);
 844         ahd_unpause(ahd);
 845 }
 846
 847 static void
 848 ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat)
 849 {
 850         uint8_t         split_status[4];
 851         uint8_t         split_status1[4];
 852         uint8_t         sg_split_status[2];
 853         uint8_t         sg_split_status1[2];
 854         ahd_mode_state  saved_modes;
 855         u_int           i;
 856         uint16_t        pcix_status;
 857
 858         /*
 859          * Check for splits in all modes.  Modes 0 and 1
 860          * additionally have SG engine splits to look at.
 861          */
 862         pcix_status = ahd_pci_read_config(ahd->dev_softc, PCIXR_STATUS,
 863                                           /*bytes*/2);
 864         printf("%s: PCI Split Interrupt - PCI-X status = 0x%x\n",
 865                ahd_name(ahd), pcix_status);
 866         saved_modes = ahd_save_modes(ahd);
 867         for (i = 0; i < 4; i++) {
 868                 ahd_set_modes(ahd, i, i);
 869
 870                 split_status[i] = ahd_inb(ahd, DCHSPLTSTAT0);
 871                 split_status1[i] = ahd_inb(ahd, DCHSPLTSTAT1);
 872                 /* Clear latched errors.  So our interrupt deasserts. */
 873                 ahd_outb(ahd, DCHSPLTSTAT0, split_status[i]);
 874                 ahd_outb(ahd, DCHSPLTSTAT1, split_status1[i]);
 875                 if (i > 1)
 876                         continue;
 877                 sg_split_status[i] = ahd_inb(ahd, SGSPLTSTAT0);
 878                 sg_split_status1[i] = ahd_inb(ahd, SGSPLTSTAT1);
 879                 /* Clear latched errors.  So our interrupt deasserts. */
 880                 ahd_outb(ahd, SGSPLTSTAT0, sg_split_status[i]);
 881                 ahd_outb(ahd, SGSPLTSTAT1, sg_split_status1[i]);
 882         }
 883
 884         for (i = 0; i < 4; i++) {
 885                 u_int bit;
 886
 887                 for (bit = 0; bit < 8; bit++) {
 888
 889                         if ((split_status[i] & (0x1 << bit)) != 0) {
 890                                 static const char *s;
 891
 892                                 s = split_status_strings[bit];
 893                                 printf(s, ahd_name(ahd),
 894                                        split_status_source[i]);
 895                         }
 896
 897                         if (i > 1)
 898                                 continue;
 899
 900                         if ((sg_split_status[i] & (0x1 << bit)) != 0) {
 901                                 static const char *s;
 902
 903                                 s = split_status_strings[bit];
 904                                 printf(s, ahd_name(ahd), "SG");
 905                         }
 906                 }
 907         }
 908         /*
 909          * Clear PCI-X status bits.
 910          */
 911         ahd_pci_write_config(ahd->dev_softc, PCIXR_STATUS,
 912                              pcix_status, /*bytes*/2);
 913         ahd_outb(ahd, CLRINT, CLRSPLTINT);
 914         ahd_restore_modes(ahd, saved_modes);
 915 }
 916
 917 static int
 918 ahd_aic7901_setup(struct ahd_softc *ahd)
 919 {
 920
 921         ahd->chip = AHD_AIC7901;
 922         ahd->features = AHD_AIC7901_FE;
 923         return (ahd_aic790X_setup(ahd));
 924 }
 925
 926 static int
 927 ahd_aic7901A_setup(struct ahd_softc *ahd)
 928 {
 929
 930         ahd->chip = AHD_AIC7901A;
 931         ahd->features = AHD_AIC7901A_FE;
 932         return (ahd_aic790X_setup(ahd));
 933 }
 934
 935 static int
 936 ahd_aic7902_setup(struct ahd_softc *ahd)
 937 {
 938         ahd->chip = AHD_AIC7902;
 939         ahd->features = AHD_AIC7902_FE;
 940         return (ahd_aic790X_setup(ahd));
 941 }
 942
 943 static int
 944 ahd_aic790X_setup(struct ahd_softc *ahd)
 945 {
 946         ahd_dev_softc_t pci;
 947         u_int rev;
 948
 949         pci = ahd->dev_softc;
 950         rev = ahd_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
 951         if (rev < ID_AIC7902_PCI_REV_A4) {
 952                 printf("%s: Unable to attach to unsupported chip revision %d\n",
 953                        ahd_name(ahd), rev);
 954                 ahd_pci_write_config(pci, PCIR_COMMAND, 0, /*bytes*/2);
 955                 return (ENXIO);
 956         }
 957         ahd->channel = ahd_get_pci_function(pci) + 'A';
 958         if (rev < ID_AIC7902_PCI_REV_B0) {
 959                 /*
 960                  * Enable A series workarounds.
 961                  */
 962                 ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG
 963                           |  AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG
 964                           |  AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG
 965                           |  AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG
 966                           |  AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG
 967                           |  AHD_PCIX_CHIPRST_BUG|AHD_PCIX_SCBRAM_RD_BUG
 968                           |  AHD_PKTIZED_STATUS_BUG|AHD_PKT_LUN_BUG
 969                           |  AHD_MDFF_WSCBPTR_BUG|AHD_REG_SLOW_SETTLE_BUG
 970                           |  AHD_SET_MODE_BUG|AHD_BUSFREEREV_BUG
 971                           |  AHD_NONPACKFIFO_BUG|AHD_PACED_NEGTABLE_BUG
 972                           |  AHD_FAINT_LED_BUG;
 973
 974                 /*
 975                  * IO Cell paramter setup.
 976                  */
 977                 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29);
 978
 979                 if ((ahd->flags & AHD_HP_BOARD) == 0)
 980                         AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVA);
 981         } else {
 982                 u_int devconfig1;
 983
 984                 ahd->features |= AHD_RTI|AHD_NEW_IOCELL_OPTS
 985                               |  AHD_NEW_DFCNTRL_OPTS|AHD_FAST_CDB_DELIVERY;
 986                 ahd->bugs |= AHD_LQOOVERRUN_BUG|AHD_EARLY_REQ_BUG;
 987
 988                 /*
 989                  * Some issues have been resolved in the 7901B.
 990                  */
 991                 if ((ahd->features & AHD_MULTI_FUNC) != 0)
 992                         ahd->bugs |= AHD_INTCOLLISION_BUG|AHD_ABORT_LQI_BUG;
 993
 994                 /*
 995                  * IO Cell paramter setup.
 996                  */
 997                 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29);
 998                 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB);
 999                 AHD_SET_AMPLITUDE(ahd, AHD_AMPLITUDE_DEF);
1000
1001                 /*
1002                  * Set the PREQDIS bit for H2B which disables some workaround
1003                  * that doesn't work on regular PCI busses.
1004                  * XXX - Find out exactly what this does from the hardware
1005                  *       folks!
1006                  */
1007                 devconfig1 = ahd_pci_read_config(pci, DEVCONFIG1, /*bytes*/1);
1008                 ahd_pci_write_config(pci, DEVCONFIG1,
1009                                      devconfig1|PREQDIS, /*bytes*/1);
1010                 devconfig1 = ahd_pci_read_config(pci, DEVCONFIG1, /*bytes*/1);
1011         }
1012
1013         return (0);
1014 }