2 * Workbit NinjaSCSI-32Bi/UDE PCI/CardBus SCSI Host Bus Adapter driver
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2, or (at your option)
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
19 //#define NSP32_DEBUG 9
24 #define PCI_VENDOR_ID_IODATA 0x10fc
25 #define PCI_VENDOR_ID_WORKBIT 0x1145
27 #define PCI_DEVICE_ID_NINJASCSI_32BI_CBSC_II 0x0005
28 #define PCI_DEVICE_ID_NINJASCSI_32BI_KME 0xf007
29 #define PCI_DEVICE_ID_NINJASCSI_32BI_WBT 0x8007
30 #define PCI_DEVICE_ID_WORKBIT_STANDARD 0xf010
31 #define PCI_DEVICE_ID_WORKBIT_DUALEDGE 0xf011
32 #define PCI_DEVICE_ID_NINJASCSI_32BI_LOGITEC 0xf012
33 #define PCI_DEVICE_ID_NINJASCSI_32BIB_LOGITEC 0xf013
34 #define PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO 0xf015
35 #define PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO_II 0x8009
45 MODEL_PCI_WORKBIT = 4,
46 MODEL_PCI_LOGITEC = 5,
50 static char * nsp32_model[] = {
51 "I-O DATA CBSC-II CardBus card",
52 "KME SCSI CardBus card",
53 "Workbit duo SCSI CardBus card",
54 "Logitec CardBus card with external ROM",
55 "Workbit / I-O DATA PCI card",
56 "Logitec PCI card with external ROM",
57 "Melco CardBus/PCI card with external ROM",
62 * SCSI Generic Definitions
64 #define EXTENDED_SDTR_LEN 0x03
73 #define NUMBER(arr) ((int) (sizeof(arr) / sizeof(arr[0])))
74 #define BIT(x) (1UL << (x))
76 # define MIN(a,b) ((a) > (b) ? (b) : (a))
96 * Don't access below register with Double Word:
97 * +00, +04, +08, +0c, +64, +80, +84, +88, +90, +c4, +c8, +cc, +d0.
99 #define IRQ_CONTROL 0x00 /* BASE+00, W, W */
100 #define IRQ_STATUS 0x00 /* BASE+00, W, R */
101 # define IRQSTATUS_LATCHED_MSG BIT(0)
102 # define IRQSTATUS_LATCHED_IO BIT(1)
103 # define IRQSTATUS_LATCHED_CD BIT(2)
104 # define IRQSTATUS_LATCHED_BUS_FREE BIT(3)
105 # define IRQSTATUS_RESELECT_OCCUER BIT(4)
106 # define IRQSTATUS_PHASE_CHANGE_IRQ BIT(5)
107 # define IRQSTATUS_SCSIRESET_IRQ BIT(6)
108 # define IRQSTATUS_TIMER_IRQ BIT(7)
109 # define IRQSTATUS_FIFO_SHLD_IRQ BIT(8)
110 # define IRQSTATUS_PCI_IRQ BIT(9)
111 # define IRQSTATUS_BMCNTERR_IRQ BIT(10)
112 # define IRQSTATUS_AUTOSCSI_IRQ BIT(11)
113 # define PCI_IRQ_MASK BIT(12)
114 # define TIMER_IRQ_MASK BIT(13)
115 # define FIFO_IRQ_MASK BIT(14)
116 # define SCSI_IRQ_MASK BIT(15)
117 # define IRQ_CONTROL_ALL_IRQ_MASK (PCI_IRQ_MASK | \
121 # define IRQSTATUS_ANY_IRQ (IRQSTATUS_RESELECT_OCCUER | \
122 IRQSTATUS_PHASE_CHANGE_IRQ | \
123 IRQSTATUS_SCSIRESET_IRQ | \
124 IRQSTATUS_TIMER_IRQ | \
125 IRQSTATUS_FIFO_SHLD_IRQ | \
126 IRQSTATUS_PCI_IRQ | \
127 IRQSTATUS_BMCNTERR_IRQ | \
128 IRQSTATUS_AUTOSCSI_IRQ )
130 #define TRANSFER_CONTROL 0x02 /* BASE+02, W, W */
131 #define TRANSFER_STATUS 0x02 /* BASE+02, W, R */
132 # define CB_MMIO_MODE BIT(0)
133 # define CB_IO_MODE BIT(1)
134 # define BM_TEST BIT(2)
135 # define BM_TEST_DIR BIT(3)
136 # define DUAL_EDGE_ENABLE BIT(4)
137 # define NO_TRANSFER_TO_HOST BIT(5)
138 # define TRANSFER_GO BIT(7)
139 # define BLIEND_MODE BIT(8)
140 # define BM_START BIT(9)
141 # define ADVANCED_BM_WRITE BIT(10)
142 # define BM_SINGLE_MODE BIT(11)
143 # define FIFO_TRUE_FULL BIT(12)
144 # define FIFO_TRUE_EMPTY BIT(13)
145 # define ALL_COUNTER_CLR BIT(14)
146 # define FIFOTEST BIT(15)
148 #define INDEX_REG 0x04 /* BASE+04, Byte(R/W), Word(R) */
150 #define TIMER_SET 0x06 /* BASE+06, W, R/W */
151 # define TIMER_CNT_MASK (0xff)
152 # define TIMER_STOP BIT(8)
154 #define DATA_REG_LOW 0x08 /* BASE+08, LowW, R/W */
155 #define DATA_REG_HI 0x0a /* BASE+0a, Hi-W, R/W */
157 #define FIFO_REST_CNT 0x0c /* BASE+0c, W, R/W */
158 # define FIFO_REST_MASK 0x1ff
159 # define FIFO_EMPTY_SHLD_FLAG BIT(14)
160 # define FIFO_FULL_SHLD_FLAG BIT(15)
162 #define SREQ_SMPL_RATE 0x0f /* BASE+0f, B, R/W */
163 # define SREQSMPLRATE_RATE0 BIT(0)
164 # define SREQSMPLRATE_RATE1 BIT(1)
165 # define SAMPLING_ENABLE BIT(2)
166 # define SMPL_40M (0) /* 40MHz: 0-100ns/period */
167 # define SMPL_20M (SREQSMPLRATE_RATE0) /* 20MHz: 100-200ns/period */
168 # define SMPL_10M (SREQSMPLRATE_RATE1) /* 10Mhz: 200- ns/period */
170 #define SCSI_BUS_CONTROL 0x10 /* BASE+10, B, R/W */
171 # define BUSCTL_SEL BIT(0)
172 # define BUSCTL_RST BIT(1)
173 # define BUSCTL_DATAOUT_ENB BIT(2)
174 # define BUSCTL_ATN BIT(3)
175 # define BUSCTL_ACK BIT(4)
176 # define BUSCTL_BSY BIT(5)
177 # define AUTODIRECTION BIT(6)
178 # define ACKENB BIT(7)
180 #define CLR_COUNTER 0x12 /* BASE+12, B, W */
181 # define ACK_COUNTER_CLR BIT(0)
182 # define SREQ_COUNTER_CLR BIT(1)
183 # define FIFO_HOST_POINTER_CLR BIT(2)
184 # define FIFO_REST_COUNT_CLR BIT(3)
185 # define BM_COUNTER_CLR BIT(4)
186 # define SAVED_ACK_CLR BIT(5)
187 # define CLRCOUNTER_ALLMASK (ACK_COUNTER_CLR | \
189 FIFO_HOST_POINTER_CLR | \
190 FIFO_REST_COUNT_CLR | \
194 #define SCSI_BUS_MONITOR 0x12 /* BASE+12, B, R */
195 # define BUSMON_MSG BIT(0)
196 # define BUSMON_IO BIT(1)
197 # define BUSMON_CD BIT(2)
198 # define BUSMON_BSY BIT(3)
199 # define BUSMON_ACK BIT(4)
200 # define BUSMON_REQ BIT(5)
201 # define BUSMON_SEL BIT(6)
202 # define BUSMON_ATN BIT(7)
204 #define COMMAND_DATA 0x14 /* BASE+14, B, R/W */
206 #define PARITY_CONTROL 0x16 /* BASE+16, B, W */
207 # define PARITY_CHECK_ENABLE BIT(0)
208 # define PARITY_ERROR_CLEAR BIT(1)
209 #define PARITY_STATUS 0x16 /* BASE+16, B, R */
210 //# define PARITY_CHECK_ENABLE BIT(0)
211 # define PARITY_ERROR_NORMAL BIT(1)
212 # define PARITY_ERROR_LSB BIT(1)
213 # define PARITY_ERROR_MSB BIT(2)
215 #define RESELECT_ID 0x18 /* BASE+18, B, R */
217 #define COMMAND_CONTROL 0x18 /* BASE+18, W, W */
218 # define CLEAR_CDB_FIFO_POINTER BIT(0)
219 # define AUTO_COMMAND_PHASE BIT(1)
220 # define AUTOSCSI_START BIT(2)
221 # define AUTOSCSI_RESTART BIT(3)
222 # define AUTO_PARAMETER BIT(4)
223 # define AUTO_ATN BIT(5)
224 # define AUTO_MSGIN_00_OR_04 BIT(6)
225 # define AUTO_MSGIN_02 BIT(7)
226 # define AUTO_MSGIN_03 BIT(8)
228 #define SET_ARBIT 0x1a /* BASE+1a, B, W */
229 # define ARBIT_GO BIT(0)
230 # define ARBIT_CLEAR BIT(1)
232 #define ARBIT_STATUS 0x1a /* BASE+1a, B, R */
233 //# define ARBIT_GO BIT(0)
234 # define ARBIT_WIN BIT(1)
235 # define ARBIT_FAIL BIT(2)
236 # define AUTO_PARAMETER_VALID BIT(3)
237 # define SGT_VALID BIT(4)
239 #define SYNC_REG 0x1c /* BASE+1c, B, R/W */
241 #define ACK_WIDTH 0x1d /* BASE+1d, B, R/W */
243 #define SCSI_DATA_WITH_ACK 0x20 /* BASE+20, B, R/W */
244 #define SCSI_OUT_LATCH_TARGET_ID 0x22 /* BASE+22, B, W */
245 #define SCSI_DATA_IN 0x22 /* BASE+22, B, R */
247 #define SCAM_CONTROL 0x24 /* BASE+24, B, W */
248 #define SCAM_STATUS 0x24 /* BASE+24, B, R */
249 # define SCAM_MSG BIT(0)
250 # define SCAM_IO BIT(1)
251 # define SCAM_CD BIT(2)
252 # define SCAM_BSY BIT(3)
253 # define SCAM_SEL BIT(4)
254 # define SCAM_XFEROK BIT(5)
256 #define SCAM_DATA 0x26 /* BASE+26, B, R/W */
266 #define SACK_CNT 0x28 /* BASE+28, DW, R/W */
267 #define SREQ_CNT 0x2c /* BASE+2c, DW, R/W */
269 #define FIFO_DATA_LOW 0x30 /* BASE+30, B/W/DW, R/W */
270 #define FIFO_DATA_HIGH 0x32 /* BASE+32, B/W, R/W */
271 #define BM_START_ADR 0x34 /* BASE+34, DW, R/W */
273 #define BM_CNT 0x38 /* BASE+38, DW, R/W */
274 # define BM_COUNT_MASK 0x0001ffffUL
275 # define SGTEND BIT(31) /* Last SGT marker */
277 #define SGT_ADR 0x3c /* BASE+3c, DW, R/W */
278 #define WAIT_REG 0x40 /* Bi only */
280 #define SCSI_EXECUTE_PHASE 0x40 /* BASE+40, W, R */
281 # define COMMAND_PHASE BIT(0)
282 # define DATA_IN_PHASE BIT(1)
283 # define DATA_OUT_PHASE BIT(2)
284 # define MSGOUT_PHASE BIT(3)
285 # define STATUS_PHASE BIT(4)
286 # define ILLEGAL_PHASE BIT(5)
287 # define BUS_FREE_OCCUER BIT(6)
288 # define MSG_IN_OCCUER BIT(7)
289 # define MSG_OUT_OCCUER BIT(8)
290 # define SELECTION_TIMEOUT BIT(9)
291 # define MSGIN_00_VALID BIT(10)
292 # define MSGIN_02_VALID BIT(11)
293 # define MSGIN_03_VALID BIT(12)
294 # define MSGIN_04_VALID BIT(13)
295 # define AUTOSCSI_BUSY BIT(15)
297 #define SCSI_CSB_IN 0x42 /* BASE+42, B, R */
299 #define SCSI_MSG_OUT 0x44 /* BASE+44, DW, R/W */
300 # define MSGOUT_COUNT_MASK (BIT(0)|BIT(1))
301 # define MV_VALID BIT(7)
303 #define SEL_TIME_OUT 0x48 /* BASE+48, W, R/W */
304 #define SAVED_SACK_CNT 0x4c /* BASE+4c, DW, R */
306 #define HTOSDATADELAY 0x50 /* BASE+50, B, R/W */
307 #define STOHDATADELAY 0x54 /* BASE+54, B, R/W */
308 #define ACKSUMCHECKRD 0x58 /* BASE+58, W, R */
309 #define REQSUMCHECKRD 0x5c /* BASE+5c, W, R */
312 /********************/
313 /* indexed register */
314 /********************/
316 #define CLOCK_DIV 0x00 /* BASE+08, IDX+00, B, R/W */
317 # define CLOCK_2 BIT(0) /* MCLK/2 */
318 # define CLOCK_4 BIT(1) /* MCLK/4 */
319 # define PCICLK BIT(7) /* PCICLK (33MHz) */
321 #define TERM_PWR_CONTROL 0x01 /* BASE+08, IDX+01, B, R/W */
323 # define SENSE BIT(1) /* Read Only */
325 #define EXT_PORT_DDR 0x02 /* BASE+08, IDX+02, B, R/W */
326 #define EXT_PORT 0x03 /* BASE+08, IDX+03, B, R/W */
328 # define LED_OFF BIT(0)
330 #define IRQ_SELECT 0x04 /* BASE+08, IDX+04, W, R/W */
331 # define IRQSELECT_RESELECT_IRQ BIT(0)
332 # define IRQSELECT_PHASE_CHANGE_IRQ BIT(1)
333 # define IRQSELECT_SCSIRESET_IRQ BIT(2)
334 # define IRQSELECT_TIMER_IRQ BIT(3)
335 # define IRQSELECT_FIFO_SHLD_IRQ BIT(4)
336 # define IRQSELECT_TARGET_ABORT_IRQ BIT(5)
337 # define IRQSELECT_MASTER_ABORT_IRQ BIT(6)
338 # define IRQSELECT_SERR_IRQ BIT(7)
339 # define IRQSELECT_PERR_IRQ BIT(8)
340 # define IRQSELECT_BMCNTERR_IRQ BIT(9)
341 # define IRQSELECT_AUTO_SCSI_SEQ_IRQ BIT(10)
343 #define OLD_SCSI_PHASE 0x05 /* BASE+08, IDX+05, B, R */
344 # define OLD_MSG BIT(0)
345 # define OLD_IO BIT(1)
346 # define OLD_CD BIT(2)
347 # define OLD_BUSY BIT(3)
349 #define FIFO_FULL_SHLD_COUNT 0x06 /* BASE+08, IDX+06, B, R/W */
350 #define FIFO_EMPTY_SHLD_COUNT 0x07 /* BASE+08, IDX+07, B, R/W */
352 #define EXP_ROM_CONTROL 0x08 /* BASE+08, IDX+08, B, R/W */ /* external ROM control */
353 # define ROM_WRITE_ENB BIT(0)
354 # define IO_ACCESS_ENB BIT(1)
355 # define ROM_ADR_CLEAR BIT(2)
357 #define EXP_ROM_ADR 0x09 /* BASE+08, IDX+09, W, R/W */
359 #define EXP_ROM_DATA 0x0a /* BASE+08, IDX+0a, B, R/W */
361 #define CHIP_MODE 0x0b /* BASE+08, IDX+0b, B, R */ /* NinjaSCSI-32Bi only */
362 # define OEM0 BIT(1) /* OEM select */ /* 00=I-O DATA, 01=KME, 10=Workbit, 11=Ext ROM */
363 # define OEM1 BIT(2) /* OEM select */
364 # define OPTB BIT(3) /* KME mode select */
365 # define OPTC BIT(4) /* KME mode select */
366 # define OPTD BIT(5) /* KME mode select */
367 # define OPTE BIT(6) /* KME mode select */
368 # define OPTF BIT(7) /* Power management */
370 #define MISC_WR 0x0c /* BASE+08, IDX+0c, W, R/W */
372 # define SCSI_DIRECTION_DETECTOR_SELECT BIT(0)
373 # define SCSI2_HOST_DIRECTION_VALID BIT(1) /* Read only */
374 # define HOST2_SCSI_DIRECTION_VALID BIT(2) /* Read only */
375 # define DELAYED_BMSTART BIT(3)
376 # define MASTER_TERMINATION_SELECT BIT(4)
377 # define BMREQ_NEGATE_TIMING_SEL BIT(5)
378 # define AUTOSEL_TIMING_SEL BIT(6)
379 # define MISC_MABORT_MASK BIT(7)
380 # define BMSTOP_CHANGE2_NONDATA_PHASE BIT(8)
382 #define BM_CYCLE 0x0d /* BASE+08, IDX+0d, B, R/W */
383 # define BM_CYCLE0 BIT(0)
384 # define BM_CYCLE1 BIT(1)
385 # define BM_FRAME_ASSERT_TIMING BIT(2)
386 # define BM_IRDY_ASSERT_TIMING BIT(3)
387 # define BM_SINGLE_BUS_MASTER BIT(4)
388 # define MEMRD_CMD0 BIT(5)
389 # define SGT_AUTO_PARA_MEMED_CMD BIT(6)
390 # define MEMRD_CMD1 BIT(7)
393 #define SREQ_EDGH 0x0e /* BASE+08, IDX+0e, B, W */
394 # define SREQ_EDGH_SELECT BIT(0)
396 #define UP_CNT 0x0f /* BASE+08, IDX+0f, B, W */
397 # define REQCNT_UP BIT(0)
398 # define ACKCNT_UP BIT(1)
399 # define BMADR_UP BIT(4)
400 # define BMCNT_UP BIT(5)
401 # define SGT_CNT_UP BIT(7)
403 #define CFG_CMD_STR 0x10 /* BASE+08, IDX+10, W, R */
404 #define CFG_LATE_CACHE 0x11 /* BASE+08, IDX+11, W, R/W */
405 #define CFG_BASE_ADR_1 0x12 /* BASE+08, IDX+12, W, R */
406 #define CFG_BASE_ADR_2 0x13 /* BASE+08, IDX+13, W, R */
407 #define CFG_INLINE 0x14 /* BASE+08, IDX+14, W, R */
409 #define SERIAL_ROM_CTL 0x15 /* BASE+08, IDX+15, B, R */
414 #define FIFO_HST_POINTER 0x16 /* BASE+08, IDX+16, B, R/W */
415 #define SREQ_DELAY 0x17 /* BASE+08, IDX+17, B, R/W */
416 #define SACK_DELAY 0x18 /* BASE+08, IDX+18, B, R/W */
417 #define SREQ_NOISE_CANCEL 0x19 /* BASE+08, IDX+19, B, R/W */
418 #define SDP_NOISE_CANCEL 0x1a /* BASE+08, IDX+1a, B, R/W */
419 #define DELAY_TEST 0x1b /* BASE+08, IDX+1b, B, R/W */
420 #define SD0_NOISE_CANCEL 0x20 /* BASE+08, IDX+20, B, R/W */
421 #define SD1_NOISE_CANCEL 0x21 /* BASE+08, IDX+21, B, R/W */
422 #define SD2_NOISE_CANCEL 0x22 /* BASE+08, IDX+22, B, R/W */
423 #define SD3_NOISE_CANCEL 0x23 /* BASE+08, IDX+23, B, R/W */
424 #define SD4_NOISE_CANCEL 0x24 /* BASE+08, IDX+24, B, R/W */
425 #define SD5_NOISE_CANCEL 0x25 /* BASE+08, IDX+25, B, R/W */
426 #define SD6_NOISE_CANCEL 0x26 /* BASE+08, IDX+26, B, R/W */
427 #define SD7_NOISE_CANCEL 0x27 /* BASE+08, IDX+27, B, R/W */
431 * Useful Bus Monitor status combinations.
433 #define BUSMON_BUS_FREE 0
434 #define BUSMON_COMMAND ( BUSMON_BSY | BUSMON_CD | BUSMON_REQ )
435 #define BUSMON_MESSAGE_IN ( BUSMON_BSY | BUSMON_MSG | BUSMON_IO | BUSMON_CD | BUSMON_REQ )
436 #define BUSMON_MESSAGE_OUT ( BUSMON_BSY | BUSMON_MSG | BUSMON_CD | BUSMON_REQ )
437 #define BUSMON_DATA_IN ( BUSMON_BSY | BUSMON_IO | BUSMON_REQ )
438 #define BUSMON_DATA_OUT ( BUSMON_BSY | BUSMON_REQ )
439 #define BUSMON_STATUS ( BUSMON_BSY | BUSMON_IO | BUSMON_CD | BUSMON_REQ )
440 #define BUSMON_RESELECT ( BUSMON_IO | BUSMON_SEL)
441 #define BUSMON_PHASE_MASK ( BUSMON_MSG | BUSMON_IO | BUSMON_CD | BUSMON_SEL)
443 #define BUSPHASE_COMMAND ( BUSMON_COMMAND & BUSMON_PHASE_MASK )
444 #define BUSPHASE_MESSAGE_IN ( BUSMON_MESSAGE_IN & BUSMON_PHASE_MASK )
445 #define BUSPHASE_MESSAGE_OUT ( BUSMON_MESSAGE_OUT & BUSMON_PHASE_MASK )
446 #define BUSPHASE_DATA_IN ( BUSMON_DATA_IN & BUSMON_PHASE_MASK )
447 #define BUSPHASE_DATA_OUT ( BUSMON_DATA_OUT & BUSMON_PHASE_MASK )
448 #define BUSPHASE_STATUS ( BUSMON_STATUS & BUSMON_PHASE_MASK )
449 #define BUSPHASE_SELECT ( BUSMON_SEL | BUSMON_IO )
452 /************************************************************************
453 * structure for DMA/Scatter Gather list
455 #define NSP32_SG_SIZE SG_ALL
457 typedef struct _nsp32_sgtable {
458 /* values must be little endian */
459 u32_le addr; /* transfer address */
460 u32_le len; /* transfer length. BIT(31) is for SGT_END mark */
461 } __attribute__ ((packed)) nsp32_sgtable;
463 typedef struct _nsp32_sglun {
464 nsp32_sgtable sgt[NSP32_SG_SIZE+1]; /* SG table */
465 } __attribute__ ((packed)) nsp32_sglun;
466 #define NSP32_SG_TABLE_SIZE (sizeof(nsp32_sgtable) * NSP32_SG_SIZE * MAX_TARGET * MAX_LUN)
468 /* Auto parameter mode memory map. */
469 /* All values must be little endian. */
470 typedef struct _nsp32_autoparam {
471 u8 cdb[4 * 0x10]; /* SCSI Command */
472 u32_le msgout; /* outgoing messages */
473 u8 syncreg; /* sync register value */
474 u8 ackwidth; /* ack width register value */
475 u8 target_id; /* target/host device id */
476 u8 sample_reg; /* hazard killer sampling rate */
477 u16_le command_control; /* command control register */
478 u16_le transfer_control; /* transfer control register */
479 u32_le sgt_pointer; /* SG table physical address for DMA */
481 } __attribute__ ((packed)) nsp32_autoparam; /* must be packed struct */
484 * host data structure
486 /* message in/out buffer */
487 #define MSGOUTBUF_MAX 20
488 #define MSGINBUF_MAX 20
490 /* flag for trans_method */
491 #define NSP32_TRANSFER_BUSMASTER BIT(0)
492 #define NSP32_TRANSFER_MMIO BIT(1) /* Not supported yet */
493 #define NSP32_TRANSFER_PIO BIT(2) /* Not supported yet */
497 * structure for connected LUN dynamic data
499 * Note: Currently tagged queuing is disabled, each nsp32_lunt holds
500 * one SCSI command and one state.
502 #define DISCPRIV_OK BIT(0) /* DISCPRIV Enable mode */
503 #define MSGIN03 BIT(1) /* Auto Msg In 03 Flag */
505 typedef struct _nsp32_lunt {
506 Scsi_Cmnd *SCpnt; /* Current Handling Scsi_Cmnd */
507 unsigned long save_datp; /* Save Data Pointer - saved position from initial address */
508 int msgin03; /* auto msg in 03 flag */
509 unsigned int sg_num; /* Total number of SG entries */
510 int cur_entry; /* Current SG entry number */
511 nsp32_sglun *sglun; /* sg table per lun */
512 dma_addr_t sglun_paddr; /* sglun physical address */
517 * SCSI TARGET/LUN definition
519 #define NSP32_HOST_SCSIID 7 /* SCSI initiator is everytime defined as 7 */
521 #define MAX_LUN 8 /* XXX: In SPI3, max number of LUN is 64. */
524 typedef struct _nsp32_sync_table {
525 unsigned char period_num; /* period number */
526 unsigned char ackwidth; /* ack width designated by period */
527 unsigned char start_period; /* search range - start period */
528 unsigned char end_period; /* search range - end period */
529 unsigned char sample_rate; /* hazard killer parameter */
534 * structure for target device static data
536 /* flag for nsp32_target.sync_flag */
537 #define SDTR_INITIATOR BIT(0) /* sending SDTR from initiator */
538 #define SDTR_TARGET BIT(1) /* sending SDTR from target */
539 #define SDTR_DONE BIT(2) /* exchanging SDTR has been processed */
541 /* syncronous period value for nsp32_target.config_max */
544 #define ULTRA20M 0x0c
546 /* flag for nsp32_target.{sync_offset}, period */
547 #define ASYNC_OFFSET 0 /* asynchronous transfer */
548 #define SYNC_OFFSET 0xf /* synchronous transfer max offset */
551 bit:07 06 05 04 03 02 01 00
552 ---PERIOD-- ---OFFSET-- */
553 #define TO_SYNCREG(period, offset) (((period) & 0x0f) << 4 | ((offset) & 0x0f))
555 typedef struct _nsp32_target {
556 unsigned char syncreg; /* value for SYNCREG */
557 unsigned char ackwidth; /* value for ACKWIDTH */
558 unsigned char period; /* sync period (0-255) */
559 unsigned char offset; /* sync offset (0-15) */
560 int sync_flag; /* SDTR_*, 0 */
561 int limit_entry; /* max speed limit entry designated
562 by EEPROM configuration */
563 unsigned char sample_reg; /* SREQ hazard killer register */
566 typedef struct _nsp32_hw_data {
570 unsigned long MmioAddress;
571 #define NSP32_MMIO_OFFSET 0x0800
572 unsigned long MmioLength;
574 Scsi_Cmnd *CurrentSC;
577 const struct pci_device_id *pci_devid;
578 struct Scsi_Host *Host;
583 /* allocated memory region */
584 nsp32_sglun *sg_list; /* sglist virtuxal address */
585 dma_addr_t sg_paddr; /* physical address of hw_sg_table */
586 nsp32_autoparam *autoparam; /* auto parameter transfer region */
587 dma_addr_t auto_paddr; /* physical address of autoparam */
588 int cur_entry; /* current sgt entry */
591 nsp32_lunt *cur_lunt; /* Current connected LUN table */
592 nsp32_lunt lunt[MAX_TARGET][MAX_LUN]; /* All LUN table */
594 nsp32_target *cur_target; /* Current connected SCSI ID */
595 nsp32_target target[MAX_TARGET]; /* SCSI ID */
596 int cur_id; /* Current connected target ID */
597 int cur_lun; /* Current connected target LUN */
599 /* behavior setting parameters */
600 int trans_method; /* transfer method flag */
601 int resettime; /* Reset time */
602 int clock; /* clock dividing flag */
603 nsp32_sync_table *synct; /* sync_table determined by clock */
604 int syncnum; /* the max number of synct element */
607 unsigned char msgoutbuf[MSGOUTBUF_MAX]; /* msgout buffer */
608 char msgout_len; /* msgoutbuf length */
609 unsigned char msginbuf [MSGINBUF_MAX]; /* megin buffer */
610 char msgin_len; /* msginbuf length */
613 u32 PciState[16]; /* save PCI state to this area */
620 #define RESET_HOLD_TIME 10000 /* reset time in us (SCSI-2 says the
622 #define SEL_TIMEOUT_TIME 10000 /* 250ms defined in SCSI specification
624 #define ARBIT_TIMEOUT_TIME 100 /* 100us */
625 #define REQSACK_TIMEOUT_TIME 10000 /* max wait time for REQ/SACK assertion
626 or negation, 10000us == 10ms */
628 /**************************************************************************
629 * Compatibility functions
633 #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
634 # define scsi_register_host(template) scsi_register_module(MODULE_SCSI_HA, template)
635 # define scsi_unregister_host(template) scsi_unregister_module(MODULE_SCSI_HA, template)
636 # define scsi_host_put(host) scsi_unregister(host)
637 # define pci_name(pci_dev) ((pci_dev)->slot_name)
639 typedef void irqreturn_t;
640 # define IRQ_NONE /* */
641 # define IRQ_HANDLED /* */
642 # define IRQ_RETVAL(x) /* */
644 /* This is ad-hoc version of scsi_host_get_next() */
645 static inline struct Scsi_Host *scsi_host_get_next(struct Scsi_Host *host)
648 return scsi_hostlist;
654 /* This is ad-hoc version of scsi_host_hn_get() */
655 static inline struct Scsi_Host *scsi_host_hn_get(unsigned short hostno)
657 struct Scsi_Host *host;
659 for (host = scsi_host_get_next(NULL); host != NULL;
660 host = scsi_host_get_next(host)) {
661 if (host->host_no == hostno) {
670 #endif /* _NSP32_H */