drivers/scsi/qla2xxx/qla_dbg.c

   1 /*
   2  *                  QLOGIC LINUX SOFTWARE
   3  *
   4  * QLogic ISP2x00 device driver for Linux 2.6.x
   5  * Copyright (C) 2003-2004 QLogic Corporation
   6  * (www.qlogic.com)
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of the GNU General Public License as published by the
  10  * Free Software Foundation; either version 2, or (at your option) any
  11  * later version.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  */
  19 #include "qla_def.h"
  20
  21 #include <linux/delay.h>
  22
  23 static int qla_uprintf(char **, char *, ...);
  24
  25 /**
  26  * qla2300_fw_dump() - Dumps binary data from the 2300 firmware.
  27  * @ha: HA context
  28  * @hardware_locked: Called with the hardware_lock
  29  */
  30 void
  31 qla2300_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
  32 {
  33         int             rval;
  34         uint32_t        cnt, timer;
  35         uint32_t        risc_address;
  36         uint16_t        mb0, mb2;
  37
  38         uint32_t        stat;
  39         device_reg_t    *reg;
  40         uint16_t        *dmp_reg;
  41         unsigned long   flags;
  42         struct qla2300_fw_dump  *fw;
  43         uint32_t        dump_size, data_ram_cnt;
  44
  45         reg = ha->iobase;
  46         risc_address = data_ram_cnt = 0;
  47         mb0 = mb2 = 0;
  48         flags = 0;
  49
  50         if (!hardware_locked)
  51                 spin_lock_irqsave(&ha->hardware_lock, flags);
  52
  53         if (ha->fw_dump != NULL) {
  54                 qla_printk(KERN_WARNING, ha,
  55                     "Firmware has been previously dumped (%p) -- ignoring "
  56                     "request...\n", ha->fw_dump);
  57                 goto qla2300_fw_dump_failed;
  58         }
  59
  60         /* Allocate (large) dump buffer. */
  61         dump_size = sizeof(struct qla2300_fw_dump);
  62         dump_size += (ha->fw_memory_size - 0x11000) * sizeof(uint16_t);
  63         ha->fw_dump_order = get_order(dump_size);
  64         ha->fw_dump = (struct qla2300_fw_dump *) __get_free_pages(GFP_ATOMIC,
  65             ha->fw_dump_order);
  66         if (ha->fw_dump == NULL) {
  67                 qla_printk(KERN_WARNING, ha,
  68                     "Unable to allocated memory for firmware dump (%d/%d).\n",
  69                     ha->fw_dump_order, dump_size);
  70                 goto qla2300_fw_dump_failed;
  71         }
  72         fw = ha->fw_dump;
  73
  74         rval = QLA_SUCCESS;
  75         fw->hccr = RD_REG_WORD(&reg->hccr);
  76
  77         /* Pause RISC. */
  78         WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
  79         if (IS_QLA2300(ha)) {
  80                 for (cnt = 30000;
  81                     (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
  82                         rval == QLA_SUCCESS; cnt--) {
  83                         if (cnt)
  84                                 udelay(100);
  85                         else
  86                                 rval = QLA_FUNCTION_TIMEOUT;
  87                 }
  88         } else {
  89                 udelay(10);
  90         }
  91
  92         if (rval == QLA_SUCCESS) {
  93                 dmp_reg = (uint16_t *)(reg + 0);
  94                 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
  95                         fw->pbiu_reg[cnt] = RD_REG_WORD(dmp_reg++);
  96
  97                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x10);
  98                 for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++)
  99                         fw->risc_host_reg[cnt] = RD_REG_WORD(dmp_reg++);
 100
 101                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x40);
 102                 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
 103                         fw->mailbox_reg[cnt] = RD_REG_WORD(dmp_reg++);
 104
 105                 WRT_REG_WORD(&reg->ctrl_status, 0x40);
 106                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 107                 for (cnt = 0; cnt < sizeof(fw->resp_dma_reg) / 2; cnt++)
 108                         fw->resp_dma_reg[cnt] = RD_REG_WORD(dmp_reg++);
 109
 110                 WRT_REG_WORD(&reg->ctrl_status, 0x50);
 111                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 112                 for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
 113                         fw->dma_reg[cnt] = RD_REG_WORD(dmp_reg++);
 114
 115                 WRT_REG_WORD(&reg->ctrl_status, 0x00);
 116                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0xA0);
 117                 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
 118                         fw->risc_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++);
 119
 120                 WRT_REG_WORD(&reg->pcr, 0x2000);
 121                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 122                 for (cnt = 0; cnt < sizeof(fw->risc_gp0_reg) / 2; cnt++)
 123                         fw->risc_gp0_reg[cnt] = RD_REG_WORD(dmp_reg++);
 124
 125                 WRT_REG_WORD(&reg->pcr, 0x2200);
 126                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 127                 for (cnt = 0; cnt < sizeof(fw->risc_gp1_reg) / 2; cnt++)
 128                         fw->risc_gp1_reg[cnt] = RD_REG_WORD(dmp_reg++);
 129
 130                 WRT_REG_WORD(&reg->pcr, 0x2400);
 131                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 132                 for (cnt = 0; cnt < sizeof(fw->risc_gp2_reg) / 2; cnt++)
 133                         fw->risc_gp2_reg[cnt] = RD_REG_WORD(dmp_reg++);
 134
 135                 WRT_REG_WORD(&reg->pcr, 0x2600);
 136                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 137                 for (cnt = 0; cnt < sizeof(fw->risc_gp3_reg) / 2; cnt++)
 138                         fw->risc_gp3_reg[cnt] = RD_REG_WORD(dmp_reg++);
 139
 140                 WRT_REG_WORD(&reg->pcr, 0x2800);
 141                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 142                 for (cnt = 0; cnt < sizeof(fw->risc_gp4_reg) / 2; cnt++)
 143                         fw->risc_gp4_reg[cnt] = RD_REG_WORD(dmp_reg++);
 144
 145                 WRT_REG_WORD(&reg->pcr, 0x2A00);
 146                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 147                 for (cnt = 0; cnt < sizeof(fw->risc_gp5_reg) / 2; cnt++)
 148                         fw->risc_gp5_reg[cnt] = RD_REG_WORD(dmp_reg++);
 149
 150                 WRT_REG_WORD(&reg->pcr, 0x2C00);
 151                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 152                 for (cnt = 0; cnt < sizeof(fw->risc_gp6_reg) / 2; cnt++)
 153                         fw->risc_gp6_reg[cnt] = RD_REG_WORD(dmp_reg++);
 154
 155                 WRT_REG_WORD(&reg->pcr, 0x2E00);
 156                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 157                 for (cnt = 0; cnt < sizeof(fw->risc_gp7_reg) / 2; cnt++)
 158                         fw->risc_gp7_reg[cnt] = RD_REG_WORD(dmp_reg++);
 159
 160                 WRT_REG_WORD(&reg->ctrl_status, 0x10);
 161                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 162                 for (cnt = 0; cnt < sizeof(fw->frame_buf_hdw_reg) / 2; cnt++)
 163                         fw->frame_buf_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++);
 164
 165                 WRT_REG_WORD(&reg->ctrl_status, 0x20);
 166                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 167                 for (cnt = 0; cnt < sizeof(fw->fpm_b0_reg) / 2; cnt++)
 168                         fw->fpm_b0_reg[cnt] = RD_REG_WORD(dmp_reg++);
 169
 170                 WRT_REG_WORD(&reg->ctrl_status, 0x30);
 171                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 172                 for (cnt = 0; cnt < sizeof(fw->fpm_b1_reg) / 2; cnt++)
 173                         fw->fpm_b1_reg[cnt] = RD_REG_WORD(dmp_reg++);
 174
 175                 /* Reset RISC. */
 176                 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
 177                 for (cnt = 0; cnt < 30000; cnt++) {
 178                         if ((RD_REG_WORD(&reg->ctrl_status) &
 179                             CSR_ISP_SOFT_RESET) == 0)
 180                                 break;
 181
 182                         udelay(10);
 183                 }
 184         }
 185
 186         if (!IS_QLA2300(ha)) {
 187                 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
 188                     rval == QLA_SUCCESS; cnt--) {
 189                         if (cnt)
 190                                 udelay(100);
 191                         else
 192                                 rval = QLA_FUNCTION_TIMEOUT;
 193                 }
 194         }
 195
 196         if (rval == QLA_SUCCESS) {
 197                 /* Get RISC SRAM. */
 198                 risc_address = 0x800;
 199                 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD);
 200                 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
 201         }
 202         for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS;
 203             cnt++, risc_address++) {
 204                 WRT_MAILBOX_REG(ha, reg, 1, (uint16_t)risc_address);
 205                 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
 206
 207                 for (timer = 6000000; timer; timer--) {
 208                         /* Check for pending interrupts. */
 209                         stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
 210                         if (stat & HSR_RISC_INT) {
 211                                 stat &= 0xff;
 212
 213                                 if (stat == 0x1 || stat == 0x2) {
 214                                         set_bit(MBX_INTERRUPT,
 215                                             &ha->mbx_cmd_flags);
 216
 217                                         mb0 = RD_MAILBOX_REG(ha, reg, 0);
 218                                         mb2 = RD_MAILBOX_REG(ha, reg, 2);
 219
 220                                         /* Release mailbox registers. */
 221                                         WRT_REG_WORD(&reg->semaphore, 0);
 222                                         WRT_REG_WORD(&reg->hccr,
 223                                             HCCR_CLR_RISC_INT);
 224                                         break;
 225                                 } else if (stat == 0x10 || stat == 0x11) {
 226                                         set_bit(MBX_INTERRUPT,
 227                                             &ha->mbx_cmd_flags);
 228
 229                                         mb0 = RD_MAILBOX_REG(ha, reg, 0);
 230                                         mb2 = RD_MAILBOX_REG(ha, reg, 2);
 231
 232                                         WRT_REG_WORD(&reg->hccr,
 233                                             HCCR_CLR_RISC_INT);
 234                                         break;
 235                                 }
 236
 237                                 /* clear this intr; it wasn't a mailbox intr */
 238                                 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
 239                         }
 240                         udelay(5);
 241                 }
 242
 243                 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
 244                         rval = mb0 & MBS_MASK;
 245                         fw->risc_ram[cnt] = mb2;
 246                 } else {
 247                         rval = QLA_FUNCTION_FAILED;
 248                 }
 249         }
 250
 251         if (rval == QLA_SUCCESS) {
 252                 /* Get stack SRAM. */
 253                 risc_address = 0x10000;
 254                 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_EXTENDED);
 255                 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
 256         }
 257         for (cnt = 0; cnt < sizeof(fw->stack_ram) / 2 && rval == QLA_SUCCESS;
 258             cnt++, risc_address++) {
 259                 WRT_MAILBOX_REG(ha, reg, 1, LSW(risc_address));
 260                 WRT_MAILBOX_REG(ha, reg, 8, MSW(risc_address));
 261                 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
 262
 263                 for (timer = 6000000; timer; timer--) {
 264                         /* Check for pending interrupts. */
 265                         stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
 266                         if (stat & HSR_RISC_INT) {
 267                                 stat &= 0xff;
 268
 269                                 if (stat == 0x1 || stat == 0x2) {
 270                                         set_bit(MBX_INTERRUPT,
 271                                             &ha->mbx_cmd_flags);
 272
 273                                         mb0 = RD_MAILBOX_REG(ha, reg, 0);
 274                                         mb2 = RD_MAILBOX_REG(ha, reg, 2);
 275
 276                                         /* Release mailbox registers. */
 277                                         WRT_REG_WORD(&reg->semaphore, 0);
 278                                         WRT_REG_WORD(&reg->hccr,
 279                                             HCCR_CLR_RISC_INT);
 280                                         break;
 281                                 } else if (stat == 0x10 || stat == 0x11) {
 282                                         set_bit(MBX_INTERRUPT,
 283                                             &ha->mbx_cmd_flags);
 284
 285                                         mb0 = RD_MAILBOX_REG(ha, reg, 0);
 286                                         mb2 = RD_MAILBOX_REG(ha, reg, 2);
 287
 288                                         WRT_REG_WORD(&reg->hccr,
 289                                             HCCR_CLR_RISC_INT);
 290                                         break;
 291                                 }
 292
 293                                 /* clear this intr; it wasn't a mailbox intr */
 294                                 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
 295                         }
 296                         udelay(5);
 297                 }
 298
 299                 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
 300                         rval = mb0 & MBS_MASK;
 301                         fw->stack_ram[cnt] = mb2;
 302                 } else {
 303                         rval = QLA_FUNCTION_FAILED;
 304                 }
 305         }
 306
 307         if (rval == QLA_SUCCESS) {
 308                 /* Get data SRAM. */
 309                 risc_address = 0x11000;
 310                 data_ram_cnt = ha->fw_memory_size - risc_address + 1;
 311                 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_EXTENDED);
 312                 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
 313         }
 314         for (cnt = 0; cnt < data_ram_cnt && rval == QLA_SUCCESS;
 315             cnt++, risc_address++) {
 316                 WRT_MAILBOX_REG(ha, reg, 1, LSW(risc_address));
 317                 WRT_MAILBOX_REG(ha, reg, 8, MSW(risc_address));
 318                 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
 319
 320                 for (timer = 6000000; timer; timer--) {
 321                         /* Check for pending interrupts. */
 322                         stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
 323                         if (stat & HSR_RISC_INT) {
 324                                 stat &= 0xff;
 325
 326                                 if (stat == 0x1 || stat == 0x2) {
 327                                         set_bit(MBX_INTERRUPT,
 328                                             &ha->mbx_cmd_flags);
 329
 330                                         mb0 = RD_MAILBOX_REG(ha, reg, 0);
 331                                         mb2 = RD_MAILBOX_REG(ha, reg, 2);
 332
 333                                         /* Release mailbox registers. */
 334                                         WRT_REG_WORD(&reg->semaphore, 0);
 335                                         WRT_REG_WORD(&reg->hccr,
 336                                             HCCR_CLR_RISC_INT);
 337                                         break;
 338                                 } else if (stat == 0x10 || stat == 0x11) {
 339                                         set_bit(MBX_INTERRUPT,
 340                                             &ha->mbx_cmd_flags);
 341
 342                                         mb0 = RD_MAILBOX_REG(ha, reg, 0);
 343                                         mb2 = RD_MAILBOX_REG(ha, reg, 2);
 344
 345                                         WRT_REG_WORD(&reg->hccr,
 346                                             HCCR_CLR_RISC_INT);
 347                                         break;
 348                                 }
 349
 350                                 /* clear this intr; it wasn't a mailbox intr */
 351                                 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
 352                         }
 353                         udelay(5);
 354                 }
 355
 356                 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
 357                         rval = mb0 & MBS_MASK;
 358                         fw->data_ram[cnt] = mb2;
 359                 } else {
 360                         rval = QLA_FUNCTION_FAILED;
 361                 }
 362         }
 363
 364
 365         if (rval != QLA_SUCCESS) {
 366                 qla_printk(KERN_WARNING, ha,
 367                     "Failed to dump firmware (%x)!!!\n", rval);
 368
 369                 free_pages((unsigned long)ha->fw_dump, ha->fw_dump_order);
 370                 ha->fw_dump = NULL;
 371         } else {
 372                 qla_printk(KERN_INFO, ha,
 373                     "Firmware dump saved to temp buffer (%ld/%p).\n",
 374                     ha->host_no, ha->fw_dump);
 375         }
 376
 377 qla2300_fw_dump_failed:
 378         if (!hardware_locked)
 379                 spin_unlock_irqrestore(&ha->hardware_lock, flags);
 380 }
 381
 382 /**
 383  * qla2300_ascii_fw_dump() - Converts a binary firmware dump to ASCII.
 384  * @ha: HA context
 385  */
 386 void
 387 qla2300_ascii_fw_dump(scsi_qla_host_t *ha)
 388 {
 389         uint32_t cnt;
 390         char *uiter;
 391         char fw_info[30];
 392         struct qla2300_fw_dump *fw;
 393         uint32_t data_ram_cnt;
 394
 395         uiter = ha->fw_dump_buffer;
 396         fw = ha->fw_dump;
 397
 398         qla_uprintf(&uiter, "%s Firmware Version %s\n", ha->model_number,
 399             qla2x00_get_fw_version_str(ha, fw_info));
 400
 401         qla_uprintf(&uiter, "\n[==>BEG]\n");
 402
 403         qla_uprintf(&uiter, "HCCR Register:\n%04x\n\n", fw->hccr);
 404
 405         qla_uprintf(&uiter, "PBIU Registers:");
 406         for (cnt = 0; cnt < sizeof (fw->pbiu_reg) / 2; cnt++) {
 407                 if (cnt % 8 == 0) {
 408                         qla_uprintf(&uiter, "\n");
 409                 }
 410                 qla_uprintf(&uiter, "%04x ", fw->pbiu_reg[cnt]);
 411         }
 412
 413         qla_uprintf(&uiter, "\n\nReqQ-RspQ-Risc2Host Status registers:");
 414         for (cnt = 0; cnt < sizeof (fw->risc_host_reg) / 2; cnt++) {
 415                 if (cnt % 8 == 0) {
 416                         qla_uprintf(&uiter, "\n");
 417                 }
 418                 qla_uprintf(&uiter, "%04x ", fw->risc_host_reg[cnt]);
 419         }
 420
 421         qla_uprintf(&uiter, "\n\nMailbox Registers:");
 422         for (cnt = 0; cnt < sizeof (fw->mailbox_reg) / 2; cnt++) {
 423                 if (cnt % 8 == 0) {
 424                         qla_uprintf(&uiter, "\n");
 425                 }
 426                 qla_uprintf(&uiter, "%04x ", fw->mailbox_reg[cnt]);
 427         }
 428
 429         qla_uprintf(&uiter, "\n\nAuto Request Response DMA Registers:");
 430         for (cnt = 0; cnt < sizeof (fw->resp_dma_reg) / 2; cnt++) {
 431                 if (cnt % 8 == 0) {
 432                         qla_uprintf(&uiter, "\n");
 433                 }
 434                 qla_uprintf(&uiter, "%04x ", fw->resp_dma_reg[cnt]);
 435         }
 436
 437         qla_uprintf(&uiter, "\n\nDMA Registers:");
 438         for (cnt = 0; cnt < sizeof (fw->dma_reg) / 2; cnt++) {
 439                 if (cnt % 8 == 0) {
 440                         qla_uprintf(&uiter, "\n");
 441                 }
 442                 qla_uprintf(&uiter, "%04x ", fw->dma_reg[cnt]);
 443         }
 444
 445         qla_uprintf(&uiter, "\n\nRISC Hardware Registers:");
 446         for (cnt = 0; cnt < sizeof (fw->risc_hdw_reg) / 2; cnt++) {
 447                 if (cnt % 8 == 0) {
 448                         qla_uprintf(&uiter, "\n");
 449                 }
 450                 qla_uprintf(&uiter, "%04x ", fw->risc_hdw_reg[cnt]);
 451         }
 452
 453         qla_uprintf(&uiter, "\n\nRISC GP0 Registers:");
 454         for (cnt = 0; cnt < sizeof (fw->risc_gp0_reg) / 2; cnt++) {
 455                 if (cnt % 8 == 0) {
 456                         qla_uprintf(&uiter, "\n");
 457                 }
 458                 qla_uprintf(&uiter, "%04x ", fw->risc_gp0_reg[cnt]);
 459         }
 460
 461         qla_uprintf(&uiter, "\n\nRISC GP1 Registers:");
 462         for (cnt = 0; cnt < sizeof (fw->risc_gp1_reg) / 2; cnt++) {
 463                 if (cnt % 8 == 0) {
 464                         qla_uprintf(&uiter, "\n");
 465                 }
 466                 qla_uprintf(&uiter, "%04x ", fw->risc_gp1_reg[cnt]);
 467         }
 468
 469         qla_uprintf(&uiter, "\n\nRISC GP2 Registers:");
 470         for (cnt = 0; cnt < sizeof (fw->risc_gp2_reg) / 2; cnt++) {
 471                 if (cnt % 8 == 0) {
 472                         qla_uprintf(&uiter, "\n");
 473                 }
 474                 qla_uprintf(&uiter, "%04x ", fw->risc_gp2_reg[cnt]);
 475         }
 476
 477         qla_uprintf(&uiter, "\n\nRISC GP3 Registers:");
 478         for (cnt = 0; cnt < sizeof (fw->risc_gp3_reg) / 2; cnt++) {
 479                 if (cnt % 8 == 0) {
 480                         qla_uprintf(&uiter, "\n");
 481                 }
 482                 qla_uprintf(&uiter, "%04x ", fw->risc_gp3_reg[cnt]);
 483         }
 484
 485         qla_uprintf(&uiter, "\n\nRISC GP4 Registers:");
 486         for (cnt = 0; cnt < sizeof (fw->risc_gp4_reg) / 2; cnt++) {
 487                 if (cnt % 8 == 0) {
 488                         qla_uprintf(&uiter, "\n");
 489                 }
 490                 qla_uprintf(&uiter, "%04x ", fw->risc_gp4_reg[cnt]);
 491         }
 492
 493         qla_uprintf(&uiter, "\n\nRISC GP5 Registers:");
 494         for (cnt = 0; cnt < sizeof (fw->risc_gp5_reg) / 2; cnt++) {
 495                 if (cnt % 8 == 0) {
 496                         qla_uprintf(&uiter, "\n");
 497                 }
 498                 qla_uprintf(&uiter, "%04x ", fw->risc_gp5_reg[cnt]);
 499         }
 500
 501         qla_uprintf(&uiter, "\n\nRISC GP6 Registers:");
 502         for (cnt = 0; cnt < sizeof (fw->risc_gp6_reg) / 2; cnt++) {
 503                 if (cnt % 8 == 0) {
 504                         qla_uprintf(&uiter, "\n");
 505                 }
 506                 qla_uprintf(&uiter, "%04x ", fw->risc_gp6_reg[cnt]);
 507         }
 508
 509         qla_uprintf(&uiter, "\n\nRISC GP7 Registers:");
 510         for (cnt = 0; cnt < sizeof (fw->risc_gp7_reg) / 2; cnt++) {
 511                 if (cnt % 8 == 0) {
 512                         qla_uprintf(&uiter, "\n");
 513                 }
 514                 qla_uprintf(&uiter, "%04x ", fw->risc_gp7_reg[cnt]);
 515         }
 516
 517         qla_uprintf(&uiter, "\n\nFrame Buffer Hardware Registers:");
 518         for (cnt = 0; cnt < sizeof (fw->frame_buf_hdw_reg) / 2; cnt++) {
 519                 if (cnt % 8 == 0) {
 520                         qla_uprintf(&uiter, "\n");
 521                 }
 522                 qla_uprintf(&uiter, "%04x ", fw->frame_buf_hdw_reg[cnt]);
 523         }
 524
 525         qla_uprintf(&uiter, "\n\nFPM B0 Registers:");
 526         for (cnt = 0; cnt < sizeof (fw->fpm_b0_reg) / 2; cnt++) {
 527                 if (cnt % 8 == 0) {
 528                         qla_uprintf(&uiter, "\n");
 529                 }
 530                 qla_uprintf(&uiter, "%04x ", fw->fpm_b0_reg[cnt]);
 531         }
 532
 533         qla_uprintf(&uiter, "\n\nFPM B1 Registers:");
 534         for (cnt = 0; cnt < sizeof (fw->fpm_b1_reg) / 2; cnt++) {
 535                 if (cnt % 8 == 0) {
 536                         qla_uprintf(&uiter, "\n");
 537                 }
 538                 qla_uprintf(&uiter, "%04x ", fw->fpm_b1_reg[cnt]);
 539         }
 540
 541         qla_uprintf(&uiter, "\n\nCode RAM Dump:");
 542         for (cnt = 0; cnt < sizeof (fw->risc_ram) / 2; cnt++) {
 543                 if (cnt % 8 == 0) {
 544                         qla_uprintf(&uiter, "\n%04x: ", cnt + 0x0800);
 545                 }
 546                 qla_uprintf(&uiter, "%04x ", fw->risc_ram[cnt]);
 547         }
 548
 549         qla_uprintf(&uiter, "\n\nStack RAM Dump:");
 550         for (cnt = 0; cnt < sizeof (fw->stack_ram) / 2; cnt++) {
 551                 if (cnt % 8 == 0) {
 552                         qla_uprintf(&uiter, "\n%05x: ", cnt + 0x10000);
 553                 }
 554                 qla_uprintf(&uiter, "%04x ", fw->stack_ram[cnt]);
 555         }
 556
 557         qla_uprintf(&uiter, "\n\nData RAM Dump:");
 558         data_ram_cnt = ha->fw_memory_size - 0x11000 + 1;
 559         for (cnt = 0; cnt < data_ram_cnt; cnt++) {
 560                 if (cnt % 8 == 0) {
 561                         qla_uprintf(&uiter, "\n%05x: ", cnt + 0x11000);
 562                 }
 563                 qla_uprintf(&uiter, "%04x ", fw->data_ram[cnt]);
 564         }
 565
 566         qla_uprintf(&uiter, "\n\n[<==END] ISP Debug Dump.");
 567 }
 568
 569 /**
 570  * qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware.
 571  * @ha: HA context
 572  * @hardware_locked: Called with the hardware_lock
 573  */
 574 void
 575 qla2100_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
 576 {
 577         int             rval;
 578         uint32_t        cnt, timer;
 579         uint16_t        risc_address;
 580         uint16_t        mb0, mb2;
 581
 582         device_reg_t    *reg;
 583         uint16_t        *dmp_reg;
 584         unsigned long   flags;
 585         struct qla2100_fw_dump  *fw;
 586
 587         reg = ha->iobase;
 588         risc_address = 0;
 589         mb0 = mb2 = 0;
 590         flags = 0;
 591
 592         if (!hardware_locked)
 593                 spin_lock_irqsave(&ha->hardware_lock, flags);
 594
 595         if (ha->fw_dump != NULL) {
 596                 qla_printk(KERN_WARNING, ha,
 597                     "Firmware has been previously dumped (%p) -- ignoring "
 598                     "request...\n", ha->fw_dump);
 599                 goto qla2100_fw_dump_failed;
 600         }
 601
 602         /* Allocate (large) dump buffer. */
 603         ha->fw_dump_order = get_order(sizeof(struct qla2100_fw_dump));
 604         ha->fw_dump = (struct qla2100_fw_dump *) __get_free_pages(GFP_ATOMIC,
 605             ha->fw_dump_order);
 606         if (ha->fw_dump == NULL) {
 607                 qla_printk(KERN_WARNING, ha,
 608                     "Unable to allocated memory for firmware dump (%d/%Zd).\n",
 609                     ha->fw_dump_order, sizeof(struct qla2100_fw_dump));
 610                 goto qla2100_fw_dump_failed;
 611         }
 612         fw = ha->fw_dump;
 613
 614         rval = QLA_SUCCESS;
 615         fw->hccr = RD_REG_WORD(&reg->hccr);
 616
 617         /* Pause RISC. */
 618         WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
 619         for (cnt = 30000; (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
 620             rval == QLA_SUCCESS; cnt--) {
 621                 if (cnt)
 622                         udelay(100);
 623                 else
 624                         rval = QLA_FUNCTION_TIMEOUT;
 625         }
 626         if (rval == QLA_SUCCESS) {
 627                 dmp_reg = (uint16_t *)(reg + 0);
 628                 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
 629                         fw->pbiu_reg[cnt] = RD_REG_WORD(dmp_reg++);
 630
 631                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x10);
 632                 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
 633                         if (cnt == 8) {
 634                                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0xe0);
 635                         }
 636                         fw->mailbox_reg[cnt] = RD_REG_WORD(dmp_reg++);
 637                 }
 638
 639                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x20);
 640                 for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
 641                         fw->dma_reg[cnt] = RD_REG_WORD(dmp_reg++);
 642
 643                 WRT_REG_WORD(&reg->ctrl_status, 0x00);
 644                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0xA0);
 645                 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
 646                         fw->risc_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++);
 647
 648                 WRT_REG_WORD(&reg->pcr, 0x2000);
 649                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 650                 for (cnt = 0; cnt < sizeof(fw->risc_gp0_reg) / 2; cnt++)
 651                         fw->risc_gp0_reg[cnt] = RD_REG_WORD(dmp_reg++);
 652
 653                 WRT_REG_WORD(&reg->pcr, 0x2100);
 654                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 655                 for (cnt = 0; cnt < sizeof(fw->risc_gp1_reg) / 2; cnt++)
 656                         fw->risc_gp1_reg[cnt] = RD_REG_WORD(dmp_reg++);
 657
 658                 WRT_REG_WORD(&reg->pcr, 0x2200);
 659                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 660                 for (cnt = 0; cnt < sizeof(fw->risc_gp2_reg) / 2; cnt++)
 661                         fw->risc_gp2_reg[cnt] = RD_REG_WORD(dmp_reg++);
 662
 663                 WRT_REG_WORD(&reg->pcr, 0x2300);
 664                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 665                 for (cnt = 0; cnt < sizeof(fw->risc_gp3_reg) / 2; cnt++)
 666                         fw->risc_gp3_reg[cnt] = RD_REG_WORD(dmp_reg++);
 667
 668                 WRT_REG_WORD(&reg->pcr, 0x2400);
 669                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 670                 for (cnt = 0; cnt < sizeof(fw->risc_gp4_reg) / 2; cnt++)
 671                         fw->risc_gp4_reg[cnt] = RD_REG_WORD(dmp_reg++);
 672
 673                 WRT_REG_WORD(&reg->pcr, 0x2500);
 674                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 675                 for (cnt = 0; cnt < sizeof(fw->risc_gp5_reg) / 2; cnt++)
 676                         fw->risc_gp5_reg[cnt] = RD_REG_WORD(dmp_reg++);
 677
 678                 WRT_REG_WORD(&reg->pcr, 0x2600);
 679                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 680                 for (cnt = 0; cnt < sizeof(fw->risc_gp6_reg) / 2; cnt++)
 681                         fw->risc_gp6_reg[cnt] = RD_REG_WORD(dmp_reg++);
 682
 683                 WRT_REG_WORD(&reg->pcr, 0x2700);
 684                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 685                 for (cnt = 0; cnt < sizeof(fw->risc_gp7_reg) / 2; cnt++)
 686                         fw->risc_gp7_reg[cnt] = RD_REG_WORD(dmp_reg++);
 687
 688                 WRT_REG_WORD(&reg->ctrl_status, 0x10);
 689                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 690                 for (cnt = 0; cnt < sizeof(fw->frame_buf_hdw_reg) / 2; cnt++)
 691                         fw->frame_buf_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++);
 692
 693                 WRT_REG_WORD(&reg->ctrl_status, 0x20);
 694                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 695                 for (cnt = 0; cnt < sizeof(fw->fpm_b0_reg) / 2; cnt++)
 696                         fw->fpm_b0_reg[cnt] = RD_REG_WORD(dmp_reg++);
 697
 698                 WRT_REG_WORD(&reg->ctrl_status, 0x30);
 699                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 700                 for (cnt = 0; cnt < sizeof(fw->fpm_b1_reg) / 2; cnt++)
 701                         fw->fpm_b1_reg[cnt] = RD_REG_WORD(dmp_reg++);
 702
 703                 /* Reset the ISP. */
 704                 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
 705         }
 706
 707         for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
 708             rval == QLA_SUCCESS; cnt--) {
 709                 if (cnt)
 710                         udelay(100);
 711                 else
 712                         rval = QLA_FUNCTION_TIMEOUT;
 713         }
 714
 715         /* Pause RISC. */
 716         if (rval == QLA_SUCCESS && (IS_QLA2200(ha) || (IS_QLA2100(ha) &&
 717             (RD_REG_WORD(&reg->mctr) & (BIT_1 | BIT_0)) != 0))) {
 718
 719                 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
 720                 for (cnt = 30000;
 721                     (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
 722                     rval == QLA_SUCCESS; cnt--) {
 723                         if (cnt)
 724                                 udelay(100);
 725                         else
 726                                 rval = QLA_FUNCTION_TIMEOUT;
 727                 }
 728                 if (rval == QLA_SUCCESS) {
 729                         /* Set memory configuration and timing. */
 730                         if (IS_QLA2100(ha))
 731                                 WRT_REG_WORD(&reg->mctr, 0xf1);
 732                         else
 733                                 WRT_REG_WORD(&reg->mctr, 0xf2);
 734
 735                         /* Release RISC. */
 736                         WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
 737                 }
 738         }
 739
 740         if (rval == QLA_SUCCESS) {
 741                 /* Get RISC SRAM. */
 742                 risc_address = 0x1000;
 743                 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD);
 744                 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
 745         }
 746         for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS;
 747             cnt++, risc_address++) {
 748                 WRT_MAILBOX_REG(ha, reg, 1, risc_address);
 749                 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
 750
 751                 for (timer = 6000000; timer != 0; timer--) {
 752                         /* Check for pending interrupts. */
 753                         if (RD_REG_WORD(&reg->istatus) & ISR_RISC_INT) {
 754                                 if (RD_REG_WORD(&reg->semaphore) & BIT_0) {
 755                                         set_bit(MBX_INTERRUPT,
 756                                             &ha->mbx_cmd_flags);
 757
 758                                         mb0 = RD_MAILBOX_REG(ha, reg, 0);
 759                                         mb2 = RD_MAILBOX_REG(ha, reg, 2);
 760
 761                                         WRT_REG_WORD(&reg->semaphore, 0);
 762                                         WRT_REG_WORD(&reg->hccr,
 763                                             HCCR_CLR_RISC_INT);
 764                                         break;
 765                                 }
 766                                 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
 767                         }
 768                         udelay(5);
 769                 }
 770
 771                 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
 772                         rval = mb0 & MBS_MASK;
 773                         fw->risc_ram[cnt] = mb2;
 774                 } else {
 775                         rval = QLA_FUNCTION_FAILED;
 776                 }
 777         }
 778
 779         if (rval != QLA_SUCCESS) {
 780                 qla_printk(KERN_WARNING, ha,
 781                     "Failed to dump firmware (%x)!!!\n", rval);
 782
 783                 free_pages((unsigned long)ha->fw_dump, ha->fw_dump_order);
 784                 ha->fw_dump = NULL;
 785         } else {
 786                 qla_printk(KERN_INFO, ha,
 787                     "Firmware dump saved to temp buffer (%ld/%p).\n",
 788                     ha->host_no, ha->fw_dump);
 789         }
 790
 791 qla2100_fw_dump_failed:
 792         if (!hardware_locked)
 793                 spin_unlock_irqrestore(&ha->hardware_lock, flags);
 794 }
 795
 796 /**
 797  * qla2100_ascii_fw_dump() - Converts a binary firmware dump to ASCII.
 798  * @ha: HA context
 799  */
 800 void
 801 qla2100_ascii_fw_dump(scsi_qla_host_t *ha)
 802 {
 803         uint32_t cnt;
 804         char *uiter;
 805         char fw_info[30];
 806         struct qla2100_fw_dump *fw;
 807
 808         uiter = ha->fw_dump_buffer;
 809         fw = ha->fw_dump;
 810
 811         qla_uprintf(&uiter, "%s Firmware Version %s\n", ha->model_number,
 812             qla2x00_get_fw_version_str(ha, fw_info));
 813
 814         qla_uprintf(&uiter, "\n[==>BEG]\n");
 815
 816         qla_uprintf(&uiter, "HCCR Register:\n%04x\n\n", fw->hccr);
 817
 818         qla_uprintf(&uiter, "PBIU Registers:");
 819         for (cnt = 0; cnt < sizeof (fw->pbiu_reg) / 2; cnt++) {
 820                 if (cnt % 8 == 0) {
 821                         qla_uprintf(&uiter, "\n");
 822                 }
 823                 qla_uprintf(&uiter, "%04x ", fw->pbiu_reg[cnt]);
 824         }
 825
 826         qla_uprintf(&uiter, "\n\nMailbox Registers:");
 827         for (cnt = 0; cnt < sizeof (fw->mailbox_reg) / 2; cnt++) {
 828                 if (cnt % 8 == 0) {
 829                         qla_uprintf(&uiter, "\n");
 830                 }
 831                 qla_uprintf(&uiter, "%04x ", fw->mailbox_reg[cnt]);
 832         }
 833
 834         qla_uprintf(&uiter, "\n\nDMA Registers:");
 835         for (cnt = 0; cnt < sizeof (fw->dma_reg) / 2; cnt++) {
 836                 if (cnt % 8 == 0) {
 837                         qla_uprintf(&uiter, "\n");
 838                 }
 839                 qla_uprintf(&uiter, "%04x ", fw->dma_reg[cnt]);
 840         }
 841
 842         qla_uprintf(&uiter, "\n\nRISC Hardware Registers:");
 843         for (cnt = 0; cnt < sizeof (fw->risc_hdw_reg) / 2; cnt++) {
 844                 if (cnt % 8 == 0) {
 845                         qla_uprintf(&uiter, "\n");
 846                 }
 847                 qla_uprintf(&uiter, "%04x ", fw->risc_hdw_reg[cnt]);
 848         }
 849
 850         qla_uprintf(&uiter, "\n\nRISC GP0 Registers:");
 851         for (cnt = 0; cnt < sizeof (fw->risc_gp0_reg) / 2; cnt++) {
 852                 if (cnt % 8 == 0) {
 853                         qla_uprintf(&uiter, "\n");
 854                 }
 855                 qla_uprintf(&uiter, "%04x ", fw->risc_gp0_reg[cnt]);
 856         }
 857
 858         qla_uprintf(&uiter, "\n\nRISC GP1 Registers:");
 859         for (cnt = 0; cnt < sizeof (fw->risc_gp1_reg) / 2; cnt++) {
 860                 if (cnt % 8 == 0) {
 861                         qla_uprintf(&uiter, "\n");
 862                 }
 863                 qla_uprintf(&uiter, "%04x ", fw->risc_gp1_reg[cnt]);
 864         }
 865
 866         qla_uprintf(&uiter, "\n\nRISC GP2 Registers:");
 867         for (cnt = 0; cnt < sizeof (fw->risc_gp2_reg) / 2; cnt++) {
 868                 if (cnt % 8 == 0) {
 869                         qla_uprintf(&uiter, "\n");
 870                 }
 871                 qla_uprintf(&uiter, "%04x ", fw->risc_gp2_reg[cnt]);
 872         }
 873
 874         qla_uprintf(&uiter, "\n\nRISC GP3 Registers:");
 875         for (cnt = 0; cnt < sizeof (fw->risc_gp3_reg) / 2; cnt++) {
 876                 if (cnt % 8 == 0) {
 877                         qla_uprintf(&uiter, "\n");
 878                 }
 879                 qla_uprintf(&uiter, "%04x ", fw->risc_gp3_reg[cnt]);
 880         }
 881
 882         qla_uprintf(&uiter, "\n\nRISC GP4 Registers:");
 883         for (cnt = 0; cnt < sizeof (fw->risc_gp4_reg) / 2; cnt++) {
 884                 if (cnt % 8 == 0) {
 885                         qla_uprintf(&uiter, "\n");
 886                 }
 887                 qla_uprintf(&uiter, "%04x ", fw->risc_gp4_reg[cnt]);
 888         }
 889
 890         qla_uprintf(&uiter, "\n\nRISC GP5 Registers:");
 891         for (cnt = 0; cnt < sizeof (fw->risc_gp5_reg) / 2; cnt++) {
 892                 if (cnt % 8 == 0) {
 893                         qla_uprintf(&uiter, "\n");
 894                 }
 895                 qla_uprintf(&uiter, "%04x ", fw->risc_gp5_reg[cnt]);
 896         }
 897
 898         qla_uprintf(&uiter, "\n\nRISC GP6 Registers:");
 899         for (cnt = 0; cnt < sizeof (fw->risc_gp6_reg) / 2; cnt++) {
 900                 if (cnt % 8 == 0) {
 901                         qla_uprintf(&uiter, "\n");
 902                 }
 903                 qla_uprintf(&uiter, "%04x ", fw->risc_gp6_reg[cnt]);
 904         }
 905
 906         qla_uprintf(&uiter, "\n\nRISC GP7 Registers:");
 907         for (cnt = 0; cnt < sizeof (fw->risc_gp7_reg) / 2; cnt++) {
 908                 if (cnt % 8 == 0) {
 909                         qla_uprintf(&uiter, "\n");
 910                 }
 911                 qla_uprintf(&uiter, "%04x ", fw->risc_gp7_reg[cnt]);
 912         }
 913
 914         qla_uprintf(&uiter, "\n\nFrame Buffer Hardware Registers:");
 915         for (cnt = 0; cnt < sizeof (fw->frame_buf_hdw_reg) / 2; cnt++) {
 916                 if (cnt % 8 == 0) {
 917                         qla_uprintf(&uiter, "\n");
 918                 }
 919                 qla_uprintf(&uiter, "%04x ", fw->frame_buf_hdw_reg[cnt]);
 920         }
 921
 922         qla_uprintf(&uiter, "\n\nFPM B0 Registers:");
 923         for (cnt = 0; cnt < sizeof (fw->fpm_b0_reg) / 2; cnt++) {
 924                 if (cnt % 8 == 0) {
 925                         qla_uprintf(&uiter, "\n");
 926                 }
 927                 qla_uprintf(&uiter, "%04x ", fw->fpm_b0_reg[cnt]);
 928         }
 929
 930         qla_uprintf(&uiter, "\n\nFPM B1 Registers:");
 931         for (cnt = 0; cnt < sizeof (fw->fpm_b1_reg) / 2; cnt++) {
 932                 if (cnt % 8 == 0) {
 933                         qla_uprintf(&uiter, "\n");
 934                 }
 935                 qla_uprintf(&uiter, "%04x ", fw->fpm_b1_reg[cnt]);
 936         }
 937
 938         qla_uprintf(&uiter, "\n\nRISC SRAM:");
 939         for (cnt = 0; cnt < sizeof (fw->risc_ram) / 2; cnt++) {
 940                 if (cnt % 8 == 0) {
 941                         qla_uprintf(&uiter, "\n%04x: ", cnt + 0x1000);
 942                 }
 943                 qla_uprintf(&uiter, "%04x ", fw->risc_ram[cnt]);
 944         }
 945
 946         qla_uprintf(&uiter, "\n\n[<==END] ISP Debug Dump.");
 947
 948         return;
 949 }
 950
 951 static int
 952 qla_uprintf(char **uiter, char *fmt, ...)
 953 {
 954         int     iter, len;
 955         char    buf[128];
 956         va_list args;
 957
 958         va_start(args, fmt);
 959         len = vsprintf(buf, fmt, args);
 960         va_end(args);
 961
 962         for (iter = 0; iter < len; iter++, *uiter += 1)
 963                 *uiter[0] = buf[iter];
 964
 965         return (len);
 966 }
 967
 968 //FIXME
 969
 970 /****************************************************************************/
 971 /*                         Driver Debug Functions.                          */
 972 /****************************************************************************/
 973
 974 void
 975 qla2x00_dump_regs(scsi_qla_host_t *ha)
 976 {
 977         device_reg_t    *reg;
 978
 979         reg = ha->iobase;
 980
 981         printk("Mailbox registers:\n");
 982         printk("scsi(%ld): mbox 0 0x%04x \n",
 983             ha->host_no, RD_MAILBOX_REG(ha, reg, 0));
 984         printk("scsi(%ld): mbox 1 0x%04x \n",
 985             ha->host_no, RD_MAILBOX_REG(ha, reg, 1));
 986         printk("scsi(%ld): mbox 2 0x%04x \n",
 987             ha->host_no, RD_MAILBOX_REG(ha, reg, 2));
 988         printk("scsi(%ld): mbox 3 0x%04x \n",
 989             ha->host_no, RD_MAILBOX_REG(ha, reg, 3));
 990         printk("scsi(%ld): mbox 4 0x%04x \n",
 991             ha->host_no, RD_MAILBOX_REG(ha, reg, 4));
 992         printk("scsi(%ld): mbox 5 0x%04x \n",
 993             ha->host_no, RD_MAILBOX_REG(ha, reg, 5));
 994 }
 995
 996
 997 void
 998 qla2x00_dump_buffer(uint8_t * b, uint32_t size)
 999 {
1000         uint32_t cnt;
1001         uint8_t c;
1002
1003         printk(" 0   1   2   3   4   5   6   7   8   9  "
1004             "Ah  Bh  Ch  Dh  Eh  Fh\n");
1005         printk("----------------------------------------"
1006             "----------------------\n");
1007
1008         for (cnt = 0; cnt < size;) {
1009                 c = *b++;
1010                 printk("%02x",(uint32_t) c);
1011                 cnt++;
1012                 if (!(cnt % 16))
1013                         printk("\n");
1014                 else
1015                         printk("  ");
1016         }
1017         if (cnt % 16)
1018                 printk("\n");
1019 }
1020
1021 /**************************************************************************
1022  *   qla2x00_print_scsi_cmd
1023  *       Dumps out info about the scsi cmd and srb.
1024  *   Input
1025  *       cmd : struct scsi_cmnd
1026  **************************************************************************/
1027 void
1028 qla2x00_print_scsi_cmd(struct scsi_cmnd * cmd)
1029 {
1030         int i;
1031         struct scsi_qla_host *ha;
1032         srb_t *sp;
1033
1034         ha = (struct scsi_qla_host *)cmd->device->host->hostdata;
1035
1036         sp = (srb_t *) cmd->SCp.ptr;
1037         printk("SCSI Command @=0x%p, Handle=0x%p\n", cmd, cmd->host_scribble);
1038         printk("  chan=0x%02x, target=0x%02x, lun=0x%02x, cmd_len=0x%02x\n",
1039             cmd->device->channel, cmd->device->id, cmd->device->lun,
1040             cmd->cmd_len);
1041         printk(" CDB: ");
1042         for (i = 0; i < cmd->cmd_len; i++) {
1043                 printk("0x%02x ", cmd->cmnd[i]);
1044         }
1045         printk("\n  seg_cnt=%d, allowed=%d, retries=%d, "
1046             "serial_number_at_timeout=0x%lx\n",
1047             cmd->use_sg, cmd->allowed, cmd->retries,
1048             cmd->serial_number_at_timeout);
1049         printk("  request buffer=0x%p, request buffer len=0x%x\n",
1050             cmd->request_buffer, cmd->request_bufflen);
1051         printk("  tag=%d, transfersize=0x%x\n",
1052             cmd->tag, cmd->transfersize);
1053         printk("  serial_number=%lx, SP=%p\n", cmd->serial_number, sp);
1054         printk("  data direction=%d\n", cmd->sc_data_direction);
1055
1056         if (!sp)
1057                 return;
1058
1059         printk("  sp flags=0x%x\n", sp->flags);
1060         printk("  r_start=0x%lx, u_start=0x%lx, f_start=0x%lx, state=%d\n",
1061             sp->r_start, sp->u_start, sp->f_start, sp->state);
1062
1063         printk(" e_start= 0x%lx, ext_history=%d, fo retry=%d, loopid=%x, "
1064             "port path=%d\n", sp->e_start, sp->ext_history, sp->fo_retry_cnt,
1065             sp->lun_queue->fclun->fcport->loop_id,
1066             sp->lun_queue->fclun->fcport->cur_path);
1067 }
1068
1069 #if defined(QL_DEBUG_ROUTINES)
1070 /*
1071  * qla2x00_formatted_dump_buffer
1072  *       Prints string plus buffer.
1073  *
1074  * Input:
1075  *       string  = Null terminated string (no newline at end).
1076  *       buffer  = buffer address.
1077  *       wd_size = word size 8, 16, 32 or 64 bits
1078  *       count   = number of words.
1079  */
1080 void
1081 qla2x00_formatted_dump_buffer(char *string, uint8_t * buffer,
1082                                 uint8_t wd_size, uint32_t count)
1083 {
1084         uint32_t cnt;
1085         uint16_t *buf16;
1086         uint32_t *buf32;
1087
1088         if (strcmp(string, "") != 0)
1089                 printk("%s\n",string);
1090
1091         switch (wd_size) {
1092                 case 8:
1093                         printk(" 0    1    2    3    4    5    6    7    "
1094                                 "8    9    Ah   Bh   Ch   Dh   Eh   Fh\n");
1095                         printk("-----------------------------------------"
1096                                 "-------------------------------------\n");
1097
1098                         for (cnt = 1; cnt <= count; cnt++, buffer++) {
1099                                 printk("%02x",*buffer);
1100                                 if (cnt % 16 == 0)
1101                                         printk("\n");
1102                                 else
1103                                         printk("  ");
1104                         }
1105                         if (cnt % 16 != 0)
1106                                 printk("\n");
1107                         break;
1108                 case 16:
1109                         printk("   0      2      4      6      8      Ah "
1110                                 "       Ch     Eh\n");
1111                         printk("-----------------------------------------"
1112                                 "-------------\n");
1113
1114                         buf16 = (uint16_t *) buffer;
1115                         for (cnt = 1; cnt <= count; cnt++, buf16++) {
1116                                 printk("%4x",*buf16);
1117
1118                                 if (cnt % 8 == 0)
1119                                         printk("\n");
1120                                 else if (*buf16 < 10)
1121                                         printk("   ");
1122                                 else
1123                                         printk("  ");
1124                         }
1125                         if (cnt % 8 != 0)
1126                                 printk("\n");
1127                         break;
1128                 case 32:
1129                         printk("       0          4          8          Ch\n");
1130                         printk("------------------------------------------\n");
1131
1132                         buf32 = (uint32_t *) buffer;
1133                         for (cnt = 1; cnt <= count; cnt++, buf32++) {
1134                                 printk("%8x", *buf32);
1135
1136                                 if (cnt % 4 == 0)
1137                                         printk("\n");
1138                                 else if (*buf32 < 10)
1139                                         printk("   ");
1140                                 else
1141                                         printk("  ");
1142                         }
1143                         if (cnt % 4 != 0)
1144                                 printk("\n");
1145                         break;
1146                 default:
1147                         break;
1148         }
1149 }
1150 #endif