drivers/scsi/qla2xxx/qla_dbg.c

   1 /*
   2  *                  QLOGIC LINUX SOFTWARE
   3  *
   4  * QLogic ISP2x00 device driver for Linux 2.6.x
   5  * Copyright (C) 2003-2004 QLogic Corporation
   6  * (www.qlogic.com)
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of the GNU General Public License as published by the
  10  * Free Software Foundation; either version 2, or (at your option) any
  11  * later version.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  */
  19 #include "qla_os.h"
  20
  21 #include "qla_def.h"
  22
  23 static int qla_uprintf(char **, char *, ...);
  24
  25 /**
  26  * qla2300_fw_dump() - Dumps binary data from the 2300 firmware.
  27  * @ha: HA context
  28  * @hardware_locked: Called with the hardware_lock
  29  */
  30 void
  31 qla2300_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
  32 {
  33         int             rval;
  34         uint32_t        cnt, timer;
  35         uint32_t        risc_address;
  36         uint16_t        mb0, mb2;
  37
  38         uint32_t        stat;
  39         device_reg_t    *reg;
  40         uint16_t        *dmp_reg;
  41         unsigned long   flags;
  42         struct qla2300_fw_dump  *fw;
  43
  44         reg = ha->iobase;
  45         risc_address = 0;
  46         mb0 = mb2 = 0;
  47         flags = 0;
  48
  49         if (!hardware_locked)
  50                 spin_lock_irqsave(&ha->hardware_lock, flags);
  51
  52         if (ha->fw_dump != NULL) {
  53                 qla_printk(KERN_WARNING, ha,
  54                     "Firmware has been previously dumped (%p) -- ignoring "
  55                     "request...\n", ha->fw_dump);
  56                 goto qla2300_fw_dump_failed;
  57         }
  58
  59         /* Allocate (large) dump buffer. */
  60         ha->fw_dump_order = get_order(sizeof(struct qla2300_fw_dump));
  61         ha->fw_dump = (struct qla2300_fw_dump *) __get_free_pages(GFP_ATOMIC,
  62             ha->fw_dump_order);
  63         if (ha->fw_dump == NULL) {
  64                 qla_printk(KERN_WARNING, ha,
  65                     "Unable to allocated memory for firmware dump (%d/%Zd).\n",
  66                     ha->fw_dump_order, sizeof(struct qla2300_fw_dump));
  67                 goto qla2300_fw_dump_failed;
  68         }
  69         fw = ha->fw_dump;
  70
  71         rval = QLA_SUCCESS;
  72         fw->hccr = RD_REG_WORD(&reg->hccr);
  73
  74         /* Pause RISC. */
  75         WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
  76         if (IS_QLA2300(ha)) {
  77                 for (cnt = 30000;
  78                     (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
  79                         rval == QLA_SUCCESS; cnt--) {
  80                         if (cnt)
  81                                 udelay(100);
  82                         else
  83                                 rval = QLA_FUNCTION_TIMEOUT;
  84                 }
  85         } else {
  86                 udelay(10);
  87         }
  88
  89         if (rval == QLA_SUCCESS) {
  90                 dmp_reg = (uint16_t *)(reg + 0);
  91                 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
  92                         fw->pbiu_reg[cnt] = RD_REG_WORD(dmp_reg++);
  93
  94                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x10);
  95                 for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++)
  96                         fw->risc_host_reg[cnt] = RD_REG_WORD(dmp_reg++);
  97
  98                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x40);
  99                 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
 100                         fw->mailbox_reg[cnt] = RD_REG_WORD(dmp_reg++);
 101
 102                 WRT_REG_WORD(&reg->ctrl_status, 0x40);
 103                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 104                 for (cnt = 0; cnt < sizeof(fw->resp_dma_reg) / 2; cnt++)
 105                         fw->resp_dma_reg[cnt] = RD_REG_WORD(dmp_reg++);
 106
 107                 WRT_REG_WORD(&reg->ctrl_status, 0x50);
 108                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 109                 for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
 110                         fw->dma_reg[cnt] = RD_REG_WORD(dmp_reg++);
 111
 112                 WRT_REG_WORD(&reg->ctrl_status, 0x00);
 113                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0xA0);
 114                 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
 115                         fw->risc_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++);
 116
 117                 WRT_REG_WORD(&reg->pcr, 0x2000);
 118                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 119                 for (cnt = 0; cnt < sizeof(fw->risc_gp0_reg) / 2; cnt++)
 120                         fw->risc_gp0_reg[cnt] = RD_REG_WORD(dmp_reg++);
 121
 122                 WRT_REG_WORD(&reg->pcr, 0x2200);
 123                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 124                 for (cnt = 0; cnt < sizeof(fw->risc_gp1_reg) / 2; cnt++)
 125                         fw->risc_gp1_reg[cnt] = RD_REG_WORD(dmp_reg++);
 126
 127                 WRT_REG_WORD(&reg->pcr, 0x2400);
 128                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 129                 for (cnt = 0; cnt < sizeof(fw->risc_gp2_reg) / 2; cnt++)
 130                         fw->risc_gp2_reg[cnt] = RD_REG_WORD(dmp_reg++);
 131
 132                 WRT_REG_WORD(&reg->pcr, 0x2600);
 133                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 134                 for (cnt = 0; cnt < sizeof(fw->risc_gp3_reg) / 2; cnt++)
 135                         fw->risc_gp3_reg[cnt] = RD_REG_WORD(dmp_reg++);
 136
 137                 WRT_REG_WORD(&reg->pcr, 0x2800);
 138                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 139                 for (cnt = 0; cnt < sizeof(fw->risc_gp4_reg) / 2; cnt++)
 140                         fw->risc_gp4_reg[cnt] = RD_REG_WORD(dmp_reg++);
 141
 142                 WRT_REG_WORD(&reg->pcr, 0x2A00);
 143                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 144                 for (cnt = 0; cnt < sizeof(fw->risc_gp5_reg) / 2; cnt++)
 145                         fw->risc_gp5_reg[cnt] = RD_REG_WORD(dmp_reg++);
 146
 147                 WRT_REG_WORD(&reg->pcr, 0x2C00);
 148                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 149                 for (cnt = 0; cnt < sizeof(fw->risc_gp6_reg) / 2; cnt++)
 150                         fw->risc_gp6_reg[cnt] = RD_REG_WORD(dmp_reg++);
 151
 152                 WRT_REG_WORD(&reg->pcr, 0x2E00);
 153                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 154                 for (cnt = 0; cnt < sizeof(fw->risc_gp7_reg) / 2; cnt++)
 155                         fw->risc_gp7_reg[cnt] = RD_REG_WORD(dmp_reg++);
 156
 157                 WRT_REG_WORD(&reg->ctrl_status, 0x10);
 158                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 159                 for (cnt = 0; cnt < sizeof(fw->frame_buf_hdw_reg) / 2; cnt++)
 160                         fw->frame_buf_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++);
 161
 162                 WRT_REG_WORD(&reg->ctrl_status, 0x20);
 163                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 164                 for (cnt = 0; cnt < sizeof(fw->fpm_b0_reg) / 2; cnt++)
 165                         fw->fpm_b0_reg[cnt] = RD_REG_WORD(dmp_reg++);
 166
 167                 WRT_REG_WORD(&reg->ctrl_status, 0x30);
 168                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 169                 for (cnt = 0; cnt < sizeof(fw->fpm_b1_reg) / 2; cnt++)
 170                         fw->fpm_b1_reg[cnt] = RD_REG_WORD(dmp_reg++);
 171
 172                 /* Reset RISC. */
 173                 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
 174                 for (cnt = 0; cnt < 30000; cnt++) {
 175                         if ((RD_REG_WORD(&reg->ctrl_status) &
 176                             CSR_ISP_SOFT_RESET) == 0)
 177                                 break;
 178
 179                         udelay(10);
 180                 }
 181         }
 182
 183         if (!IS_QLA2300(ha)) {
 184                 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
 185                     rval == QLA_SUCCESS; cnt--) {
 186                         if (cnt)
 187                                 udelay(100);
 188                         else
 189                                 rval = QLA_FUNCTION_TIMEOUT;
 190                 }
 191         }
 192
 193         if (rval == QLA_SUCCESS) {
 194                 /* Get RISC SRAM. */
 195                 risc_address = 0x800;
 196                 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD);
 197                 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
 198         }
 199         for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS;
 200             cnt++, risc_address++) {
 201                 WRT_MAILBOX_REG(ha, reg, 1, (uint16_t)risc_address);
 202                 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
 203
 204                 for (timer = 6000000; timer; timer--) {
 205                         /* Check for pending interrupts. */
 206                         stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
 207                         if (stat & HSR_RISC_INT) {
 208                                 stat &= 0xff;
 209
 210                                 if (stat == 0x1 || stat == 0x2) {
 211                                         set_bit(MBX_INTERRUPT,
 212                                             &ha->mbx_cmd_flags);
 213
 214                                         mb0 = RD_MAILBOX_REG(ha, reg, 0);
 215                                         mb2 = RD_MAILBOX_REG(ha, reg, 2);
 216
 217                                         /* Release mailbox registers. */
 218                                         WRT_REG_WORD(&reg->semaphore, 0);
 219                                         WRT_REG_WORD(&reg->hccr,
 220                                             HCCR_CLR_RISC_INT);
 221                                         break;
 222                                 } else if (stat == 0x10 || stat == 0x11) {
 223                                         set_bit(MBX_INTERRUPT,
 224                                             &ha->mbx_cmd_flags);
 225
 226                                         mb0 = RD_MAILBOX_REG(ha, reg, 0);
 227                                         mb2 = RD_MAILBOX_REG(ha, reg, 2);
 228
 229                                         WRT_REG_WORD(&reg->hccr,
 230                                             HCCR_CLR_RISC_INT);
 231                                         break;
 232                                 }
 233
 234                                 /* clear this intr; it wasn't a mailbox intr */
 235                                 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
 236                         }
 237                         udelay(5);
 238                 }
 239
 240                 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
 241                         rval = mb0 & MBS_MASK;
 242                         fw->risc_ram[cnt] = mb2;
 243                 } else {
 244                         rval = QLA_FUNCTION_FAILED;
 245                 }
 246         }
 247
 248         if (rval == QLA_SUCCESS) {
 249                 /* Get stack SRAM. */
 250                 risc_address = 0x10000;
 251                 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_EXTENDED);
 252                 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
 253         }
 254         for (cnt = 0; cnt < sizeof(fw->stack_ram) / 2 && rval == QLA_SUCCESS;
 255             cnt++, risc_address++) {
 256                 WRT_MAILBOX_REG(ha, reg, 1, LSW(risc_address));
 257                 WRT_MAILBOX_REG(ha, reg, 8, MSW(risc_address));
 258                 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
 259
 260                 for (timer = 6000000; timer; timer--) {
 261                         /* Check for pending interrupts. */
 262                         stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
 263                         if (stat & HSR_RISC_INT) {
 264                                 stat &= 0xff;
 265
 266                                 if (stat == 0x1 || stat == 0x2) {
 267                                         set_bit(MBX_INTERRUPT,
 268                                             &ha->mbx_cmd_flags);
 269
 270                                         mb0 = RD_MAILBOX_REG(ha, reg, 0);
 271                                         mb2 = RD_MAILBOX_REG(ha, reg, 2);
 272
 273                                         /* Release mailbox registers. */
 274                                         WRT_REG_WORD(&reg->semaphore, 0);
 275                                         WRT_REG_WORD(&reg->hccr,
 276                                             HCCR_CLR_RISC_INT);
 277                                         break;
 278                                 } else if (stat == 0x10 || stat == 0x11) {
 279                                         set_bit(MBX_INTERRUPT,
 280                                             &ha->mbx_cmd_flags);
 281
 282                                         mb0 = RD_MAILBOX_REG(ha, reg, 0);
 283                                         mb2 = RD_MAILBOX_REG(ha, reg, 2);
 284
 285                                         WRT_REG_WORD(&reg->hccr,
 286                                             HCCR_CLR_RISC_INT);
 287                                         break;
 288                                 }
 289
 290                                 /* clear this intr; it wasn't a mailbox intr */
 291                                 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
 292                         }
 293                         udelay(5);
 294                 }
 295
 296                 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
 297                         rval = mb0 & MBS_MASK;
 298                         fw->stack_ram[cnt] = mb2;
 299                 } else {
 300                         rval = QLA_FUNCTION_FAILED;
 301                 }
 302         }
 303
 304         if (rval == QLA_SUCCESS) {
 305                 /* Get data SRAM. */
 306                 risc_address = 0x11000;
 307                 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_EXTENDED);
 308                 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
 309         }
 310         for (cnt = 0; cnt < sizeof(fw->data_ram) / 2 && rval == QLA_SUCCESS;
 311             cnt++, risc_address++) {
 312                 WRT_MAILBOX_REG(ha, reg, 1, LSW(risc_address));
 313                 WRT_MAILBOX_REG(ha, reg, 8, MSW(risc_address));
 314                 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
 315
 316                 for (timer = 6000000; timer; timer--) {
 317                         /* Check for pending interrupts. */
 318                         stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
 319                         if (stat & HSR_RISC_INT) {
 320                                 stat &= 0xff;
 321
 322                                 if (stat == 0x1 || stat == 0x2) {
 323                                         set_bit(MBX_INTERRUPT,
 324                                             &ha->mbx_cmd_flags);
 325
 326                                         mb0 = RD_MAILBOX_REG(ha, reg, 0);
 327                                         mb2 = RD_MAILBOX_REG(ha, reg, 2);
 328
 329                                         /* Release mailbox registers. */
 330                                         WRT_REG_WORD(&reg->semaphore, 0);
 331                                         WRT_REG_WORD(&reg->hccr,
 332                                             HCCR_CLR_RISC_INT);
 333                                         break;
 334                                 } else if (stat == 0x10 || stat == 0x11) {
 335                                         set_bit(MBX_INTERRUPT,
 336                                             &ha->mbx_cmd_flags);
 337
 338                                         mb0 = RD_MAILBOX_REG(ha, reg, 0);
 339                                         mb2 = RD_MAILBOX_REG(ha, reg, 2);
 340
 341                                         WRT_REG_WORD(&reg->hccr,
 342                                             HCCR_CLR_RISC_INT);
 343                                         break;
 344                                 }
 345
 346                                 /* clear this intr; it wasn't a mailbox intr */
 347                                 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
 348                         }
 349                         udelay(5);
 350                 }
 351
 352                 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
 353                         rval = mb0 & MBS_MASK;
 354                         fw->data_ram[cnt] = mb2;
 355                 } else {
 356                         rval = QLA_FUNCTION_FAILED;
 357                 }
 358         }
 359
 360
 361         if (rval != QLA_SUCCESS) {
 362                 qla_printk(KERN_WARNING, ha,
 363                     "Failed to dump firmware (%x)!!!\n", rval);
 364
 365                 free_pages((unsigned long)ha->fw_dump, ha->fw_dump_order);
 366                 ha->fw_dump = NULL;
 367         } else {
 368                 qla_printk(KERN_INFO, ha,
 369                     "Firmware dump saved to temp buffer (%ld/%p).\n",
 370                     ha->host_no, ha->fw_dump);
 371         }
 372
 373 qla2300_fw_dump_failed:
 374         if (!hardware_locked)
 375                 spin_unlock_irqrestore(&ha->hardware_lock, flags);
 376 }
 377
 378 /**
 379  * qla2300_ascii_fw_dump() - Converts a binary firmware dump to ASCII.
 380  * @ha: HA context
 381  */
 382 void
 383 qla2300_ascii_fw_dump(scsi_qla_host_t *ha)
 384 {
 385         uint32_t cnt;
 386         char *uiter;
 387         char fw_info[30];
 388         struct qla2300_fw_dump *fw;
 389
 390         uiter = ha->fw_dump_buffer;
 391         fw = ha->fw_dump;
 392
 393         qla_uprintf(&uiter, "%s Firmware Version %s\n", ha->model_number,
 394             qla2x00_get_fw_version_str(ha, fw_info));
 395
 396         qla_uprintf(&uiter, "\n[==>BEG]\n");
 397
 398         qla_uprintf(&uiter, "HCCR Register:\n%04x\n\n", fw->hccr);
 399
 400         qla_uprintf(&uiter, "PBIU Registers:");
 401         for (cnt = 0; cnt < sizeof (fw->pbiu_reg) / 2; cnt++) {
 402                 if (cnt % 8 == 0) {
 403                         qla_uprintf(&uiter, "\n");
 404                 }
 405                 qla_uprintf(&uiter, "%04x ", fw->pbiu_reg[cnt]);
 406         }
 407
 408         qla_uprintf(&uiter, "\n\nReqQ-RspQ-Risc2Host Status registers:");
 409         for (cnt = 0; cnt < sizeof (fw->risc_host_reg) / 2; cnt++) {
 410                 if (cnt % 8 == 0) {
 411                         qla_uprintf(&uiter, "\n");
 412                 }
 413                 qla_uprintf(&uiter, "%04x ", fw->risc_host_reg[cnt]);
 414         }
 415
 416         qla_uprintf(&uiter, "\n\nMailbox Registers:");
 417         for (cnt = 0; cnt < sizeof (fw->mailbox_reg) / 2; cnt++) {
 418                 if (cnt % 8 == 0) {
 419                         qla_uprintf(&uiter, "\n");
 420                 }
 421                 qla_uprintf(&uiter, "%04x ", fw->mailbox_reg[cnt]);
 422         }
 423
 424         qla_uprintf(&uiter, "\n\nAuto Request Response DMA Registers:");
 425         for (cnt = 0; cnt < sizeof (fw->resp_dma_reg) / 2; cnt++) {
 426                 if (cnt % 8 == 0) {
 427                         qla_uprintf(&uiter, "\n");
 428                 }
 429                 qla_uprintf(&uiter, "%04x ", fw->resp_dma_reg[cnt]);
 430         }
 431
 432         qla_uprintf(&uiter, "\n\nDMA Registers:");
 433         for (cnt = 0; cnt < sizeof (fw->dma_reg) / 2; cnt++) {
 434                 if (cnt % 8 == 0) {
 435                         qla_uprintf(&uiter, "\n");
 436                 }
 437                 qla_uprintf(&uiter, "%04x ", fw->dma_reg[cnt]);
 438         }
 439
 440         qla_uprintf(&uiter, "\n\nRISC Hardware Registers:");
 441         for (cnt = 0; cnt < sizeof (fw->risc_hdw_reg) / 2; cnt++) {
 442                 if (cnt % 8 == 0) {
 443                         qla_uprintf(&uiter, "\n");
 444                 }
 445                 qla_uprintf(&uiter, "%04x ", fw->risc_hdw_reg[cnt]);
 446         }
 447
 448         qla_uprintf(&uiter, "\n\nRISC GP0 Registers:");
 449         for (cnt = 0; cnt < sizeof (fw->risc_gp0_reg) / 2; cnt++) {
 450                 if (cnt % 8 == 0) {
 451                         qla_uprintf(&uiter, "\n");
 452                 }
 453                 qla_uprintf(&uiter, "%04x ", fw->risc_gp0_reg[cnt]);
 454         }
 455
 456         qla_uprintf(&uiter, "\n\nRISC GP1 Registers:");
 457         for (cnt = 0; cnt < sizeof (fw->risc_gp1_reg) / 2; cnt++) {
 458                 if (cnt % 8 == 0) {
 459                         qla_uprintf(&uiter, "\n");
 460                 }
 461                 qla_uprintf(&uiter, "%04x ", fw->risc_gp1_reg[cnt]);
 462         }
 463
 464         qla_uprintf(&uiter, "\n\nRISC GP2 Registers:");
 465         for (cnt = 0; cnt < sizeof (fw->risc_gp2_reg) / 2; cnt++) {
 466                 if (cnt % 8 == 0) {
 467                         qla_uprintf(&uiter, "\n");
 468                 }
 469                 qla_uprintf(&uiter, "%04x ", fw->risc_gp2_reg[cnt]);
 470         }
 471
 472         qla_uprintf(&uiter, "\n\nRISC GP3 Registers:");
 473         for (cnt = 0; cnt < sizeof (fw->risc_gp3_reg) / 2; cnt++) {
 474                 if (cnt % 8 == 0) {
 475                         qla_uprintf(&uiter, "\n");
 476                 }
 477                 qla_uprintf(&uiter, "%04x ", fw->risc_gp3_reg[cnt]);
 478         }
 479
 480         qla_uprintf(&uiter, "\n\nRISC GP4 Registers:");
 481         for (cnt = 0; cnt < sizeof (fw->risc_gp4_reg) / 2; cnt++) {
 482                 if (cnt % 8 == 0) {
 483                         qla_uprintf(&uiter, "\n");
 484                 }
 485                 qla_uprintf(&uiter, "%04x ", fw->risc_gp4_reg[cnt]);
 486         }
 487
 488         qla_uprintf(&uiter, "\n\nRISC GP5 Registers:");
 489         for (cnt = 0; cnt < sizeof (fw->risc_gp5_reg) / 2; cnt++) {
 490                 if (cnt % 8 == 0) {
 491                         qla_uprintf(&uiter, "\n");
 492                 }
 493                 qla_uprintf(&uiter, "%04x ", fw->risc_gp5_reg[cnt]);
 494         }
 495
 496         qla_uprintf(&uiter, "\n\nRISC GP6 Registers:");
 497         for (cnt = 0; cnt < sizeof (fw->risc_gp6_reg) / 2; cnt++) {
 498                 if (cnt % 8 == 0) {
 499                         qla_uprintf(&uiter, "\n");
 500                 }
 501                 qla_uprintf(&uiter, "%04x ", fw->risc_gp6_reg[cnt]);
 502         }
 503
 504         qla_uprintf(&uiter, "\n\nRISC GP7 Registers:");
 505         for (cnt = 0; cnt < sizeof (fw->risc_gp7_reg) / 2; cnt++) {
 506                 if (cnt % 8 == 0) {
 507                         qla_uprintf(&uiter, "\n");
 508                 }
 509                 qla_uprintf(&uiter, "%04x ", fw->risc_gp7_reg[cnt]);
 510         }
 511
 512         qla_uprintf(&uiter, "\n\nFrame Buffer Hardware Registers:");
 513         for (cnt = 0; cnt < sizeof (fw->frame_buf_hdw_reg) / 2; cnt++) {
 514                 if (cnt % 8 == 0) {
 515                         qla_uprintf(&uiter, "\n");
 516                 }
 517                 qla_uprintf(&uiter, "%04x ", fw->frame_buf_hdw_reg[cnt]);
 518         }
 519
 520         qla_uprintf(&uiter, "\n\nFPM B0 Registers:");
 521         for (cnt = 0; cnt < sizeof (fw->fpm_b0_reg) / 2; cnt++) {
 522                 if (cnt % 8 == 0) {
 523                         qla_uprintf(&uiter, "\n");
 524                 }
 525                 qla_uprintf(&uiter, "%04x ", fw->fpm_b0_reg[cnt]);
 526         }
 527
 528         qla_uprintf(&uiter, "\n\nFPM B1 Registers:");
 529         for (cnt = 0; cnt < sizeof (fw->fpm_b1_reg) / 2; cnt++) {
 530                 if (cnt % 8 == 0) {
 531                         qla_uprintf(&uiter, "\n");
 532                 }
 533                 qla_uprintf(&uiter, "%04x ", fw->fpm_b1_reg[cnt]);
 534         }
 535
 536         qla_uprintf(&uiter, "\n\nCode RAM Dump:");
 537         for (cnt = 0; cnt < sizeof (fw->risc_ram) / 2; cnt++) {
 538                 if (cnt % 8 == 0) {
 539                         qla_uprintf(&uiter, "\n%04x: ", cnt + 0x0800);
 540                 }
 541                 qla_uprintf(&uiter, "%04x ", fw->risc_ram[cnt]);
 542         }
 543
 544         qla_uprintf(&uiter, "\n\nStack RAM Dump:");
 545         for (cnt = 0; cnt < sizeof (fw->stack_ram) / 2; cnt++) {
 546                 if (cnt % 8 == 0) {
 547                         qla_uprintf(&uiter, "\n%05x: ", cnt + 0x10000);
 548                 }
 549                 qla_uprintf(&uiter, "%04x ", fw->stack_ram[cnt]);
 550         }
 551
 552         qla_uprintf(&uiter, "\n\nData RAM Dump:");
 553         for (cnt = 0; cnt < sizeof (fw->data_ram) / 2; cnt++) {
 554                 if (cnt % 8 == 0) {
 555                         qla_uprintf(&uiter, "\n%05x: ", cnt + 0x11000);
 556                 }
 557                 qla_uprintf(&uiter, "%04x ", fw->data_ram[cnt]);
 558         }
 559
 560         qla_uprintf(&uiter, "\n\n[<==END] ISP Debug Dump.");
 561 }
 562
 563 /**
 564  * qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware.
 565  * @ha: HA context
 566  * @hardware_locked: Called with the hardware_lock
 567  */
 568 void
 569 qla2100_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
 570 {
 571         int             rval;
 572         uint32_t        cnt, timer;
 573         uint16_t        risc_address;
 574         uint16_t        mb0, mb2;
 575
 576         device_reg_t    *reg;
 577         uint16_t        *dmp_reg;
 578         unsigned long   flags;
 579         struct qla2100_fw_dump  *fw;
 580
 581         reg = ha->iobase;
 582         risc_address = 0;
 583         mb0 = mb2 = 0;
 584         flags = 0;
 585
 586         if (!hardware_locked)
 587                 spin_lock_irqsave(&ha->hardware_lock, flags);
 588
 589         if (ha->fw_dump != NULL) {
 590                 qla_printk(KERN_WARNING, ha,
 591                     "Firmware has been previously dumped (%p) -- ignoring "
 592                     "request...\n", ha->fw_dump);
 593                 goto qla2100_fw_dump_failed;
 594         }
 595
 596         /* Allocate (large) dump buffer. */
 597         ha->fw_dump_order = get_order(sizeof(struct qla2100_fw_dump));
 598         ha->fw_dump = (struct qla2100_fw_dump *) __get_free_pages(GFP_ATOMIC,
 599             ha->fw_dump_order);
 600         if (ha->fw_dump == NULL) {
 601                 qla_printk(KERN_WARNING, ha,
 602                     "Unable to allocated memory for firmware dump (%d/%Zd).\n",
 603                     ha->fw_dump_order, sizeof(struct qla2100_fw_dump));
 604                 goto qla2100_fw_dump_failed;
 605         }
 606         fw = ha->fw_dump;
 607
 608         rval = QLA_SUCCESS;
 609         fw->hccr = RD_REG_WORD(&reg->hccr);
 610
 611         /* Pause RISC. */
 612         WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
 613         for (cnt = 30000; (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
 614             rval == QLA_SUCCESS; cnt--) {
 615                 if (cnt)
 616                         udelay(100);
 617                 else
 618                         rval = QLA_FUNCTION_TIMEOUT;
 619         }
 620         if (rval == QLA_SUCCESS) {
 621                 dmp_reg = (uint16_t *)(reg + 0);
 622                 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
 623                         fw->pbiu_reg[cnt] = RD_REG_WORD(dmp_reg++);
 624
 625                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x10);
 626                 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
 627                         if (cnt == 8) {
 628                                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0xe0);
 629                         }
 630                         fw->mailbox_reg[cnt] = RD_REG_WORD(dmp_reg++);
 631                 }
 632
 633                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x20);
 634                 for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
 635                         fw->dma_reg[cnt] = RD_REG_WORD(dmp_reg++);
 636
 637                 WRT_REG_WORD(&reg->ctrl_status, 0x00);
 638                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0xA0);
 639                 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
 640                         fw->risc_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++);
 641
 642                 WRT_REG_WORD(&reg->pcr, 0x2000);
 643                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 644                 for (cnt = 0; cnt < sizeof(fw->risc_gp0_reg) / 2; cnt++)
 645                         fw->risc_gp0_reg[cnt] = RD_REG_WORD(dmp_reg++);
 646
 647                 WRT_REG_WORD(&reg->pcr, 0x2100);
 648                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 649                 for (cnt = 0; cnt < sizeof(fw->risc_gp1_reg) / 2; cnt++)
 650                         fw->risc_gp1_reg[cnt] = RD_REG_WORD(dmp_reg++);
 651
 652                 WRT_REG_WORD(&reg->pcr, 0x2200);
 653                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 654                 for (cnt = 0; cnt < sizeof(fw->risc_gp2_reg) / 2; cnt++)
 655                         fw->risc_gp2_reg[cnt] = RD_REG_WORD(dmp_reg++);
 656
 657                 WRT_REG_WORD(&reg->pcr, 0x2300);
 658                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 659                 for (cnt = 0; cnt < sizeof(fw->risc_gp3_reg) / 2; cnt++)
 660                         fw->risc_gp3_reg[cnt] = RD_REG_WORD(dmp_reg++);
 661
 662                 WRT_REG_WORD(&reg->pcr, 0x2400);
 663                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 664                 for (cnt = 0; cnt < sizeof(fw->risc_gp4_reg) / 2; cnt++)
 665                         fw->risc_gp4_reg[cnt] = RD_REG_WORD(dmp_reg++);
 666
 667                 WRT_REG_WORD(&reg->pcr, 0x2500);
 668                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 669                 for (cnt = 0; cnt < sizeof(fw->risc_gp5_reg) / 2; cnt++)
 670                         fw->risc_gp5_reg[cnt] = RD_REG_WORD(dmp_reg++);
 671
 672                 WRT_REG_WORD(&reg->pcr, 0x2600);
 673                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 674                 for (cnt = 0; cnt < sizeof(fw->risc_gp6_reg) / 2; cnt++)
 675                         fw->risc_gp6_reg[cnt] = RD_REG_WORD(dmp_reg++);
 676
 677                 WRT_REG_WORD(&reg->pcr, 0x2700);
 678                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 679                 for (cnt = 0; cnt < sizeof(fw->risc_gp7_reg) / 2; cnt++)
 680                         fw->risc_gp7_reg[cnt] = RD_REG_WORD(dmp_reg++);
 681
 682                 WRT_REG_WORD(&reg->ctrl_status, 0x10);
 683                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 684                 for (cnt = 0; cnt < sizeof(fw->frame_buf_hdw_reg) / 2; cnt++)
 685                         fw->frame_buf_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++);
 686
 687                 WRT_REG_WORD(&reg->ctrl_status, 0x20);
 688                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 689                 for (cnt = 0; cnt < sizeof(fw->fpm_b0_reg) / 2; cnt++)
 690                         fw->fpm_b0_reg[cnt] = RD_REG_WORD(dmp_reg++);
 691
 692                 WRT_REG_WORD(&reg->ctrl_status, 0x30);
 693                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 694                 for (cnt = 0; cnt < sizeof(fw->fpm_b1_reg) / 2; cnt++)
 695                         fw->fpm_b1_reg[cnt] = RD_REG_WORD(dmp_reg++);
 696
 697                 /* Reset the ISP. */
 698                 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
 699         }
 700
 701         for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
 702             rval == QLA_SUCCESS; cnt--) {
 703                 if (cnt)
 704                         udelay(100);
 705                 else
 706                         rval = QLA_FUNCTION_TIMEOUT;
 707         }
 708
 709         /* Pause RISC. */
 710         if (rval == QLA_SUCCESS && (IS_QLA2200(ha) || (IS_QLA2100(ha) &&
 711             (RD_REG_WORD(&reg->mctr) & (BIT_1 | BIT_0)) != 0))) {
 712
 713                 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
 714                 for (cnt = 30000;
 715                     (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
 716                     rval == QLA_SUCCESS; cnt--) {
 717                         if (cnt)
 718                                 udelay(100);
 719                         else
 720                                 rval = QLA_FUNCTION_TIMEOUT;
 721                 }
 722                 if (rval == QLA_SUCCESS) {
 723                         /* Set memory configuration and timing. */
 724                         if (IS_QLA2100(ha))
 725                                 WRT_REG_WORD(&reg->mctr, 0xf1);
 726                         else
 727                                 WRT_REG_WORD(&reg->mctr, 0xf2);
 728
 729                         /* Release RISC. */
 730                         WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
 731                 }
 732         }
 733
 734         if (rval == QLA_SUCCESS) {
 735                 /* Get RISC SRAM. */
 736                 risc_address = 0x1000;
 737                 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD);
 738                 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
 739         }
 740         for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS;
 741             cnt++, risc_address++) {
 742                 WRT_MAILBOX_REG(ha, reg, 1, risc_address);
 743                 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
 744
 745                 for (timer = 6000000; timer != 0; timer--) {
 746                         /* Check for pending interrupts. */
 747                         if (RD_REG_WORD(&reg->istatus) & ISR_RISC_INT) {
 748                                 if (RD_REG_WORD(&reg->semaphore) & BIT_0) {
 749                                         set_bit(MBX_INTERRUPT,
 750                                             &ha->mbx_cmd_flags);
 751
 752                                         mb0 = RD_MAILBOX_REG(ha, reg, 0);
 753                                         mb2 = RD_MAILBOX_REG(ha, reg, 2);
 754
 755                                         WRT_REG_WORD(&reg->semaphore, 0);
 756                                         WRT_REG_WORD(&reg->hccr,
 757                                             HCCR_CLR_RISC_INT);
 758                                         break;
 759                                 }
 760                                 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
 761                         }
 762                         udelay(5);
 763                 }
 764
 765                 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
 766                         rval = mb0 & MBS_MASK;
 767                         fw->risc_ram[cnt] = mb2;
 768                 } else {
 769                         rval = QLA_FUNCTION_FAILED;
 770                 }
 771         }
 772
 773         if (rval != QLA_SUCCESS) {
 774                 qla_printk(KERN_WARNING, ha,
 775                     "Failed to dump firmware (%x)!!!\n", rval);
 776
 777                 free_pages((unsigned long)ha->fw_dump, ha->fw_dump_order);
 778                 ha->fw_dump = NULL;
 779         } else {
 780                 qla_printk(KERN_INFO, ha,
 781                     "Firmware dump saved to temp buffer (%ld/%p).\n",
 782                     ha->host_no, ha->fw_dump);
 783         }
 784
 785 qla2100_fw_dump_failed:
 786         if (!hardware_locked)
 787                 spin_unlock_irqrestore(&ha->hardware_lock, flags);
 788 }
 789
 790 /**
 791  * qla2100_ascii_fw_dump() - Converts a binary firmware dump to ASCII.
 792  * @ha: HA context
 793  */
 794 void
 795 qla2100_ascii_fw_dump(scsi_qla_host_t *ha)
 796 {
 797         uint32_t cnt;
 798         char *uiter;
 799         char fw_info[30];
 800         struct qla2100_fw_dump *fw;
 801
 802         uiter = ha->fw_dump_buffer;
 803         fw = ha->fw_dump;
 804
 805         qla_uprintf(&uiter, "%s Firmware Version %s\n", ha->model_number,
 806             qla2x00_get_fw_version_str(ha, fw_info));
 807
 808         qla_uprintf(&uiter, "\n[==>BEG]\n");
 809
 810         qla_uprintf(&uiter, "HCCR Register:\n%04x\n\n", fw->hccr);
 811
 812         qla_uprintf(&uiter, "PBIU Registers:");
 813         for (cnt = 0; cnt < sizeof (fw->pbiu_reg) / 2; cnt++) {
 814                 if (cnt % 8 == 0) {
 815                         qla_uprintf(&uiter, "\n");
 816                 }
 817                 qla_uprintf(&uiter, "%04x ", fw->pbiu_reg[cnt]);
 818         }
 819
 820         qla_uprintf(&uiter, "\n\nMailbox Registers:");
 821         for (cnt = 0; cnt < sizeof (fw->mailbox_reg) / 2; cnt++) {
 822                 if (cnt % 8 == 0) {
 823                         qla_uprintf(&uiter, "\n");
 824                 }
 825                 qla_uprintf(&uiter, "%04x ", fw->mailbox_reg[cnt]);
 826         }
 827
 828         qla_uprintf(&uiter, "\n\nDMA Registers:");
 829         for (cnt = 0; cnt < sizeof (fw->dma_reg) / 2; cnt++) {
 830                 if (cnt % 8 == 0) {
 831                         qla_uprintf(&uiter, "\n");
 832                 }
 833                 qla_uprintf(&uiter, "%04x ", fw->dma_reg[cnt]);
 834         }
 835
 836         qla_uprintf(&uiter, "\n\nRISC Hardware Registers:");
 837         for (cnt = 0; cnt < sizeof (fw->risc_hdw_reg) / 2; cnt++) {
 838                 if (cnt % 8 == 0) {
 839                         qla_uprintf(&uiter, "\n");
 840                 }
 841                 qla_uprintf(&uiter, "%04x ", fw->risc_hdw_reg[cnt]);
 842         }
 843
 844         qla_uprintf(&uiter, "\n\nRISC GP0 Registers:");
 845         for (cnt = 0; cnt < sizeof (fw->risc_gp0_reg) / 2; cnt++) {
 846                 if (cnt % 8 == 0) {
 847                         qla_uprintf(&uiter, "\n");
 848                 }
 849                 qla_uprintf(&uiter, "%04x ", fw->risc_gp0_reg[cnt]);
 850         }
 851
 852         qla_uprintf(&uiter, "\n\nRISC GP1 Registers:");
 853         for (cnt = 0; cnt < sizeof (fw->risc_gp1_reg) / 2; cnt++) {
 854                 if (cnt % 8 == 0) {
 855                         qla_uprintf(&uiter, "\n");
 856                 }
 857                 qla_uprintf(&uiter, "%04x ", fw->risc_gp1_reg[cnt]);
 858         }
 859
 860         qla_uprintf(&uiter, "\n\nRISC GP2 Registers:");
 861         for (cnt = 0; cnt < sizeof (fw->risc_gp2_reg) / 2; cnt++) {
 862                 if (cnt % 8 == 0) {
 863                         qla_uprintf(&uiter, "\n");
 864                 }
 865                 qla_uprintf(&uiter, "%04x ", fw->risc_gp2_reg[cnt]);
 866         }
 867
 868         qla_uprintf(&uiter, "\n\nRISC GP3 Registers:");
 869         for (cnt = 0; cnt < sizeof (fw->risc_gp3_reg) / 2; cnt++) {
 870                 if (cnt % 8 == 0) {
 871                         qla_uprintf(&uiter, "\n");
 872                 }
 873                 qla_uprintf(&uiter, "%04x ", fw->risc_gp3_reg[cnt]);
 874         }
 875
 876         qla_uprintf(&uiter, "\n\nRISC GP4 Registers:");
 877         for (cnt = 0; cnt < sizeof (fw->risc_gp4_reg) / 2; cnt++) {
 878                 if (cnt % 8 == 0) {
 879                         qla_uprintf(&uiter, "\n");
 880                 }
 881                 qla_uprintf(&uiter, "%04x ", fw->risc_gp4_reg[cnt]);
 882         }
 883
 884         qla_uprintf(&uiter, "\n\nRISC GP5 Registers:");
 885         for (cnt = 0; cnt < sizeof (fw->risc_gp5_reg) / 2; cnt++) {
 886                 if (cnt % 8 == 0) {
 887                         qla_uprintf(&uiter, "\n");
 888                 }
 889                 qla_uprintf(&uiter, "%04x ", fw->risc_gp5_reg[cnt]);
 890         }
 891
 892         qla_uprintf(&uiter, "\n\nRISC GP6 Registers:");
 893         for (cnt = 0; cnt < sizeof (fw->risc_gp6_reg) / 2; cnt++) {
 894                 if (cnt % 8 == 0) {
 895                         qla_uprintf(&uiter, "\n");
 896                 }
 897                 qla_uprintf(&uiter, "%04x ", fw->risc_gp6_reg[cnt]);
 898         }
 899
 900         qla_uprintf(&uiter, "\n\nRISC GP7 Registers:");
 901         for (cnt = 0; cnt < sizeof (fw->risc_gp7_reg) / 2; cnt++) {
 902                 if (cnt % 8 == 0) {
 903                         qla_uprintf(&uiter, "\n");
 904                 }
 905                 qla_uprintf(&uiter, "%04x ", fw->risc_gp7_reg[cnt]);
 906         }
 907
 908         qla_uprintf(&uiter, "\n\nFrame Buffer Hardware Registers:");
 909         for (cnt = 0; cnt < sizeof (fw->frame_buf_hdw_reg) / 2; cnt++) {
 910                 if (cnt % 8 == 0) {
 911                         qla_uprintf(&uiter, "\n");
 912                 }
 913                 qla_uprintf(&uiter, "%04x ", fw->frame_buf_hdw_reg[cnt]);
 914         }
 915
 916         qla_uprintf(&uiter, "\n\nFPM B0 Registers:");
 917         for (cnt = 0; cnt < sizeof (fw->fpm_b0_reg) / 2; cnt++) {
 918                 if (cnt % 8 == 0) {
 919                         qla_uprintf(&uiter, "\n");
 920                 }
 921                 qla_uprintf(&uiter, "%04x ", fw->fpm_b0_reg[cnt]);
 922         }
 923
 924         qla_uprintf(&uiter, "\n\nFPM B1 Registers:");
 925         for (cnt = 0; cnt < sizeof (fw->fpm_b1_reg) / 2; cnt++) {
 926                 if (cnt % 8 == 0) {
 927                         qla_uprintf(&uiter, "\n");
 928                 }
 929                 qla_uprintf(&uiter, "%04x ", fw->fpm_b1_reg[cnt]);
 930         }
 931
 932         qla_uprintf(&uiter, "\n\nRISC SRAM:");
 933         for (cnt = 0; cnt < sizeof (fw->risc_ram) / 2; cnt++) {
 934                 if (cnt % 8 == 0) {
 935                         qla_uprintf(&uiter, "\n%04x: ", cnt + 0x1000);
 936                 }
 937                 qla_uprintf(&uiter, "%04x ", fw->risc_ram[cnt]);
 938         }
 939
 940         qla_uprintf(&uiter, "\n\n[<==END] ISP Debug Dump.");
 941
 942         return;
 943 }
 944
 945 static int
 946 qla_uprintf(char **uiter, char *fmt, ...)
 947 {
 948         int     iter, len;
 949         char    buf[128];
 950         va_list args;
 951
 952         va_start(args, fmt);
 953         len = vsprintf(buf, fmt, args);
 954         va_end(args);
 955
 956         for (iter = 0; iter < len; iter++, *uiter += 1)
 957                 *uiter[0] = buf[iter];
 958
 959         return (len);
 960 }
 961
 962 //FIXME
 963
 964 /****************************************************************************/
 965 /*                         Driver Debug Functions.                          */
 966 /****************************************************************************/
 967
 968 void
 969 qla2x00_dump_regs(scsi_qla_host_t *ha)
 970 {
 971         device_reg_t    *reg;
 972
 973         reg = ha->iobase;
 974
 975         printk("Mailbox registers:\n");
 976         printk("scsi(%ld): mbox 0 0x%04x \n",
 977             ha->host_no, RD_MAILBOX_REG(ha, reg, 0));
 978         printk("scsi(%ld): mbox 1 0x%04x \n",
 979             ha->host_no, RD_MAILBOX_REG(ha, reg, 1));
 980         printk("scsi(%ld): mbox 2 0x%04x \n",
 981             ha->host_no, RD_MAILBOX_REG(ha, reg, 2));
 982         printk("scsi(%ld): mbox 3 0x%04x \n",
 983             ha->host_no, RD_MAILBOX_REG(ha, reg, 3));
 984         printk("scsi(%ld): mbox 4 0x%04x \n",
 985             ha->host_no, RD_MAILBOX_REG(ha, reg, 4));
 986         printk("scsi(%ld): mbox 5 0x%04x \n",
 987             ha->host_no, RD_MAILBOX_REG(ha, reg, 5));
 988 }
 989
 990
 991 void
 992 qla2x00_dump_buffer(uint8_t * b, uint32_t size)
 993 {
 994         uint32_t cnt;
 995         uint8_t c;
 996
 997         printk(" 0   1   2   3   4   5   6   7   8   9  "
 998             "Ah  Bh  Ch  Dh  Eh  Fh\n");
 999         printk("----------------------------------------"
1000             "----------------------\n");
1001
1002         for (cnt = 0; cnt < size;) {
1003                 c = *b++;
1004                 printk("%02x",(uint32_t) c);
1005                 cnt++;
1006                 if (!(cnt % 16))
1007                         printk("\n");
1008                 else
1009                         printk("  ");
1010         }
1011         if (cnt % 16)
1012                 printk("\n");
1013 }
1014
1015 /**************************************************************************
1016  *   qla2x00_print_scsi_cmd
1017  *       Dumps out info about the scsi cmd and srb.
1018  *   Input
1019  *       cmd : struct scsi_cmnd
1020  **************************************************************************/
1021 void
1022 qla2x00_print_scsi_cmd(struct scsi_cmnd * cmd)
1023 {
1024         int i;
1025         struct scsi_qla_host *ha;
1026         srb_t *sp;
1027
1028         ha = (struct scsi_qla_host *)cmd->device->host->hostdata;
1029
1030         sp = (srb_t *) cmd->SCp.ptr;
1031         printk("SCSI Command @=0x%p, Handle=0x%p\n", cmd, cmd->host_scribble);
1032         printk("  chan=0x%02x, target=0x%02x, lun=0x%02x, cmd_len=0x%02x\n",
1033             cmd->device->channel, cmd->device->id, cmd->device->lun,
1034             cmd->cmd_len);
1035         printk(" CDB: ");
1036         for (i = 0; i < cmd->cmd_len; i++) {
1037                 printk("0x%02x ", cmd->cmnd[i]);
1038         }
1039         printk("\n  seg_cnt=%d, allowed=%d, retries=%d, "
1040             "serial_number_at_timeout=0x%lx\n",
1041             cmd->use_sg, cmd->allowed, cmd->retries,
1042             cmd->serial_number_at_timeout);
1043         printk("  request buffer=0x%p, request buffer len=0x%x\n",
1044             cmd->request_buffer, cmd->request_bufflen);
1045         printk("  tag=%d, transfersize=0x%x\n",
1046             cmd->tag, cmd->transfersize);
1047         printk("  serial_number=%lx, SP=%p\n", cmd->serial_number, sp);
1048         printk("  data direction=%d\n", cmd->sc_data_direction);
1049
1050         if (!sp)
1051                 return;
1052
1053         printk("  sp flags=0x%x\n", sp->flags);
1054         printk("  r_start=0x%lx, u_start=0x%lx, f_start=0x%lx, state=%d\n",
1055             sp->r_start, sp->u_start, sp->f_start, sp->state);
1056
1057         printk(" e_start= 0x%lx, ext_history=%d, fo retry=%d, loopid=%x, "
1058             "port path=%d\n", sp->e_start, sp->ext_history, sp->fo_retry_cnt,
1059             sp->lun_queue->fclun->fcport->loop_id,
1060             sp->lun_queue->fclun->fcport->cur_path);
1061 }
1062
1063 #if defined(QL_DEBUG_ROUTINES)
1064 /*
1065  * qla2x00_formatted_dump_buffer
1066  *       Prints string plus buffer.
1067  *
1068  * Input:
1069  *       string  = Null terminated string (no newline at end).
1070  *       buffer  = buffer address.
1071  *       wd_size = word size 8, 16, 32 or 64 bits
1072  *       count   = number of words.
1073  */
1074 void
1075 qla2x00_formatted_dump_buffer(char *string, uint8_t * buffer,
1076                                 uint8_t wd_size, uint32_t count)
1077 {
1078         uint32_t cnt;
1079         uint16_t *buf16;
1080         uint32_t *buf32;
1081
1082         if (strcmp(string, "") != 0)
1083                 printk("%s\n",string);
1084
1085         switch (wd_size) {
1086                 case 8:
1087                         printk(" 0    1    2    3    4    5    6    7    "
1088                                 "8    9    Ah   Bh   Ch   Dh   Eh   Fh\n");
1089                         printk("-----------------------------------------"
1090                                 "-------------------------------------\n");
1091
1092                         for (cnt = 1; cnt <= count; cnt++, buffer++) {
1093                                 printk("%02x",*buffer);
1094                                 if (cnt % 16 == 0)
1095                                         printk("\n");
1096                                 else
1097                                         printk("  ");
1098                         }
1099                         if (cnt % 16 != 0)
1100                                 printk("\n");
1101                         break;
1102                 case 16:
1103                         printk("   0      2      4      6      8      Ah "
1104                                 "       Ch     Eh\n");
1105                         printk("-----------------------------------------"
1106                                 "-------------\n");
1107
1108                         buf16 = (uint16_t *) buffer;
1109                         for (cnt = 1; cnt <= count; cnt++, buf16++) {
1110                                 printk("%4x",*buf16);
1111
1112                                 if (cnt % 8 == 0)
1113                                         printk("\n");
1114                                 else if (*buf16 < 10)
1115                                         printk("   ");
1116                                 else
1117                                         printk("  ");
1118                         }
1119                         if (cnt % 8 != 0)
1120                                 printk("\n");
1121                         break;
1122                 case 32:
1123                         printk("       0          4          8          Ch\n");
1124                         printk("------------------------------------------\n");
1125
1126                         buf32 = (uint32_t *) buffer;
1127                         for (cnt = 1; cnt <= count; cnt++, buf32++) {
1128                                 printk("%8x", *buf32);
1129
1130                                 if (cnt % 4 == 0)
1131                                         printk("\n");
1132                                 else if (*buf32 < 10)
1133                                         printk("   ");
1134                                 else
1135                                         printk("  ");
1136                         }
1137                         if (cnt % 4 != 0)
1138                                 printk("\n");
1139                         break;
1140                 default:
1141                         break;
1142         }
1143 }
1144 #endif