drivers/scsi/qla2xxx/qla_dbg.c

   1 /*
   2  *                  QLOGIC LINUX SOFTWARE
   3  *
   4  * QLogic ISP2x00 device driver for Linux 2.6.x
   5  * Copyright (C) 2003-2004 QLogic Corporation
   6  * (www.qlogic.com)
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of the GNU General Public License as published by the
  10  * Free Software Foundation; either version 2, or (at your option) any
  11  * later version.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  */
  19 #include "qla_os.h"
  20
  21 #include "qla_def.h"
  22
  23 static int qla_uprintf(char **, char *, ...);
  24
  25 /**
  26  * qla2300_fw_dump() - Dumps binary data from the 2300 firmware.
  27  * @ha: HA context
  28  * @hardware_locked: Called with the hardware_lock
  29  */
  30 void
  31 qla2300_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
  32 {
  33         int             rval;
  34         uint32_t        cnt, timer;
  35         uint32_t        risc_address;
  36         uint16_t        mb0, mb2;
  37
  38         uint32_t        stat;
  39         device_reg_t    *reg;
  40         uint16_t        *dmp_reg;
  41         unsigned long   flags;
  42         struct qla2300_fw_dump  *fw;
  43
  44         reg = ha->iobase;
  45         risc_address = 0;
  46         mb0 = mb2 = 0;
  47         flags = 0;
  48
  49         if (!hardware_locked)
  50                 spin_lock_irqsave(&ha->hardware_lock, flags);
  51
  52         if (ha->fw_dump != NULL) {
  53                 qla_printk(KERN_WARNING, ha,
  54                     "Firmware has been previously dumped (%p) -- ignoring "
  55                     "request...\n", ha->fw_dump);
  56                 return;
  57         }
  58
  59         /* Allocate (large) dump buffer. */
  60         ha->fw_dump_order = get_order(sizeof(struct qla2300_fw_dump));
  61         ha->fw_dump = (struct qla2300_fw_dump *) __get_free_pages(GFP_ATOMIC,
  62             ha->fw_dump_order);
  63         if (ha->fw_dump == NULL) {
  64                 qla_printk(KERN_WARNING, ha,
  65                     "Unable to allocated memory for firmware dump (%d/%Zd).\n",
  66                     ha->fw_dump_order, sizeof(struct qla2300_fw_dump));
  67                 return;
  68         }
  69         fw = ha->fw_dump;
  70
  71         rval = QLA_SUCCESS;
  72         fw->hccr = RD_REG_WORD(&reg->hccr);
  73
  74         /* Pause RISC. */
  75         WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
  76         if (IS_QLA2300(ha)) {
  77                 for (cnt = 30000;
  78                     (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
  79                         rval == QLA_SUCCESS; cnt--) {
  80                         if (cnt)
  81                                 udelay(100);
  82                         else
  83                                 rval = QLA_FUNCTION_TIMEOUT;
  84                 }
  85         } else {
  86                 udelay(10);
  87         }
  88
  89         if (rval == QLA_SUCCESS) {
  90                 dmp_reg = (uint16_t *)(reg + 0);
  91                 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
  92                         fw->pbiu_reg[cnt] = RD_REG_WORD(dmp_reg++);
  93
  94                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x10);
  95                 for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++)
  96                         fw->risc_host_reg[cnt] = RD_REG_WORD(dmp_reg++);
  97
  98                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x40);
  99                 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
 100                         fw->mailbox_reg[cnt] = RD_REG_WORD(dmp_reg++);
 101
 102                 WRT_REG_WORD(&reg->ctrl_status, 0x40);
 103                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 104                 for (cnt = 0; cnt < sizeof(fw->resp_dma_reg) / 2; cnt++)
 105                         fw->resp_dma_reg[cnt] = RD_REG_WORD(dmp_reg++);
 106
 107                 WRT_REG_WORD(&reg->ctrl_status, 0x50);
 108                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 109                 for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
 110                         fw->dma_reg[cnt] = RD_REG_WORD(dmp_reg++);
 111
 112                 WRT_REG_WORD(&reg->ctrl_status, 0x00);
 113                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0xA0);
 114                 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
 115                         fw->risc_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++);
 116
 117                 WRT_REG_WORD(&reg->pcr, 0x2000);
 118                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 119                 for (cnt = 0; cnt < sizeof(fw->risc_gp0_reg) / 2; cnt++)
 120                         fw->risc_gp0_reg[cnt] = RD_REG_WORD(dmp_reg++);
 121
 122                 WRT_REG_WORD(&reg->pcr, 0x2200);
 123                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 124                 for (cnt = 0; cnt < sizeof(fw->risc_gp1_reg) / 2; cnt++)
 125                         fw->risc_gp1_reg[cnt] = RD_REG_WORD(dmp_reg++);
 126
 127                 WRT_REG_WORD(&reg->pcr, 0x2400);
 128                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 129                 for (cnt = 0; cnt < sizeof(fw->risc_gp2_reg) / 2; cnt++)
 130                         fw->risc_gp2_reg[cnt] = RD_REG_WORD(dmp_reg++);
 131
 132                 WRT_REG_WORD(&reg->pcr, 0x2600);
 133                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 134                 for (cnt = 0; cnt < sizeof(fw->risc_gp3_reg) / 2; cnt++)
 135                         fw->risc_gp3_reg[cnt] = RD_REG_WORD(dmp_reg++);
 136
 137                 WRT_REG_WORD(&reg->pcr, 0x2800);
 138                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 139                 for (cnt = 0; cnt < sizeof(fw->risc_gp4_reg) / 2; cnt++)
 140                         fw->risc_gp4_reg[cnt] = RD_REG_WORD(dmp_reg++);
 141
 142                 WRT_REG_WORD(&reg->pcr, 0x2A00);
 143                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 144                 for (cnt = 0; cnt < sizeof(fw->risc_gp5_reg) / 2; cnt++)
 145                         fw->risc_gp5_reg[cnt] = RD_REG_WORD(dmp_reg++);
 146
 147                 WRT_REG_WORD(&reg->pcr, 0x2C00);
 148                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 149                 for (cnt = 0; cnt < sizeof(fw->risc_gp6_reg) / 2; cnt++)
 150                         fw->risc_gp6_reg[cnt] = RD_REG_WORD(dmp_reg++);
 151
 152                 WRT_REG_WORD(&reg->pcr, 0x2E00);
 153                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 154                 for (cnt = 0; cnt < sizeof(fw->risc_gp7_reg) / 2; cnt++)
 155                         fw->risc_gp7_reg[cnt] = RD_REG_WORD(dmp_reg++);
 156
 157                 WRT_REG_WORD(&reg->ctrl_status, 0x10);
 158                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 159                 for (cnt = 0; cnt < sizeof(fw->frame_buf_hdw_reg) / 2; cnt++)
 160                         fw->frame_buf_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++);
 161
 162                 WRT_REG_WORD(&reg->ctrl_status, 0x20);
 163                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 164                 for (cnt = 0; cnt < sizeof(fw->fpm_b0_reg) / 2; cnt++)
 165                         fw->fpm_b0_reg[cnt] = RD_REG_WORD(dmp_reg++);
 166
 167                 WRT_REG_WORD(&reg->ctrl_status, 0x30);
 168                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 169                 for (cnt = 0; cnt < sizeof(fw->fpm_b1_reg) / 2; cnt++)
 170                         fw->fpm_b1_reg[cnt] = RD_REG_WORD(dmp_reg++);
 171
 172                 /* Reset RISC. */
 173                 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
 174                 for (cnt = 0; cnt < 30000; cnt++) {
 175                         if ((RD_REG_WORD(&reg->ctrl_status) &
 176                             CSR_ISP_SOFT_RESET) == 0)
 177                                 break;
 178
 179                         udelay(10);
 180                 }
 181         }
 182
 183         if (!IS_QLA2300(ha)) {
 184                 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
 185                     rval == QLA_SUCCESS; cnt--) {
 186                         if (cnt)
 187                                 udelay(100);
 188                         else
 189                                 rval = QLA_FUNCTION_TIMEOUT;
 190                 }
 191         }
 192
 193         if (rval == QLA_SUCCESS) {
 194                 /* Get RISC SRAM. */
 195                 risc_address = 0x800;
 196                 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD);
 197                 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
 198         }
 199         for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS;
 200             cnt++, risc_address++) {
 201                 WRT_MAILBOX_REG(ha, reg, 1, (uint16_t)risc_address);
 202                 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
 203
 204                 for (timer = 6000000; timer; timer--) {
 205                         /* Check for pending interrupts. */
 206                         stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
 207                         if (stat & HSR_RISC_INT) {
 208                                 stat &= 0xff;
 209
 210                                 if (stat == 0x1 || stat == 0x2) {
 211                                         set_bit(MBX_INTERRUPT,
 212                                             &ha->mbx_cmd_flags);
 213
 214                                         mb0 = RD_MAILBOX_REG(ha, reg, 0);
 215                                         mb2 = RD_MAILBOX_REG(ha, reg, 2);
 216
 217                                         /* Release mailbox registers. */
 218                                         WRT_REG_WORD(&reg->semaphore, 0);
 219                                         WRT_REG_WORD(&reg->hccr,
 220                                             HCCR_CLR_RISC_INT);
 221                                         break;
 222                                 } else if (stat == 0x10 || stat == 0x11) {
 223                                         set_bit(MBX_INTERRUPT,
 224                                             &ha->mbx_cmd_flags);
 225
 226                                         mb0 = RD_MAILBOX_REG(ha, reg, 0);
 227                                         mb2 = RD_MAILBOX_REG(ha, reg, 2);
 228
 229                                         WRT_REG_WORD(&reg->hccr,
 230                                             HCCR_CLR_RISC_INT);
 231                                         break;
 232                                 }
 233
 234                                 /* clear this intr; it wasn't a mailbox intr */
 235                                 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
 236                         }
 237                         udelay(5);
 238                 }
 239
 240                 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
 241                         rval = mb0 & MBS_MASK;
 242                         fw->risc_ram[cnt] = mb2;
 243                 } else {
 244                         rval = QLA_FUNCTION_FAILED;
 245                 }
 246         }
 247
 248         if (rval == QLA_SUCCESS) {
 249                 /* Get stack SRAM. */
 250                 risc_address = 0x10000;
 251                 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_EXTENDED);
 252                 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
 253         }
 254         for (cnt = 0; cnt < sizeof(fw->stack_ram) / 2 && rval == QLA_SUCCESS;
 255             cnt++, risc_address++) {
 256                 WRT_MAILBOX_REG(ha, reg, 1, LSW(risc_address));
 257                 WRT_MAILBOX_REG(ha, reg, 8, MSW(risc_address));
 258                 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
 259
 260                 for (timer = 6000000; timer; timer--) {
 261                         /* Check for pending interrupts. */
 262                         stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
 263                         if (stat & HSR_RISC_INT) {
 264                                 stat &= 0xff;
 265
 266                                 if (stat == 0x1 || stat == 0x2) {
 267                                         set_bit(MBX_INTERRUPT,
 268                                             &ha->mbx_cmd_flags);
 269
 270                                         mb0 = RD_MAILBOX_REG(ha, reg, 0);
 271                                         mb2 = RD_MAILBOX_REG(ha, reg, 2);
 272
 273                                         /* Release mailbox registers. */
 274                                         WRT_REG_WORD(&reg->semaphore, 0);
 275                                         WRT_REG_WORD(&reg->hccr,
 276                                             HCCR_CLR_RISC_INT);
 277                                         break;
 278                                 } else if (stat == 0x10 || stat == 0x11) {
 279                                         set_bit(MBX_INTERRUPT,
 280                                             &ha->mbx_cmd_flags);
 281
 282                                         mb0 = RD_MAILBOX_REG(ha, reg, 0);
 283                                         mb2 = RD_MAILBOX_REG(ha, reg, 2);
 284
 285                                         WRT_REG_WORD(&reg->hccr,
 286                                             HCCR_CLR_RISC_INT);
 287                                         break;
 288                                 }
 289
 290                                 /* clear this intr; it wasn't a mailbox intr */
 291                                 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
 292                         }
 293                         udelay(5);
 294                 }
 295
 296                 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
 297                         rval = mb0 & MBS_MASK;
 298                         fw->stack_ram[cnt] = mb2;
 299                 } else {
 300                         rval = QLA_FUNCTION_FAILED;
 301                 }
 302         }
 303
 304         if (rval == QLA_SUCCESS) {
 305                 /* Get data SRAM. */
 306                 risc_address = 0x11000;
 307                 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_EXTENDED);
 308                 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
 309         }
 310         for (cnt = 0; cnt < sizeof(fw->data_ram) / 2 && rval == QLA_SUCCESS;
 311             cnt++, risc_address++) {
 312                 WRT_MAILBOX_REG(ha, reg, 1, LSW(risc_address));
 313                 WRT_MAILBOX_REG(ha, reg, 8, MSW(risc_address));
 314                 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
 315
 316                 for (timer = 6000000; timer; timer--) {
 317                         /* Check for pending interrupts. */
 318                         stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
 319                         if (stat & HSR_RISC_INT) {
 320                                 stat &= 0xff;
 321
 322                                 if (stat == 0x1 || stat == 0x2) {
 323                                         set_bit(MBX_INTERRUPT,
 324                                             &ha->mbx_cmd_flags);
 325
 326                                         mb0 = RD_MAILBOX_REG(ha, reg, 0);
 327                                         mb2 = RD_MAILBOX_REG(ha, reg, 2);
 328
 329                                         /* Release mailbox registers. */
 330                                         WRT_REG_WORD(&reg->semaphore, 0);
 331                                         WRT_REG_WORD(&reg->hccr,
 332                                             HCCR_CLR_RISC_INT);
 333                                         break;
 334                                 } else if (stat == 0x10 || stat == 0x11) {
 335                                         set_bit(MBX_INTERRUPT,
 336                                             &ha->mbx_cmd_flags);
 337
 338                                         mb0 = RD_MAILBOX_REG(ha, reg, 0);
 339                                         mb2 = RD_MAILBOX_REG(ha, reg, 2);
 340
 341                                         WRT_REG_WORD(&reg->hccr,
 342                                             HCCR_CLR_RISC_INT);
 343                                         break;
 344                                 }
 345
 346                                 /* clear this intr; it wasn't a mailbox intr */
 347                                 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
 348                         }
 349                         udelay(5);
 350                 }
 351
 352                 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
 353                         rval = mb0 & MBS_MASK;
 354                         fw->data_ram[cnt] = mb2;
 355                 } else {
 356                         rval = QLA_FUNCTION_FAILED;
 357                 }
 358         }
 359
 360
 361         if (rval != QLA_SUCCESS) {
 362                 qla_printk(KERN_WARNING, ha,
 363                     "Failed to dump firmware (%d)!!!\n", rval);
 364
 365                 free_pages((unsigned long)ha->fw_dump, ha->fw_dump_order);
 366                 ha->fw_dump = NULL;
 367         } else {
 368                 qla_printk(KERN_INFO, ha,
 369                     "Firmware dump saved to temp buffer (%ld/%p).\n",
 370                     ha->host_no, ha->fw_dump);
 371         }
 372
 373         if (!hardware_locked)
 374                 spin_unlock_irqrestore(&ha->hardware_lock, flags);
 375 }
 376
 377 /**
 378  * qla2300_ascii_fw_dump() - Converts a binary firmware dump to ASCII.
 379  * @ha: HA context
 380  */
 381 void
 382 qla2300_ascii_fw_dump(scsi_qla_host_t *ha)
 383 {
 384         uint32_t cnt;
 385         char *uiter;
 386         char fw_info[30];
 387         struct qla2300_fw_dump *fw;
 388
 389         uiter = ha->fw_dump_buffer;
 390         fw = ha->fw_dump;
 391
 392         qla_uprintf(&uiter, "%s Firmware Version %s\n", ha->model_number,
 393             qla2x00_get_fw_version_str(ha, fw_info));
 394
 395         qla_uprintf(&uiter, "\n[==>BEG]\n");
 396
 397         qla_uprintf(&uiter, "HCCR Register:\n%04x\n\n", fw->hccr);
 398
 399         qla_uprintf(&uiter, "PBIU Registers:");
 400         for (cnt = 0; cnt < sizeof (fw->pbiu_reg) / 2; cnt++) {
 401                 if (cnt % 8 == 0) {
 402                         qla_uprintf(&uiter, "\n");
 403                 }
 404                 qla_uprintf(&uiter, "%04x ", fw->pbiu_reg[cnt]);
 405         }
 406
 407         qla_uprintf(&uiter, "\n\nReqQ-RspQ-Risc2Host Status registers:");
 408         for (cnt = 0; cnt < sizeof (fw->risc_host_reg) / 2; cnt++) {
 409                 if (cnt % 8 == 0) {
 410                         qla_uprintf(&uiter, "\n");
 411                 }
 412                 qla_uprintf(&uiter, "%04x ", fw->risc_host_reg[cnt]);
 413         }
 414
 415         qla_uprintf(&uiter, "\n\nMailbox Registers:");
 416         for (cnt = 0; cnt < sizeof (fw->mailbox_reg) / 2; cnt++) {
 417                 if (cnt % 8 == 0) {
 418                         qla_uprintf(&uiter, "\n");
 419                 }
 420                 qla_uprintf(&uiter, "%04x ", fw->mailbox_reg[cnt]);
 421         }
 422
 423         qla_uprintf(&uiter, "\n\nAuto Request Response DMA Registers:");
 424         for (cnt = 0; cnt < sizeof (fw->resp_dma_reg) / 2; cnt++) {
 425                 if (cnt % 8 == 0) {
 426                         qla_uprintf(&uiter, "\n");
 427                 }
 428                 qla_uprintf(&uiter, "%04x ", fw->resp_dma_reg[cnt]);
 429         }
 430
 431         qla_uprintf(&uiter, "\n\nDMA Registers:");
 432         for (cnt = 0; cnt < sizeof (fw->dma_reg) / 2; cnt++) {
 433                 if (cnt % 8 == 0) {
 434                         qla_uprintf(&uiter, "\n");
 435                 }
 436                 qla_uprintf(&uiter, "%04x ", fw->dma_reg[cnt]);
 437         }
 438
 439         qla_uprintf(&uiter, "\n\nRISC Hardware Registers:");
 440         for (cnt = 0; cnt < sizeof (fw->risc_hdw_reg) / 2; cnt++) {
 441                 if (cnt % 8 == 0) {
 442                         qla_uprintf(&uiter, "\n");
 443                 }
 444                 qla_uprintf(&uiter, "%04x ", fw->risc_hdw_reg[cnt]);
 445         }
 446
 447         qla_uprintf(&uiter, "\n\nRISC GP0 Registers:");
 448         for (cnt = 0; cnt < sizeof (fw->risc_gp0_reg) / 2; cnt++) {
 449                 if (cnt % 8 == 0) {
 450                         qla_uprintf(&uiter, "\n");
 451                 }
 452                 qla_uprintf(&uiter, "%04x ", fw->risc_gp0_reg[cnt]);
 453         }
 454
 455         qla_uprintf(&uiter, "\n\nRISC GP1 Registers:");
 456         for (cnt = 0; cnt < sizeof (fw->risc_gp1_reg) / 2; cnt++) {
 457                 if (cnt % 8 == 0) {
 458                         qla_uprintf(&uiter, "\n");
 459                 }
 460                 qla_uprintf(&uiter, "%04x ", fw->risc_gp1_reg[cnt]);
 461         }
 462
 463         qla_uprintf(&uiter, "\n\nRISC GP2 Registers:");
 464         for (cnt = 0; cnt < sizeof (fw->risc_gp2_reg) / 2; cnt++) {
 465                 if (cnt % 8 == 0) {
 466                         qla_uprintf(&uiter, "\n");
 467                 }
 468                 qla_uprintf(&uiter, "%04x ", fw->risc_gp2_reg[cnt]);
 469         }
 470
 471         qla_uprintf(&uiter, "\n\nRISC GP3 Registers:");
 472         for (cnt = 0; cnt < sizeof (fw->risc_gp3_reg) / 2; cnt++) {
 473                 if (cnt % 8 == 0) {
 474                         qla_uprintf(&uiter, "\n");
 475                 }
 476                 qla_uprintf(&uiter, "%04x ", fw->risc_gp3_reg[cnt]);
 477         }
 478
 479         qla_uprintf(&uiter, "\n\nRISC GP4 Registers:");
 480         for (cnt = 0; cnt < sizeof (fw->risc_gp4_reg) / 2; cnt++) {
 481                 if (cnt % 8 == 0) {
 482                         qla_uprintf(&uiter, "\n");
 483                 }
 484                 qla_uprintf(&uiter, "%04x ", fw->risc_gp4_reg[cnt]);
 485         }
 486
 487         qla_uprintf(&uiter, "\n\nRISC GP5 Registers:");
 488         for (cnt = 0; cnt < sizeof (fw->risc_gp5_reg) / 2; cnt++) {
 489                 if (cnt % 8 == 0) {
 490                         qla_uprintf(&uiter, "\n");
 491                 }
 492                 qla_uprintf(&uiter, "%04x ", fw->risc_gp5_reg[cnt]);
 493         }
 494
 495         qla_uprintf(&uiter, "\n\nRISC GP6 Registers:");
 496         for (cnt = 0; cnt < sizeof (fw->risc_gp6_reg) / 2; cnt++) {
 497                 if (cnt % 8 == 0) {
 498                         qla_uprintf(&uiter, "\n");
 499                 }
 500                 qla_uprintf(&uiter, "%04x ", fw->risc_gp6_reg[cnt]);
 501         }
 502
 503         qla_uprintf(&uiter, "\n\nRISC GP7 Registers:");
 504         for (cnt = 0; cnt < sizeof (fw->risc_gp7_reg) / 2; cnt++) {
 505                 if (cnt % 8 == 0) {
 506                         qla_uprintf(&uiter, "\n");
 507                 }
 508                 qla_uprintf(&uiter, "%04x ", fw->risc_gp7_reg[cnt]);
 509         }
 510
 511         qla_uprintf(&uiter, "\n\nFrame Buffer Hardware Registers:");
 512         for (cnt = 0; cnt < sizeof (fw->frame_buf_hdw_reg) / 2; cnt++) {
 513                 if (cnt % 8 == 0) {
 514                         qla_uprintf(&uiter, "\n");
 515                 }
 516                 qla_uprintf(&uiter, "%04x ", fw->frame_buf_hdw_reg[cnt]);
 517         }
 518
 519         qla_uprintf(&uiter, "\n\nFPM B0 Registers:");
 520         for (cnt = 0; cnt < sizeof (fw->fpm_b0_reg) / 2; cnt++) {
 521                 if (cnt % 8 == 0) {
 522                         qla_uprintf(&uiter, "\n");
 523                 }
 524                 qla_uprintf(&uiter, "%04x ", fw->fpm_b0_reg[cnt]);
 525         }
 526
 527         qla_uprintf(&uiter, "\n\nFPM B1 Registers:");
 528         for (cnt = 0; cnt < sizeof (fw->fpm_b1_reg) / 2; cnt++) {
 529                 if (cnt % 8 == 0) {
 530                         qla_uprintf(&uiter, "\n");
 531                 }
 532                 qla_uprintf(&uiter, "%04x ", fw->fpm_b1_reg[cnt]);
 533         }
 534
 535         qla_uprintf(&uiter, "\n\nCode RAM Dump:");
 536         for (cnt = 0; cnt < sizeof (fw->risc_ram) / 2; cnt++) {
 537                 if (cnt % 8 == 0) {
 538                         qla_uprintf(&uiter, "\n%04x: ", cnt + 0x0800);
 539                 }
 540                 qla_uprintf(&uiter, "%04x ", fw->risc_ram[cnt]);
 541         }
 542
 543         qla_uprintf(&uiter, "\n\nStack RAM Dump:");
 544         for (cnt = 0; cnt < sizeof (fw->stack_ram) / 2; cnt++) {
 545                 if (cnt % 8 == 0) {
 546                         qla_uprintf(&uiter, "\n%05x: ", cnt + 0x10000);
 547                 }
 548                 qla_uprintf(&uiter, "%04x ", fw->stack_ram[cnt]);
 549         }
 550
 551         qla_uprintf(&uiter, "\n\nData RAM Dump:");
 552         for (cnt = 0; cnt < sizeof (fw->data_ram) / 2; cnt++) {
 553                 if (cnt % 8 == 0) {
 554                         qla_uprintf(&uiter, "\n%05x: ", cnt + 0x11000);
 555                 }
 556                 qla_uprintf(&uiter, "%04x ", fw->data_ram[cnt]);
 557         }
 558
 559         qla_uprintf(&uiter, "\n\n[<==END] ISP Debug Dump.");
 560 }
 561
 562 /**
 563  * qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware.
 564  * @ha: HA context
 565  * @hardware_locked: Called with the hardware_lock
 566  */
 567 void
 568 qla2100_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
 569 {
 570         int             rval;
 571         uint32_t        cnt, timer;
 572         uint32_t        risc_address;
 573         uint16_t        mb0, mb2;
 574
 575         device_reg_t    *reg;
 576         uint16_t        *dmp_reg;
 577         unsigned long   flags;
 578         struct qla2100_fw_dump  *fw;
 579
 580         reg = ha->iobase;
 581         risc_address = 0;
 582         mb0 = mb2 = 0;
 583         flags = 0;
 584
 585         if (!hardware_locked)
 586                 spin_lock_irqsave(&ha->hardware_lock, flags);
 587
 588         if (ha->fw_dump != NULL) {
 589                 qla_printk(KERN_WARNING, ha,
 590                     "Firmware has been previously dumped (%p) -- ignoring "
 591                     "request...\n", ha->fw_dump);
 592                 return;
 593         }
 594
 595         /* Allocate (large) dump buffer. */
 596         ha->fw_dump_order = get_order(sizeof(struct qla2100_fw_dump));
 597         ha->fw_dump = (struct qla2100_fw_dump *) __get_free_pages(GFP_ATOMIC,
 598             ha->fw_dump_order);
 599         if (ha->fw_dump == NULL) {
 600                 qla_printk(KERN_WARNING, ha,
 601                     "Unable to allocated memory for firmware dump (%d/%Zd).\n",
 602                     ha->fw_dump_order, sizeof(struct qla2100_fw_dump));
 603                 return;
 604         }
 605         fw = ha->fw_dump;
 606
 607         rval = QLA_SUCCESS;
 608         fw->hccr = RD_REG_WORD(&reg->hccr);
 609
 610         /* Pause RISC. */
 611         WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
 612         for (cnt = 30000; (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
 613             rval == QLA_SUCCESS; cnt--) {
 614                 if (cnt)
 615                         udelay(100);
 616                 else
 617                         rval = QLA_FUNCTION_TIMEOUT;
 618         }
 619
 620         if (rval == QLA_SUCCESS) {
 621                 dmp_reg = (uint16_t *)(reg + 0);
 622                 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
 623                         fw->pbiu_reg[cnt] = RD_REG_WORD(dmp_reg++);
 624
 625                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x10);
 626                 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
 627                         if (cnt == 8) {
 628                                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0xe0);
 629                         }
 630                         fw->mailbox_reg[cnt] = RD_REG_WORD(dmp_reg++);
 631                 }
 632
 633                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x20);
 634                 for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
 635                         fw->dma_reg[cnt] = RD_REG_WORD(dmp_reg++);
 636
 637                 WRT_REG_WORD(&reg->ctrl_status, 0x00);
 638                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0xA0);
 639                 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
 640                         fw->risc_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++);
 641
 642                 WRT_REG_WORD(&reg->pcr, 0x2000);
 643                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 644                 for (cnt = 0; cnt < sizeof(fw->risc_gp0_reg) / 2; cnt++)
 645                         fw->risc_gp0_reg[cnt] = RD_REG_WORD(dmp_reg++);
 646
 647                 WRT_REG_WORD(&reg->pcr, 0x2100);
 648                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 649                 for (cnt = 0; cnt < sizeof(fw->risc_gp1_reg) / 2; cnt++)
 650                         fw->risc_gp1_reg[cnt] = RD_REG_WORD(dmp_reg++);
 651
 652                 WRT_REG_WORD(&reg->pcr, 0x2200);
 653                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 654                 for (cnt = 0; cnt < sizeof(fw->risc_gp2_reg) / 2; cnt++)
 655                         fw->risc_gp2_reg[cnt] = RD_REG_WORD(dmp_reg++);
 656
 657                 WRT_REG_WORD(&reg->pcr, 0x2300);
 658                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 659                 for (cnt = 0; cnt < sizeof(fw->risc_gp3_reg) / 2; cnt++)
 660                         fw->risc_gp3_reg[cnt] = RD_REG_WORD(dmp_reg++);
 661
 662                 WRT_REG_WORD(&reg->pcr, 0x2400);
 663                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 664                 for (cnt = 0; cnt < sizeof(fw->risc_gp4_reg) / 2; cnt++)
 665                         fw->risc_gp4_reg[cnt] = RD_REG_WORD(dmp_reg++);
 666
 667                 WRT_REG_WORD(&reg->pcr, 0x2500);
 668                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 669                 for (cnt = 0; cnt < sizeof(fw->risc_gp5_reg) / 2; cnt++)
 670                         fw->risc_gp5_reg[cnt] = RD_REG_WORD(dmp_reg++);
 671
 672                 WRT_REG_WORD(&reg->pcr, 0x2600);
 673                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 674                 for (cnt = 0; cnt < sizeof(fw->risc_gp6_reg) / 2; cnt++)
 675                         fw->risc_gp6_reg[cnt] = RD_REG_WORD(dmp_reg++);
 676
 677                 WRT_REG_WORD(&reg->pcr, 0x2700);
 678                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 679                 for (cnt = 0; cnt < sizeof(fw->risc_gp7_reg) / 2; cnt++)
 680                         fw->risc_gp7_reg[cnt] = RD_REG_WORD(dmp_reg++);
 681
 682                 WRT_REG_WORD(&reg->ctrl_status, 0x10);
 683                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 684                 for (cnt = 0; cnt < sizeof(fw->frame_buf_hdw_reg) / 2; cnt++)
 685                         fw->frame_buf_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++);
 686
 687                 WRT_REG_WORD(&reg->ctrl_status, 0x20);
 688                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 689                 for (cnt = 0; cnt < sizeof(fw->fpm_b0_reg) / 2; cnt++)
 690                         fw->fpm_b0_reg[cnt] = RD_REG_WORD(dmp_reg++);
 691
 692                 WRT_REG_WORD(&reg->ctrl_status, 0x30);
 693                 dmp_reg = (uint16_t *)((uint8_t *)reg + 0x80);
 694                 for (cnt = 0; cnt < sizeof(fw->fpm_b1_reg) / 2; cnt++)
 695                         fw->fpm_b1_reg[cnt] = RD_REG_WORD(dmp_reg++);
 696
 697                 /* Disable ISP interrupts. */
 698                 WRT_REG_WORD(&reg->ictrl, 0);
 699
 700                 /* Reset RISC module. */
 701                 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
 702
 703                 /* Release RISC module. */
 704                 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
 705
 706                 /* Insure mailbox registers are free. */
 707                 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
 708                 WRT_REG_WORD(&reg->hccr, HCCR_CLR_HOST_INT);
 709         }
 710
 711         for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
 712             rval == QLA_SUCCESS; cnt--) {
 713                 if (cnt)
 714                         udelay(100);
 715                 else
 716                         rval = QLA_FUNCTION_TIMEOUT;
 717         }
 718
 719         /* Pause RISC. */
 720         if (rval == QLA_SUCCESS && (IS_QLA2200(ha) || (IS_QLA2100(ha) &&
 721             (RD_REG_WORD(&reg->mctr) & (BIT_1 | BIT_0)) != 0))) {
 722
 723                 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
 724                 for (cnt = 30000;
 725                     (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
 726                     rval == QLA_SUCCESS; cnt--) {
 727                         if (cnt)
 728                                 udelay(100);
 729                         else
 730                                 rval = QLA_FUNCTION_TIMEOUT;
 731                 }
 732
 733                 if (rval == QLA_SUCCESS) {
 734                         /* Set memory configuration and timing. */
 735                         if (IS_QLA2100(ha))
 736                                 WRT_REG_WORD(&reg->mctr, 0xf1);
 737                         else
 738                                 WRT_REG_WORD(&reg->mctr, 0xf2);
 739
 740                         /* Release RISC. */
 741                         WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
 742                 }
 743         }
 744
 745         if (rval == QLA_SUCCESS) {
 746                 /* Get RISC SRAM. */
 747                 risc_address = 0x1000;
 748                 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD);
 749                 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
 750         }
 751         for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS;
 752             cnt++, risc_address++) {
 753                 WRT_MAILBOX_REG(ha, reg, 1, (uint16_t)risc_address);
 754                 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
 755
 756                 for (timer = 6000000; timer != 0; timer--) {
 757                         /* Check for pending interrupts. */
 758                         if (RD_REG_WORD(&reg->istatus) & ISR_RISC_INT) {
 759                                 if (RD_REG_WORD(&reg->semaphore) & BIT_0) {
 760                                         set_bit(MBX_INTERRUPT,
 761                                             &ha->mbx_cmd_flags);
 762
 763                                         mb0 = RD_MAILBOX_REG(ha, reg, 0);
 764                                         mb2 = RD_MAILBOX_REG(ha, reg, 2);
 765
 766                                         WRT_REG_WORD(&reg->semaphore, 0);
 767                                         WRT_REG_WORD(&reg->hccr,
 768                                             HCCR_CLR_RISC_INT);
 769                                         break;
 770                                 }
 771                                 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
 772                         }
 773                         udelay(5);
 774                 }
 775
 776                 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
 777                         rval = mb0 & MBS_MASK;
 778                         fw->risc_ram[cnt] = mb2;
 779                 } else {
 780                         rval = QLA_FUNCTION_FAILED;
 781                 }
 782         }
 783
 784         if (rval != QLA_SUCCESS) {
 785                 qla_printk(KERN_WARNING, ha,
 786                     "Failed to dump firmware (%d)!!!\n", rval);
 787
 788                 free_pages((unsigned long)ha->fw_dump, ha->fw_dump_order);
 789                 ha->fw_dump = NULL;
 790         } else {
 791                 qla_printk(KERN_INFO, ha,
 792                     "Firmware dump saved to temp buffer (%ld/%p).\n",
 793                     ha->host_no, ha->fw_dump);
 794         }
 795
 796         if (!hardware_locked)
 797                 spin_unlock_irqrestore(&ha->hardware_lock, flags);
 798 }
 799
 800 /**
 801  * qla2100_ascii_fw_dump() - Converts a binary firmware dump to ASCII.
 802  * @ha: HA context
 803  */
 804 void
 805 qla2100_ascii_fw_dump(scsi_qla_host_t *ha)
 806 {
 807         uint32_t cnt;
 808         char *uiter;
 809         char fw_info[30];
 810         struct qla2100_fw_dump *fw;
 811
 812         uiter = ha->fw_dump_buffer;
 813         fw = ha->fw_dump;
 814
 815         qla_uprintf(&uiter, "%s Firmware Version %s\n", ha->model_number,
 816             qla2x00_get_fw_version_str(ha, fw_info));
 817
 818         qla_uprintf(&uiter, "\n[==>BEG]\n");
 819
 820         qla_uprintf(&uiter, "HCCR Register:\n%04x\n\n", fw->hccr);
 821
 822         qla_uprintf(&uiter, "PBIU Registers:");
 823         for (cnt = 0; cnt < sizeof (fw->pbiu_reg) / 2; cnt++) {
 824                 if (cnt % 8 == 0) {
 825                         qla_uprintf(&uiter, "\n");
 826                 }
 827                 qla_uprintf(&uiter, "%04x ", fw->pbiu_reg[cnt]);
 828         }
 829
 830         qla_uprintf(&uiter, "\n\nMailbox Registers:");
 831         for (cnt = 0; cnt < sizeof (fw->mailbox_reg) / 2; cnt++) {
 832                 if (cnt % 8 == 0) {
 833                         qla_uprintf(&uiter, "\n");
 834                 }
 835                 qla_uprintf(&uiter, "%04x ", fw->mailbox_reg[cnt]);
 836         }
 837
 838         qla_uprintf(&uiter, "\n\nDMA Registers:");
 839         for (cnt = 0; cnt < sizeof (fw->dma_reg) / 2; cnt++) {
 840                 if (cnt % 8 == 0) {
 841                         qla_uprintf(&uiter, "\n");
 842                 }
 843                 qla_uprintf(&uiter, "%04x ", fw->dma_reg[cnt]);
 844         }
 845
 846         qla_uprintf(&uiter, "\n\nRISC Hardware Registers:");
 847         for (cnt = 0; cnt < sizeof (fw->risc_hdw_reg) / 2; cnt++) {
 848                 if (cnt % 8 == 0) {
 849                         qla_uprintf(&uiter, "\n");
 850                 }
 851                 qla_uprintf(&uiter, "%04x ", fw->risc_hdw_reg[cnt]);
 852         }
 853
 854         qla_uprintf(&uiter, "\n\nRISC GP0 Registers:");
 855         for (cnt = 0; cnt < sizeof (fw->risc_gp0_reg) / 2; cnt++) {
 856                 if (cnt % 8 == 0) {
 857                         qla_uprintf(&uiter, "\n");
 858                 }
 859                 qla_uprintf(&uiter, "%04x ", fw->risc_gp0_reg[cnt]);
 860         }
 861
 862         qla_uprintf(&uiter, "\n\nRISC GP1 Registers:");
 863         for (cnt = 0; cnt < sizeof (fw->risc_gp1_reg) / 2; cnt++) {
 864                 if (cnt % 8 == 0) {
 865                         qla_uprintf(&uiter, "\n");
 866                 }
 867                 qla_uprintf(&uiter, "%04x ", fw->risc_gp1_reg[cnt]);
 868         }
 869
 870         qla_uprintf(&uiter, "\n\nRISC GP2 Registers:");
 871         for (cnt = 0; cnt < sizeof (fw->risc_gp2_reg) / 2; cnt++) {
 872                 if (cnt % 8 == 0) {
 873                         qla_uprintf(&uiter, "\n");
 874                 }
 875                 qla_uprintf(&uiter, "%04x ", fw->risc_gp2_reg[cnt]);
 876         }
 877
 878         qla_uprintf(&uiter, "\n\nRISC GP3 Registers:");
 879         for (cnt = 0; cnt < sizeof (fw->risc_gp3_reg) / 2; cnt++) {
 880                 if (cnt % 8 == 0) {
 881                         qla_uprintf(&uiter, "\n");
 882                 }
 883                 qla_uprintf(&uiter, "%04x ", fw->risc_gp3_reg[cnt]);
 884         }
 885
 886         qla_uprintf(&uiter, "\n\nRISC GP4 Registers:");
 887         for (cnt = 0; cnt < sizeof (fw->risc_gp4_reg) / 2; cnt++) {
 888                 if (cnt % 8 == 0) {
 889                         qla_uprintf(&uiter, "\n");
 890                 }
 891                 qla_uprintf(&uiter, "%04x ", fw->risc_gp4_reg[cnt]);
 892         }
 893
 894         qla_uprintf(&uiter, "\n\nRISC GP5 Registers:");
 895         for (cnt = 0; cnt < sizeof (fw->risc_gp5_reg) / 2; cnt++) {
 896                 if (cnt % 8 == 0) {
 897                         qla_uprintf(&uiter, "\n");
 898                 }
 899                 qla_uprintf(&uiter, "%04x ", fw->risc_gp5_reg[cnt]);
 900         }
 901
 902         qla_uprintf(&uiter, "\n\nRISC GP6 Registers:");
 903         for (cnt = 0; cnt < sizeof (fw->risc_gp6_reg) / 2; cnt++) {
 904                 if (cnt % 8 == 0) {
 905                         qla_uprintf(&uiter, "\n");
 906                 }
 907                 qla_uprintf(&uiter, "%04x ", fw->risc_gp6_reg[cnt]);
 908         }
 909
 910         qla_uprintf(&uiter, "\n\nRISC GP7 Registers:");
 911         for (cnt = 0; cnt < sizeof (fw->risc_gp7_reg) / 2; cnt++) {
 912                 if (cnt % 8 == 0) {
 913                         qla_uprintf(&uiter, "\n");
 914                 }
 915                 qla_uprintf(&uiter, "%04x ", fw->risc_gp7_reg[cnt]);
 916         }
 917
 918         qla_uprintf(&uiter, "\n\nFrame Buffer Hardware Registers:");
 919         for (cnt = 0; cnt < sizeof (fw->frame_buf_hdw_reg) / 2; cnt++) {
 920                 if (cnt % 8 == 0) {
 921                         qla_uprintf(&uiter, "\n");
 922                 }
 923                 qla_uprintf(&uiter, "%04x ", fw->frame_buf_hdw_reg[cnt]);
 924         }
 925
 926         qla_uprintf(&uiter, "\n\nFPM B0 Registers:");
 927         for (cnt = 0; cnt < sizeof (fw->fpm_b0_reg) / 2; cnt++) {
 928                 if (cnt % 8 == 0) {
 929                         qla_uprintf(&uiter, "\n");
 930                 }
 931                 qla_uprintf(&uiter, "%04x ", fw->fpm_b0_reg[cnt]);
 932         }
 933
 934         qla_uprintf(&uiter, "\n\nFPM B1 Registers:");
 935         for (cnt = 0; cnt < sizeof (fw->fpm_b1_reg) / 2; cnt++) {
 936                 if (cnt % 8 == 0) {
 937                         qla_uprintf(&uiter, "\n");
 938                 }
 939                 qla_uprintf(&uiter, "%04x ", fw->fpm_b1_reg[cnt]);
 940         }
 941
 942         qla_uprintf(&uiter, "\n\nRISC SRAM:");
 943         for (cnt = 0; cnt < sizeof (fw->risc_ram) / 2; cnt++) {
 944                 if (cnt % 8 == 0) {
 945                         qla_uprintf(&uiter, "\n%04x: ", cnt + 0x1000);
 946                 }
 947                 qla_uprintf(&uiter, "%04x ", fw->risc_ram[cnt]);
 948         }
 949
 950         qla_uprintf(&uiter, "\n\n[<==END] ISP Debug Dump.");
 951
 952         return;
 953 }
 954
 955 static int
 956 qla_uprintf(char **uiter, char *fmt, ...)
 957 {
 958         int     iter, len;
 959         char    buf[128];
 960         va_list args;
 961
 962         va_start(args, fmt);
 963         len = vsprintf(buf, fmt, args);
 964         va_end(args);
 965
 966         for (iter = 0; iter < len; iter++, *uiter += 1)
 967                 *uiter[0] = buf[iter];
 968
 969         return (len);
 970 }
 971
 972 //FIXME
 973
 974 /****************************************************************************/
 975 /*                         Driver Debug Functions.                          */
 976 /****************************************************************************/
 977
 978 void
 979 qla2x00_dump_regs(scsi_qla_host_t *ha)
 980 {
 981         device_reg_t    *reg;
 982
 983         reg = ha->iobase;
 984
 985         printk("Mailbox registers:\n");
 986         printk("scsi(%ld): mbox 0 0x%04x \n",
 987             ha->host_no, RD_MAILBOX_REG(ha, reg, 0));
 988         printk("scsi(%ld): mbox 1 0x%04x \n",
 989             ha->host_no, RD_MAILBOX_REG(ha, reg, 1));
 990         printk("scsi(%ld): mbox 2 0x%04x \n",
 991             ha->host_no, RD_MAILBOX_REG(ha, reg, 2));
 992         printk("scsi(%ld): mbox 3 0x%04x \n",
 993             ha->host_no, RD_MAILBOX_REG(ha, reg, 3));
 994         printk("scsi(%ld): mbox 4 0x%04x \n",
 995             ha->host_no, RD_MAILBOX_REG(ha, reg, 4));
 996         printk("scsi(%ld): mbox 5 0x%04x \n",
 997             ha->host_no, RD_MAILBOX_REG(ha, reg, 5));
 998 }
 999
1000
1001 void
1002 qla2x00_dump_buffer(uint8_t * b, uint32_t size)
1003 {
1004         uint32_t cnt;
1005         uint8_t c;
1006
1007         printk(" 0   1   2   3   4   5   6   7   8   9  "
1008             "Ah  Bh  Ch  Dh  Eh  Fh\n");
1009         printk("----------------------------------------"
1010             "----------------------\n");
1011
1012         for (cnt = 0; cnt < size;) {
1013                 c = *b++;
1014                 printk("%02x",(uint32_t) c);
1015                 cnt++;
1016                 if (!(cnt % 16))
1017                         printk("\n");
1018                 else
1019                         printk("  ");
1020         }
1021         if (cnt % 16)
1022                 printk("\n");
1023 }
1024
1025 /**************************************************************************
1026  *   qla2x00_print_scsi_cmd
1027  *       Dumps out info about the scsi cmd and srb.
1028  *   Input
1029  *       cmd : struct scsi_cmnd
1030  **************************************************************************/
1031 void
1032 qla2x00_print_scsi_cmd(struct scsi_cmnd * cmd)
1033 {
1034         int i;
1035         struct scsi_qla_host *ha;
1036         srb_t *sp;
1037
1038         ha = (struct scsi_qla_host *)cmd->device->host->hostdata;
1039
1040         sp = (srb_t *) cmd->SCp.ptr;
1041         printk("SCSI Command @=0x%p, Handle=0x%p\n", cmd, cmd->host_scribble);
1042         printk("  chan=0x%02x, target=0x%02x, lun=0x%02x, cmd_len=0x%02x\n",
1043             cmd->device->channel, cmd->device->id, cmd->device->lun,
1044             cmd->cmd_len);
1045         printk(" CDB: ");
1046         for (i = 0; i < cmd->cmd_len; i++) {
1047                 printk("0x%02x ", cmd->cmnd[i]);
1048         }
1049         printk("\n  seg_cnt=%d, allowed=%d, retries=%d, "
1050             "serial_number_at_timeout=0x%lx\n",
1051             cmd->use_sg, cmd->allowed, cmd->retries,
1052             cmd->serial_number_at_timeout);
1053         printk("  request buffer=0x%p, request buffer len=0x%x\n",
1054             cmd->request_buffer, cmd->request_bufflen);
1055         printk("  tag=%d, transfersize=0x%x\n",
1056             cmd->tag, cmd->transfersize);
1057         printk("  serial_number=%lx, SP=%p\n", cmd->serial_number, sp);
1058         printk("  data direction=%d\n", cmd->sc_data_direction);
1059
1060         if (!sp)
1061                 return;
1062
1063         printk("  sp flags=0x%x\n", sp->flags);
1064         printk("  r_start=0x%lx, u_start=0x%lx, f_start=0x%lx, state=%d\n",
1065             sp->r_start, sp->u_start, sp->f_start, sp->state);
1066
1067         printk(" e_start= 0x%lx, ext_history=%d, fo retry=%d, loopid=%x, "
1068             "port path=%d\n", sp->e_start, sp->ext_history, sp->fo_retry_cnt,
1069             sp->lun_queue->fclun->fcport->loop_id,
1070             sp->lun_queue->fclun->fcport->cur_path);
1071 }
1072
1073 #if defined(QL_DEBUG_ROUTINES)
1074 /*
1075  * qla2x00_formatted_dump_buffer
1076  *       Prints string plus buffer.
1077  *
1078  * Input:
1079  *       string  = Null terminated string (no newline at end).
1080  *       buffer  = buffer address.
1081  *       wd_size = word size 8, 16, 32 or 64 bits
1082  *       count   = number of words.
1083  */
1084 void
1085 qla2x00_formatted_dump_buffer(char *string, uint8_t * buffer,
1086                                 uint8_t wd_size, uint32_t count)
1087 {
1088         uint32_t cnt;
1089         uint16_t *buf16;
1090         uint32_t *buf32;
1091
1092         if (strcmp(string, "") != 0)
1093                 printk("%s\n",string);
1094
1095         switch (wd_size) {
1096                 case 8:
1097                         printk(" 0    1    2    3    4    5    6    7    "
1098                                 "8    9    Ah   Bh   Ch   Dh   Eh   Fh\n");
1099                         printk("-----------------------------------------"
1100                                 "-------------------------------------\n");
1101
1102                         for (cnt = 1; cnt <= count; cnt++, buffer++) {
1103                                 printk("%02x",*buffer);
1104                                 if (cnt % 16 == 0)
1105                                         printk("\n");
1106                                 else
1107                                         printk("  ");
1108                         }
1109                         if (cnt % 16 != 0)
1110                                 printk("\n");
1111                         break;
1112                 case 16:
1113                         printk("   0      2      4      6      8      Ah "
1114                                 "       Ch     Eh\n");
1115                         printk("-----------------------------------------"
1116                                 "-------------\n");
1117
1118                         buf16 = (uint16_t *) buffer;
1119                         for (cnt = 1; cnt <= count; cnt++, buf16++) {
1120                                 printk("%4x",*buf16);
1121
1122                                 if (cnt % 8 == 0)
1123                                         printk("\n");
1124                                 else if (*buf16 < 10)
1125                                         printk("   ");
1126                                 else
1127                                         printk("  ");
1128                         }
1129                         if (cnt % 8 != 0)
1130                                 printk("\n");
1131                         break;
1132                 case 32:
1133                         printk("       0          4          8          Ch\n");
1134                         printk("------------------------------------------\n");
1135
1136                         buf32 = (uint32_t *) buffer;
1137                         for (cnt = 1; cnt <= count; cnt++, buf32++) {
1138                                 printk("%8x", *buf32);
1139
1140                                 if (cnt % 4 == 0)
1141                                         printk("\n");
1142                                 else if (*buf32 < 10)
1143                                         printk("   ");
1144                                 else
1145                                         printk("  ");
1146                         }
1147                         if (cnt % 4 != 0)
1148                                 printk("\n");
1149                         break;
1150                 default:
1151                         break;
1152         }
1153 }
1154 #endif