1 /********************************************************************************
2 * QLOGIC LINUX SOFTWARE
4 * QLogic ISP2x00 device driver for Linux 2.6.x
5 * Copyright (C) 2003-2004 QLogic Corporation
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2, or (at your option) any
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 ******************************************************************************/
23 /* XXX(hch): move to pci_ids.h */
24 #ifndef PCI_DEVICE_ID_QLOGIC_ISP2300
25 #define PCI_DEVICE_ID_QLOGIC_ISP2300 0x2300
28 #ifndef PCI_DEVICE_ID_QLOGIC_ISP2312
29 #define PCI_DEVICE_ID_QLOGIC_ISP2312 0x2312
32 #ifndef PCI_DEVICE_ID_QLOGIC_ISP2322
33 #define PCI_DEVICE_ID_QLOGIC_ISP2322 0x2322
36 #ifndef PCI_DEVICE_ID_QLOGIC_ISP6312
37 #define PCI_DEVICE_ID_QLOGIC_ISP6312 0x6312
40 #ifndef PCI_DEVICE_ID_QLOGIC_ISP6322
41 #define PCI_DEVICE_ID_QLOGIC_ISP6322 0x6322
44 #if defined(CONFIG_SCSI_QLA21XX) || defined(CONFIG_SCSI_QLA21XX_MODULE)
45 #define IS_QLA2100(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2100)
47 #define IS_QLA2100(ha) 0
50 #if defined(CONFIG_SCSI_QLA22XX) || defined(CONFIG_SCSI_QLA22XX_MODULE)
51 #define IS_QLA2200(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2200)
53 #define IS_QLA2200(ha) 0
56 #if defined(CONFIG_SCSI_QLA2300) || defined(CONFIG_SCSI_QLA2300_MODULE)
57 #define IS_QLA2300(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2300)
58 #define IS_QLA2312(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2312)
60 #define IS_QLA2300(ha) 0
61 #define IS_QLA2312(ha) 0
64 #if defined(CONFIG_SCSI_QLA2322) || defined(CONFIG_SCSI_QLA2322_MODULE)
65 #define IS_QLA2322(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2322)
67 #define IS_QLA2322(ha) 0
70 #if defined(CONFIG_SCSI_QLA6312) || defined(CONFIG_SCSI_QLA6312_MODULE)
71 #define IS_QLA6312(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP6312)
73 #define IS_QLA6312(ha) 0
76 #if defined(CONFIG_SCSI_QLA6322) || defined(CONFIG_SCSI_QLA6322_MODULE)
77 #define IS_QLA6322(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP6322)
79 #define IS_QLA6322(ha) 0
82 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
83 IS_QLA6312(ha) || IS_QLA6322(ha))
86 * Only non-ISP2[12]00 have extended addressing support in the firmware.
88 #define HAS_EXTENDED_IDS(ha) (!IS_QLA2100(ha) && !IS_QLA2200(ha))
91 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
92 * but that's fine as we don't look at the last 24 ones for
95 #define MAILBOX_REGISTER_COUNT_2100 8
96 #define MAILBOX_REGISTER_COUNT 32
98 #define QLA2200A_RISC_ROM_VER 4
102 #include "qla_settings.h"
105 * Data bit definitions
119 #define BIT_12 0x1000
120 #define BIT_13 0x2000
121 #define BIT_14 0x4000
122 #define BIT_15 0x8000
123 #define BIT_16 0x10000
124 #define BIT_17 0x20000
125 #define BIT_18 0x40000
126 #define BIT_19 0x80000
127 #define BIT_20 0x100000
128 #define BIT_21 0x200000
129 #define BIT_22 0x400000
130 #define BIT_23 0x800000
131 #define BIT_24 0x1000000
132 #define BIT_25 0x2000000
133 #define BIT_26 0x4000000
134 #define BIT_27 0x8000000
135 #define BIT_28 0x10000000
136 #define BIT_29 0x20000000
137 #define BIT_30 0x40000000
138 #define BIT_31 0x80000000
140 #define LSB(x) ((uint8_t)(x))
141 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
143 #define LSW(x) ((uint16_t)(x))
144 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
146 #define LSD(x) ((uint32_t)((uint64_t)(x)))
147 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
154 #define RD_REG_BYTE(addr) readb(addr)
155 #define RD_REG_WORD(addr) readw(addr)
156 #define RD_REG_DWORD(addr) readl(addr)
157 #define WRT_REG_BYTE(addr, data) writeb(data,addr)
158 #define WRT_REG_WORD(addr, data) writew(data,addr)
159 #define WRT_REG_DWORD(addr, data) writel(data,addr)
162 * Fibre Channel device definitions.
164 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */
165 #define MAX_FIBRE_DEVICES 512
166 #define MAX_FIBRE_LUNS 256
167 #define MAX_RSCN_COUNT 32
168 #define MAX_HOST_COUNT 16
171 * Host adapter default definitions.
173 #define MAX_BUSES 1 /* We only have one bus today */
174 #define MAX_TARGETS_2100 MAX_FIBRE_DEVICES
175 #define MAX_TARGETS_2200 MAX_FIBRE_DEVICES
176 #define MAX_TARGETS MAX_FIBRE_DEVICES
178 #define MAX_LUNS MAX_FIBRE_LUNS
179 #define MAX_CMDS_PER_LUN 255
182 * Fibre Channel device definitions.
184 #define SNS_LAST_LOOP_ID_2100 0xfe
185 #define SNS_LAST_LOOP_ID_2300 0x7ff
187 #define LAST_LOCAL_LOOP_ID 0x7d
188 #define SNS_FL_PORT 0x7e
189 #define FABRIC_CONTROLLER 0x7f
190 #define SIMPLE_NAME_SERVER 0x80
191 #define SNS_FIRST_LOOP_ID 0x81
192 #define MANAGEMENT_SERVER 0xfe
193 #define BROADCAST 0xff
195 #define RESERVED_LOOP_ID(x) ((x > LAST_LOCAL_LOOP_ID && \
196 x < SNS_FIRST_LOOP_ID) || \
197 x == MANAGEMENT_SERVER || \
201 * Timeout timer counts in seconds
203 #define PORT_RETRY_TIME 2
204 #define LOOP_DOWN_TIMEOUT 60
205 #define LOOP_DOWN_TIME 255 /* 240 */
206 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
208 /* Maximum outstanding commands in ISP queues (1-65535) */
209 #define MAX_OUTSTANDING_COMMANDS 1024
211 /* ISP request and response entry counts (37-65535) */
212 #define REQUEST_ENTRY_CNT 2048 /* Number of request entries. */
213 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
214 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
216 /* Calculations for SG segments */
217 #define SEGS_PER_REQUEST_32 3
218 #define SEGS_PER_CONT_32 7
219 #define SG_SEGMENTS_32 (SEGS_PER_REQUEST_32 + \
220 (SEGS_PER_CONT_32 * (REQUEST_ENTRY_CNT - 2)))
221 #define SEGS_PER_REQUEST_64 2
222 #define SEGS_PER_CONT_64 5
223 #define SG_SEGMENTS_64 (SEGS_PER_REQUEST_64 + \
224 (SEGS_PER_CONT_64 * (REQUEST_ENTRY_CNT - 2)))
230 struct list_head list;
232 struct scsi_qla_host *ha; /* HA the SP is queued on */
234 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */
236 struct timer_list timer; /* Command timer */
237 atomic_t ref_count; /* Reference count for this structure */
243 /* Target/LUN queue pointers. */
244 struct os_tgt *tgt_queue; /* ptr to visible ha's target */
245 struct os_lun *lun_queue; /* ptr to visible ha's lun */
246 struct fc_lun *fclun; /* FC LUN context pointer. */
249 unsigned long e_start; /* Start of extend timeout */
250 unsigned long r_start; /* Start of request */
251 unsigned long u_start; /* When sent to RISC */
252 unsigned long f_start; /* When placed in FO queue*/
254 /* Single transfer DMA context */
255 dma_addr_t dma_handle;
257 uint32_t request_sense_length;
258 uint8_t *request_sense_ptr;
265 /* Raw completion info for use by failover ? */
266 uint8_t fo_retry_cnt; /* Retry count this request */
267 uint8_t err_id; /* error id */
268 #define SRB_ERR_PORT 1 /* Request failed -- "port down" */
269 #define SRB_ERR_LOOP 2 /* Request failed -- "loop down" */
270 #define SRB_ERR_DEVICE 3 /* Request failed -- "device error" */
271 #define SRB_ERR_OTHER 4
273 /* Segment/entries counts */
274 uint16_t req_cnt; /* !0 indicates counts determined */
277 /* SRB magic number */
279 #define SRB_MAGIC 0x10CB
283 * SRB flag definitions
285 #define SRB_TIMEOUT BIT_0 /* Command timed out */
286 #define SRB_DMA_VALID BIT_1 /* Command sent to ISP */
287 #define SRB_WATCHDOG BIT_2 /* Command on watchdog list */
288 #define SRB_ABORT_PENDING BIT_3 /* Command abort sent to device */
290 #define SRB_ABORTED BIT_4 /* Command aborted command already */
291 #define SRB_RETRY BIT_5 /* Command needs retrying */
292 #define SRB_GOT_SENSE BIT_6 /* Command has sense data */
293 #define SRB_FAILOVER BIT_7 /* Command in failover state */
295 #define SRB_BUSY BIT_8 /* Command is in busy retry state */
296 #define SRB_FO_CANCEL BIT_9 /* Command don't need to do failover */
297 #define SRB_IOCTL BIT_10 /* IOCTL command. */
300 * SRB state definitions
302 #define SRB_FREE_STATE 0 /* returned back */
303 #define SRB_PENDING_STATE 1 /* queued in LUN Q */
304 #define SRB_ACTIVE_STATE 2 /* in Active Array */
305 #define SRB_DONE_STATE 3 /* queued in Done Queue */
306 #define SRB_RETRY_STATE 4 /* in Retry Queue */
307 #define SRB_SUSPENDED_STATE 5 /* in suspended state */
308 #define SRB_NO_QUEUE_STATE 6 /* is in between states */
309 #define SRB_ACTIVE_TIMEOUT_STATE 7 /* in Active Array but timed out */
310 #define SRB_FAILOVER_STATE 8 /* in Failover Queue */
311 #define SRB_SCSI_RETRY_STATE 9 /* in Scsi Retry Queue */
315 * ISP I/O Register Set structure definitions.
317 typedef volatile struct {
318 volatile uint16_t flash_address; /* Flash BIOS address */
319 volatile uint16_t flash_data; /* Flash BIOS data */
320 uint16_t unused_1[1]; /* Gap */
321 volatile uint16_t ctrl_status; /* Control/Status */
322 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
323 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
324 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
326 volatile uint16_t ictrl; /* Interrupt control */
327 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
328 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
330 volatile uint16_t istatus; /* Interrupt status */
331 #define ISR_RISC_INT BIT_3 /* RISC interrupt */
333 volatile uint16_t semaphore; /* Semaphore */
334 volatile uint16_t nvram; /* NVRAM register. */
335 #define NVR_DESELECT 0
336 #define NVR_BUSY BIT_15
337 #define NVR_DATA_IN BIT_3
338 #define NVR_DATA_OUT BIT_2
339 #define NVR_SELECT BIT_1
340 #define NVR_CLOCK BIT_0
344 volatile uint16_t mailbox0;
345 volatile uint16_t mailbox1;
346 volatile uint16_t mailbox2;
347 volatile uint16_t mailbox3;
348 volatile uint16_t mailbox4;
349 volatile uint16_t mailbox5;
350 volatile uint16_t mailbox6;
351 volatile uint16_t mailbox7;
352 uint16_t unused_2[59]; /* Gap */
353 } __attribute__((packed)) isp2100;
356 volatile uint16_t req_q_in; /* In-Pointer */
357 volatile uint16_t req_q_out; /* Out-Pointer */
359 volatile uint16_t rsp_q_in; /* In-Pointer */
360 volatile uint16_t rsp_q_out; /* Out-Pointer */
362 /* RISC to Host Status */
363 volatile uint32_t host_status;
364 #define HSR_RISC_INT BIT_15 /* RISC interrupt */
365 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
367 /* Host to Host Semaphore */
368 volatile uint16_t host_semaphore;
369 uint16_t unused_3[17]; /* Gap */
370 volatile uint16_t mailbox0;
371 volatile uint16_t mailbox1;
372 volatile uint16_t mailbox2;
373 volatile uint16_t mailbox3;
374 volatile uint16_t mailbox4;
375 volatile uint16_t mailbox5;
376 volatile uint16_t mailbox6;
377 volatile uint16_t mailbox7;
378 volatile uint16_t mailbox8;
379 volatile uint16_t mailbox9;
380 volatile uint16_t mailbox10;
381 volatile uint16_t mailbox11;
382 volatile uint16_t mailbox12;
383 volatile uint16_t mailbox13;
384 volatile uint16_t mailbox14;
385 volatile uint16_t mailbox15;
386 volatile uint16_t mailbox16;
387 volatile uint16_t mailbox17;
388 volatile uint16_t mailbox18;
389 volatile uint16_t mailbox19;
390 volatile uint16_t mailbox20;
391 volatile uint16_t mailbox21;
392 volatile uint16_t mailbox22;
393 volatile uint16_t mailbox23;
394 volatile uint16_t mailbox24;
395 volatile uint16_t mailbox25;
396 volatile uint16_t mailbox26;
397 volatile uint16_t mailbox27;
398 volatile uint16_t mailbox28;
399 volatile uint16_t mailbox29;
400 volatile uint16_t mailbox30;
401 volatile uint16_t mailbox31;
402 volatile uint16_t fb_cmd;
403 uint16_t unused_4[10]; /* Gap */
404 } __attribute__((packed)) isp2300;
407 volatile uint16_t fpm_diag_config;
408 uint16_t unused_5[0x6]; /* Gap */
409 volatile uint16_t pcr; /* Processor Control Register. */
410 uint16_t unused_6[0x5]; /* Gap */
411 volatile uint16_t mctr; /* Memory Configuration and Timing. */
412 uint16_t unused_7[0x3]; /* Gap */
413 volatile uint16_t fb_cmd_2100; /* Unused on 23XX */
414 uint16_t unused_8[0x3]; /* Gap */
415 volatile uint16_t hccr; /* Host command & control register. */
416 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
417 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
419 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */
420 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */
421 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */
422 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */
423 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
424 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
425 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
426 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
428 uint16_t unused_9[5]; /* Gap */
429 volatile uint16_t gpiod; /* GPIO Data register. */
430 volatile uint16_t gpioe; /* GPIO Enable register. */
431 #define GPIO_LED_MASK 0x00C0
432 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
433 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
434 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
435 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
439 uint16_t unused_10[8]; /* Gap */
440 volatile uint16_t mailbox8;
441 volatile uint16_t mailbox9;
442 volatile uint16_t mailbox10;
443 volatile uint16_t mailbox11;
444 volatile uint16_t mailbox12;
445 volatile uint16_t mailbox13;
446 volatile uint16_t mailbox14;
447 volatile uint16_t mailbox15;
448 volatile uint16_t mailbox16;
449 volatile uint16_t mailbox17;
450 volatile uint16_t mailbox18;
451 volatile uint16_t mailbox19;
452 volatile uint16_t mailbox20;
453 volatile uint16_t mailbox21;
454 volatile uint16_t mailbox22;
455 volatile uint16_t mailbox23; /* Also probe reg. */
456 } __attribute__((packed)) isp2200;
460 #define ISP_REQ_Q_IN(ha, reg) \
461 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
462 &(reg)->u.isp2100.mailbox4 : \
463 &(reg)->u.isp2300.req_q_in)
464 #define ISP_REQ_Q_OUT(ha, reg) \
465 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
466 &(reg)->u.isp2100.mailbox4 : \
467 &(reg)->u.isp2300.req_q_out)
468 #define ISP_RSP_Q_IN(ha, reg) \
469 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
470 &(reg)->u.isp2100.mailbox5 : \
471 &(reg)->u.isp2300.rsp_q_in)
472 #define ISP_RSP_Q_OUT(ha, reg) \
473 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
474 &(reg)->u.isp2100.mailbox5 : \
475 &(reg)->u.isp2300.rsp_q_out)
477 #define MAILBOX_REG(ha, reg, num) \
478 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
480 &(reg)->u.isp2100.mailbox0 + (num) : \
481 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
482 &(reg)->u.isp2300.mailbox0 + (num))
483 #define RD_MAILBOX_REG(ha, reg, num) \
484 RD_REG_WORD(MAILBOX_REG(ha, reg, num))
485 #define WRT_MAILBOX_REG(ha, reg, num, data) \
486 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
488 #define FB_CMD_REG(ha, reg) \
489 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
490 &(reg)->fb_cmd_2100 : \
491 &(reg)->u.isp2300.fb_cmd)
492 #define RD_FB_CMD_REG(ha, reg) \
493 RD_REG_WORD(FB_CMD_REG(ha, reg))
494 #define WRT_FB_CMD_REG(ha, reg, data) \
495 WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
498 uint32_t out_mb; /* outbound from driver */
499 uint32_t in_mb; /* Incoming from RISC */
500 uint16_t mb[MAILBOX_REGISTER_COUNT];
505 #define MBX_DMA_IN BIT_0
506 #define MBX_DMA_OUT BIT_1
507 #define IOCTL_CMD BIT_2
510 #define MBX_TOV_SECONDS 30
513 * ISP product identification definitions in mailboxes after reset.
515 #define PROD_ID_1 0x4953
516 #define PROD_ID_2 0x0000
517 #define PROD_ID_2a 0x5020
518 #define PROD_ID_3 0x2020
521 * ISP mailbox Self-Test status codes
523 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */
524 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */
525 #define MBS_BUSY 4 /* Busy. */
528 * ISP mailbox command complete status codes
530 #define MBS_COMMAND_COMPLETE 0x4000
531 #define MBS_INVALID_COMMAND 0x4001
532 #define MBS_HOST_INTERFACE_ERROR 0x4002
533 #define MBS_TEST_FAILED 0x4003
534 #define MBS_COMMAND_ERROR 0x4005
535 #define MBS_COMMAND_PARAMETER_ERROR 0x4006
536 #define MBS_PORT_ID_USED 0x4007
537 #define MBS_LOOP_ID_USED 0x4008
538 #define MBS_ALL_IDS_IN_USE 0x4009
539 #define MBS_NOT_LOGGED_IN 0x400A
542 * ISP mailbox asynchronous event status codes
544 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
545 #define MBA_RESET 0x8001 /* Reset Detected. */
546 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */
547 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
548 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
549 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
550 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */
552 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */
553 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */
554 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */
555 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */
556 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */
557 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
558 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
559 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
560 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
561 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
562 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
563 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */
564 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */
565 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */
566 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */
567 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */
569 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */
570 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */
571 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */
572 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */
573 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */
574 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */
575 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */
576 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */
577 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */
578 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */
579 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */
580 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
581 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
584 * Firmware options 1, 2, 3.
586 #define FO1_AE_ON_LIPF8 BIT_0
587 #define FO1_AE_ALL_LIP_RESET BIT_1
588 #define FO1_CTIO_RETRY BIT_3
589 #define FO1_DISABLE_LIP_F7_SW BIT_4
590 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5
591 #define FO1_DISABLE_GPIO6_7 BIT_6
592 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7
593 #define FO1_SET_EMPHASIS_SWING BIT_8
594 #define FO1_AE_AUTO_BYPASS BIT_9
595 #define FO1_ENABLE_PURE_IOCB BIT_10
596 #define FO1_AE_PLOGI_RJT BIT_11
597 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12
598 #define FO1_AE_QUEUE_FULL BIT_13
600 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0
601 #define FO2_REV_LOOPBACK BIT_1
603 #define FO3_ENABLE_EMERG_IOCB BIT_0
604 #define FO3_AE_RND_ERROR BIT_1
607 * ISP mailbox commands
609 #define MBC_LOAD_RAM 1 /* Load RAM. */
610 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
611 #define MBC_WRITE_RAM_WORD 4 /* Write RAM word. */
612 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */
613 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
614 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
615 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
616 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
617 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
618 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
619 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
620 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
621 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */
622 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */
623 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
624 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
625 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
626 #define MBC_RESET 0x18 /* Reset. */
627 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
628 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
629 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
630 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
631 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
632 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
633 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
634 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
635 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
636 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
637 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */
638 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
639 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
640 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
641 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
642 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
643 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
644 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */
645 #define MBC_GET_RNID_PARAMS 0x5a /* Data Rate */
646 #define MBC_DATA_RATE 0x5d /* Get RNID parameters */
647 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
648 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */
649 /* Initialization Procedure */
650 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
651 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
652 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
653 #define MBC_TARGET_RESET 0x66 /* Target Reset. */
654 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
655 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
656 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
657 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */
658 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */
659 #define MBC_LIP_RESET 0x6c /* LIP reset. */
660 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
662 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
663 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
664 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
665 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
666 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
667 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */
668 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */
669 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */
670 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */
671 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
672 #define MBC_LUN_RESET 0x7E /* Send LUN reset */
674 /* Firmware return data sizes */
675 #define FCAL_MAP_SIZE 128
677 /* Mailbox bit definitions for out_mb and in_mb */
678 #define MBX_31 BIT_31
679 #define MBX_30 BIT_30
680 #define MBX_29 BIT_29
681 #define MBX_28 BIT_28
682 #define MBX_27 BIT_27
683 #define MBX_26 BIT_26
684 #define MBX_25 BIT_25
685 #define MBX_24 BIT_24
686 #define MBX_23 BIT_23
687 #define MBX_22 BIT_22
688 #define MBX_21 BIT_21
689 #define MBX_20 BIT_20
690 #define MBX_19 BIT_19
691 #define MBX_18 BIT_18
692 #define MBX_17 BIT_17
693 #define MBX_16 BIT_16
694 #define MBX_15 BIT_15
695 #define MBX_14 BIT_14
696 #define MBX_13 BIT_13
697 #define MBX_12 BIT_12
698 #define MBX_11 BIT_11
699 #define MBX_10 BIT_10
712 * Firmware state codes from get firmware state mailbox command
714 #define FSTATE_CONFIG_WAIT 0
715 #define FSTATE_WAIT_AL_PA 1
716 #define FSTATE_WAIT_LOGIN 2
717 #define FSTATE_READY 3
718 #define FSTATE_LOSS_OF_SYNC 4
719 #define FSTATE_ERROR 5
720 #define FSTATE_REINIT 6
721 #define FSTATE_NON_PART 7
723 #define FSTATE_CONFIG_CORRECT 0
724 #define FSTATE_P2P_RCV_LIP 1
725 #define FSTATE_P2P_CHOOSE_LOOP 2
726 #define FSTATE_P2P_RCV_UNIDEN_LIP 3
727 #define FSTATE_FATAL_ERROR 4
728 #define FSTATE_LOOP_BACK_CONN 5
731 * Port Database structure definition
732 * Little endian except where noted.
734 #define PORT_DATABASE_SIZE 128 /* bytes */
738 uint8_t master_state;
741 uint8_t hard_address;
744 uint8_t node_name[WWN_SIZE];
745 uint8_t port_name[WWN_SIZE];
746 uint16_t execution_throttle;
747 uint16_t execution_count;
750 uint16_t resource_allocation;
751 uint16_t current_allocation;
754 uint16_t transmit_execution_list_next;
755 uint16_t transmit_execution_list_previous;
756 uint16_t common_features;
757 uint16_t total_concurrent_sequences;
758 uint16_t RO_by_information_category;
761 uint16_t receive_data_size;
762 uint16_t concurrent_sequences;
763 uint16_t open_sequences_per_exchange;
764 uint16_t lun_abort_flags;
765 uint16_t lun_stop_flags;
766 uint16_t stop_queue_head;
767 uint16_t stop_queue_tail;
768 uint16_t port_retry_timer;
769 uint16_t next_sequence_id;
770 uint16_t frame_count;
771 uint16_t PRLI_payload_length;
772 uint8_t prli_svc_param_word_0[2]; /* Big endian */
773 /* Bits 15-0 of word 0 */
774 uint8_t prli_svc_param_word_3[2]; /* Big endian */
775 /* Bits 15-0 of word 3 */
777 uint16_t extended_lun_info_list_pointer;
778 uint16_t extended_lun_stop_list_pointer;
782 * Port database slave/master states
784 #define PD_STATE_DISCOVERY 0
785 #define PD_STATE_WAIT_DISCOVERY_ACK 1
786 #define PD_STATE_PORT_LOGIN 2
787 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3
788 #define PD_STATE_PROCESS_LOGIN 4
789 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
790 #define PD_STATE_PORT_LOGGED_IN 6
791 #define PD_STATE_PORT_UNAVAILABLE 7
792 #define PD_STATE_PROCESS_LOGOUT 8
793 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
794 #define PD_STATE_PORT_LOGOUT 10
795 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
799 * ISP Initialization Control Block.
800 * Little endian except where noted.
802 #define ICB_VERSION 1
808 * LSB BIT 0 = Enable Hard Loop Id
809 * LSB BIT 1 = Enable Fairness
810 * LSB BIT 2 = Enable Full-Duplex
811 * LSB BIT 3 = Enable Fast Posting
812 * LSB BIT 4 = Enable Target Mode
813 * LSB BIT 5 = Disable Initiator Mode
814 * LSB BIT 6 = Enable ADISC
815 * LSB BIT 7 = Enable Target Inquiry Data
817 * MSB BIT 0 = Enable PDBC Notify
818 * MSB BIT 1 = Non Participating LIP
819 * MSB BIT 2 = Descending Loop ID Search
820 * MSB BIT 3 = Acquire Loop ID in LIPA
821 * MSB BIT 4 = Stop PortQ on Full Status
822 * MSB BIT 5 = Full Login after LIP
823 * MSB BIT 6 = Node Name Option
824 * MSB BIT 7 = Ext IFWCB enable bit
826 uint8_t firmware_options[2];
828 uint16_t frame_payload_size;
829 uint16_t max_iocb_allocation;
830 uint16_t execution_throttle;
832 uint8_t retry_delay; /* unused */
833 uint8_t port_name[WWN_SIZE]; /* Big endian. */
834 uint16_t hard_address;
835 uint8_t inquiry_data;
836 uint8_t login_timeout;
837 uint8_t node_name[WWN_SIZE]; /* Big endian. */
839 uint16_t request_q_outpointer;
840 uint16_t response_q_inpointer;
841 uint16_t request_q_length;
842 uint16_t response_q_length;
843 uint32_t request_q_address[2];
844 uint32_t response_q_address[2];
846 uint16_t lun_enables;
847 uint8_t command_resource_count;
848 uint8_t immediate_notify_resource_count;
850 uint8_t reserved_2[2];
853 * LSB BIT 0 = Timer Operation mode bit 0
854 * LSB BIT 1 = Timer Operation mode bit 1
855 * LSB BIT 2 = Timer Operation mode bit 2
856 * LSB BIT 3 = Timer Operation mode bit 3
857 * LSB BIT 4 = Init Config Mode bit 0
858 * LSB BIT 5 = Init Config Mode bit 1
859 * LSB BIT 6 = Init Config Mode bit 2
860 * LSB BIT 7 = Enable Non part on LIHA failure
862 * MSB BIT 0 = Enable class 2
863 * MSB BIT 1 = Enable ACK0
866 * MSB BIT 4 = FC Tape Enable
867 * MSB BIT 5 = Enable FC Confirm
868 * MSB BIT 6 = Enable command queuing in target mode
869 * MSB BIT 7 = No Logo On Link Down
871 uint8_t add_firmware_options[2];
873 uint8_t response_accumulation_timer;
874 uint8_t interrupt_delay_timer;
877 * LSB BIT 0 = Enable Read xfr_rdy
878 * LSB BIT 1 = Soft ID only
881 * LSB BIT 4 = FCP RSP Payload [0]
882 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
883 * LSB BIT 6 = Enable Out-of-Order frame handling
884 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
886 * MSB BIT 0 = Sbus enable - 2300
891 * MSB BIT 5 = enable 50 ohm termination
892 * MSB BIT 6 = Data Rate (2300 only)
893 * MSB BIT 7 = Data Rate (2300 only)
895 uint8_t special_options[2];
897 uint8_t reserved_3[26];
901 * Get Link Status mailbox command return buffer.
904 uint32_t link_fail_cnt;
905 uint32_t loss_sync_cnt;
906 uint32_t loss_sig_cnt;
907 uint32_t prim_seq_err_cnt;
908 uint32_t inval_xmit_word_cnt;
909 uint32_t inval_crc_cnt;
913 * NVRAM Command values.
915 #define NV_START_BIT BIT_2
916 #define NV_WRITE_OP (BIT_26+BIT_24)
917 #define NV_READ_OP (BIT_26+BIT_25)
918 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
919 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
920 #define NV_DELAY_COUNT 10
923 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition.
930 uint8_t nvram_version;
934 * NVRAM RISC parameter block
936 uint8_t parameter_block_version;
940 * LSB BIT 0 = Enable Hard Loop Id
941 * LSB BIT 1 = Enable Fairness
942 * LSB BIT 2 = Enable Full-Duplex
943 * LSB BIT 3 = Enable Fast Posting
944 * LSB BIT 4 = Enable Target Mode
945 * LSB BIT 5 = Disable Initiator Mode
946 * LSB BIT 6 = Enable ADISC
947 * LSB BIT 7 = Enable Target Inquiry Data
949 * MSB BIT 0 = Enable PDBC Notify
950 * MSB BIT 1 = Non Participating LIP
951 * MSB BIT 2 = Descending Loop ID Search
952 * MSB BIT 3 = Acquire Loop ID in LIPA
953 * MSB BIT 4 = Stop PortQ on Full Status
954 * MSB BIT 5 = Full Login after LIP
955 * MSB BIT 6 = Node Name Option
956 * MSB BIT 7 = Ext IFWCB enable bit
958 uint8_t firmware_options[2];
960 uint16_t frame_payload_size;
961 uint16_t max_iocb_allocation;
962 uint16_t execution_throttle;
964 uint8_t retry_delay; /* unused */
965 uint8_t port_name[WWN_SIZE]; /* Big endian. */
966 uint16_t hard_address;
967 uint8_t inquiry_data;
968 uint8_t login_timeout;
969 uint8_t node_name[WWN_SIZE]; /* Big endian. */
972 * LSB BIT 0 = Timer Operation mode bit 0
973 * LSB BIT 1 = Timer Operation mode bit 1
974 * LSB BIT 2 = Timer Operation mode bit 2
975 * LSB BIT 3 = Timer Operation mode bit 3
976 * LSB BIT 4 = Init Config Mode bit 0
977 * LSB BIT 5 = Init Config Mode bit 1
978 * LSB BIT 6 = Init Config Mode bit 2
979 * LSB BIT 7 = Enable Non part on LIHA failure
981 * MSB BIT 0 = Enable class 2
982 * MSB BIT 1 = Enable ACK0
985 * MSB BIT 4 = FC Tape Enable
986 * MSB BIT 5 = Enable FC Confirm
987 * MSB BIT 6 = Enable command queuing in target mode
988 * MSB BIT 7 = No Logo On Link Down
990 uint8_t add_firmware_options[2];
992 uint8_t response_accumulation_timer;
993 uint8_t interrupt_delay_timer;
996 * LSB BIT 0 = Enable Read xfr_rdy
997 * LSB BIT 1 = Soft ID only
1000 * LSB BIT 4 = FCP RSP Payload [0]
1001 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1002 * LSB BIT 6 = Enable Out-of-Order frame handling
1003 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1005 * MSB BIT 0 = Sbus enable - 2300
1010 * MSB BIT 5 = enable 50 ohm termination
1011 * MSB BIT 6 = Data Rate (2300 only)
1012 * MSB BIT 7 = Data Rate (2300 only)
1014 uint8_t special_options[2];
1016 /* Reserved for expanded RISC parameter block */
1017 uint8_t reserved_2[24];
1020 * LSB BIT 0 = Output Swing 1G bit 0
1021 * LSB BIT 1 = Output Swing 1G bit 1
1022 * LSB BIT 2 = Output Swing 1G bit 2
1023 * LSB BIT 3 = Output Emphasis 1G bit 0
1024 * LSB BIT 4 = Output Emphasis 1G bit 1
1025 * LSB BIT 5 = Output Swing 2G bit 0
1026 * LSB BIT 6 = Output Swing 2G bit 1
1027 * LSB BIT 7 = Output Swing 2G bit 2
1029 * MSB BIT 0 = Output Emphasis 2G bit 0
1030 * MSB BIT 1 = Output Emphasis 2G bit 1
1031 * MSB BIT 2 = Output Enable
1038 uint8_t seriallink_options[2];
1041 * NVRAM host parameter block
1043 * LSB BIT 0 = Enable spinup delay
1044 * LSB BIT 1 = Disable BIOS
1045 * LSB BIT 2 = Enable Memory Map BIOS
1046 * LSB BIT 3 = Enable Selectable Boot
1047 * LSB BIT 4 = Disable RISC code load
1048 * LSB BIT 5 = Set cache line size 1
1049 * LSB BIT 6 = PCI Parity Disable
1050 * LSB BIT 7 = Enable extended logging
1052 * MSB BIT 0 = Enable 64bit addressing
1053 * MSB BIT 1 = Enable lip reset
1054 * MSB BIT 2 = Enable lip full login
1055 * MSB BIT 3 = Enable target reset
1056 * MSB BIT 4 = Enable database storage
1057 * MSB BIT 5 = Enable cache flush read
1058 * MSB BIT 6 = Enable database load
1059 * MSB BIT 7 = Enable alternate WWN
1063 uint8_t boot_node_name[WWN_SIZE];
1064 uint8_t boot_lun_number;
1065 uint8_t reset_delay;
1066 uint8_t port_down_retry_count;
1067 uint8_t boot_id_number;
1068 uint16_t max_luns_per_target;
1069 uint8_t fcode_boot_port_name[WWN_SIZE];
1070 uint8_t alternate_port_name[WWN_SIZE];
1071 uint8_t alternate_node_name[WWN_SIZE];
1074 * BIT 0 = Boot Zoning
1075 * BIT 1 = Alt-Boot Enable
1076 * BIT 2 = Report SCSI Path
1083 uint8_t efi_parameters;
1085 uint8_t link_down_timeout;
1087 uint8_t adapter_id_0[4];
1088 uint8_t adapter_id_1[4];
1089 uint8_t adapter_id_2[4];
1090 uint8_t adapter_id_3[4];
1092 uint8_t alt1_boot_node_name[WWN_SIZE];
1093 uint16_t alt1_boot_lun_number;
1094 uint8_t alt2_boot_node_name[WWN_SIZE];
1095 uint16_t alt2_boot_lun_number;
1096 uint8_t alt3_boot_node_name[WWN_SIZE];
1097 uint16_t alt3_boot_lun_number;
1098 uint8_t alt4_boot_node_name[WWN_SIZE];
1099 uint16_t alt4_boot_lun_number;
1100 uint8_t alt5_boot_node_name[WWN_SIZE];
1101 uint16_t alt5_boot_lun_number;
1102 uint8_t alt6_boot_node_name[WWN_SIZE];
1103 uint16_t alt6_boot_lun_number;
1104 uint8_t alt7_boot_node_name[WWN_SIZE];
1105 uint16_t alt7_boot_lun_number;
1107 uint8_t reserved_3[2];
1109 /* Offset 200-215 : Model Number */
1110 uint8_t model_number[16];
1112 /* OEM related items */
1113 uint8_t oem_specific[16];
1116 * NVRAM Adapter Features offset 232-239
1118 * LSB BIT 0 = External GBIC
1119 * LSB BIT 1 = Risc RAM parity
1120 * LSB BIT 2 = Buffer Plus Module
1121 * LSB BIT 3 = Multi Chip Adapter
1122 * LSB BIT 4 = Internal connector
1136 uint8_t adapter_features[2];
1138 uint8_t reserved_4[16];
1140 /* Subsystem vendor ID for ISP2200 */
1141 uint16_t subsystem_vendor_id_2200;
1143 /* Subsystem device ID for ISP2200 */
1144 uint16_t subsystem_device_id_2200;
1151 * ISP queue - response queue entry definition.
1156 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
1167 #define SET_TARGET_ID(ha, to, from) \
1169 if (HAS_EXTENDED_IDS(ha)) \
1170 to.extended = cpu_to_le16(from); \
1172 to.id.standard = (uint8_t)from; \
1176 * ISP queue - command entry structure definition.
1178 #define COMMAND_TYPE 0x11 /* Command entry */
1179 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
1181 uint8_t entry_type; /* Entry type. */
1182 uint8_t entry_count; /* Entry count. */
1183 uint8_t sys_define; /* System defined. */
1184 uint8_t entry_status; /* Entry Status. */
1185 uint32_t handle; /* System handle. */
1186 target_id_t target; /* SCSI ID */
1187 uint16_t lun; /* SCSI LUN */
1188 uint16_t control_flags; /* Control flags. */
1189 #define CF_WRITE BIT_6
1190 #define CF_READ BIT_5
1191 #define CF_SIMPLE_TAG BIT_3
1192 #define CF_ORDERED_TAG BIT_2
1193 #define CF_HEAD_TAG BIT_1
1194 uint16_t reserved_1;
1195 uint16_t timeout; /* Command timeout. */
1196 uint16_t dseg_count; /* Data segment count. */
1197 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1198 uint32_t byte_count; /* Total byte count. */
1199 uint32_t dseg_0_address; /* Data segment 0 address. */
1200 uint32_t dseg_0_length; /* Data segment 0 length. */
1201 uint32_t dseg_1_address; /* Data segment 1 address. */
1202 uint32_t dseg_1_length; /* Data segment 1 length. */
1203 uint32_t dseg_2_address; /* Data segment 2 address. */
1204 uint32_t dseg_2_length; /* Data segment 2 length. */
1208 * ISP queue - 64-Bit addressing, command entry structure definition.
1210 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */
1212 uint8_t entry_type; /* Entry type. */
1213 uint8_t entry_count; /* Entry count. */
1214 uint8_t sys_define; /* System defined. */
1215 uint8_t entry_status; /* Entry Status. */
1216 uint32_t handle; /* System handle. */
1217 target_id_t target; /* SCSI ID */
1218 uint16_t lun; /* SCSI LUN */
1219 uint16_t control_flags; /* Control flags. */
1220 uint16_t reserved_1;
1221 uint16_t timeout; /* Command timeout. */
1222 uint16_t dseg_count; /* Data segment count. */
1223 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1224 uint32_t byte_count; /* Total byte count. */
1225 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1226 uint32_t dseg_0_length; /* Data segment 0 length. */
1227 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1228 uint32_t dseg_1_length; /* Data segment 1 length. */
1229 } cmd_a64_entry_t, request_t;
1232 * ISP queue - continuation entry structure definition.
1234 #define CONTINUE_TYPE 0x02 /* Continuation entry. */
1236 uint8_t entry_type; /* Entry type. */
1237 uint8_t entry_count; /* Entry count. */
1238 uint8_t sys_define; /* System defined. */
1239 uint8_t entry_status; /* Entry Status. */
1241 uint32_t dseg_0_address; /* Data segment 0 address. */
1242 uint32_t dseg_0_length; /* Data segment 0 length. */
1243 uint32_t dseg_1_address; /* Data segment 1 address. */
1244 uint32_t dseg_1_length; /* Data segment 1 length. */
1245 uint32_t dseg_2_address; /* Data segment 2 address. */
1246 uint32_t dseg_2_length; /* Data segment 2 length. */
1247 uint32_t dseg_3_address; /* Data segment 3 address. */
1248 uint32_t dseg_3_length; /* Data segment 3 length. */
1249 uint32_t dseg_4_address; /* Data segment 4 address. */
1250 uint32_t dseg_4_length; /* Data segment 4 length. */
1251 uint32_t dseg_5_address; /* Data segment 5 address. */
1252 uint32_t dseg_5_length; /* Data segment 5 length. */
1253 uint32_t dseg_6_address; /* Data segment 6 address. */
1254 uint32_t dseg_6_length; /* Data segment 6 length. */
1258 * ISP queue - 64-Bit addressing, continuation entry structure definition.
1260 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */
1262 uint8_t entry_type; /* Entry type. */
1263 uint8_t entry_count; /* Entry count. */
1264 uint8_t sys_define; /* System defined. */
1265 uint8_t entry_status; /* Entry Status. */
1266 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1267 uint32_t dseg_0_length; /* Data segment 0 length. */
1268 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1269 uint32_t dseg_1_length; /* Data segment 1 length. */
1270 uint32_t dseg_2_address [2]; /* Data segment 2 address. */
1271 uint32_t dseg_2_length; /* Data segment 2 length. */
1272 uint32_t dseg_3_address[2]; /* Data segment 3 address. */
1273 uint32_t dseg_3_length; /* Data segment 3 length. */
1274 uint32_t dseg_4_address[2]; /* Data segment 4 address. */
1275 uint32_t dseg_4_length; /* Data segment 4 length. */
1279 * ISP queue - status entry structure definition.
1281 #define STATUS_TYPE 0x03 /* Status entry. */
1283 uint8_t entry_type; /* Entry type. */
1284 uint8_t entry_count; /* Entry count. */
1285 uint8_t sys_define; /* System defined. */
1286 uint8_t entry_status; /* Entry Status. */
1287 uint32_t handle; /* System handle. */
1288 uint16_t scsi_status; /* SCSI status. */
1289 uint16_t comp_status; /* Completion status. */
1290 uint16_t state_flags; /* State flags. */
1291 uint16_t status_flags; /* Status flags. */
1292 uint16_t rsp_info_len; /* Response Info Length. */
1293 uint16_t req_sense_length; /* Request sense data length. */
1294 uint32_t residual_length; /* Residual transfer length. */
1295 uint8_t rsp_info[8]; /* FCP response information. */
1296 uint8_t req_sense_data[32]; /* Request sense data. */
1300 * Status entry entry status
1302 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
1303 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
1304 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
1305 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
1306 #define RF_BUSY BIT_1 /* Busy */
1309 * Status entry SCSI status bit definitions.
1311 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
1312 #define SS_RESIDUAL_UNDER BIT_11
1313 #define SS_RESIDUAL_OVER BIT_10
1314 #define SS_SENSE_LEN_VALID BIT_9
1315 #define SS_RESIDUAL_LEN_VALID BIT_8 /* ISP2100 only */
1316 #define SS_RESPONSE_INFO_LEN_VALID BIT_8 /* ISP2200 and 23xx */
1318 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
1319 #define SS_BUSY_CONDITION BIT_3
1320 #define SS_CONDITION_MET BIT_2
1321 #define SS_CHECK_CONDITION BIT_1
1324 * Status entry completion status
1326 #define CS_COMPLETE 0x0 /* No errors */
1327 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
1328 #define CS_DMA 0x2 /* A DMA direction error. */
1329 #define CS_TRANSPORT 0x3 /* Transport error. */
1330 #define CS_RESET 0x4 /* SCSI bus reset occurred */
1331 #define CS_ABORTED 0x5 /* System aborted command. */
1332 #define CS_TIMEOUT 0x6 /* Timeout error. */
1333 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */
1335 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
1336 #define CS_QUEUE_FULL 0x1C /* Queue Full. */
1337 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */
1338 /* (selection timeout) */
1339 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */
1340 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */
1341 #define CS_PORT_BUSY 0x2B /* Port Busy */
1342 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */
1343 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */
1344 #define CS_UNKNOWN 0x81 /* Driver defined */
1345 #define CS_RETRY 0x82 /* Driver defined */
1346 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */
1349 * Status entry status flags
1351 #define SF_LOGOUT_SENT BIT_13
1354 * ISP queue - status continuation entry structure definition.
1356 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */
1358 uint8_t entry_type; /* Entry type. */
1359 uint8_t entry_count; /* Entry count. */
1360 uint8_t sys_define; /* System defined. */
1361 uint8_t entry_status; /* Entry Status. */
1362 uint8_t data[60]; /* data */
1366 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles)
1367 * structure definition.
1369 #define STATUS_TYPE_21 0x21 /* Status entry. */
1371 uint8_t entry_type; /* Entry type. */
1372 uint8_t entry_count; /* Entry count. */
1373 uint8_t handle_count; /* Handle count. */
1374 uint8_t entry_status; /* Entry Status. */
1375 uint32_t handle[15]; /* System handles. */
1379 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles)
1380 * structure definition.
1382 #define STATUS_TYPE_22 0x22 /* Status entry. */
1384 uint8_t entry_type; /* Entry type. */
1385 uint8_t entry_count; /* Entry count. */
1386 uint8_t handle_count; /* Handle count. */
1387 uint8_t entry_status; /* Entry Status. */
1388 uint16_t handle[30]; /* System handles. */
1392 * ISP queue - marker entry structure definition.
1394 #define MARKER_TYPE 0x04 /* Marker entry. */
1396 uint8_t entry_type; /* Entry type. */
1397 uint8_t entry_count; /* Entry count. */
1398 uint8_t handle_count; /* Handle count. */
1399 uint8_t entry_status; /* Entry Status. */
1400 uint32_t sys_define_2; /* System defined. */
1401 target_id_t target; /* SCSI ID */
1402 uint8_t modifier; /* Modifier (7-0). */
1403 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
1404 #define MK_SYNC_ID 1 /* Synchronize ID */
1405 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
1406 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */
1407 /* clear port changed, */
1408 /* use sequence number. */
1410 uint16_t sequence_number; /* Sequence number of event */
1411 uint16_t lun; /* SCSI LUN */
1412 uint8_t reserved_2[48];
1416 * ISP queue - Management Server entry structure definition.
1418 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */
1420 uint8_t entry_type; /* Entry type. */
1421 uint8_t entry_count; /* Entry count. */
1422 uint8_t handle_count; /* Handle count. */
1423 uint8_t entry_status; /* Entry Status. */
1424 uint32_t handle1; /* System handle. */
1425 target_id_t loop_id;
1427 uint16_t control_flags; /* Control flags. */
1430 uint16_t cmd_dsd_count;
1431 uint16_t total_dsd_count;
1437 uint32_t rsp_bytecount;
1438 uint32_t req_bytecount;
1439 uint32_t dseg_req_address[2]; /* Data segment 0 address. */
1440 uint32_t dseg_req_length; /* Data segment 0 length. */
1441 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */
1442 uint32_t dseg_rsp_length; /* Data segment 1 length. */
1447 * ISP queue - Mailbox Command entry structure definition.
1449 #define MBX_IOCB_TYPE 0x39
1452 uint8_t entry_count;
1453 uint8_t sys_define1;
1454 /* Use sys_define1 for source type */
1455 #define SOURCE_SCSI 0x00
1456 #define SOURCE_IP 0x01
1457 #define SOURCE_VI 0x02
1458 #define SOURCE_SCTP 0x03
1459 #define SOURCE_MP 0x04
1460 #define SOURCE_MPIOCTL 0x05
1461 #define SOURCE_ASYNC_IOCB 0x07
1463 uint8_t entry_status;
1466 target_id_t loop_id;
1469 uint16_t state_flags;
1470 uint16_t status_flags;
1472 uint32_t sys_define2[2];
1482 uint32_t reserved_2[2];
1483 uint8_t node_name[WWN_SIZE];
1484 uint8_t port_name[WWN_SIZE];
1488 * ISP request and response queue entry sizes
1490 #define RESPONSE_ENTRY_SIZE (sizeof(response_t))
1491 #define REQUEST_ENTRY_SIZE (sizeof(request_t))
1495 * 24 bit port ID type definition.
1512 #define INVALID_PORT_ID 0xFFFFFF
1515 * Switch info gathering structure.
1519 uint8_t node_name[WWN_SIZE];
1520 uint8_t port_name[WWN_SIZE];
1522 #define SW_TYPE_IP BIT_1
1523 #define SW_TYPE_SCSI BIT_0
1527 * Inquiry command structure.
1529 #define INQ_DATA_SIZE 36
1532 * Inquiry mailbox IOCB packet definition.
1536 cmd_a64_entry_t cmd;
1539 uint8_t inq[INQ_DATA_SIZE];
1543 * Report LUN command structure.
1545 #define CHAR_TO_SHORT(a, b) (uint16_t)((uint8_t)b << 8 | (uint8_t)a)
1555 uint8_t address_method : 2;
1563 rpt_lun_t lst[MAX_LUNS];
1567 * Report Lun mailbox IOCB packet definition.
1571 cmd_a64_entry_t cmd;
1575 } rpt_lun_cmd_rsp_t;
1578 * SCSI Target Queue structure
1580 typedef struct os_tgt {
1581 struct os_lun *olun[MAX_LUNS]; /* LUN context pointer. */
1582 struct fc_port *fcport;
1583 unsigned long flags;
1584 uint8_t port_down_retry_count;
1585 uint32_t down_timer;
1586 struct scsi_qla_host *ha;
1588 /* Persistent binding information */
1590 uint8_t node_name[WWN_SIZE];
1591 uint8_t port_name[WWN_SIZE];
1595 * SCSI Target Queue flags
1597 #define TQF_ONLINE 0 /* Device online to OS. */
1598 #define TQF_SUSPENDED 1
1599 #define TQF_RETRY_CMDS 2
1602 * SCSI LUN Queue structure
1604 typedef struct os_lun {
1605 struct fc_lun *fclun; /* FC LUN context pointer. */
1606 spinlock_t q_lock; /* Lun Lock */
1608 unsigned long q_flag;
1609 #define LUN_MPIO_BUSY 2 /* Lun is changing paths */
1610 #define LUN_EXEC_DELAYED 7 /* Lun execution is delayed */
1612 u_long q_timeout; /* total command timeouts */
1613 atomic_t q_timer; /* suspend timer */
1614 uint32_t q_count; /* current count */
1615 uint32_t q_max; /* maxmum count lun can be suspended */
1616 uint8_t q_state; /* lun State */
1617 #define LUN_STATE_READY 1 /* lun is ready for i/o */
1618 #define LUN_STATE_RUN 2 /* lun has a timer running */
1619 #define LUN_STATE_WAIT 3 /* lun is suspended */
1620 #define LUN_STATE_TIMEOUT 4 /* lun has timed out */
1622 u_long io_cnt; /* total xfer count since boot */
1623 u_long out_cnt; /* total outstanding IO count */
1624 u_long w_cnt; /* total writes */
1625 u_long r_cnt; /* total reads */
1626 u_long avg_time; /* */
1630 /* LUN BitMask structure definition, array of 32bit words,
1631 * 1 bit per lun. When bit == 1, the lun is masked.
1632 * Most significant bit of mask[0] is lun 0, bit 24 is lun 7.
1634 typedef struct lun_bit_mask {
1635 /* Must allocate at least enough bits to accomodate all LUNs */
1636 #if ((MAX_FIBRE_LUNS & 0x7) == 0)
1637 uint8_t mask[MAX_FIBRE_LUNS >> 3];
1639 uint8_t mask[(MAX_FIBRE_LUNS + 8) >> 3];
1644 * Fibre channel port type.
1656 * Fibre channel port structure.
1658 typedef struct fc_port {
1659 struct list_head list;
1660 struct list_head fcluns;
1662 struct scsi_qla_host *ha;
1663 struct scsi_qla_host *vis_ha; /* only used when suspending lun */
1665 uint8_t node_name[WWN_SIZE];
1666 uint8_t port_name[WWN_SIZE];
1669 uint16_t old_loop_id;
1671 fc_port_type_t port_type;
1676 os_tgt_t *tgt_queue;
1677 uint16_t os_target_id;
1679 uint16_t iodesc_idx_sent;
1681 int port_login_retry_count;
1683 atomic_t port_down_timer;
1685 uint8_t device_type;
1688 uint8_t mp_byte; /* multi-path byte (not used) */
1689 uint8_t cur_path; /* current path id */
1691 lun_bit_mask_t lun_mask;
1695 * Fibre channel port/lun states.
1697 #define FCS_UNCONFIGURED 1
1698 #define FCS_DEVICE_DEAD 2
1699 #define FCS_DEVICE_LOST 3
1700 #define FCS_ONLINE 4
1701 #define FCS_NOT_SUPPORTED 5
1702 #define FCS_FAILOVER 6
1703 #define FCS_FAILOVER_FAILED 7
1708 #define FCF_FABRIC_DEVICE BIT_0
1709 #define FCF_LOGIN_NEEDED BIT_1
1710 #define FCF_FO_MASKED BIT_2
1711 #define FCF_FAILOVER_NEEDED BIT_3
1712 #define FCF_RESET_NEEDED BIT_4
1713 #define FCF_PERSISTENT_BOUND BIT_5
1714 #define FCF_TAPE_PRESENT BIT_6
1715 #define FCF_FARP_DONE BIT_7
1716 #define FCF_FARP_FAILED BIT_8
1717 #define FCF_FARP_REPLY_NEEDED BIT_9
1718 #define FCF_AUTH_REQ BIT_10
1719 #define FCF_SEND_AUTH_REQ BIT_11
1720 #define FCF_RECEIVE_AUTH_REQ BIT_12
1721 #define FCF_AUTH_SUCCESS BIT_13
1722 #define FCF_RLC_SUPPORT BIT_14
1723 #define FCF_CONFIG BIT_15 /* Needed? */
1724 #define FCF_RESCAN_NEEDED BIT_16
1725 #define FCF_XP_DEVICE BIT_17
1726 #define FCF_MSA_DEVICE BIT_18
1727 #define FCF_EVA_DEVICE BIT_19
1728 #define FCF_MSA_PORT_ACTIVE BIT_20
1729 #define FCF_FAILBACK_DISABLE BIT_21
1730 #define FCF_FAILOVER_DISABLE BIT_22
1732 /* No loop ID flag. */
1733 #define FC_NO_LOOP_ID 0x1000
1736 * Fibre channel LUN structure.
1738 typedef struct fc_lun {
1739 struct list_head list;
1742 fc_port_t *o_fcport;
1745 uint8_t device_type;
1747 uint8_t max_path_retries;
1751 #define FLF_VISIBLE_LUN BIT_0
1752 #define FLF_ACTIVE_LUN BIT_1
1757 * NOTE: All structures are big-endian in form.
1760 #define CT_REJECT_RESPONSE 0x8001
1761 #define CT_ACCEPT_RESPONSE 0x8002
1763 #define NS_N_PORT_TYPE 0x01
1764 #define NS_NL_PORT_TYPE 0x02
1765 #define NS_NX_PORT_TYPE 0x7F
1767 #define GA_NXT_CMD 0x100
1768 #define GA_NXT_REQ_SIZE (16 + 4)
1769 #define GA_NXT_RSP_SIZE (16 + 620)
1771 #define GID_PT_CMD 0x1A1
1772 #define GID_PT_REQ_SIZE (16 + 4)
1773 #define GID_PT_RSP_SIZE (16 + (MAX_FIBRE_DEVICES * 4))
1775 #define GPN_ID_CMD 0x112
1776 #define GPN_ID_REQ_SIZE (16 + 4)
1777 #define GPN_ID_RSP_SIZE (16 + 8)
1779 #define GNN_ID_CMD 0x113
1780 #define GNN_ID_REQ_SIZE (16 + 4)
1781 #define GNN_ID_RSP_SIZE (16 + 8)
1783 #define GFT_ID_CMD 0x117
1784 #define GFT_ID_REQ_SIZE (16 + 4)
1785 #define GFT_ID_RSP_SIZE (16 + 32)
1787 #define RFT_ID_CMD 0x217
1788 #define RFT_ID_REQ_SIZE (16 + 4 + 32)
1789 #define RFT_ID_RSP_SIZE 16
1791 #define RFF_ID_CMD 0x21F
1792 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
1793 #define RFF_ID_RSP_SIZE 16
1795 #define RNN_ID_CMD 0x213
1796 #define RNN_ID_REQ_SIZE (16 + 4 + 8)
1797 #define RNN_ID_RSP_SIZE 16
1799 #define RSNN_NN_CMD 0x239
1800 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
1801 #define RSNN_NN_RSP_SIZE 16
1803 /* CT command header -- request/response common fields */
1813 /* CT command request */
1815 struct ct_cmd_hdr header;
1817 uint16_t max_rsp_size;
1818 uint8_t fragment_id;
1819 uint8_t reserved[3];
1822 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID */
1838 uint8_t fc4_types[32];
1845 uint8_t fc4_feature;
1852 uint8_t node_name[8];
1856 uint8_t node_name[8];
1858 uint8_t sym_node_name[255];
1863 /* CT command response header */
1865 struct ct_cmd_hdr header;
1868 uint8_t fragment_id;
1869 uint8_t reason_code;
1870 uint8_t explanation_code;
1871 uint8_t vendor_unique;
1874 struct ct_sns_gid_pt_data {
1875 uint8_t control_byte;
1880 struct ct_rsp_hdr header;
1886 uint8_t port_name[8];
1887 uint8_t sym_port_name_len;
1888 uint8_t sym_port_name[255];
1889 uint8_t node_name[8];
1890 uint8_t sym_node_name_len;
1891 uint8_t sym_node_name[255];
1892 uint8_t init_proc_assoc[8];
1893 uint8_t node_ip_addr[16];
1894 uint8_t class_of_service[4];
1895 uint8_t fc4_types[32];
1896 uint8_t ip_address[16];
1897 uint8_t fabric_port_name[8];
1899 uint8_t hard_address[3];
1903 struct ct_sns_gid_pt_data entries[MAX_FIBRE_DEVICES];
1907 uint8_t port_name[8];
1911 uint8_t node_name[8];
1915 uint8_t fc4_types[32];
1922 struct ct_sns_req req;
1923 struct ct_sns_rsp rsp;
1928 * SNS command structures -- for 2200 compatability.
1930 #define RFT_ID_SNS_SCMD_LEN 22
1931 #define RFT_ID_SNS_CMD_SIZE 60
1932 #define RFT_ID_SNS_DATA_SIZE 16
1934 #define RFF_ID_SNS_SCMD_LEN 8
1935 #define RFF_ID_SNS_CMD_SIZE 32
1936 #define RFF_ID_SNS_DATA_SIZE 16
1938 #define RNN_ID_SNS_SCMD_LEN 10
1939 #define RNN_ID_SNS_CMD_SIZE 36
1940 #define RNN_ID_SNS_DATA_SIZE 16
1942 #define GA_NXT_SNS_SCMD_LEN 6
1943 #define GA_NXT_SNS_CMD_SIZE 28
1944 #define GA_NXT_SNS_DATA_SIZE (620 + 16)
1946 #define GID_PT_SNS_SCMD_LEN 6
1947 #define GID_PT_SNS_CMD_SIZE 28
1948 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES * 4 + 16)
1950 #define GPN_ID_SNS_SCMD_LEN 6
1951 #define GPN_ID_SNS_CMD_SIZE 28
1952 #define GPN_ID_SNS_DATA_SIZE (8 + 16)
1954 #define GNN_ID_SNS_SCMD_LEN 6
1955 #define GNN_ID_SNS_CMD_SIZE 28
1956 #define GNN_ID_SNS_DATA_SIZE (8 + 16)
1958 struct sns_cmd_pkt {
1961 uint16_t buffer_length;
1962 uint16_t reserved_1;
1963 uint32_t buffer_address[2];
1964 uint16_t subcommand_length;
1965 uint16_t reserved_2;
1966 uint16_t subcommand;
1968 uint32_t reserved_3;
1972 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
1973 uint8_t rff_data[RFF_ID_SNS_DATA_SIZE];
1974 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
1975 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
1976 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
1977 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
1978 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
1982 /* IO descriptors */
1983 #define MAX_IO_DESCRIPTORS 32
1985 #define ABORT_IOCB_CB 0
1986 #define ADISC_PORT_IOCB_CB 1
1987 #define LOGOUT_PORT_IOCB_CB 2
1988 #define LOGIN_PORT_IOCB_CB 3
1989 #define LAST_IOCB_CB 4
1991 #define IODESC_INVALID_INDEX 0xFFFF
1992 #define IODESC_ADISC_NEEDED 0xFFFE
1993 #define IODESC_LOGIN_NEEDED 0xFFFD
1995 struct io_descriptor {
2000 struct timer_list timer;
2002 struct scsi_qla_host *ha;
2005 fc_port_t *remote_fcport;
2010 struct qla_fw_info {
2011 unsigned short addressing; /* addressing method used to load fw */
2012 #define FW_INFO_ADDR_NORMAL 0
2013 #define FW_INFO_ADDR_EXTENDED 1
2014 #define FW_INFO_ADDR_NOMORE 0xffff
2015 unsigned short *fwcode; /* pointer to FW array */
2016 unsigned short *fwlen; /* number of words in array */
2017 unsigned short *fwstart; /* start address for F/W */
2018 unsigned long *lfwstart; /* start address (long) for F/W */
2021 struct qla_board_info {
2025 struct qla_fw_info *fw_info;
2029 * Linux Host Adapter structure
2031 typedef struct scsi_qla_host {
2032 struct list_head list;
2034 /* Commonly used flags and state information. */
2035 struct Scsi_Host *host;
2036 struct pci_dev *pdev;
2038 unsigned long host_no;
2039 unsigned long instance;
2042 uint32_t init_done :1;
2044 uint32_t mbox_int :1;
2045 uint32_t mbox_busy :1;
2046 uint32_t rscn_queue_overflow :1;
2047 uint32_t reset_active :1;
2049 uint32_t management_server_logged_in :1;
2050 uint32_t process_response_queue :1;
2052 uint32_t disable_risc_code_load :1;
2053 uint32_t enable_64bit_addressing :1;
2054 uint32_t enable_lip_reset :1;
2055 uint32_t enable_lip_full_login :1;
2056 uint32_t enable_target_reset :1;
2059 atomic_t loop_state;
2060 #define LOOP_TIMEOUT 1
2063 #define LOOP_UPDATE 4
2064 #define LOOP_READY 5
2067 unsigned long dpc_flags;
2068 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */
2069 #define RESET_ACTIVE 1
2070 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */
2071 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */
2072 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */
2073 #define LOOP_RESYNC_ACTIVE 5
2074 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */
2075 #define RSCN_UPDATE 7 /* Perform an RSCN update. */
2076 #define MAILBOX_RETRY 8
2077 #define ISP_RESET_NEEDED 9 /* Initiate a ISP reset. */
2078 #define FAILOVER_EVENT_NEEDED 10
2079 #define FAILOVER_EVENT 11
2080 #define FAILOVER_NEEDED 12
2081 #define SCSI_RESTART_NEEDED 13 /* Processes SCSI retry queue. */
2082 #define PORT_RESTART_NEEDED 14 /* Processes Retry queue. */
2083 #define RESTART_QUEUES_NEEDED 15 /* Restarts the Lun queue. */
2084 #define ABORT_QUEUES_NEEDED 16
2085 #define RELOGIN_NEEDED 17
2086 #define LOGIN_RETRY_NEEDED 18 /* Initiate required fabric logins. */
2087 #define REGISTER_FC4_NEEDED 19 /* SNS FC4 registration required. */
2088 #define ISP_ABORT_RETRY 20 /* ISP aborted. */
2089 #define FCPORT_RESCAN_NEEDED 21 /* IO descriptor processing needed */
2090 #define IODESC_PROCESS_NEEDED 22 /* IO descriptor processing needed */
2091 #define IOCTL_ERROR_RECOVERY 23
2093 uint32_t device_flags;
2094 #define DFLG_LOCAL_DEVICES BIT_0
2095 #define DFLG_RETRY_LOCAL_DEVICES BIT_1
2096 #define DFLG_FABRIC_DEVICES BIT_2
2097 #define SWITCH_FOUND BIT_3
2098 #define DFLG_NO_CABLE BIT_4
2101 #define SRB_MIN_REQ 128
2102 mempool_t *srb_mempool;
2104 /* This spinlock is used to protect "io transactions", you must
2105 * aquire it before doing any IO to the card, eg with RD_REG*() and
2106 * WRT_REG*() for the duration of your entire commandtransaction.
2108 * This spinlock is of lower priority than the io request lock.
2111 spinlock_t hardware_lock ____cacheline_aligned;
2113 device_reg_t *iobase; /* Base I/O address */
2114 unsigned long pio_address;
2115 unsigned long pio_length;
2116 void * mmio_address;
2117 unsigned long mmio_length;
2118 #define MIN_IOBASE_LEN 0x100
2120 /* ISP ring lock, rings, and indexes */
2121 dma_addr_t request_dma; /* Physical address. */
2122 request_t *request_ring; /* Base virtual address */
2123 request_t *request_ring_ptr; /* Current address. */
2124 uint16_t req_ring_index; /* Current index. */
2125 uint16_t req_q_cnt; /* Number of available entries. */
2127 dma_addr_t response_dma; /* Physical address. */
2128 response_t *response_ring; /* Base virtual address */
2129 response_t *response_ring_ptr; /* Current address. */
2130 uint16_t rsp_ring_index; /* Current index. */
2131 uint16_t response_q_length;
2133 uint16_t (*calc_request_entries)(uint16_t);
2134 void (*build_scsi_iocbs)(srb_t *, cmd_entry_t *, uint16_t);
2136 /* Outstandings ISP commands. */
2137 srb_t *outstanding_cmds[MAX_OUTSTANDING_COMMANDS];
2138 uint32_t current_outstanding_cmd;
2139 srb_t *status_srb; /* Status continuation entry. */
2142 * Need to hold the list_lock with irq's disabled in order to access
2143 * the following list.
2145 * This list_lock is of lower priority than the host_lock.
2147 spinlock_t list_lock ____cacheline_aligned;
2148 /* lock to guard lists which
2150 struct list_head retry_queue; /* watchdog queue */
2151 struct list_head done_queue; /* job on done queue */
2152 struct list_head failover_queue; /* failover list link. */
2153 struct list_head scsi_retry_queue; /* SCSI retry queue */
2154 struct list_head pending_queue; /* SCSI command pending queue */
2156 unsigned long done_q_cnt;
2157 unsigned long pending_in_q;
2158 uint32_t retry_q_cnt;
2159 uint32_t scsi_retry_q_cnt;
2160 uint32_t failover_cnt;
2162 unsigned long last_irq_cpu; /* cpu where we got our last irq */
2170 uint32_t total_isr_cnt; /* Interrupt count */
2171 uint32_t total_isp_aborts; /* controller err cnt */
2172 uint32_t total_lip_cnt; /* LIP cnt */
2173 uint32_t total_dev_errs; /* device error cnt */
2174 uint32_t total_ios; /* IO cnt */
2175 uint64_t total_bytes; /* xfr byte cnt */
2176 uint32_t total_mbx_timeout; /* mailbox timeout cnt */
2177 uint32_t total_loop_resync; /* loop resyn cnt */
2178 uint32_t dropped_frame_error_cnt;
2180 /* ISP configuration data. */
2181 uint16_t loop_id; /* Host adapter loop id */
2184 port_id_t d_id; /* Host adapter port id */
2185 uint16_t max_public_loop_ids;
2186 uint16_t min_external_loopid; /* First external loop Id */
2188 uint16_t link_data_rate; /* F/W operating speed */
2190 uint8_t current_topology;
2191 uint8_t prev_topology;
2192 #define ISP_CFG_NL 1
2194 #define ISP_CFG_FL 4
2197 uint8_t operating_mode; /* F/W operating mode */
2203 uint8_t marker_needed;
2204 uint8_t sns_retry_cnt;
2207 uint8_t interrupts_on;
2209 /* HBA serial number */
2214 /* NVRAM configuration data */
2215 uint16_t nvram_base;
2217 uint16_t loop_reset_delay;
2218 uint16_t minimum_timeout;
2219 uint8_t retry_count;
2220 uint8_t login_timeout;
2222 int port_down_retry_count;
2223 uint8_t loop_down_timeout;
2225 uint16_t max_probe_luns;
2227 uint16_t max_targets;
2228 uint16_t last_loop_id;
2230 uint32_t login_retry_count;
2232 /* Fibre Channel Device List. */
2233 struct list_head fcports;
2234 struct list_head rscn_fcports;
2236 struct io_descriptor io_descriptors[MAX_IO_DESCRIPTORS];
2237 uint16_t iodesc_signature;
2238 port_database_t *iodesc_pd;
2239 dma_addr_t iodesc_pd_dma;
2241 /* OS target queue pointers. */
2242 os_tgt_t *otgt[MAX_FIBRE_DEVICES];
2245 uint32_t rscn_queue[MAX_RSCN_COUNT];
2246 uint8_t rscn_in_ptr;
2247 uint8_t rscn_out_ptr;
2249 /* SNS command interfaces. */
2250 ms_iocb_entry_t *ms_iocb;
2251 dma_addr_t ms_iocb_dma;
2252 struct ct_sns_pkt *ct_sns;
2253 dma_addr_t ct_sns_dma;
2254 /* SNS command interfaces for 2200. */
2255 struct sns_cmd_pkt *sns_cmd;
2256 dma_addr_t sns_cmd_dma;
2260 struct completion dpc_inited;
2261 struct completion dpc_exited;
2262 struct semaphore *dpc_wait;
2263 uint8_t dpc_active; /* DPC routine is active */
2265 /* Timeout timers. */
2266 uint8_t queue_restart_timer;
2267 uint8_t loop_down_abort_time; /* port down timer */
2268 atomic_t loop_down_timer; /* loop down timer */
2269 uint8_t link_down_timeout; /* link down timeout */
2271 uint32_t timer_active;
2272 struct timer_list timer;
2274 /* Firmware Initialization Control Block data */
2275 dma_addr_t init_cb_dma; /* Physical address. */
2278 /* These are used by mailbox operations. */
2279 volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
2282 unsigned long mbx_cmd_flags;
2283 #define MBX_INTERRUPT 1
2284 #define MBX_INTR_WAIT 2
2286 spinlock_t mbx_reg_lock; /* Mbx Cmd Register Lock */
2288 struct semaphore mbx_cmd_sem; /* Serialialize mbx access */
2289 struct semaphore mbx_intr_sem; /* Used for completion notification */
2292 #define MBX_IN_PROGRESS BIT_0
2293 #define MBX_BUSY BIT_1 /* Got the Access */
2294 #define MBX_SLEEPING_ON_SEM BIT_2
2295 #define MBX_POLLING_FOR_COMP BIT_3
2296 #define MBX_COMPLETED BIT_4
2297 #define MBX_TIMEDOUT BIT_5
2298 #define MBX_ACCESS_TIMEDOUT BIT_6
2304 uint32_t failover_type;
2305 uint32_t failback_delay;
2306 unsigned long cfg_flags;
2307 #define CFG_ACTIVE 0 /* CFG during a failover, event update, or ioctl */
2308 #define CFG_FAILOVER 1 /* CFG during path change */
2310 uint32_t binding_type;
2311 #define BIND_BY_PORT_NAME 0
2312 #define BIND_BY_PORT_ID 1
2314 /* Basic firmware related information. */
2315 struct qla_board_info *brd_info;
2316 uint16_t fw_major_version;
2317 uint16_t fw_minor_version;
2318 uint16_t fw_subminor_version;
2319 uint16_t fw_attributes;
2320 uint32_t fw_transfer_size;
2322 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
2323 uint8_t fw_seriallink_options[2];
2325 /* Firmware dump information. */
2328 int fw_dump_reading;
2329 char *fw_dump_buffer;
2330 int fw_dump_buffer_len;
2332 uint8_t host_str[16];
2335 uint16_t product_id[4];
2337 uint8_t model_number[16+1];
2338 #define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
2341 uint8_t node_name[WWN_SIZE];
2342 uint8_t nvram_version;
2343 uint8_t optrom_major;
2344 uint8_t optrom_minor;
2345 uint32_t isp_abort_cnt;
2347 /* Adapter I/O statistics for failover */
2348 uint64_t IosRequested;
2349 uint64_t BytesRequested;
2350 uint64_t IosExecuted;
2351 uint64_t BytesExecuted;
2353 /* Needed for BEACON */
2354 uint16_t beacon_blink_led;
2355 uint16_t beacon_green_on;
2360 * Macros to help code, maintain, etc.
2362 #define LOOP_TRANSITION(ha) \
2363 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
2364 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags))
2366 #define LOOP_NOT_READY(ha) \
2367 ((test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
2368 test_bit(ABORT_ISP_ACTIVE, &ha->dpc_flags) || \
2369 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
2370 test_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) || \
2371 atomic_read(&ha->loop_state) == LOOP_DOWN)
2373 #define LOOP_RDY(ha) (!LOOP_NOT_READY(ha))
2375 #define TGT_Q(ha, t) (ha->otgt[t])
2376 #define LUN_Q(ha, t, l) (TGT_Q(ha, t)->olun[l])
2377 #define GET_LU_Q(ha, t, l) ((TGT_Q(ha,t) != NULL)? TGT_Q(ha, t)->olun[l] : NULL)
2379 #define to_qla_host(x) ((scsi_qla_host_t *) (x)->hostdata)
2381 #define qla_printk(level, ha, format, arg...) \
2382 dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
2385 * qla2x00 local function return status codes
2387 #define MBS_MASK 0x3fff
2389 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
2390 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
2391 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
2392 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
2393 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
2394 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
2395 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
2396 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
2397 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
2398 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
2400 #define QLA_FUNCTION_TIMEOUT 0x100
2401 #define QLA_FUNCTION_PARAMETER_ERROR 0x101
2402 #define QLA_FUNCTION_FAILED 0x102
2403 #define QLA_MEMORY_ALLOC_FAILED 0x103
2404 #define QLA_LOCK_TIMEOUT 0x104
2405 #define QLA_ABORTED 0x105
2406 #define QLA_SUSPENDED 0x106
2407 #define QLA_BUSY 0x107
2408 #define QLA_RSCNS_HANDLED 0x108
2411 * Stat info for all adpaters
2413 struct _qla2x00stats {
2414 unsigned long mboxtout; /* mailbox timeouts */
2415 unsigned long mboxerr; /* mailbox errors */
2416 unsigned long ispAbort; /* ISP aborts */
2417 unsigned long debugNo;
2418 unsigned long loop_resync;
2419 unsigned long outarray_full;
2420 unsigned long retry_q_cnt;
2423 #define NVRAM_DELAY() udelay(10)
2425 #define INVALID_HANDLE (MAX_OUTSTANDING_COMMANDS+1)
2428 * Flash support definitions
2430 #define FLASH_IMAGE_SIZE 131072
2432 #include "qla_gbl.h"
2433 #include "qla_dbg.h"
2434 #include "qla_inline.h"
2435 #include "qla_listops.h"