2 * sata_promise.c - Promise SATA
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2003-2004 Red Hat, Inc.
10 * The contents of this file are subject to the Open
11 * Software License version 1.1 that can be found at
12 * http://www.opensource.org/licenses/osl-1.1.txt and is included herein
15 * Alternatively, the contents of this file may be used under the terms
16 * of the GNU General Public License version 2 (the "GPL") as distributed
17 * in the kernel source COPYING file, in which case the provisions of
18 * the GPL are applicable instead of the above. If you wish to allow
19 * the use of your version of this file only under the terms of the
20 * GPL and not to allow others to use your version of this file under
21 * the OSL, indicate your decision by deleting the provisions above and
22 * replace them with the notice and other provisions required by the GPL.
23 * If you do not delete the provisions above, a recipient may use your
24 * version of this file under either the OSL or the GPL.
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/init.h>
32 #include <linux/blkdev.h>
33 #include <linux/delay.h>
34 #include <linux/interrupt.h>
35 #include <linux/sched.h>
37 #include <scsi/scsi_host.h>
38 #include <linux/libata.h>
40 #include "sata_promise.h"
42 #define DRV_NAME "sata_promise"
43 #define DRV_VERSION "1.00"
47 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
48 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
49 PDC_TBG_MODE = 0x41, /* TBG mode */
50 PDC_FLASH_CTL = 0x44, /* Flash control register */
51 PDC_PCI_CTL = 0x48, /* PCI control and status register */
52 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
53 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
54 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
55 PDC_SLEW_CTL = 0x470, /* slew rate control reg */
57 PDC_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
58 (1<<8) | (1<<9) | (1<<10),
60 board_2037x = 0, /* FastTrak S150 TX2plus */
61 board_20319 = 1, /* FastTrak S150 TX4 */
63 PDC_HAS_PATA = (1 << 1), /* PDC20375 has PATA */
65 PDC_RESET = (1 << 11), /* HDMA reset */
69 struct pdc_port_priv {
74 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg);
75 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
76 static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
77 static void pdc_dma_start(struct ata_queued_cmd *qc);
78 static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
79 static void pdc_eng_timeout(struct ata_port *ap);
80 static int pdc_port_start(struct ata_port *ap);
81 static void pdc_port_stop(struct ata_port *ap);
82 static void pdc_phy_reset(struct ata_port *ap);
83 static void pdc_qc_prep(struct ata_queued_cmd *qc);
84 static void pdc_tf_load_mmio(struct ata_port *ap, struct ata_taskfile *tf);
85 static void pdc_exec_command_mmio(struct ata_port *ap, struct ata_taskfile *tf);
86 static inline void pdc_dma_complete (struct ata_port *ap,
87 struct ata_queued_cmd *qc, int have_err);
88 static void pdc_irq_clear(struct ata_port *ap);
89 static int pdc_qc_issue_prot(struct ata_queued_cmd *qc);
91 static Scsi_Host_Template pdc_sata_sht = {
92 .module = THIS_MODULE,
94 .queuecommand = ata_scsi_queuecmd,
95 .eh_strategy_handler = ata_scsi_error,
96 .can_queue = ATA_DEF_QUEUE,
97 .this_id = ATA_SHT_THIS_ID,
98 .sg_tablesize = LIBATA_MAX_PRD,
99 .max_sectors = ATA_MAX_SECTORS,
100 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
101 .emulated = ATA_SHT_EMULATED,
102 .use_clustering = ATA_SHT_USE_CLUSTERING,
103 .proc_name = DRV_NAME,
104 .dma_boundary = ATA_DMA_BOUNDARY,
105 .slave_configure = ata_scsi_slave_config,
106 .bios_param = ata_std_bios_param,
109 static struct ata_port_operations pdc_sata_ops = {
110 .port_disable = ata_port_disable,
111 .tf_load = pdc_tf_load_mmio,
112 .tf_read = ata_tf_read_mmio,
113 .check_status = ata_check_status_mmio,
114 .exec_command = pdc_exec_command_mmio,
115 .phy_reset = pdc_phy_reset,
116 .qc_prep = pdc_qc_prep,
117 .qc_issue = pdc_qc_issue_prot,
118 .eng_timeout = pdc_eng_timeout,
119 .irq_handler = pdc_interrupt,
120 .irq_clear = pdc_irq_clear,
121 .scr_read = pdc_sata_scr_read,
122 .scr_write = pdc_sata_scr_write,
123 .port_start = pdc_port_start,
124 .port_stop = pdc_port_stop,
127 static struct ata_port_info pdc_port_info[] = {
130 .sht = &pdc_sata_sht,
131 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
132 ATA_FLAG_SRST | ATA_FLAG_MMIO,
133 .pio_mask = 0x03, /* pio3-4 */
134 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
135 .port_ops = &pdc_sata_ops,
140 .sht = &pdc_sata_sht,
141 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
142 ATA_FLAG_SRST | ATA_FLAG_MMIO,
143 .pio_mask = 0x03, /* pio3-4 */
144 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
145 .port_ops = &pdc_sata_ops,
149 static struct pci_device_id pdc_sata_pci_tbl[] = {
150 { PCI_VENDOR_ID_PROMISE, 0x3371, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
152 { PCI_VENDOR_ID_PROMISE, 0x3373, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
154 { PCI_VENDOR_ID_PROMISE, 0x3375, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
156 { PCI_VENDOR_ID_PROMISE, 0x3376, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
158 { PCI_VENDOR_ID_PROMISE, 0x3318, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
160 { PCI_VENDOR_ID_PROMISE, 0x3319, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
162 { } /* terminate list */
166 static struct pci_driver pdc_sata_pci_driver = {
168 .id_table = pdc_sata_pci_tbl,
169 .probe = pdc_sata_init_one,
170 .remove = ata_pci_remove_one,
174 static int pdc_port_start(struct ata_port *ap)
176 struct pci_dev *pdev = ap->host_set->pdev;
177 struct pdc_port_priv *pp;
180 rc = ata_port_start(ap);
184 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
189 memset(pp, 0, sizeof(*pp));
191 pp->pkt = pci_alloc_consistent(pdev, 128, &pp->pkt_dma);
197 ap->private_data = pp;
209 static void pdc_port_stop(struct ata_port *ap)
211 struct pci_dev *pdev = ap->host_set->pdev;
212 struct pdc_port_priv *pp = ap->private_data;
214 ap->private_data = NULL;
215 pci_free_consistent(pdev, 128, pp->pkt, pp->pkt_dma);
221 static void pdc_reset_port(struct ata_port *ap)
223 void *mmio = (void *) ap->ioaddr.cmd_addr + PDC_CTLSTAT;
227 for (i = 11; i > 0; i--) {
240 readl(mmio); /* flush */
243 static void pdc_phy_reset(struct ata_port *ap)
249 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
251 if (sc_reg > SCR_CONTROL)
253 return readl((void *) ap->ioaddr.scr_addr + (sc_reg * 4));
257 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
260 if (sc_reg > SCR_CONTROL)
262 writel(val, (void *) ap->ioaddr.scr_addr + (sc_reg * 4));
265 static void pdc_qc_prep(struct ata_queued_cmd *qc)
267 struct pdc_port_priv *pp = qc->ap->private_data;
274 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma, qc->dev->devno, pp->pkt);
276 if (qc->tf.flags & ATA_TFLAG_LBA48)
277 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
279 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
281 pdc_pkt_footer(&qc->tf, pp->pkt, i);
284 static inline void pdc_dma_complete (struct ata_port *ap,
285 struct ata_queued_cmd *qc,
288 u8 err_bit = have_err ? ATA_ERR : 0;
290 /* get drive status; clear intr; complete txn */
291 ata_qc_complete(qc, ata_wait_idle(ap) | err_bit);
294 static void pdc_eng_timeout(struct ata_port *ap)
297 struct ata_queued_cmd *qc;
301 qc = ata_qc_from_tag(ap, ap->active_tag);
303 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
308 /* hack alert! We cannot use the supplied completion
309 * function from inside the ->eh_strategy_handler() thread.
310 * libata is the only user of ->eh_strategy_handler() in
311 * any kernel, so the default scsi_done() assumes it is
312 * not being called from the SCSI EH.
314 qc->scsidone = scsi_finish_command;
316 switch (qc->tf.protocol) {
318 printk(KERN_ERR "ata%u: DMA timeout\n", ap->id);
319 ata_qc_complete(qc, ata_wait_idle(ap) | ATA_ERR);
322 case ATA_PROT_NODATA:
323 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
325 printk(KERN_ERR "ata%u: command 0x%x timeout, stat 0x%x\n",
326 ap->id, qc->tf.command, drv_stat);
328 ata_qc_complete(qc, drv_stat);
332 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
334 printk(KERN_ERR "ata%u: unknown timeout, cmd 0x%x stat 0x%x\n",
335 ap->id, qc->tf.command, drv_stat);
337 ata_qc_complete(qc, drv_stat);
345 static inline unsigned int pdc_host_intr( struct ata_port *ap,
346 struct ata_queued_cmd *qc)
349 unsigned int handled = 0, have_err = 0;
351 void *mmio = (void *) ap->ioaddr.cmd_addr + PDC_GLOBAL_CTL;
354 if (tmp & PDC_ERR_MASK) {
359 switch (qc->tf.protocol) {
361 pdc_dma_complete(ap, qc, have_err);
365 case ATA_PROT_NODATA: /* command completion, but no data xfer */
366 status = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
367 DPRINTK("BUS_NODATA (drv_stat 0x%X)\n", status);
370 ata_qc_complete(qc, status);
375 ap->stats.idle_irq++;
382 static void pdc_irq_clear(struct ata_port *ap)
384 struct ata_host_set *host_set = ap->host_set;
385 void *mmio = host_set->mmio_base;
387 readl(mmio + PDC_INT_SEQMASK);
390 static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
392 struct ata_host_set *host_set = dev_instance;
396 unsigned int handled = 0;
401 if (!host_set || !host_set->mmio_base) {
402 VPRINTK("QUICK EXIT\n");
406 mmio_base = host_set->mmio_base;
408 /* reading should also clear interrupts */
409 mask = readl(mmio_base + PDC_INT_SEQMASK);
411 if (mask == 0xffffffff) {
412 VPRINTK("QUICK EXIT 2\n");
415 mask &= 0xffff; /* only 16 tags possible */
417 VPRINTK("QUICK EXIT 3\n");
421 spin_lock(&host_set->lock);
423 for (i = 0; i < host_set->n_ports; i++) {
424 VPRINTK("port %u\n", i);
425 ap = host_set->ports[i];
426 tmp = mask & (1 << (i + 1));
427 if (tmp && ap && (!(ap->flags & ATA_FLAG_PORT_DISABLED))) {
428 struct ata_queued_cmd *qc;
430 qc = ata_qc_from_tag(ap, ap->active_tag);
431 if (qc && (!(qc->tf.ctl & ATA_NIEN)))
432 handled += pdc_host_intr(ap, qc);
436 spin_unlock(&host_set->lock);
440 return IRQ_RETVAL(handled);
443 static inline void pdc_dma_start(struct ata_queued_cmd *qc)
445 struct ata_port *ap = qc->ap;
446 struct pdc_port_priv *pp = ap->private_data;
447 unsigned int port_no = ap->port_no;
448 u8 seq = (u8) (port_no + 1);
450 VPRINTK("ENTER, ap %p\n", ap);
452 writel(0x00000001, ap->host_set->mmio_base + (seq * 4));
453 readl(ap->host_set->mmio_base + (seq * 4)); /* flush */
456 wmb(); /* flush PRD, pkt writes */
457 writel(pp->pkt_dma, (void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
458 readl((void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */
461 static int pdc_qc_issue_prot(struct ata_queued_cmd *qc)
463 switch (qc->tf.protocol) {
468 case ATA_PROT_ATAPI_DMA:
476 return ata_qc_issue_prot(qc);
479 static void pdc_tf_load_mmio(struct ata_port *ap, struct ata_taskfile *tf)
481 WARN_ON (tf->protocol == ATA_PROT_DMA);
482 ata_tf_load_mmio(ap, tf);
486 static void pdc_exec_command_mmio(struct ata_port *ap, struct ata_taskfile *tf)
488 WARN_ON (tf->protocol == ATA_PROT_DMA);
489 ata_exec_command_mmio(ap, tf);
493 static void pdc_sata_setup_port(struct ata_ioports *port, unsigned long base)
495 port->cmd_addr = base;
496 port->data_addr = base;
498 port->error_addr = base + 0x4;
499 port->nsect_addr = base + 0x8;
500 port->lbal_addr = base + 0xc;
501 port->lbam_addr = base + 0x10;
502 port->lbah_addr = base + 0x14;
503 port->device_addr = base + 0x18;
505 port->status_addr = base + 0x1c;
506 port->altstatus_addr =
507 port->ctl_addr = base + 0x38;
511 static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
513 void *mmio = pe->mmio_base;
517 * Except for the hotplug stuff, this is voodoo from the
518 * Promise driver. Label this entire section
519 * "TODO: figure out why we do this"
522 /* change FIFO_SHD to 8 dwords, enable BMR_BURST */
523 tmp = readl(mmio + PDC_FLASH_CTL);
524 tmp |= 0x12000; /* bit 16 (fifo 8 dw) and 13 (bmr burst?) */
525 writel(tmp, mmio + PDC_FLASH_CTL);
527 /* clear plug/unplug flags for all ports */
528 tmp = readl(mmio + PDC_SATA_PLUG_CSR);
529 writel(tmp | 0xff, mmio + PDC_SATA_PLUG_CSR);
531 /* mask plug/unplug ints */
532 tmp = readl(mmio + PDC_SATA_PLUG_CSR);
533 writel(tmp | 0xff0000, mmio + PDC_SATA_PLUG_CSR);
535 /* reduce TBG clock to 133 Mhz. */
536 tmp = readl(mmio + PDC_TBG_MODE);
537 tmp &= ~0x30000; /* clear bit 17, 16*/
538 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
539 writel(tmp, mmio + PDC_TBG_MODE);
541 readl(mmio + PDC_TBG_MODE); /* flush */
542 set_current_state(TASK_UNINTERRUPTIBLE);
543 schedule_timeout(msecs_to_jiffies(10) + 1);
545 /* adjust slew rate control register. */
546 tmp = readl(mmio + PDC_SLEW_CTL);
547 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
548 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
549 writel(tmp, mmio + PDC_SLEW_CTL);
552 static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
554 static int printed_version;
555 struct ata_probe_ent *probe_ent = NULL;
558 unsigned int board_idx = (unsigned int) ent->driver_data;
561 if (!printed_version++)
562 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
565 * If this driver happens to only be useful on Apple's K2, then
566 * we should check that here as it has a normal Serverworks ID
568 rc = pci_enable_device(pdev);
572 rc = pci_request_regions(pdev, DRV_NAME);
576 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
578 goto err_out_regions;
579 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
581 goto err_out_regions;
583 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
584 if (probe_ent == NULL) {
586 goto err_out_regions;
589 memset(probe_ent, 0, sizeof(*probe_ent));
590 probe_ent->pdev = pdev;
591 INIT_LIST_HEAD(&probe_ent->node);
593 mmio_base = ioremap(pci_resource_start(pdev, 3),
594 pci_resource_len(pdev, 3));
595 if (mmio_base == NULL) {
597 goto err_out_free_ent;
599 base = (unsigned long) mmio_base;
601 probe_ent->sht = pdc_port_info[board_idx].sht;
602 probe_ent->host_flags = pdc_port_info[board_idx].host_flags;
603 probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask;
604 probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask;
605 probe_ent->port_ops = pdc_port_info[board_idx].port_ops;
607 probe_ent->irq = pdev->irq;
608 probe_ent->irq_flags = SA_SHIRQ;
609 probe_ent->mmio_base = mmio_base;
611 pdc_sata_setup_port(&probe_ent->port[0], base + 0x200);
612 pdc_sata_setup_port(&probe_ent->port[1], base + 0x280);
614 probe_ent->port[0].scr_addr = base + 0x400;
615 probe_ent->port[1].scr_addr = base + 0x500;
617 /* notice 4-port boards */
620 probe_ent->n_ports = 4;
622 pdc_sata_setup_port(&probe_ent->port[2], base + 0x300);
623 pdc_sata_setup_port(&probe_ent->port[3], base + 0x380);
625 probe_ent->port[2].scr_addr = base + 0x600;
626 probe_ent->port[3].scr_addr = base + 0x700;
629 probe_ent->n_ports = 2;
636 pci_set_master(pdev);
638 /* initialize adapter */
639 pdc_host_init(board_idx, probe_ent);
641 /* FIXME: check ata_device_add return value */
642 ata_device_add(probe_ent);
650 pci_release_regions(pdev);
652 pci_disable_device(pdev);
657 static int __init pdc_sata_init(void)
659 return pci_module_init(&pdc_sata_pci_driver);
663 static void __exit pdc_sata_exit(void)
665 pci_unregister_driver(&pdc_sata_pci_driver);
669 MODULE_AUTHOR("Jeff Garzik");
670 MODULE_DESCRIPTION("Promise SATA TX2/TX4 low-level driver");
671 MODULE_LICENSE("GPL");
672 MODULE_DEVICE_TABLE(pci, pdc_sata_pci_tbl);
674 module_init(pdc_sata_init);
675 module_exit(pdc_sata_exit);