2 * sata_sil.c - Silicon Image SATA
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2003 Red Hat, Inc.
9 * Copyright 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
11 * The contents of this file are subject to the Open
12 * Software License version 1.1 that can be found at
13 * http://www.opensource.org/licenses/osl-1.1.txt and is included herein
16 * Alternatively, the contents of this file may be used under the terms
17 * of the GNU General Public License version 2 (the "GPL") as distributed
18 * in the kernel source COPYING file, in which case the provisions of
19 * the GPL are applicable instead of the above. If you wish to allow
20 * the use of your version of this file only under the terms of the
21 * GPL and not to allow others to use your version of this file under
22 * the OSL, indicate your decision by deleting the provisions above and
23 * replace them with the notice and other provisions required by the GPL.
24 * If you do not delete the provisions above, a recipient may use your
25 * version of this file under either the OSL or the GPL.
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <linux/pci.h>
32 #include <linux/init.h>
33 #include <linux/blkdev.h>
34 #include <linux/delay.h>
35 #include <linux/interrupt.h>
37 #include <scsi/scsi_host.h>
38 #include <linux/libata.h>
40 #define DRV_NAME "sata_sil"
41 #define DRV_VERSION "0.54"
48 SIL_MASK_IDE0_INT = (1 << 22),
49 SIL_MASK_IDE1_INT = (1 << 23),
50 SIL_MASK_IDE2_INT = (1 << 24),
51 SIL_MASK_IDE3_INT = (1 << 25),
52 SIL_MASK_2PORT = SIL_MASK_IDE0_INT | SIL_MASK_IDE1_INT,
53 SIL_MASK_4PORT = SIL_MASK_2PORT |
54 SIL_MASK_IDE2_INT | SIL_MASK_IDE3_INT,
56 SIL_IDE2_BMDMA = 0x200,
58 SIL_INTR_STEERING = (1 << 1),
59 SIL_QUIRK_MOD15WRITE = (1 << 0),
60 SIL_QUIRK_UDMA5MAX = (1 << 1),
63 static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
64 static void sil_dev_config(struct ata_port *ap, struct ata_device *dev);
65 static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg);
66 static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
67 static void sil_post_set_mode (struct ata_port *ap);
69 static struct pci_device_id sil_pci_tbl[] = {
70 { 0x1095, 0x3112, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
71 { 0x1095, 0x0240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
72 { 0x1095, 0x3512, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
73 { 0x1095, 0x3114, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3114 },
74 { } /* terminate list */
78 /* TODO firmware versions should be added - eric */
79 struct sil_drivelist {
82 } sil_blacklist [] = {
83 { "ST320012AS", SIL_QUIRK_MOD15WRITE },
84 { "ST330013AS", SIL_QUIRK_MOD15WRITE },
85 { "ST340017AS", SIL_QUIRK_MOD15WRITE },
86 { "ST360015AS", SIL_QUIRK_MOD15WRITE },
87 { "ST380023AS", SIL_QUIRK_MOD15WRITE },
88 { "ST3120023AS", SIL_QUIRK_MOD15WRITE },
89 { "ST340014ASL", SIL_QUIRK_MOD15WRITE },
90 { "ST360014ASL", SIL_QUIRK_MOD15WRITE },
91 { "ST380011ASL", SIL_QUIRK_MOD15WRITE },
92 { "ST3120022ASL", SIL_QUIRK_MOD15WRITE },
93 { "ST3160021ASL", SIL_QUIRK_MOD15WRITE },
94 { "Maxtor 4D060H3", SIL_QUIRK_UDMA5MAX },
98 static struct pci_driver sil_pci_driver = {
100 .id_table = sil_pci_tbl,
101 .probe = sil_init_one,
102 .remove = ata_pci_remove_one,
105 static Scsi_Host_Template sil_sht = {
106 .module = THIS_MODULE,
108 .queuecommand = ata_scsi_queuecmd,
109 .eh_strategy_handler = ata_scsi_error,
110 .can_queue = ATA_DEF_QUEUE,
111 .this_id = ATA_SHT_THIS_ID,
112 .sg_tablesize = LIBATA_MAX_PRD,
113 .max_sectors = ATA_MAX_SECTORS,
114 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
115 .emulated = ATA_SHT_EMULATED,
116 .use_clustering = ATA_SHT_USE_CLUSTERING,
117 .proc_name = DRV_NAME,
118 .dma_boundary = ATA_DMA_BOUNDARY,
119 .slave_configure = ata_scsi_slave_config,
120 .bios_param = ata_std_bios_param,
123 static struct ata_port_operations sil_ops = {
124 .port_disable = ata_port_disable,
125 .dev_config = sil_dev_config,
126 .tf_load = ata_tf_load_mmio,
127 .tf_read = ata_tf_read_mmio,
128 .check_status = ata_check_status_mmio,
129 .exec_command = ata_exec_command_mmio,
130 .phy_reset = sata_phy_reset,
131 .post_set_mode = sil_post_set_mode,
132 .bmdma_setup = ata_bmdma_setup_mmio,
133 .bmdma_start = ata_bmdma_start_mmio,
134 .fill_sg = ata_fill_sg,
135 .eng_timeout = ata_eng_timeout,
136 .irq_handler = ata_interrupt,
137 .scr_read = sil_scr_read,
138 .scr_write = sil_scr_write,
139 .port_start = ata_port_start,
140 .port_stop = ata_port_stop,
143 static struct ata_port_info sil_port_info[] = {
147 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
148 ATA_FLAG_SRST | ATA_FLAG_MMIO,
149 .pio_mask = 0x03, /* pio3-4 */
150 .udma_mask = 0x3f, /* udma0-5 */
151 .port_ops = &sil_ops,
155 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
156 ATA_FLAG_SRST | ATA_FLAG_MMIO,
157 .pio_mask = 0x03, /* pio3-4 */
158 .udma_mask = 0x3f, /* udma0-5 */
159 .port_ops = &sil_ops,
163 /* per-port register offsets */
164 /* TODO: we can probably calculate rather than use a table */
165 static const struct {
166 unsigned long tf; /* ATA taskfile register block */
167 unsigned long ctl; /* ATA control/altstatus register block */
168 unsigned long bmdma; /* DMA register block */
169 unsigned long scr; /* SATA control register block */
170 unsigned long sien; /* SATA Interrupt Enable register */
171 unsigned long xfer_mode;/* data transfer mode register */
174 { 0x80, 0x8A, 0x00, 0x100, 0x148, 0xb4 },
175 { 0xC0, 0xCA, 0x08, 0x180, 0x1c8, 0xf4 },
176 { 0x280, 0x28A, 0x200, 0x300, 0x348, 0x2b4 },
177 { 0x2C0, 0x2CA, 0x208, 0x380, 0x3c8, 0x2f4 },
181 MODULE_AUTHOR("Jeff Garzik");
182 MODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller");
183 MODULE_LICENSE("GPL");
184 MODULE_DEVICE_TABLE(pci, sil_pci_tbl);
186 static void sil_post_set_mode (struct ata_port *ap)
188 struct ata_host_set *host_set = ap->host_set;
189 struct ata_device *dev;
190 void *addr = host_set->mmio_base + sil_port[ap->port_no].xfer_mode;
191 u32 tmp, dev_mode[2];
194 for (i = 0; i < 2; i++) {
195 dev = &ap->device[i];
196 if (!ata_dev_present(dev))
197 dev_mode[i] = 0; /* PIO0/1/2 */
198 else if (dev->flags & ATA_DFLAG_PIO)
199 dev_mode[i] = 1; /* PIO3/4 */
201 dev_mode[i] = 3; /* UDMA */
202 /* value 2 indicates MDMA */
206 tmp &= ~((1<<5) | (1<<4) | (1<<1) | (1<<0));
208 tmp |= (dev_mode[1] << 4);
210 readl(addr); /* flush */
213 static inline unsigned long sil_scr_addr(struct ata_port *ap, unsigned int sc_reg)
215 unsigned long offset = ap->ioaddr.scr_addr;
232 static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg)
234 void *mmio = (void *) sil_scr_addr(ap, sc_reg);
240 static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
242 void *mmio = (void *) sil_scr_addr(ap, sc_reg);
248 * sil_dev_config - Apply device/host-specific errata fixups
249 * @ap: Port containing device to be examined
250 * @dev: Device to be examined
252 * After the IDENTIFY [PACKET] DEVICE step is complete, and a
253 * device is known to be present, this function is called.
254 * We apply two errata fixups which are specific to Silicon Image,
255 * a Seagate and a Maxtor fixup.
257 * For certain Seagate devices, we must limit the maximum sectors
260 * For certain Maxtor devices, we must not program the drive
263 * Both fixups are unfairly pessimistic. As soon as I get more
264 * information on these errata, I will create a more exhaustive
265 * list, and apply the fixups to only the specific
266 * devices/hosts/firmwares that need it.
268 * 20040111 - Seagate drives affected by the Mod15Write bug are blacklisted
269 * The Maxtor quirk is in the blacklist, but I'm keeping the original
270 * pessimistic fix for the following reasons...
271 * - There seems to be less info on it, only one device gleaned off the
272 * Windows driver, maybe only one is affected. More info would be greatly
274 * - But then again UDMA5 is hardly anything to complain about
276 static void sil_dev_config(struct ata_port *ap, struct ata_device *dev)
278 unsigned int n, quirks = 0;
279 unsigned char model_num[40];
283 ata_dev_id_string(dev, model_num, ATA_ID_PROD_OFS,
286 len = strnlen(s, sizeof(model_num));
288 /* ATAPI specifies that empty space is blank-filled; remove blanks */
289 while ((len > 0) && (s[len - 1] == ' '))
292 for (n = 0; sil_blacklist[n].product; n++)
293 if (!memcmp(sil_blacklist[n].product, s,
294 strlen(sil_blacklist[n].product))) {
295 quirks = sil_blacklist[n].quirk;
299 /* limit requests to 15 sectors */
300 if (quirks & SIL_QUIRK_MOD15WRITE) {
301 printk(KERN_INFO "ata%u(%u): applying Seagate errata fix\n",
303 ap->host->max_sectors = 15;
304 ap->host->hostt->max_sectors = 15;
309 if (quirks & SIL_QUIRK_UDMA5MAX) {
310 printk(KERN_INFO "ata%u(%u): applying Maxtor errata fix %s\n",
311 ap->id, dev->devno, s);
312 ap->udma_mask &= ATA_UDMA5;
317 static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
319 static int printed_version;
320 struct ata_probe_ent *probe_ent = NULL;
327 if (!printed_version++)
328 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
331 * If this driver happens to only be useful on Apple's K2, then
332 * we should check that here as it has a normal Serverworks ID
334 rc = pci_enable_device(pdev);
338 rc = pci_request_regions(pdev, DRV_NAME);
342 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
344 goto err_out_regions;
345 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
347 goto err_out_regions;
349 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
350 if (probe_ent == NULL) {
352 goto err_out_regions;
355 memset(probe_ent, 0, sizeof(*probe_ent));
356 INIT_LIST_HEAD(&probe_ent->node);
357 probe_ent->pdev = pdev;
358 probe_ent->port_ops = sil_port_info[ent->driver_data].port_ops;
359 probe_ent->sht = sil_port_info[ent->driver_data].sht;
360 probe_ent->n_ports = (ent->driver_data == sil_3114) ? 4 : 2;
361 probe_ent->pio_mask = sil_port_info[ent->driver_data].pio_mask;
362 probe_ent->udma_mask = sil_port_info[ent->driver_data].udma_mask;
363 probe_ent->irq = pdev->irq;
364 probe_ent->irq_flags = SA_SHIRQ;
365 probe_ent->host_flags = sil_port_info[ent->driver_data].host_flags;
367 mmio_base = ioremap(pci_resource_start(pdev, 5),
368 pci_resource_len(pdev, 5));
369 if (mmio_base == NULL) {
371 goto err_out_free_ent;
374 probe_ent->mmio_base = mmio_base;
376 base = (unsigned long) mmio_base;
378 for (i = 0; i < probe_ent->n_ports; i++) {
379 probe_ent->port[i].cmd_addr = base + sil_port[i].tf;
380 probe_ent->port[i].altstatus_addr =
381 probe_ent->port[i].ctl_addr = base + sil_port[i].ctl;
382 probe_ent->port[i].bmdma_addr = base + sil_port[i].bmdma;
383 probe_ent->port[i].scr_addr = base + sil_port[i].scr;
384 ata_std_ports(&probe_ent->port[i]);
387 if (ent->driver_data == sil_3114) {
388 irq_mask = SIL_MASK_4PORT;
390 /* flip the magic "make 4 ports work" bit */
391 tmp = readl(mmio_base + SIL_IDE2_BMDMA);
392 if ((tmp & SIL_INTR_STEERING) == 0)
393 writel(tmp | SIL_INTR_STEERING,
394 mmio_base + SIL_IDE2_BMDMA);
397 irq_mask = SIL_MASK_2PORT;
400 /* make sure IDE0/1/2/3 interrupts are not masked */
401 tmp = readl(mmio_base + SIL_SYSCFG);
402 if (tmp & irq_mask) {
404 writel(tmp, mmio_base + SIL_SYSCFG);
405 readl(mmio_base + SIL_SYSCFG); /* flush */
408 /* mask all SATA phy-related interrupts */
409 /* TODO: unmask bit 6 (SError N bit) for hotplug */
410 for (i = 0; i < probe_ent->n_ports; i++)
411 writel(0, mmio_base + sil_port[i].sien);
413 pci_set_master(pdev);
415 /* FIXME: check ata_device_add return value */
416 ata_device_add(probe_ent);
424 pci_release_regions(pdev);
426 pci_disable_device(pdev);
430 static int __init sil_init(void)
432 return pci_module_init(&sil_pci_driver);
435 static void __exit sil_exit(void)
437 pci_unregister_driver(&sil_pci_driver);
441 module_init(sil_init);
442 module_exit(sil_exit);