drivers/scsi/sata_sx4.c

   1 /*
   2  *  sata_sx4.c - Promise SATA
   3  *
   4  *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
   5  *                  Please ALWAYS copy linux-ide@vger.kernel.org
   6  *                  on emails.
   7  *
   8  *  Copyright 2003-2004 Red Hat, Inc.
   9  *
  10  *  The contents of this file are subject to the Open
  11  *  Software License version 1.1 that can be found at
  12  *  http://www.opensource.org/licenses/osl-1.1.txt and is included herein
  13  *  by reference.
  14  *
  15  *  Alternatively, the contents of this file may be used under the terms
  16  *  of the GNU General Public License version 2 (the "GPL") as distributed
  17  *  in the kernel source COPYING file, in which case the provisions of
  18  *  the GPL are applicable instead of the above.  If you wish to allow
  19  *  the use of your version of this file only under the terms of the
  20  *  GPL and not to allow others to use your version of this file under
  21  *  the OSL, indicate your decision by deleting the provisions above and
  22  *  replace them with the notice and other provisions required by the GPL.
  23  *  If you do not delete the provisions above, a recipient may use your
  24  *  version of this file under either the OSL or the GPL.
  25  *
  26  */
  27
  28 #include <linux/kernel.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/init.h>
  32 #include <linux/blkdev.h>
  33 #include <linux/delay.h>
  34 #include <linux/interrupt.h>
  35 #include <linux/sched.h>
  36 #include "scsi.h"
  37 #include <scsi/scsi_host.h>
  38 #include <linux/libata.h>
  39 #include <asm/io.h>
  40 #include "sata_promise.h"
  41
  42 #define DRV_NAME        "sata_sx4"
  43 #define DRV_VERSION     "0.50"
  44
  45
  46 enum {
  47         PDC_PRD_TBL             = 0x44, /* Direct command DMA table addr */
  48
  49         PDC_PKT_SUBMIT          = 0x40, /* Command packet pointer addr */
  50         PDC_HDMA_PKT_SUBMIT     = 0x100, /* Host DMA packet pointer addr */
  51         PDC_INT_SEQMASK         = 0x40, /* Mask of asserted SEQ INTs */
  52         PDC_HDMA_CTLSTAT        = 0x12C, /* Host DMA control / status */
  53
  54         PDC_20621_SEQCTL        = 0x400,
  55         PDC_20621_SEQMASK       = 0x480,
  56         PDC_20621_GENERAL_CTL   = 0x484,
  57         PDC_20621_PAGE_SIZE     = (32 * 1024),
  58
  59         /* chosen, not constant, values; we design our own DIMM mem map */
  60         PDC_20621_DIMM_WINDOW   = 0x0C, /* page# for 32K DIMM window */
  61         PDC_20621_DIMM_BASE     = 0x00200000,
  62         PDC_20621_DIMM_DATA     = (64 * 1024),
  63         PDC_DIMM_DATA_STEP      = (256 * 1024),
  64         PDC_DIMM_WINDOW_STEP    = (8 * 1024),
  65         PDC_DIMM_HOST_PRD       = (6 * 1024),
  66         PDC_DIMM_HOST_PKT       = (128 * 0),
  67         PDC_DIMM_HPKT_PRD       = (128 * 1),
  68         PDC_DIMM_ATA_PKT        = (128 * 2),
  69         PDC_DIMM_APKT_PRD       = (128 * 3),
  70         PDC_DIMM_HEADER_SZ      = PDC_DIMM_APKT_PRD + 128,
  71         PDC_PAGE_WINDOW         = 0x40,
  72         PDC_PAGE_DATA           = PDC_PAGE_WINDOW +
  73                                   (PDC_20621_DIMM_DATA / PDC_20621_PAGE_SIZE),
  74         PDC_PAGE_SET            = PDC_DIMM_DATA_STEP / PDC_20621_PAGE_SIZE,
  75
  76         PDC_CHIP0_OFS           = 0xC0000, /* offset of chip #0 */
  77
  78         PDC_20621_ERR_MASK      = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
  79                                   (1<<23),
  80
  81         board_20621             = 0,    /* FastTrak S150 SX4 */
  82
  83         PDC_RESET               = (1 << 11), /* HDMA reset */
  84
  85         PDC_MAX_HDMA            = 32,
  86         PDC_HDMA_Q_MASK         = (PDC_MAX_HDMA - 1),
  87
  88         PDC_DIMM0_SPD_DEV_ADDRESS     = 0x50,
  89         PDC_DIMM1_SPD_DEV_ADDRESS     = 0x51,
  90         PDC_MAX_DIMM_MODULE           = 0x02,
  91         PDC_I2C_CONTROL_OFFSET        = 0x48,
  92         PDC_I2C_ADDR_DATA_OFFSET      = 0x4C,
  93         PDC_DIMM0_CONTROL_OFFSET      = 0x80,
  94         PDC_DIMM1_CONTROL_OFFSET      = 0x84,
  95         PDC_SDRAM_CONTROL_OFFSET      = 0x88,
  96         PDC_I2C_WRITE                 = 0x00000000,
  97         PDC_I2C_READ                  = 0x00000040,
  98         PDC_I2C_START                 = 0x00000080,
  99         PDC_I2C_MASK_INT              = 0x00000020,
 100         PDC_I2C_COMPLETE              = 0x00010000,
 101         PDC_I2C_NO_ACK                = 0x00100000,
 102         PDC_DIMM_SPD_SUBADDRESS_START = 0x00,
 103         PDC_DIMM_SPD_SUBADDRESS_END   = 0x7F,
 104         PDC_DIMM_SPD_ROW_NUM          = 3,
 105         PDC_DIMM_SPD_COLUMN_NUM       = 4,
 106         PDC_DIMM_SPD_MODULE_ROW       = 5,
 107         PDC_DIMM_SPD_TYPE             = 11,
 108         PDC_DIMM_SPD_FRESH_RATE       = 12,
 109         PDC_DIMM_SPD_BANK_NUM         = 17,
 110         PDC_DIMM_SPD_CAS_LATENCY      = 18,
 111         PDC_DIMM_SPD_ATTRIBUTE        = 21,
 112         PDC_DIMM_SPD_ROW_PRE_CHARGE   = 27,
 113         PDC_DIMM_SPD_ROW_ACTIVE_DELAY = 28,
 114         PDC_DIMM_SPD_RAS_CAS_DELAY    = 29,
 115         PDC_DIMM_SPD_ACTIVE_PRECHARGE = 30,
 116         PDC_DIMM_SPD_SYSTEM_FREQ      = 126,
 117         PDC_CTL_STATUS                = 0x08,
 118         PDC_DIMM_WINDOW_CTLR          = 0x0C,
 119         PDC_TIME_CONTROL              = 0x3C,
 120         PDC_TIME_PERIOD               = 0x40,
 121         PDC_TIME_COUNTER              = 0x44,
 122         PDC_GENERAL_CTLR              = 0x484,
 123         PCI_PLL_INIT                  = 0x8A531824,
 124         PCI_X_TCOUNT                  = 0xEE1E5CFF
 125 };
 126
 127
 128 struct pdc_port_priv {
 129         u8                      dimm_buf[(ATA_PRD_SZ * ATA_MAX_PRD) + 512];
 130         u8                      *pkt;
 131         dma_addr_t              pkt_dma;
 132 };
 133
 134 struct pdc_host_priv {
 135         void                    *dimm_mmio;
 136
 137         unsigned int            doing_hdma;
 138         unsigned int            hdma_prod;
 139         unsigned int            hdma_cons;
 140         struct {
 141                 struct ata_queued_cmd *qc;
 142                 unsigned int    seq;
 143                 unsigned long   pkt_ofs;
 144         } hdma[32];
 145 };
 146
 147
 148 static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
 149 static void pdc20621_dma_setup(struct ata_queued_cmd *qc);
 150 static void pdc20621_dma_start(struct ata_queued_cmd *qc);
 151 static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
 152 static void pdc_eng_timeout(struct ata_port *ap);
 153 static void pdc_20621_phy_reset (struct ata_port *ap);
 154 static int pdc_port_start(struct ata_port *ap);
 155 static void pdc_port_stop(struct ata_port *ap);
 156 static void pdc20621_fill_sg(struct ata_queued_cmd *qc);
 157 static void pdc_tf_load_mmio(struct ata_port *ap, struct ata_taskfile *tf);
 158 static void pdc_exec_command_mmio(struct ata_port *ap, struct ata_taskfile *tf);
 159 static void pdc20621_host_stop(struct ata_host_set *host_set);
 160 static inline void pdc_dma_complete (struct ata_port *ap,
 161                                      struct ata_queued_cmd *qc, int have_err);
 162 static unsigned int pdc20621_dimm_init(struct ata_probe_ent *pe);
 163 static int pdc20621_detect_dimm(struct ata_probe_ent *pe);
 164 static unsigned int pdc20621_i2c_read(struct ata_probe_ent *pe,
 165                                       u32 device, u32 subaddr, u32 *pdata);
 166 static int pdc20621_prog_dimm0(struct ata_probe_ent *pe);
 167 static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent *pe);
 168 #ifdef ATA_VERBOSE_DEBUG
 169 static void pdc20621_get_from_dimm(struct ata_probe_ent *pe,
 170                                    void *psource, u32 offset, u32 size);
 171 #endif
 172 static void pdc20621_put_to_dimm(struct ata_probe_ent *pe,
 173                                  void *psource, u32 offset, u32 size);
 174
 175
 176 static Scsi_Host_Template pdc_sata_sht = {
 177         .module                 = THIS_MODULE,
 178         .name                   = DRV_NAME,
 179         .queuecommand           = ata_scsi_queuecmd,
 180         .eh_strategy_handler    = ata_scsi_error,
 181         .can_queue              = ATA_DEF_QUEUE,
 182         .this_id                = ATA_SHT_THIS_ID,
 183         .sg_tablesize           = LIBATA_MAX_PRD,
 184         .max_sectors            = ATA_MAX_SECTORS,
 185         .cmd_per_lun            = ATA_SHT_CMD_PER_LUN,
 186         .emulated               = ATA_SHT_EMULATED,
 187         .use_clustering         = ATA_SHT_USE_CLUSTERING,
 188         .proc_name              = DRV_NAME,
 189         .dma_boundary           = ATA_DMA_BOUNDARY,
 190         .slave_configure        = ata_scsi_slave_config,
 191         .bios_param             = ata_std_bios_param,
 192 };
 193
 194 static struct ata_port_operations pdc_20621_ops = {
 195         .port_disable           = ata_port_disable,
 196         .tf_load                = pdc_tf_load_mmio,
 197         .tf_read                = ata_tf_read_mmio,
 198         .check_status           = ata_check_status_mmio,
 199         .exec_command           = pdc_exec_command_mmio,
 200         .phy_reset              = pdc_20621_phy_reset,
 201         .bmdma_setup            = pdc20621_dma_setup,
 202         .bmdma_start            = pdc20621_dma_start,
 203         .fill_sg                = pdc20621_fill_sg,
 204         .eng_timeout            = pdc_eng_timeout,
 205         .irq_handler            = pdc20621_interrupt,
 206         .port_start             = pdc_port_start,
 207         .port_stop              = pdc_port_stop,
 208         .host_stop              = pdc20621_host_stop,
 209 };
 210
 211 static struct ata_port_info pdc_port_info[] = {
 212         /* board_20621 */
 213         {
 214                 .sht            = &pdc_sata_sht,
 215                 .host_flags     = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
 216                                   ATA_FLAG_SRST | ATA_FLAG_MMIO,
 217                 .pio_mask       = 0x03, /* pio3-4 */
 218                 .udma_mask      = 0x7f, /* udma0-6 ; FIXME */
 219                 .port_ops       = &pdc_20621_ops,
 220         },
 221
 222 };
 223
 224 static struct pci_device_id pdc_sata_pci_tbl[] = {
 225         { PCI_VENDOR_ID_PROMISE, 0x6622, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
 226           board_20621 },
 227         { }     /* terminate list */
 228 };
 229
 230
 231 static struct pci_driver pdc_sata_pci_driver = {
 232         .name                   = DRV_NAME,
 233         .id_table               = pdc_sata_pci_tbl,
 234         .probe                  = pdc_sata_init_one,
 235         .remove                 = ata_pci_remove_one,
 236 };
 237
 238
 239 static void pdc20621_host_stop(struct ata_host_set *host_set)
 240 {
 241         struct pdc_host_priv *hpriv = host_set->private_data;
 242         void *dimm_mmio = hpriv->dimm_mmio;
 243
 244         iounmap(dimm_mmio);
 245         kfree(hpriv);
 246 }
 247
 248 static int pdc_port_start(struct ata_port *ap)
 249 {
 250         struct pci_dev *pdev = ap->host_set->pdev;
 251         struct pdc_port_priv *pp;
 252         int rc;
 253
 254         rc = ata_port_start(ap);
 255         if (rc)
 256                 return rc;
 257
 258         pp = kmalloc(sizeof(*pp), GFP_KERNEL);
 259         if (!pp) {
 260                 rc = -ENOMEM;
 261                 goto err_out;
 262         }
 263         memset(pp, 0, sizeof(*pp));
 264
 265         pp->pkt = pci_alloc_consistent(pdev, 128, &pp->pkt_dma);
 266         if (!pp->pkt) {
 267                 rc = -ENOMEM;
 268                 goto err_out_kfree;
 269         }
 270
 271         ap->private_data = pp;
 272
 273         return 0;
 274
 275 err_out_kfree:
 276         kfree(pp);
 277 err_out:
 278         ata_port_stop(ap);
 279         return rc;
 280 }
 281
 282
 283 static void pdc_port_stop(struct ata_port *ap)
 284 {
 285         struct pci_dev *pdev = ap->host_set->pdev;
 286         struct pdc_port_priv *pp = ap->private_data;
 287
 288         ap->private_data = NULL;
 289         pci_free_consistent(pdev, 128, pp->pkt, pp->pkt_dma);
 290         kfree(pp);
 291         ata_port_stop(ap);
 292 }
 293
 294
 295 static void pdc_20621_phy_reset (struct ata_port *ap)
 296 {
 297         VPRINTK("ENTER\n");
 298         ap->cbl = ATA_CBL_SATA;
 299         ata_port_probe(ap);
 300         ata_bus_reset(ap);
 301 }
 302
 303 static inline void pdc20621_ata_sg(struct ata_taskfile *tf, u8 *buf,
 304                                            unsigned int portno,
 305                                            unsigned int total_len)
 306 {
 307         u32 addr;
 308         unsigned int dw = PDC_DIMM_APKT_PRD >> 2;
 309         u32 *buf32 = (u32 *) buf;
 310
 311         /* output ATA packet S/G table */
 312         addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
 313                (PDC_DIMM_DATA_STEP * portno);
 314         VPRINTK("ATA sg addr 0x%x, %d\n", addr, addr);
 315         buf32[dw] = cpu_to_le32(addr);
 316         buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
 317
 318         VPRINTK("ATA PSG @ %x == (0x%x, 0x%x)\n",
 319                 PDC_20621_DIMM_BASE +
 320                        (PDC_DIMM_WINDOW_STEP * portno) +
 321                        PDC_DIMM_APKT_PRD,
 322                 buf32[dw], buf32[dw + 1]);
 323 }
 324
 325 static inline void pdc20621_host_sg(struct ata_taskfile *tf, u8 *buf,
 326                                             unsigned int portno,
 327                                             unsigned int total_len)
 328 {
 329         u32 addr;
 330         unsigned int dw = PDC_DIMM_HPKT_PRD >> 2;
 331         u32 *buf32 = (u32 *) buf;
 332
 333         /* output Host DMA packet S/G table */
 334         addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
 335                (PDC_DIMM_DATA_STEP * portno);
 336
 337         buf32[dw] = cpu_to_le32(addr);
 338         buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
 339
 340         VPRINTK("HOST PSG @ %x == (0x%x, 0x%x)\n",
 341                 PDC_20621_DIMM_BASE +
 342                        (PDC_DIMM_WINDOW_STEP * portno) +
 343                        PDC_DIMM_HPKT_PRD,
 344                 buf32[dw], buf32[dw + 1]);
 345 }
 346
 347 static inline unsigned int pdc20621_ata_pkt(struct ata_taskfile *tf,
 348                                             unsigned int devno, u8 *buf,
 349                                             unsigned int portno)
 350 {
 351         unsigned int i, dw;
 352         u32 *buf32 = (u32 *) buf;
 353         u8 dev_reg;
 354
 355         unsigned int dimm_sg = PDC_20621_DIMM_BASE +
 356                                (PDC_DIMM_WINDOW_STEP * portno) +
 357                                PDC_DIMM_APKT_PRD;
 358         VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
 359
 360         i = PDC_DIMM_ATA_PKT;
 361
 362         /*
 363          * Set up ATA packet
 364          */
 365         if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
 366                 buf[i++] = PDC_PKT_READ;
 367         else if (tf->protocol == ATA_PROT_NODATA)
 368                 buf[i++] = PDC_PKT_NODATA;
 369         else
 370                 buf[i++] = 0;
 371         buf[i++] = 0;                   /* reserved */
 372         buf[i++] = portno + 1;          /* seq. id */
 373         buf[i++] = 0xff;                /* delay seq. id */
 374
 375         /* dimm dma S/G, and next-pkt */
 376         dw = i >> 2;
 377         buf32[dw] = cpu_to_le32(dimm_sg);
 378         buf32[dw + 1] = 0;
 379         i += 8;
 380
 381         if (devno == 0)
 382                 dev_reg = ATA_DEVICE_OBS;
 383         else
 384                 dev_reg = ATA_DEVICE_OBS | ATA_DEV1;
 385
 386         /* select device */
 387         buf[i++] = (1 << 5) | PDC_PKT_CLEAR_BSY | ATA_REG_DEVICE;
 388         buf[i++] = dev_reg;
 389
 390         /* device control register */
 391         buf[i++] = (1 << 5) | PDC_REG_DEVCTL;
 392         buf[i++] = tf->ctl;
 393
 394         return i;
 395 }
 396
 397 static inline void pdc20621_host_pkt(struct ata_taskfile *tf, u8 *buf,
 398                                      unsigned int portno)
 399 {
 400         unsigned int dw;
 401         u32 tmp, *buf32 = (u32 *) buf;
 402
 403         unsigned int host_sg = PDC_20621_DIMM_BASE +
 404                                (PDC_DIMM_WINDOW_STEP * portno) +
 405                                PDC_DIMM_HOST_PRD;
 406         unsigned int dimm_sg = PDC_20621_DIMM_BASE +
 407                                (PDC_DIMM_WINDOW_STEP * portno) +
 408                                PDC_DIMM_HPKT_PRD;
 409         VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
 410         VPRINTK("host_sg == 0x%x, %d\n", host_sg, host_sg);
 411
 412         dw = PDC_DIMM_HOST_PKT >> 2;
 413
 414         /*
 415          * Set up Host DMA packet
 416          */
 417         if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
 418                 tmp = PDC_PKT_READ;
 419         else
 420                 tmp = 0;
 421         tmp |= ((portno + 1 + 4) << 16);        /* seq. id */
 422         tmp |= (0xff << 24);                    /* delay seq. id */
 423         buf32[dw + 0] = cpu_to_le32(tmp);
 424         buf32[dw + 1] = cpu_to_le32(host_sg);
 425         buf32[dw + 2] = cpu_to_le32(dimm_sg);
 426         buf32[dw + 3] = 0;
 427
 428         VPRINTK("HOST PKT @ %x == (0x%x 0x%x 0x%x 0x%x)\n",
 429                 PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * portno) +
 430                         PDC_DIMM_HOST_PKT,
 431                 buf32[dw + 0],
 432                 buf32[dw + 1],
 433                 buf32[dw + 2],
 434                 buf32[dw + 3]);
 435 }
 436
 437 static void pdc20621_fill_sg(struct ata_queued_cmd *qc)
 438 {
 439         struct scatterlist *sg = qc->sg;
 440         struct ata_port *ap = qc->ap;
 441         struct pdc_port_priv *pp = ap->private_data;
 442         void *mmio = ap->host_set->mmio_base;
 443         struct pdc_host_priv *hpriv = ap->host_set->private_data;
 444         void *dimm_mmio = hpriv->dimm_mmio;
 445         unsigned int portno = ap->port_no;
 446         unsigned int i, last, idx, total_len = 0, sgt_len;
 447         u32 *buf = (u32 *) &pp->dimm_buf[PDC_DIMM_HEADER_SZ];
 448
 449         VPRINTK("ata%u: ENTER\n", ap->id);
 450
 451         /* hard-code chip #0 */
 452         mmio += PDC_CHIP0_OFS;
 453
 454         /*
 455          * Build S/G table
 456          */
 457         last = qc->n_elem;
 458         idx = 0;
 459         for (i = 0; i < last; i++) {
 460                 buf[idx++] = cpu_to_le32(sg_dma_address(&sg[i]));
 461                 buf[idx++] = cpu_to_le32(sg_dma_len(&sg[i]));
 462                 total_len += sg[i].length;
 463         }
 464         buf[idx - 1] |= cpu_to_le32(ATA_PRD_EOT);
 465         sgt_len = idx * 4;
 466
 467         /*
 468          * Build ATA, host DMA packets
 469          */
 470         pdc20621_host_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len);
 471         pdc20621_host_pkt(&qc->tf, &pp->dimm_buf[0], portno);
 472
 473         pdc20621_ata_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len);
 474         i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
 475
 476         if (qc->tf.flags & ATA_TFLAG_LBA48)
 477                 i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
 478         else
 479                 i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
 480
 481         pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
 482
 483         /* copy three S/G tables and two packets to DIMM MMIO window */
 484         memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
 485                     &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
 486         memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP) +
 487                     PDC_DIMM_HOST_PRD,
 488                     &pp->dimm_buf[PDC_DIMM_HEADER_SZ], sgt_len);
 489
 490         /* force host FIFO dump */
 491         writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
 492
 493         readl(dimm_mmio);       /* MMIO PCI posting flush */
 494
 495         VPRINTK("ata pkt buf ofs %u, prd size %u, mmio copied\n", i, sgt_len);
 496 }
 497
 498 static void __pdc20621_push_hdma(struct ata_queued_cmd *qc,
 499                                  unsigned int seq,
 500                                  u32 pkt_ofs)
 501 {
 502         struct ata_port *ap = qc->ap;
 503         struct ata_host_set *host_set = ap->host_set;
 504         void *mmio = host_set->mmio_base;
 505
 506         /* hard-code chip #0 */
 507         mmio += PDC_CHIP0_OFS;
 508
 509         writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
 510         readl(mmio + PDC_20621_SEQCTL + (seq * 4));     /* flush */
 511
 512         writel(pkt_ofs, mmio + PDC_HDMA_PKT_SUBMIT);
 513         readl(mmio + PDC_HDMA_PKT_SUBMIT);      /* flush */
 514 }
 515
 516 static void pdc20621_push_hdma(struct ata_queued_cmd *qc,
 517                                 unsigned int seq,
 518                                 u32 pkt_ofs)
 519 {
 520         struct ata_port *ap = qc->ap;
 521         struct pdc_host_priv *pp = ap->host_set->private_data;
 522         unsigned int idx = pp->hdma_prod & PDC_HDMA_Q_MASK;
 523
 524         if (!pp->doing_hdma) {
 525                 __pdc20621_push_hdma(qc, seq, pkt_ofs);
 526                 pp->doing_hdma = 1;
 527                 return;
 528         }
 529
 530         pp->hdma[idx].qc = qc;
 531         pp->hdma[idx].seq = seq;
 532         pp->hdma[idx].pkt_ofs = pkt_ofs;
 533         pp->hdma_prod++;
 534 }
 535
 536 static void pdc20621_pop_hdma(struct ata_queued_cmd *qc)
 537 {
 538         struct ata_port *ap = qc->ap;
 539         struct pdc_host_priv *pp = ap->host_set->private_data;
 540         unsigned int idx = pp->hdma_cons & PDC_HDMA_Q_MASK;
 541
 542         /* if nothing on queue, we're done */
 543         if (pp->hdma_prod == pp->hdma_cons) {
 544                 pp->doing_hdma = 0;
 545                 return;
 546         }
 547
 548         __pdc20621_push_hdma(pp->hdma[idx].qc, pp->hdma[idx].seq,
 549                              pp->hdma[idx].pkt_ofs);
 550         pp->hdma_cons++;
 551 }
 552
 553 #ifdef ATA_VERBOSE_DEBUG
 554 static void pdc20621_dump_hdma(struct ata_queued_cmd *qc)
 555 {
 556         struct ata_port *ap = qc->ap;
 557         unsigned int port_no = ap->port_no;
 558         struct pdc_host_priv *hpriv = ap->host_set->private_data;
 559         void *dimm_mmio = hpriv->dimm_mmio;
 560
 561         dimm_mmio += (port_no * PDC_DIMM_WINDOW_STEP);
 562         dimm_mmio += PDC_DIMM_HOST_PKT;
 563
 564         printk(KERN_ERR "HDMA[0] == 0x%08X\n", readl(dimm_mmio));
 565         printk(KERN_ERR "HDMA[1] == 0x%08X\n", readl(dimm_mmio + 4));
 566         printk(KERN_ERR "HDMA[2] == 0x%08X\n", readl(dimm_mmio + 8));
 567         printk(KERN_ERR "HDMA[3] == 0x%08X\n", readl(dimm_mmio + 12));
 568 }
 569 #else
 570 static inline void pdc20621_dump_hdma(struct ata_queued_cmd *qc) { }
 571 #endif /* ATA_VERBOSE_DEBUG */
 572
 573 static void pdc20621_dma_setup(struct ata_queued_cmd *qc)
 574 {
 575         /* nothing for now.  later, we will call standard
 576          * code in libata-core for ATAPI here */
 577 }
 578
 579 static void pdc20621_dma_start(struct ata_queued_cmd *qc)
 580 {
 581         struct ata_port *ap = qc->ap;
 582         struct ata_host_set *host_set = ap->host_set;
 583         unsigned int port_no = ap->port_no;
 584         void *mmio = host_set->mmio_base;
 585         unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
 586         u8 seq = (u8) (port_no + 1);
 587         unsigned int doing_hdma = 0, port_ofs;
 588
 589         /* hard-code chip #0 */
 590         mmio += PDC_CHIP0_OFS;
 591
 592         VPRINTK("ata%u: ENTER\n", ap->id);
 593
 594         port_ofs = PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
 595
 596         /* if writing, we (1) DMA to DIMM, then (2) do ATA command */
 597         if (rw) {
 598                 doing_hdma = 1;
 599                 seq += 4;
 600         }
 601
 602         wmb();                  /* flush PRD, pkt writes */
 603
 604         if (doing_hdma) {
 605                 pdc20621_dump_hdma(qc);
 606                 pdc20621_push_hdma(qc, seq, port_ofs + PDC_DIMM_HOST_PKT);
 607                 VPRINTK("queued ofs 0x%x (%u), seq %u\n",
 608                         port_ofs + PDC_DIMM_HOST_PKT,
 609                         port_ofs + PDC_DIMM_HOST_PKT,
 610                         seq);
 611         } else {
 612                 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
 613                 readl(mmio + PDC_20621_SEQCTL + (seq * 4));     /* flush */
 614
 615                 writel(port_ofs + PDC_DIMM_ATA_PKT,
 616                        (void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
 617                 readl((void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
 618                 VPRINTK("submitted ofs 0x%x (%u), seq %u\n",
 619                         port_ofs + PDC_DIMM_ATA_PKT,
 620                         port_ofs + PDC_DIMM_ATA_PKT,
 621                         seq);
 622         }
 623 }
 624
 625 static inline unsigned int pdc20621_host_intr( struct ata_port *ap,
 626                                           struct ata_queued_cmd *qc,
 627                                           unsigned int doing_hdma,
 628                                           void *mmio)
 629 {
 630         unsigned int port_no = ap->port_no;
 631         unsigned int port_ofs =
 632                 PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
 633         u8 status;
 634         unsigned int handled = 0;
 635
 636         VPRINTK("ENTER\n");
 637
 638         if ((qc->tf.protocol == ATA_PROT_DMA) &&        /* read */
 639             (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
 640
 641                 /* step two - DMA from DIMM to host */
 642                 if (doing_hdma) {
 643                         VPRINTK("ata%u: read hdma, 0x%x 0x%x\n", ap->id,
 644                                 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
 645                         pdc_dma_complete(ap, qc, 0);
 646                         pdc20621_pop_hdma(qc);
 647                 }
 648
 649                 /* step one - exec ATA command */
 650                 else {
 651                         u8 seq = (u8) (port_no + 1 + 4);
 652                         VPRINTK("ata%u: read ata, 0x%x 0x%x\n", ap->id,
 653                                 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
 654
 655                         /* submit hdma pkt */
 656                         pdc20621_dump_hdma(qc);
 657                         pdc20621_push_hdma(qc, seq,
 658                                            port_ofs + PDC_DIMM_HOST_PKT);
 659                 }
 660                 handled = 1;
 661
 662         } else if (qc->tf.protocol == ATA_PROT_DMA) {   /* write */
 663
 664                 /* step one - DMA from host to DIMM */
 665                 if (doing_hdma) {
 666                         u8 seq = (u8) (port_no + 1);
 667                         VPRINTK("ata%u: write hdma, 0x%x 0x%x\n", ap->id,
 668                                 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
 669
 670                         /* submit ata pkt */
 671                         writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
 672                         readl(mmio + PDC_20621_SEQCTL + (seq * 4));
 673                         writel(port_ofs + PDC_DIMM_ATA_PKT,
 674                                (void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
 675                         readl((void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
 676                 }
 677
 678                 /* step two - execute ATA command */
 679                 else {
 680                         VPRINTK("ata%u: write ata, 0x%x 0x%x\n", ap->id,
 681                                 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
 682                         pdc_dma_complete(ap, qc, 0);
 683                         pdc20621_pop_hdma(qc);
 684                 }
 685                 handled = 1;
 686
 687         /* command completion, but no data xfer */
 688         } else if (qc->tf.protocol == ATA_PROT_NODATA) {
 689
 690                 status = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
 691                 DPRINTK("BUS_NODATA (drv_stat 0x%X)\n", status);
 692                 ata_qc_complete(qc, status);
 693                 handled = 1;
 694
 695         } else {
 696                 ap->stats.idle_irq++;
 697         }
 698
 699         return handled;
 700 }
 701
 702 static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
 703 {
 704         struct ata_host_set *host_set = dev_instance;
 705         struct ata_port *ap;
 706         u32 mask = 0;
 707         unsigned int i, tmp, port_no;
 708         unsigned int handled = 0;
 709         void *mmio_base;
 710
 711         VPRINTK("ENTER\n");
 712
 713         if (!host_set || !host_set->mmio_base) {
 714                 VPRINTK("QUICK EXIT\n");
 715                 return IRQ_NONE;
 716         }
 717
 718         mmio_base = host_set->mmio_base;
 719
 720         /* reading should also clear interrupts */
 721         mmio_base += PDC_CHIP0_OFS;
 722         mask = readl(mmio_base + PDC_20621_SEQMASK);
 723         VPRINTK("mask == 0x%x\n", mask);
 724
 725         if (mask == 0xffffffff) {
 726                 VPRINTK("QUICK EXIT 2\n");
 727                 return IRQ_NONE;
 728         }
 729         mask &= 0xffff;         /* only 16 tags possible */
 730         if (!mask) {
 731                 VPRINTK("QUICK EXIT 3\n");
 732                 return IRQ_NONE;
 733         }
 734
 735         spin_lock(&host_set->lock);
 736
 737         for (i = 1; i < 9; i++) {
 738                 port_no = i - 1;
 739                 if (port_no > 3)
 740                         port_no -= 4;
 741                 if (port_no >= host_set->n_ports)
 742                         ap = NULL;
 743                 else
 744                         ap = host_set->ports[port_no];
 745                 tmp = mask & (1 << i);
 746                 VPRINTK("seq %u, port_no %u, ap %p, tmp %x\n", i, port_no, ap, tmp);
 747                 if (tmp && ap && (!(ap->flags & ATA_FLAG_PORT_DISABLED))) {
 748                         struct ata_queued_cmd *qc;
 749
 750                         qc = ata_qc_from_tag(ap, ap->active_tag);
 751                         if (qc && (!(qc->tf.ctl & ATA_NIEN)))
 752                                 handled += pdc20621_host_intr(ap, qc, (i > 4),
 753                                                               mmio_base);
 754                 }
 755         }
 756
 757         spin_unlock(&host_set->lock);
 758
 759         VPRINTK("mask == 0x%x\n", mask);
 760
 761         VPRINTK("EXIT\n");
 762
 763         return IRQ_RETVAL(handled);
 764 }
 765
 766 static inline void pdc_dma_complete (struct ata_port *ap,
 767                                      struct ata_queued_cmd *qc,
 768                                      int have_err)
 769 {
 770         u8 err_bit = have_err ? ATA_ERR : 0;
 771
 772         /* get drive status; clear intr; complete txn */
 773         ata_qc_complete(qc, ata_wait_idle(ap) | err_bit);
 774 }
 775
 776 static void pdc_eng_timeout(struct ata_port *ap)
 777 {
 778         u8 drv_stat;
 779         struct ata_queued_cmd *qc;
 780
 781         DPRINTK("ENTER\n");
 782
 783         qc = ata_qc_from_tag(ap, ap->active_tag);
 784         if (!qc) {
 785                 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
 786                        ap->id);
 787                 goto out;
 788         }
 789
 790         /* hack alert!  We cannot use the supplied completion
 791          * function from inside the ->eh_strategy_handler() thread.
 792          * libata is the only user of ->eh_strategy_handler() in
 793          * any kernel, so the default scsi_done() assumes it is
 794          * not being called from the SCSI EH.
 795          */
 796         qc->scsidone = scsi_finish_command;
 797
 798         switch (qc->tf.protocol) {
 799         case ATA_PROT_DMA:
 800                 printk(KERN_ERR "ata%u: DMA timeout\n", ap->id);
 801                 ata_qc_complete(qc, ata_wait_idle(ap) | ATA_ERR);
 802                 break;
 803
 804         case ATA_PROT_NODATA:
 805                 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
 806
 807                 printk(KERN_ERR "ata%u: command 0x%x timeout, stat 0x%x\n",
 808                        ap->id, qc->tf.command, drv_stat);
 809
 810                 ata_qc_complete(qc, drv_stat);
 811                 break;
 812
 813         default:
 814                 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
 815
 816                 printk(KERN_ERR "ata%u: unknown timeout, cmd 0x%x stat 0x%x\n",
 817                        ap->id, qc->tf.command, drv_stat);
 818
 819                 ata_qc_complete(qc, drv_stat);
 820                 break;
 821         }
 822
 823 out:
 824         DPRINTK("EXIT\n");
 825 }
 826
 827 static void pdc_tf_load_mmio(struct ata_port *ap, struct ata_taskfile *tf)
 828 {
 829         if (tf->protocol != ATA_PROT_DMA)
 830                 ata_tf_load_mmio(ap, tf);
 831 }
 832
 833
 834 static void pdc_exec_command_mmio(struct ata_port *ap, struct ata_taskfile *tf)
 835 {
 836         if (tf->protocol != ATA_PROT_DMA)
 837                 ata_exec_command_mmio(ap, tf);
 838 }
 839
 840
 841 static void pdc_sata_setup_port(struct ata_ioports *port, unsigned long base)
 842 {
 843         port->cmd_addr          = base;
 844         port->data_addr         = base;
 845         port->feature_addr      =
 846         port->error_addr        = base + 0x4;
 847         port->nsect_addr        = base + 0x8;
 848         port->lbal_addr         = base + 0xc;
 849         port->lbam_addr         = base + 0x10;
 850         port->lbah_addr         = base + 0x14;
 851         port->device_addr       = base + 0x18;
 852         port->command_addr      =
 853         port->status_addr       = base + 0x1c;
 854         port->altstatus_addr    =
 855         port->ctl_addr          = base + 0x38;
 856 }
 857
 858
 859 #ifdef ATA_VERBOSE_DEBUG
 860 static void pdc20621_get_from_dimm(struct ata_probe_ent *pe, void *psource,
 861                                    u32 offset, u32 size)
 862 {
 863         u32 window_size;
 864         u16 idx;
 865         u8 page_mask;
 866         long dist;
 867         void *mmio = pe->mmio_base;
 868         struct pdc_host_priv *hpriv = pe->private_data;
 869         void *dimm_mmio = hpriv->dimm_mmio;
 870
 871         /* hard-code chip #0 */
 872         mmio += PDC_CHIP0_OFS;
 873
 874         page_mask = 0x00;
 875         window_size = 0x2000 * 4; /* 32K byte uchar size */
 876         idx = (u16) (offset / window_size);
 877
 878         writel(0x01, mmio + PDC_GENERAL_CTLR);
 879         readl(mmio + PDC_GENERAL_CTLR);
 880         writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
 881         readl(mmio + PDC_DIMM_WINDOW_CTLR);
 882
 883         offset -= (idx * window_size);
 884         idx++;
 885         dist = ((long) (window_size - (offset + size))) >= 0 ? size :
 886                 (long) (window_size - offset);
 887         memcpy_fromio((char *) psource, (char *) (dimm_mmio + offset / 4),
 888                       dist);
 889
 890         psource += dist;
 891         size -= dist;
 892         for (; (long) size >= (long) window_size ;) {
 893                 writel(0x01, mmio + PDC_GENERAL_CTLR);
 894                 readl(mmio + PDC_GENERAL_CTLR);
 895                 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
 896                 readl(mmio + PDC_DIMM_WINDOW_CTLR);
 897                 memcpy_fromio((char *) psource, (char *) (dimm_mmio),
 898                               window_size / 4);
 899                 psource += window_size;
 900                 size -= window_size;
 901                 idx ++;
 902         }
 903
 904         if (size) {
 905                 writel(0x01, mmio + PDC_GENERAL_CTLR);
 906                 readl(mmio + PDC_GENERAL_CTLR);
 907                 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
 908                 readl(mmio + PDC_DIMM_WINDOW_CTLR);
 909                 memcpy_fromio((char *) psource, (char *) (dimm_mmio),
 910                               size / 4);
 911         }
 912 }
 913 #endif
 914
 915
 916 static void pdc20621_put_to_dimm(struct ata_probe_ent *pe, void *psource,
 917                                  u32 offset, u32 size)
 918 {
 919         u32 window_size;
 920         u16 idx;
 921         u8 page_mask;
 922         long dist;
 923         void *mmio = pe->mmio_base;
 924         struct pdc_host_priv *hpriv = pe->private_data;
 925         void *dimm_mmio = hpriv->dimm_mmio;
 926
 927         /* hard-code chip #0 */
 928         mmio += PDC_CHIP0_OFS;
 929
 930         page_mask = 0x00;
 931         window_size = 0x2000 * 4;       /* 32K byte uchar size */
 932         idx = (u16) (offset / window_size);
 933
 934         writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
 935         readl(mmio + PDC_DIMM_WINDOW_CTLR);
 936         offset -= (idx * window_size);
 937         idx++;
 938         dist = ((long)(s32)(window_size - (offset + size))) >= 0 ? size :
 939                 (long) (window_size - offset);
 940         memcpy_toio((char *) (dimm_mmio + offset / 4), (char *) psource, dist);
 941         writel(0x01, mmio + PDC_GENERAL_CTLR);
 942         readl(mmio + PDC_GENERAL_CTLR);
 943
 944         psource += dist;
 945         size -= dist;
 946         for (; (long) size >= (long) window_size ;) {
 947                 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
 948                 readl(mmio + PDC_DIMM_WINDOW_CTLR);
 949                 memcpy_toio((char *) (dimm_mmio), (char *) psource,
 950                             window_size / 4);
 951                 writel(0x01, mmio + PDC_GENERAL_CTLR);
 952                 readl(mmio + PDC_GENERAL_CTLR);
 953                 psource += window_size;
 954                 size -= window_size;
 955                 idx ++;
 956         }
 957
 958         if (size) {
 959                 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
 960                 readl(mmio + PDC_DIMM_WINDOW_CTLR);
 961                 memcpy_toio((char *) (dimm_mmio), (char *) psource, size / 4);
 962                 writel(0x01, mmio + PDC_GENERAL_CTLR);
 963                 readl(mmio + PDC_GENERAL_CTLR);
 964         }
 965 }
 966
 967
 968 static unsigned int pdc20621_i2c_read(struct ata_probe_ent *pe, u32 device,
 969                                       u32 subaddr, u32 *pdata)
 970 {
 971         void *mmio = pe->mmio_base;
 972         u32 i2creg  = 0;
 973         u32 status;
 974         u32 count =0;
 975
 976         /* hard-code chip #0 */
 977         mmio += PDC_CHIP0_OFS;
 978
 979         i2creg |= device << 24;
 980         i2creg |= subaddr << 16;
 981
 982         /* Set the device and subaddress */
 983         writel(i2creg, mmio + PDC_I2C_ADDR_DATA_OFFSET);
 984         readl(mmio + PDC_I2C_ADDR_DATA_OFFSET);
 985
 986         /* Write Control to perform read operation, mask int */
 987         writel(PDC_I2C_READ | PDC_I2C_START | PDC_I2C_MASK_INT,
 988                mmio + PDC_I2C_CONTROL_OFFSET);
 989
 990         for (count = 0; count <= 1000; count ++) {
 991                 status = readl(mmio + PDC_I2C_CONTROL_OFFSET);
 992                 if (status & PDC_I2C_COMPLETE) {
 993                         status = readl(mmio + PDC_I2C_ADDR_DATA_OFFSET);
 994                         break;
 995                 } else if (count == 1000)
 996                         return 0;
 997         }
 998
 999         *pdata = (status >> 8) & 0x000000ff;
1000         return 1;
1001 }
1002
1003
1004 static int pdc20621_detect_dimm(struct ata_probe_ent *pe)
1005 {
1006         u32 data=0 ;
1007         if (pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1008                              PDC_DIMM_SPD_SYSTEM_FREQ, &data)) {
1009                 if (data == 100)
1010                         return 100;
1011         } else
1012                 return 0;
1013
1014         if (pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS, 9, &data)) {
1015                 if(data <= 0x75)
1016                         return 133;
1017         } else
1018                 return 0;
1019
1020         return 0;
1021 }
1022
1023
1024 static int pdc20621_prog_dimm0(struct ata_probe_ent *pe)
1025 {
1026         u32 spd0[50];
1027         u32 data = 0;
1028         int size, i;
1029         u8 bdimmsize;
1030         void *mmio = pe->mmio_base;
1031         static const struct {
1032                 unsigned int reg;
1033                 unsigned int ofs;
1034         } pdc_i2c_read_data [] = {
1035                 { PDC_DIMM_SPD_TYPE, 11 },
1036                 { PDC_DIMM_SPD_FRESH_RATE, 12 },
1037                 { PDC_DIMM_SPD_COLUMN_NUM, 4 },
1038                 { PDC_DIMM_SPD_ATTRIBUTE, 21 },
1039                 { PDC_DIMM_SPD_ROW_NUM, 3 },
1040                 { PDC_DIMM_SPD_BANK_NUM, 17 },
1041                 { PDC_DIMM_SPD_MODULE_ROW, 5 },
1042                 { PDC_DIMM_SPD_ROW_PRE_CHARGE, 27 },
1043                 { PDC_DIMM_SPD_ROW_ACTIVE_DELAY, 28 },
1044                 { PDC_DIMM_SPD_RAS_CAS_DELAY, 29 },
1045                 { PDC_DIMM_SPD_ACTIVE_PRECHARGE, 30 },
1046                 { PDC_DIMM_SPD_CAS_LATENCY, 18 },
1047         };
1048
1049         /* hard-code chip #0 */
1050         mmio += PDC_CHIP0_OFS;
1051
1052         for(i=0; i<ARRAY_SIZE(pdc_i2c_read_data); i++)
1053                 pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1054                                   pdc_i2c_read_data[i].reg,
1055                                   &spd0[pdc_i2c_read_data[i].ofs]);
1056
1057         data |= (spd0[4] - 8) | ((spd0[21] != 0) << 3) | ((spd0[3]-11) << 4);
1058         data |= ((spd0[17] / 4) << 6) | ((spd0[5] / 2) << 7) |
1059                 ((((spd0[27] + 9) / 10) - 1) << 8) ;
1060         data |= (((((spd0[29] > spd0[28])
1061                     ? spd0[29] : spd0[28]) + 9) / 10) - 1) << 10;
1062         data |= ((spd0[30] - spd0[29] + 9) / 10 - 2) << 12;
1063
1064         if (spd0[18] & 0x08)
1065                 data |= ((0x03) << 14);
1066         else if (spd0[18] & 0x04)
1067                 data |= ((0x02) << 14);
1068         else if (spd0[18] & 0x01)
1069                 data |= ((0x01) << 14);
1070         else
1071                 data |= (0 << 14);
1072
1073         /*
1074            Calculate the size of bDIMMSize (power of 2) and
1075            merge the DIMM size by program start/end address.
1076         */
1077
1078         bdimmsize = spd0[4] + (spd0[5] / 2) + spd0[3] + (spd0[17] / 2) + 3;
1079         size = (1 << bdimmsize) >> 20;  /* size = xxx(MB) */
1080         data |= (((size / 16) - 1) << 16);
1081         data |= (0 << 23);
1082         data |= 8;
1083         writel(data, mmio + PDC_DIMM0_CONTROL_OFFSET);
1084         readl(mmio + PDC_DIMM0_CONTROL_OFFSET);
1085         return size;
1086 }
1087
1088
1089 static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent *pe)
1090 {
1091         u32 data, spd0;
1092         int error, i;
1093         void *mmio = pe->mmio_base;
1094
1095         /* hard-code chip #0 */
1096         mmio += PDC_CHIP0_OFS;
1097
1098         /*
1099           Set To Default : DIMM Module Global Control Register (0x022259F1)
1100           DIMM Arbitration Disable (bit 20)
1101           DIMM Data/Control Output Driving Selection (bit12 - bit15)
1102           Refresh Enable (bit 17)
1103         */
1104
1105         data = 0x022259F1;
1106         writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
1107         readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
1108
1109         /* Turn on for ECC */
1110         pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1111                           PDC_DIMM_SPD_TYPE, &spd0);
1112         if (spd0 == 0x02) {
1113                 data |= (0x01 << 16);
1114                 writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
1115                 readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
1116                 printk(KERN_ERR "Local DIMM ECC Enabled\n");
1117         }
1118
1119         /* DIMM Initialization Select/Enable (bit 18/19) */
1120         data &= (~(1<<18));
1121         data |= (1<<19);
1122         writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
1123
1124         error = 1;
1125         for (i = 1; i <= 10; i++) {   /* polling ~5 secs */
1126                 data = readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
1127                 if (!(data & (1<<19))) {
1128                         error = 0;
1129                         break;
1130                 }
1131                 set_current_state(TASK_UNINTERRUPTIBLE);
1132                 schedule_timeout((i * 100) * HZ / 1000 + 1);
1133         }
1134         return error;
1135 }
1136
1137
1138 static unsigned int pdc20621_dimm_init(struct ata_probe_ent *pe)
1139 {
1140         int speed, size, length;
1141         u32 addr,spd0,pci_status;
1142         u32 tmp=0;
1143         u32 time_period=0;
1144         u32 tcount=0;
1145         u32 ticks=0;
1146         u32 clock=0;
1147         u32 fparam=0;
1148         void *mmio = pe->mmio_base;
1149
1150         /* hard-code chip #0 */
1151         mmio += PDC_CHIP0_OFS;
1152
1153         /* Initialize PLL based upon PCI Bus Frequency */
1154
1155         /* Initialize Time Period Register */
1156         writel(0xffffffff, mmio + PDC_TIME_PERIOD);
1157         time_period = readl(mmio + PDC_TIME_PERIOD);
1158         VPRINTK("Time Period Register (0x40): 0x%x\n", time_period);
1159
1160         /* Enable timer */
1161         writel(0x00001a0, mmio + PDC_TIME_CONTROL);
1162         readl(mmio + PDC_TIME_CONTROL);
1163
1164         /* Wait 3 seconds */
1165         set_current_state(TASK_UNINTERRUPTIBLE);
1166         schedule_timeout(3 * HZ);
1167
1168         /*
1169            When timer is enabled, counter is decreased every internal
1170            clock cycle.
1171         */
1172
1173         tcount = readl(mmio + PDC_TIME_COUNTER);
1174         VPRINTK("Time Counter Register (0x44): 0x%x\n", tcount);
1175
1176         /*
1177            If SX4 is on PCI-X bus, after 3 seconds, the timer counter
1178            register should be >= (0xffffffff - 3x10^8).
1179         */
1180         if(tcount >= PCI_X_TCOUNT) {
1181                 ticks = (time_period - tcount);
1182                 VPRINTK("Num counters 0x%x (%d)\n", ticks, ticks);
1183
1184                 clock = (ticks / 300000);
1185                 VPRINTK("10 * Internal clk = 0x%x (%d)\n", clock, clock);
1186
1187                 clock = (clock * 33);
1188                 VPRINTK("10 * Internal clk * 33 = 0x%x (%d)\n", clock, clock);
1189
1190                 /* PLL F Param (bit 22:16) */
1191                 fparam = (1400000 / clock) - 2;
1192                 VPRINTK("PLL F Param: 0x%x (%d)\n", fparam, fparam);
1193
1194                 /* OD param = 0x2 (bit 31:30), R param = 0x5 (bit 29:25) */
1195                 pci_status = (0x8a001824 | (fparam << 16));
1196         } else
1197                 pci_status = PCI_PLL_INIT;
1198
1199         /* Initialize PLL. */
1200         VPRINTK("pci_status: 0x%x\n", pci_status);
1201         writel(pci_status, mmio + PDC_CTL_STATUS);
1202         readl(mmio + PDC_CTL_STATUS);
1203
1204         /*
1205            Read SPD of DIMM by I2C interface,
1206            and program the DIMM Module Controller.
1207         */
1208         if (!(speed = pdc20621_detect_dimm(pe))) {
1209                 printk(KERN_ERR "Detect Local DIMM Fail\n");
1210                 return 1;       /* DIMM error */
1211         }
1212         VPRINTK("Local DIMM Speed = %d\n", speed);
1213
1214         /* Programming DIMM0 Module Control Register (index_CID0:80h) */
1215         size = pdc20621_prog_dimm0(pe);
1216         VPRINTK("Local DIMM Size = %dMB\n",size);
1217
1218         /* Programming DIMM Module Global Control Register (index_CID0:88h) */
1219         if (pdc20621_prog_dimm_global(pe)) {
1220                 printk(KERN_ERR "Programming DIMM Module Global Control Register Fail\n");
1221                 return 1;
1222         }
1223
1224 #ifdef ATA_VERBOSE_DEBUG
1225         {
1226                 u8 test_parttern1[40] = {0x55,0xAA,'P','r','o','m','i','s','e',' ',
1227                                 'N','o','t',' ','Y','e','t',' ','D','e','f','i','n','e','d',' ',
1228                                  '1','.','1','0',
1229                                 '9','8','0','3','1','6','1','2',0,0};
1230                 u8 test_parttern2[40] = {0};
1231
1232                 pdc20621_put_to_dimm(pe, (void *) test_parttern2, 0x10040, 40);
1233                 pdc20621_put_to_dimm(pe, (void *) test_parttern2, 0x40, 40);
1234
1235                 pdc20621_put_to_dimm(pe, (void *) test_parttern1, 0x10040, 40);
1236                 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x40, 40);
1237                 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1238                        test_parttern2[1], &(test_parttern2[2]));
1239                 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x10040,
1240                                        40);
1241                 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1242                        test_parttern2[1], &(test_parttern2[2]));
1243
1244                 pdc20621_put_to_dimm(pe, (void *) test_parttern1, 0x40, 40);
1245                 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x40, 40);
1246                 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1247                        test_parttern2[1], &(test_parttern2[2]));
1248         }
1249 #endif
1250
1251         /* ECC initiliazation. */
1252
1253         pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1254                           PDC_DIMM_SPD_TYPE, &spd0);
1255         if (spd0 == 0x02) {
1256                 VPRINTK("Start ECC initialization\n");
1257                 addr = 0;
1258                 length = size * 1024 * 1024;
1259                 while (addr < length) {
1260                         pdc20621_put_to_dimm(pe, (void *) &tmp, addr,
1261                                              sizeof(u32));
1262                         addr += sizeof(u32);
1263                 }
1264                 VPRINTK("Finish ECC initialization\n");
1265         }
1266         return 0;
1267 }
1268
1269
1270 static void pdc_20621_init(struct ata_probe_ent *pe)
1271 {
1272         u32 tmp;
1273         void *mmio = pe->mmio_base;
1274
1275         /* hard-code chip #0 */
1276         mmio += PDC_CHIP0_OFS;
1277
1278         /*
1279          * Select page 0x40 for our 32k DIMM window
1280          */
1281         tmp = readl(mmio + PDC_20621_DIMM_WINDOW) & 0xffff0000;
1282         tmp |= PDC_PAGE_WINDOW; /* page 40h; arbitrarily selected */
1283         writel(tmp, mmio + PDC_20621_DIMM_WINDOW);
1284
1285         /*
1286          * Reset Host DMA
1287          */
1288         tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1289         tmp |= PDC_RESET;
1290         writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1291         readl(mmio + PDC_HDMA_CTLSTAT);         /* flush */
1292
1293         udelay(10);
1294
1295         tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1296         tmp &= ~PDC_RESET;
1297         writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1298         readl(mmio + PDC_HDMA_CTLSTAT);         /* flush */
1299 }
1300
1301 static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1302 {
1303         static int printed_version;
1304         struct ata_probe_ent *probe_ent = NULL;
1305         unsigned long base;
1306         void *mmio_base, *dimm_mmio = NULL;
1307         struct pdc_host_priv *hpriv = NULL;
1308         unsigned int board_idx = (unsigned int) ent->driver_data;
1309         int rc;
1310
1311         if (!printed_version++)
1312                 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
1313
1314         /*
1315          * If this driver happens to only be useful on Apple's K2, then
1316          * we should check that here as it has a normal Serverworks ID
1317          */
1318         rc = pci_enable_device(pdev);
1319         if (rc)
1320                 return rc;
1321
1322         rc = pci_request_regions(pdev, DRV_NAME);
1323         if (rc)
1324                 goto err_out;
1325
1326         rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1327         if (rc)
1328                 goto err_out_regions;
1329         rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1330         if (rc)
1331                 goto err_out_regions;
1332
1333         probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1334         if (probe_ent == NULL) {
1335                 rc = -ENOMEM;
1336                 goto err_out_regions;
1337         }
1338
1339         memset(probe_ent, 0, sizeof(*probe_ent));
1340         probe_ent->pdev = pdev;
1341         INIT_LIST_HEAD(&probe_ent->node);
1342
1343         mmio_base = ioremap(pci_resource_start(pdev, 3),
1344                             pci_resource_len(pdev, 3));
1345         if (mmio_base == NULL) {
1346                 rc = -ENOMEM;
1347                 goto err_out_free_ent;
1348         }
1349         base = (unsigned long) mmio_base;
1350
1351         hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1352         if (!hpriv) {
1353                 rc = -ENOMEM;
1354                 goto err_out_iounmap;
1355         }
1356         memset(hpriv, 0, sizeof(*hpriv));
1357
1358         dimm_mmio = ioremap(pci_resource_start(pdev, 4),
1359                             pci_resource_len(pdev, 4));
1360         if (!dimm_mmio) {
1361                 kfree(hpriv);
1362                 rc = -ENOMEM;
1363                 goto err_out_iounmap;
1364         }
1365
1366         hpriv->dimm_mmio = dimm_mmio;
1367
1368         probe_ent->sht          = pdc_port_info[board_idx].sht;
1369         probe_ent->host_flags   = pdc_port_info[board_idx].host_flags;
1370         probe_ent->pio_mask     = pdc_port_info[board_idx].pio_mask;
1371         probe_ent->udma_mask    = pdc_port_info[board_idx].udma_mask;
1372         probe_ent->port_ops     = pdc_port_info[board_idx].port_ops;
1373
1374         probe_ent->irq = pdev->irq;
1375         probe_ent->irq_flags = SA_SHIRQ;
1376         probe_ent->mmio_base = mmio_base;
1377
1378         probe_ent->private_data = hpriv;
1379         base += PDC_CHIP0_OFS;
1380
1381         pdc_sata_setup_port(&probe_ent->port[0], base + 0x200);
1382         pdc_sata_setup_port(&probe_ent->port[1], base + 0x280);
1383
1384         /* notice 4-port boards */
1385         switch (board_idx) {
1386         case board_20621:
1387                 probe_ent->n_ports = 4;
1388
1389                 pdc_sata_setup_port(&probe_ent->port[2], base + 0x300);
1390                 pdc_sata_setup_port(&probe_ent->port[3], base + 0x380);
1391                 break;
1392         default:
1393                 BUG();
1394                 break;
1395         }
1396
1397         pci_set_master(pdev);
1398
1399         /* initialize adapter */
1400         /* initialize local dimm */
1401         if (pdc20621_dimm_init(probe_ent)) {
1402                 rc = -ENOMEM;
1403                 goto err_out_iounmap_dimm;
1404         }
1405         pdc_20621_init(probe_ent);
1406
1407         /* FIXME: check ata_device_add return value */
1408         ata_device_add(probe_ent);
1409         kfree(probe_ent);
1410
1411         return 0;
1412
1413 err_out_iounmap_dimm:           /* only get to this label if 20621 */
1414         kfree(hpriv);
1415         iounmap(dimm_mmio);
1416 err_out_iounmap:
1417         iounmap(mmio_base);
1418 err_out_free_ent:
1419         kfree(probe_ent);
1420 err_out_regions:
1421         pci_release_regions(pdev);
1422 err_out:
1423         pci_disable_device(pdev);
1424         return rc;
1425 }
1426
1427
1428 static int __init pdc_sata_init(void)
1429 {
1430         return pci_module_init(&pdc_sata_pci_driver);
1431 }
1432
1433
1434 static void __exit pdc_sata_exit(void)
1435 {
1436         pci_unregister_driver(&pdc_sata_pci_driver);
1437 }
1438
1439
1440 MODULE_AUTHOR("Jeff Garzik");
1441 MODULE_DESCRIPTION("Promise SATA low-level driver");
1442 MODULE_LICENSE("GPL");
1443 MODULE_DEVICE_TABLE(pci, pdc_sata_pci_tbl);
1444
1445 module_init(pdc_sata_init);
1446 module_exit(pdc_sata_exit);