drivers/scsi/sata_sx4.c

   1 /*
   2  *  sata_sx4.c - Promise SATA
   3  *
   4  *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
   5  *                  Please ALWAYS copy linux-ide@vger.kernel.org
   6  *                  on emails.
   7  *
   8  *  Copyright 2003-2004 Red Hat, Inc.
   9  *
  10  *  The contents of this file are subject to the Open
  11  *  Software License version 1.1 that can be found at
  12  *  http://www.opensource.org/licenses/osl-1.1.txt and is included herein
  13  *  by reference.
  14  *
  15  *  Alternatively, the contents of this file may be used under the terms
  16  *  of the GNU General Public License version 2 (the "GPL") as distributed
  17  *  in the kernel source COPYING file, in which case the provisions of
  18  *  the GPL are applicable instead of the above.  If you wish to allow
  19  *  the use of your version of this file only under the terms of the
  20  *  GPL and not to allow others to use your version of this file under
  21  *  the OSL, indicate your decision by deleting the provisions above and
  22  *  replace them with the notice and other provisions required by the GPL.
  23  *  If you do not delete the provisions above, a recipient may use your
  24  *  version of this file under either the OSL or the GPL.
  25  *
  26  */
  27
  28 #include <linux/kernel.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/init.h>
  32 #include <linux/blkdev.h>
  33 #include <linux/delay.h>
  34 #include <linux/interrupt.h>
  35 #include <linux/sched.h>
  36 #include "scsi.h"
  37 #include <scsi/scsi_host.h>
  38 #include <linux/libata.h>
  39 #include <asm/io.h>
  40 #include "sata_promise.h"
  41
  42 #define DRV_NAME        "sata_sx4"
  43 #define DRV_VERSION     "0.50"
  44
  45
  46 enum {
  47         PDC_PRD_TBL             = 0x44, /* Direct command DMA table addr */
  48
  49         PDC_PKT_SUBMIT          = 0x40, /* Command packet pointer addr */
  50         PDC_HDMA_PKT_SUBMIT     = 0x100, /* Host DMA packet pointer addr */
  51         PDC_INT_SEQMASK         = 0x40, /* Mask of asserted SEQ INTs */
  52         PDC_HDMA_CTLSTAT        = 0x12C, /* Host DMA control / status */
  53
  54         PDC_20621_SEQCTL        = 0x400,
  55         PDC_20621_SEQMASK       = 0x480,
  56         PDC_20621_GENERAL_CTL   = 0x484,
  57         PDC_20621_PAGE_SIZE     = (32 * 1024),
  58
  59         /* chosen, not constant, values; we design our own DIMM mem map */
  60         PDC_20621_DIMM_WINDOW   = 0x0C, /* page# for 32K DIMM window */
  61         PDC_20621_DIMM_BASE     = 0x00200000,
  62         PDC_20621_DIMM_DATA     = (64 * 1024),
  63         PDC_DIMM_DATA_STEP      = (256 * 1024),
  64         PDC_DIMM_WINDOW_STEP    = (8 * 1024),
  65         PDC_DIMM_HOST_PRD       = (6 * 1024),
  66         PDC_DIMM_HOST_PKT       = (128 * 0),
  67         PDC_DIMM_HPKT_PRD       = (128 * 1),
  68         PDC_DIMM_ATA_PKT        = (128 * 2),
  69         PDC_DIMM_APKT_PRD       = (128 * 3),
  70         PDC_DIMM_HEADER_SZ      = PDC_DIMM_APKT_PRD + 128,
  71         PDC_PAGE_WINDOW         = 0x40,
  72         PDC_PAGE_DATA           = PDC_PAGE_WINDOW +
  73                                   (PDC_20621_DIMM_DATA / PDC_20621_PAGE_SIZE),
  74         PDC_PAGE_SET            = PDC_DIMM_DATA_STEP / PDC_20621_PAGE_SIZE,
  75
  76         PDC_CHIP0_OFS           = 0xC0000, /* offset of chip #0 */
  77
  78         PDC_20621_ERR_MASK      = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
  79                                   (1<<23),
  80
  81         board_20621             = 0,    /* FastTrak S150 SX4 */
  82
  83         PDC_RESET               = (1 << 11), /* HDMA reset */
  84
  85         PDC_MAX_HDMA            = 32,
  86         PDC_HDMA_Q_MASK         = (PDC_MAX_HDMA - 1),
  87
  88         PDC_DIMM0_SPD_DEV_ADDRESS     = 0x50,
  89         PDC_DIMM1_SPD_DEV_ADDRESS     = 0x51,
  90         PDC_MAX_DIMM_MODULE           = 0x02,
  91         PDC_I2C_CONTROL_OFFSET        = 0x48,
  92         PDC_I2C_ADDR_DATA_OFFSET      = 0x4C,
  93         PDC_DIMM0_CONTROL_OFFSET      = 0x80,
  94         PDC_DIMM1_CONTROL_OFFSET      = 0x84,
  95         PDC_SDRAM_CONTROL_OFFSET      = 0x88,
  96         PDC_I2C_WRITE                 = 0x00000000,
  97         PDC_I2C_READ                  = 0x00000040,
  98         PDC_I2C_START                 = 0x00000080,
  99         PDC_I2C_MASK_INT              = 0x00000020,
 100         PDC_I2C_COMPLETE              = 0x00010000,
 101         PDC_I2C_NO_ACK                = 0x00100000,
 102         PDC_DIMM_SPD_SUBADDRESS_START = 0x00,
 103         PDC_DIMM_SPD_SUBADDRESS_END   = 0x7F,
 104         PDC_DIMM_SPD_ROW_NUM          = 3,
 105         PDC_DIMM_SPD_COLUMN_NUM       = 4,
 106         PDC_DIMM_SPD_MODULE_ROW       = 5,
 107         PDC_DIMM_SPD_TYPE             = 11,
 108         PDC_DIMM_SPD_FRESH_RATE       = 12,
 109         PDC_DIMM_SPD_BANK_NUM         = 17,
 110         PDC_DIMM_SPD_CAS_LATENCY      = 18,
 111         PDC_DIMM_SPD_ATTRIBUTE        = 21,
 112         PDC_DIMM_SPD_ROW_PRE_CHARGE   = 27,
 113         PDC_DIMM_SPD_ROW_ACTIVE_DELAY = 28,
 114         PDC_DIMM_SPD_RAS_CAS_DELAY    = 29,
 115         PDC_DIMM_SPD_ACTIVE_PRECHARGE = 30,
 116         PDC_DIMM_SPD_SYSTEM_FREQ      = 126,
 117         PDC_CTL_STATUS                = 0x08,
 118         PDC_DIMM_WINDOW_CTLR          = 0x0C,
 119         PDC_TIME_CONTROL              = 0x3C,
 120         PDC_TIME_PERIOD               = 0x40,
 121         PDC_TIME_COUNTER              = 0x44,
 122         PDC_GENERAL_CTLR              = 0x484,
 123         PCI_PLL_INIT                  = 0x8A531824,
 124         PCI_X_TCOUNT                  = 0xEE1E5CFF
 125 };
 126
 127
 128 struct pdc_port_priv {
 129         u8                      dimm_buf[(ATA_PRD_SZ * ATA_MAX_PRD) + 512];
 130         u8                      *pkt;
 131         dma_addr_t              pkt_dma;
 132 };
 133
 134 struct pdc_host_priv {
 135         void                    *dimm_mmio;
 136
 137         unsigned int            doing_hdma;
 138         unsigned int            hdma_prod;
 139         unsigned int            hdma_cons;
 140         struct {
 141                 struct ata_queued_cmd *qc;
 142                 unsigned int    seq;
 143                 unsigned long   pkt_ofs;
 144         } hdma[32];
 145 };
 146
 147
 148 static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
 149 static void pdc20621_dma_setup(struct ata_queued_cmd *qc);
 150 static void pdc20621_dma_start(struct ata_queued_cmd *qc);
 151 static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
 152 static void pdc_eng_timeout(struct ata_port *ap);
 153 static void pdc_20621_phy_reset (struct ata_port *ap);
 154 static int pdc_port_start(struct ata_port *ap);
 155 static void pdc_port_stop(struct ata_port *ap);
 156 static void pdc20621_qc_prep(struct ata_queued_cmd *qc);
 157 static void pdc_tf_load_mmio(struct ata_port *ap, struct ata_taskfile *tf);
 158 static void pdc_exec_command_mmio(struct ata_port *ap, struct ata_taskfile *tf);
 159 static void pdc20621_host_stop(struct ata_host_set *host_set);
 160 static inline void pdc_dma_complete (struct ata_port *ap,
 161                                      struct ata_queued_cmd *qc, int have_err);
 162 static unsigned int pdc20621_dimm_init(struct ata_probe_ent *pe);
 163 static int pdc20621_detect_dimm(struct ata_probe_ent *pe);
 164 static unsigned int pdc20621_i2c_read(struct ata_probe_ent *pe,
 165                                       u32 device, u32 subaddr, u32 *pdata);
 166 static int pdc20621_prog_dimm0(struct ata_probe_ent *pe);
 167 static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent *pe);
 168 #ifdef ATA_VERBOSE_DEBUG
 169 static void pdc20621_get_from_dimm(struct ata_probe_ent *pe,
 170                                    void *psource, u32 offset, u32 size);
 171 #endif
 172 static void pdc20621_put_to_dimm(struct ata_probe_ent *pe,
 173                                  void *psource, u32 offset, u32 size);
 174 static void pdc20621_irq_clear(struct ata_port *ap);
 175
 176
 177 static Scsi_Host_Template pdc_sata_sht = {
 178         .module                 = THIS_MODULE,
 179         .name                   = DRV_NAME,
 180         .queuecommand           = ata_scsi_queuecmd,
 181         .eh_strategy_handler    = ata_scsi_error,
 182         .can_queue              = ATA_DEF_QUEUE,
 183         .this_id                = ATA_SHT_THIS_ID,
 184         .sg_tablesize           = LIBATA_MAX_PRD,
 185         .max_sectors            = ATA_MAX_SECTORS,
 186         .cmd_per_lun            = ATA_SHT_CMD_PER_LUN,
 187         .emulated               = ATA_SHT_EMULATED,
 188         .use_clustering         = ATA_SHT_USE_CLUSTERING,
 189         .proc_name              = DRV_NAME,
 190         .dma_boundary           = ATA_DMA_BOUNDARY,
 191         .slave_configure        = ata_scsi_slave_config,
 192         .bios_param             = ata_std_bios_param,
 193 };
 194
 195 static struct ata_port_operations pdc_20621_ops = {
 196         .port_disable           = ata_port_disable,
 197         .tf_load                = pdc_tf_load_mmio,
 198         .tf_read                = ata_tf_read_mmio,
 199         .check_status           = ata_check_status_mmio,
 200         .exec_command           = pdc_exec_command_mmio,
 201         .phy_reset              = pdc_20621_phy_reset,
 202         .bmdma_setup            = pdc20621_dma_setup,
 203         .bmdma_start            = pdc20621_dma_start,
 204         .qc_prep                = pdc20621_qc_prep,
 205         .qc_issue               = ata_qc_issue_prot,
 206         .eng_timeout            = pdc_eng_timeout,
 207         .irq_handler            = pdc20621_interrupt,
 208         .irq_clear              = pdc20621_irq_clear,
 209         .port_start             = pdc_port_start,
 210         .port_stop              = pdc_port_stop,
 211         .host_stop              = pdc20621_host_stop,
 212 };
 213
 214 static struct ata_port_info pdc_port_info[] = {
 215         /* board_20621 */
 216         {
 217                 .sht            = &pdc_sata_sht,
 218                 .host_flags     = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
 219                                   ATA_FLAG_SRST | ATA_FLAG_MMIO,
 220                 .pio_mask       = 0x03, /* pio3-4 */
 221                 .udma_mask      = 0x7f, /* udma0-6 ; FIXME */
 222                 .port_ops       = &pdc_20621_ops,
 223         },
 224
 225 };
 226
 227 static struct pci_device_id pdc_sata_pci_tbl[] = {
 228         { PCI_VENDOR_ID_PROMISE, 0x6622, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
 229           board_20621 },
 230         { }     /* terminate list */
 231 };
 232
 233
 234 static struct pci_driver pdc_sata_pci_driver = {
 235         .name                   = DRV_NAME,
 236         .id_table               = pdc_sata_pci_tbl,
 237         .probe                  = pdc_sata_init_one,
 238         .remove                 = ata_pci_remove_one,
 239 };
 240
 241
 242 static void pdc20621_host_stop(struct ata_host_set *host_set)
 243 {
 244         struct pdc_host_priv *hpriv = host_set->private_data;
 245         void *dimm_mmio = hpriv->dimm_mmio;
 246
 247         iounmap(dimm_mmio);
 248         kfree(hpriv);
 249 }
 250
 251 static int pdc_port_start(struct ata_port *ap)
 252 {
 253         struct pci_dev *pdev = ap->host_set->pdev;
 254         struct pdc_port_priv *pp;
 255         int rc;
 256
 257         rc = ata_port_start(ap);
 258         if (rc)
 259                 return rc;
 260
 261         pp = kmalloc(sizeof(*pp), GFP_KERNEL);
 262         if (!pp) {
 263                 rc = -ENOMEM;
 264                 goto err_out;
 265         }
 266         memset(pp, 0, sizeof(*pp));
 267
 268         pp->pkt = pci_alloc_consistent(pdev, 128, &pp->pkt_dma);
 269         if (!pp->pkt) {
 270                 rc = -ENOMEM;
 271                 goto err_out_kfree;
 272         }
 273
 274         ap->private_data = pp;
 275
 276         return 0;
 277
 278 err_out_kfree:
 279         kfree(pp);
 280 err_out:
 281         ata_port_stop(ap);
 282         return rc;
 283 }
 284
 285
 286 static void pdc_port_stop(struct ata_port *ap)
 287 {
 288         struct pci_dev *pdev = ap->host_set->pdev;
 289         struct pdc_port_priv *pp = ap->private_data;
 290
 291         ap->private_data = NULL;
 292         pci_free_consistent(pdev, 128, pp->pkt, pp->pkt_dma);
 293         kfree(pp);
 294         ata_port_stop(ap);
 295 }
 296
 297
 298 static void pdc_20621_phy_reset (struct ata_port *ap)
 299 {
 300         VPRINTK("ENTER\n");
 301         ap->cbl = ATA_CBL_SATA;
 302         ata_port_probe(ap);
 303         ata_bus_reset(ap);
 304 }
 305
 306 static inline void pdc20621_ata_sg(struct ata_taskfile *tf, u8 *buf,
 307                                            unsigned int portno,
 308                                            unsigned int total_len)
 309 {
 310         u32 addr;
 311         unsigned int dw = PDC_DIMM_APKT_PRD >> 2;
 312         u32 *buf32 = (u32 *) buf;
 313
 314         /* output ATA packet S/G table */
 315         addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
 316                (PDC_DIMM_DATA_STEP * portno);
 317         VPRINTK("ATA sg addr 0x%x, %d\n", addr, addr);
 318         buf32[dw] = cpu_to_le32(addr);
 319         buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
 320
 321         VPRINTK("ATA PSG @ %x == (0x%x, 0x%x)\n",
 322                 PDC_20621_DIMM_BASE +
 323                        (PDC_DIMM_WINDOW_STEP * portno) +
 324                        PDC_DIMM_APKT_PRD,
 325                 buf32[dw], buf32[dw + 1]);
 326 }
 327
 328 static inline void pdc20621_host_sg(struct ata_taskfile *tf, u8 *buf,
 329                                             unsigned int portno,
 330                                             unsigned int total_len)
 331 {
 332         u32 addr;
 333         unsigned int dw = PDC_DIMM_HPKT_PRD >> 2;
 334         u32 *buf32 = (u32 *) buf;
 335
 336         /* output Host DMA packet S/G table */
 337         addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
 338                (PDC_DIMM_DATA_STEP * portno);
 339
 340         buf32[dw] = cpu_to_le32(addr);
 341         buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
 342
 343         VPRINTK("HOST PSG @ %x == (0x%x, 0x%x)\n",
 344                 PDC_20621_DIMM_BASE +
 345                        (PDC_DIMM_WINDOW_STEP * portno) +
 346                        PDC_DIMM_HPKT_PRD,
 347                 buf32[dw], buf32[dw + 1]);
 348 }
 349
 350 static inline unsigned int pdc20621_ata_pkt(struct ata_taskfile *tf,
 351                                             unsigned int devno, u8 *buf,
 352                                             unsigned int portno)
 353 {
 354         unsigned int i, dw;
 355         u32 *buf32 = (u32 *) buf;
 356         u8 dev_reg;
 357
 358         unsigned int dimm_sg = PDC_20621_DIMM_BASE +
 359                                (PDC_DIMM_WINDOW_STEP * portno) +
 360                                PDC_DIMM_APKT_PRD;
 361         VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
 362
 363         i = PDC_DIMM_ATA_PKT;
 364
 365         /*
 366          * Set up ATA packet
 367          */
 368         if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
 369                 buf[i++] = PDC_PKT_READ;
 370         else if (tf->protocol == ATA_PROT_NODATA)
 371                 buf[i++] = PDC_PKT_NODATA;
 372         else
 373                 buf[i++] = 0;
 374         buf[i++] = 0;                   /* reserved */
 375         buf[i++] = portno + 1;          /* seq. id */
 376         buf[i++] = 0xff;                /* delay seq. id */
 377
 378         /* dimm dma S/G, and next-pkt */
 379         dw = i >> 2;
 380         buf32[dw] = cpu_to_le32(dimm_sg);
 381         buf32[dw + 1] = 0;
 382         i += 8;
 383
 384         if (devno == 0)
 385                 dev_reg = ATA_DEVICE_OBS;
 386         else
 387                 dev_reg = ATA_DEVICE_OBS | ATA_DEV1;
 388
 389         /* select device */
 390         buf[i++] = (1 << 5) | PDC_PKT_CLEAR_BSY | ATA_REG_DEVICE;
 391         buf[i++] = dev_reg;
 392
 393         /* device control register */
 394         buf[i++] = (1 << 5) | PDC_REG_DEVCTL;
 395         buf[i++] = tf->ctl;
 396
 397         return i;
 398 }
 399
 400 static inline void pdc20621_host_pkt(struct ata_taskfile *tf, u8 *buf,
 401                                      unsigned int portno)
 402 {
 403         unsigned int dw;
 404         u32 tmp, *buf32 = (u32 *) buf;
 405
 406         unsigned int host_sg = PDC_20621_DIMM_BASE +
 407                                (PDC_DIMM_WINDOW_STEP * portno) +
 408                                PDC_DIMM_HOST_PRD;
 409         unsigned int dimm_sg = PDC_20621_DIMM_BASE +
 410                                (PDC_DIMM_WINDOW_STEP * portno) +
 411                                PDC_DIMM_HPKT_PRD;
 412         VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
 413         VPRINTK("host_sg == 0x%x, %d\n", host_sg, host_sg);
 414
 415         dw = PDC_DIMM_HOST_PKT >> 2;
 416
 417         /*
 418          * Set up Host DMA packet
 419          */
 420         if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
 421                 tmp = PDC_PKT_READ;
 422         else
 423                 tmp = 0;
 424         tmp |= ((portno + 1 + 4) << 16);        /* seq. id */
 425         tmp |= (0xff << 24);                    /* delay seq. id */
 426         buf32[dw + 0] = cpu_to_le32(tmp);
 427         buf32[dw + 1] = cpu_to_le32(host_sg);
 428         buf32[dw + 2] = cpu_to_le32(dimm_sg);
 429         buf32[dw + 3] = 0;
 430
 431         VPRINTK("HOST PKT @ %x == (0x%x 0x%x 0x%x 0x%x)\n",
 432                 PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * portno) +
 433                         PDC_DIMM_HOST_PKT,
 434                 buf32[dw + 0],
 435                 buf32[dw + 1],
 436                 buf32[dw + 2],
 437                 buf32[dw + 3]);
 438 }
 439
 440 static void pdc20621_qc_prep(struct ata_queued_cmd *qc)
 441 {
 442         struct scatterlist *sg = qc->sg;
 443         struct ata_port *ap = qc->ap;
 444         struct pdc_port_priv *pp = ap->private_data;
 445         void *mmio = ap->host_set->mmio_base;
 446         struct pdc_host_priv *hpriv = ap->host_set->private_data;
 447         void *dimm_mmio = hpriv->dimm_mmio;
 448         unsigned int portno = ap->port_no;
 449         unsigned int i, last, idx, total_len = 0, sgt_len;
 450         u32 *buf = (u32 *) &pp->dimm_buf[PDC_DIMM_HEADER_SZ];
 451
 452         if (!(qc->flags & ATA_QCFLAG_DMAMAP))
 453                 return;
 454
 455         VPRINTK("ata%u: ENTER\n", ap->id);
 456
 457         /* hard-code chip #0 */
 458         mmio += PDC_CHIP0_OFS;
 459
 460         /*
 461          * Build S/G table
 462          */
 463         last = qc->n_elem;
 464         idx = 0;
 465         for (i = 0; i < last; i++) {
 466                 buf[idx++] = cpu_to_le32(sg_dma_address(&sg[i]));
 467                 buf[idx++] = cpu_to_le32(sg_dma_len(&sg[i]));
 468                 total_len += sg[i].length;
 469         }
 470         buf[idx - 1] |= cpu_to_le32(ATA_PRD_EOT);
 471         sgt_len = idx * 4;
 472
 473         /*
 474          * Build ATA, host DMA packets
 475          */
 476         pdc20621_host_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len);
 477         pdc20621_host_pkt(&qc->tf, &pp->dimm_buf[0], portno);
 478
 479         pdc20621_ata_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len);
 480         i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
 481
 482         if (qc->tf.flags & ATA_TFLAG_LBA48)
 483                 i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
 484         else
 485                 i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
 486
 487         pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
 488
 489         /* copy three S/G tables and two packets to DIMM MMIO window */
 490         memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
 491                     &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
 492         memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP) +
 493                     PDC_DIMM_HOST_PRD,
 494                     &pp->dimm_buf[PDC_DIMM_HEADER_SZ], sgt_len);
 495
 496         /* force host FIFO dump */
 497         writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
 498
 499         readl(dimm_mmio);       /* MMIO PCI posting flush */
 500
 501         VPRINTK("ata pkt buf ofs %u, prd size %u, mmio copied\n", i, sgt_len);
 502 }
 503
 504 static void __pdc20621_push_hdma(struct ata_queued_cmd *qc,
 505                                  unsigned int seq,
 506                                  u32 pkt_ofs)
 507 {
 508         struct ata_port *ap = qc->ap;
 509         struct ata_host_set *host_set = ap->host_set;
 510         void *mmio = host_set->mmio_base;
 511
 512         /* hard-code chip #0 */
 513         mmio += PDC_CHIP0_OFS;
 514
 515         writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
 516         readl(mmio + PDC_20621_SEQCTL + (seq * 4));     /* flush */
 517
 518         writel(pkt_ofs, mmio + PDC_HDMA_PKT_SUBMIT);
 519         readl(mmio + PDC_HDMA_PKT_SUBMIT);      /* flush */
 520 }
 521
 522 static void pdc20621_push_hdma(struct ata_queued_cmd *qc,
 523                                 unsigned int seq,
 524                                 u32 pkt_ofs)
 525 {
 526         struct ata_port *ap = qc->ap;
 527         struct pdc_host_priv *pp = ap->host_set->private_data;
 528         unsigned int idx = pp->hdma_prod & PDC_HDMA_Q_MASK;
 529
 530         if (!pp->doing_hdma) {
 531                 __pdc20621_push_hdma(qc, seq, pkt_ofs);
 532                 pp->doing_hdma = 1;
 533                 return;
 534         }
 535
 536         pp->hdma[idx].qc = qc;
 537         pp->hdma[idx].seq = seq;
 538         pp->hdma[idx].pkt_ofs = pkt_ofs;
 539         pp->hdma_prod++;
 540 }
 541
 542 static void pdc20621_pop_hdma(struct ata_queued_cmd *qc)
 543 {
 544         struct ata_port *ap = qc->ap;
 545         struct pdc_host_priv *pp = ap->host_set->private_data;
 546         unsigned int idx = pp->hdma_cons & PDC_HDMA_Q_MASK;
 547
 548         /* if nothing on queue, we're done */
 549         if (pp->hdma_prod == pp->hdma_cons) {
 550                 pp->doing_hdma = 0;
 551                 return;
 552         }
 553
 554         __pdc20621_push_hdma(pp->hdma[idx].qc, pp->hdma[idx].seq,
 555                              pp->hdma[idx].pkt_ofs);
 556         pp->hdma_cons++;
 557 }
 558
 559 #ifdef ATA_VERBOSE_DEBUG
 560 static void pdc20621_dump_hdma(struct ata_queued_cmd *qc)
 561 {
 562         struct ata_port *ap = qc->ap;
 563         unsigned int port_no = ap->port_no;
 564         struct pdc_host_priv *hpriv = ap->host_set->private_data;
 565         void *dimm_mmio = hpriv->dimm_mmio;
 566
 567         dimm_mmio += (port_no * PDC_DIMM_WINDOW_STEP);
 568         dimm_mmio += PDC_DIMM_HOST_PKT;
 569
 570         printk(KERN_ERR "HDMA[0] == 0x%08X\n", readl(dimm_mmio));
 571         printk(KERN_ERR "HDMA[1] == 0x%08X\n", readl(dimm_mmio + 4));
 572         printk(KERN_ERR "HDMA[2] == 0x%08X\n", readl(dimm_mmio + 8));
 573         printk(KERN_ERR "HDMA[3] == 0x%08X\n", readl(dimm_mmio + 12));
 574 }
 575 #else
 576 static inline void pdc20621_dump_hdma(struct ata_queued_cmd *qc) { }
 577 #endif /* ATA_VERBOSE_DEBUG */
 578
 579 static void pdc20621_dma_setup(struct ata_queued_cmd *qc)
 580 {
 581         /* nothing for now.  later, we will call standard
 582          * code in libata-core for ATAPI here */
 583 }
 584
 585 static void pdc20621_dma_start(struct ata_queued_cmd *qc)
 586 {
 587         struct ata_port *ap = qc->ap;
 588         struct ata_host_set *host_set = ap->host_set;
 589         unsigned int port_no = ap->port_no;
 590         void *mmio = host_set->mmio_base;
 591         unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
 592         u8 seq = (u8) (port_no + 1);
 593         unsigned int doing_hdma = 0, port_ofs;
 594
 595         /* hard-code chip #0 */
 596         mmio += PDC_CHIP0_OFS;
 597
 598         VPRINTK("ata%u: ENTER\n", ap->id);
 599
 600         port_ofs = PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
 601
 602         /* if writing, we (1) DMA to DIMM, then (2) do ATA command */
 603         if (rw) {
 604                 doing_hdma = 1;
 605                 seq += 4;
 606         }
 607
 608         wmb();                  /* flush PRD, pkt writes */
 609
 610         if (doing_hdma) {
 611                 pdc20621_dump_hdma(qc);
 612                 pdc20621_push_hdma(qc, seq, port_ofs + PDC_DIMM_HOST_PKT);
 613                 VPRINTK("queued ofs 0x%x (%u), seq %u\n",
 614                         port_ofs + PDC_DIMM_HOST_PKT,
 615                         port_ofs + PDC_DIMM_HOST_PKT,
 616                         seq);
 617         } else {
 618                 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
 619                 readl(mmio + PDC_20621_SEQCTL + (seq * 4));     /* flush */
 620
 621                 writel(port_ofs + PDC_DIMM_ATA_PKT,
 622                        (void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
 623                 readl((void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
 624                 VPRINTK("submitted ofs 0x%x (%u), seq %u\n",
 625                         port_ofs + PDC_DIMM_ATA_PKT,
 626                         port_ofs + PDC_DIMM_ATA_PKT,
 627                         seq);
 628         }
 629 }
 630
 631 static inline unsigned int pdc20621_host_intr( struct ata_port *ap,
 632                                           struct ata_queued_cmd *qc,
 633                                           unsigned int doing_hdma,
 634                                           void *mmio)
 635 {
 636         unsigned int port_no = ap->port_no;
 637         unsigned int port_ofs =
 638                 PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
 639         u8 status;
 640         unsigned int handled = 0;
 641
 642         VPRINTK("ENTER\n");
 643
 644         if ((qc->tf.protocol == ATA_PROT_DMA) &&        /* read */
 645             (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
 646
 647                 /* step two - DMA from DIMM to host */
 648                 if (doing_hdma) {
 649                         VPRINTK("ata%u: read hdma, 0x%x 0x%x\n", ap->id,
 650                                 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
 651                         pdc_dma_complete(ap, qc, 0);
 652                         pdc20621_pop_hdma(qc);
 653                 }
 654
 655                 /* step one - exec ATA command */
 656                 else {
 657                         u8 seq = (u8) (port_no + 1 + 4);
 658                         VPRINTK("ata%u: read ata, 0x%x 0x%x\n", ap->id,
 659                                 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
 660
 661                         /* submit hdma pkt */
 662                         pdc20621_dump_hdma(qc);
 663                         pdc20621_push_hdma(qc, seq,
 664                                            port_ofs + PDC_DIMM_HOST_PKT);
 665                 }
 666                 handled = 1;
 667
 668         } else if (qc->tf.protocol == ATA_PROT_DMA) {   /* write */
 669
 670                 /* step one - DMA from host to DIMM */
 671                 if (doing_hdma) {
 672                         u8 seq = (u8) (port_no + 1);
 673                         VPRINTK("ata%u: write hdma, 0x%x 0x%x\n", ap->id,
 674                                 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
 675
 676                         /* submit ata pkt */
 677                         writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
 678                         readl(mmio + PDC_20621_SEQCTL + (seq * 4));
 679                         writel(port_ofs + PDC_DIMM_ATA_PKT,
 680                                (void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
 681                         readl((void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
 682                 }
 683
 684                 /* step two - execute ATA command */
 685                 else {
 686                         VPRINTK("ata%u: write ata, 0x%x 0x%x\n", ap->id,
 687                                 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
 688                         pdc_dma_complete(ap, qc, 0);
 689                         pdc20621_pop_hdma(qc);
 690                 }
 691                 handled = 1;
 692
 693         /* command completion, but no data xfer */
 694         } else if (qc->tf.protocol == ATA_PROT_NODATA) {
 695
 696                 status = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
 697                 DPRINTK("BUS_NODATA (drv_stat 0x%X)\n", status);
 698                 ata_qc_complete(qc, status);
 699                 handled = 1;
 700
 701         } else {
 702                 ap->stats.idle_irq++;
 703         }
 704
 705         return handled;
 706 }
 707
 708 static void pdc20621_irq_clear(struct ata_port *ap)
 709 {
 710         struct ata_host_set *host_set = ap->host_set;
 711         void *mmio = host_set->mmio_base;
 712
 713         mmio += PDC_CHIP0_OFS;
 714
 715         readl(mmio + PDC_20621_SEQMASK);
 716 }
 717
 718 static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
 719 {
 720         struct ata_host_set *host_set = dev_instance;
 721         struct ata_port *ap;
 722         u32 mask = 0;
 723         unsigned int i, tmp, port_no;
 724         unsigned int handled = 0;
 725         void *mmio_base;
 726
 727         VPRINTK("ENTER\n");
 728
 729         if (!host_set || !host_set->mmio_base) {
 730                 VPRINTK("QUICK EXIT\n");
 731                 return IRQ_NONE;
 732         }
 733
 734         mmio_base = host_set->mmio_base;
 735
 736         /* reading should also clear interrupts */
 737         mmio_base += PDC_CHIP0_OFS;
 738         mask = readl(mmio_base + PDC_20621_SEQMASK);
 739         VPRINTK("mask == 0x%x\n", mask);
 740
 741         if (mask == 0xffffffff) {
 742                 VPRINTK("QUICK EXIT 2\n");
 743                 return IRQ_NONE;
 744         }
 745         mask &= 0xffff;         /* only 16 tags possible */
 746         if (!mask) {
 747                 VPRINTK("QUICK EXIT 3\n");
 748                 return IRQ_NONE;
 749         }
 750
 751         spin_lock(&host_set->lock);
 752
 753         for (i = 1; i < 9; i++) {
 754                 port_no = i - 1;
 755                 if (port_no > 3)
 756                         port_no -= 4;
 757                 if (port_no >= host_set->n_ports)
 758                         ap = NULL;
 759                 else
 760                         ap = host_set->ports[port_no];
 761                 tmp = mask & (1 << i);
 762                 VPRINTK("seq %u, port_no %u, ap %p, tmp %x\n", i, port_no, ap, tmp);
 763                 if (tmp && ap && (!(ap->flags & ATA_FLAG_PORT_DISABLED))) {
 764                         struct ata_queued_cmd *qc;
 765
 766                         qc = ata_qc_from_tag(ap, ap->active_tag);
 767                         if (qc && (!(qc->tf.ctl & ATA_NIEN)))
 768                                 handled += pdc20621_host_intr(ap, qc, (i > 4),
 769                                                               mmio_base);
 770                 }
 771         }
 772
 773         spin_unlock(&host_set->lock);
 774
 775         VPRINTK("mask == 0x%x\n", mask);
 776
 777         VPRINTK("EXIT\n");
 778
 779         return IRQ_RETVAL(handled);
 780 }
 781
 782 static inline void pdc_dma_complete (struct ata_port *ap,
 783                                      struct ata_queued_cmd *qc,
 784                                      int have_err)
 785 {
 786         u8 err_bit = have_err ? ATA_ERR : 0;
 787
 788         /* get drive status; clear intr; complete txn */
 789         ata_qc_complete(qc, ata_wait_idle(ap) | err_bit);
 790 }
 791
 792 static void pdc_eng_timeout(struct ata_port *ap)
 793 {
 794         u8 drv_stat;
 795         struct ata_queued_cmd *qc;
 796
 797         DPRINTK("ENTER\n");
 798
 799         qc = ata_qc_from_tag(ap, ap->active_tag);
 800         if (!qc) {
 801                 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
 802                        ap->id);
 803                 goto out;
 804         }
 805
 806         /* hack alert!  We cannot use the supplied completion
 807          * function from inside the ->eh_strategy_handler() thread.
 808          * libata is the only user of ->eh_strategy_handler() in
 809          * any kernel, so the default scsi_done() assumes it is
 810          * not being called from the SCSI EH.
 811          */
 812         qc->scsidone = scsi_finish_command;
 813
 814         switch (qc->tf.protocol) {
 815         case ATA_PROT_DMA:
 816                 printk(KERN_ERR "ata%u: DMA timeout\n", ap->id);
 817                 ata_qc_complete(qc, ata_wait_idle(ap) | ATA_ERR);
 818                 break;
 819
 820         case ATA_PROT_NODATA:
 821                 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
 822
 823                 printk(KERN_ERR "ata%u: command 0x%x timeout, stat 0x%x\n",
 824                        ap->id, qc->tf.command, drv_stat);
 825
 826                 ata_qc_complete(qc, drv_stat);
 827                 break;
 828
 829         default:
 830                 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
 831
 832                 printk(KERN_ERR "ata%u: unknown timeout, cmd 0x%x stat 0x%x\n",
 833                        ap->id, qc->tf.command, drv_stat);
 834
 835                 ata_qc_complete(qc, drv_stat);
 836                 break;
 837         }
 838
 839 out:
 840         DPRINTK("EXIT\n");
 841 }
 842
 843 static void pdc_tf_load_mmio(struct ata_port *ap, struct ata_taskfile *tf)
 844 {
 845         if (tf->protocol != ATA_PROT_DMA)
 846                 ata_tf_load_mmio(ap, tf);
 847 }
 848
 849
 850 static void pdc_exec_command_mmio(struct ata_port *ap, struct ata_taskfile *tf)
 851 {
 852         if (tf->protocol != ATA_PROT_DMA)
 853                 ata_exec_command_mmio(ap, tf);
 854 }
 855
 856
 857 static void pdc_sata_setup_port(struct ata_ioports *port, unsigned long base)
 858 {
 859         port->cmd_addr          = base;
 860         port->data_addr         = base;
 861         port->feature_addr      =
 862         port->error_addr        = base + 0x4;
 863         port->nsect_addr        = base + 0x8;
 864         port->lbal_addr         = base + 0xc;
 865         port->lbam_addr         = base + 0x10;
 866         port->lbah_addr         = base + 0x14;
 867         port->device_addr       = base + 0x18;
 868         port->command_addr      =
 869         port->status_addr       = base + 0x1c;
 870         port->altstatus_addr    =
 871         port->ctl_addr          = base + 0x38;
 872 }
 873
 874
 875 #ifdef ATA_VERBOSE_DEBUG
 876 static void pdc20621_get_from_dimm(struct ata_probe_ent *pe, void *psource,
 877                                    u32 offset, u32 size)
 878 {
 879         u32 window_size;
 880         u16 idx;
 881         u8 page_mask;
 882         long dist;
 883         void *mmio = pe->mmio_base;
 884         struct pdc_host_priv *hpriv = pe->private_data;
 885         void *dimm_mmio = hpriv->dimm_mmio;
 886
 887         /* hard-code chip #0 */
 888         mmio += PDC_CHIP0_OFS;
 889
 890         page_mask = 0x00;
 891         window_size = 0x2000 * 4; /* 32K byte uchar size */
 892         idx = (u16) (offset / window_size);
 893
 894         writel(0x01, mmio + PDC_GENERAL_CTLR);
 895         readl(mmio + PDC_GENERAL_CTLR);
 896         writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
 897         readl(mmio + PDC_DIMM_WINDOW_CTLR);
 898
 899         offset -= (idx * window_size);
 900         idx++;
 901         dist = ((long) (window_size - (offset + size))) >= 0 ? size :
 902                 (long) (window_size - offset);
 903         memcpy_fromio((char *) psource, (char *) (dimm_mmio + offset / 4),
 904                       dist);
 905
 906         psource += dist;
 907         size -= dist;
 908         for (; (long) size >= (long) window_size ;) {
 909                 writel(0x01, mmio + PDC_GENERAL_CTLR);
 910                 readl(mmio + PDC_GENERAL_CTLR);
 911                 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
 912                 readl(mmio + PDC_DIMM_WINDOW_CTLR);
 913                 memcpy_fromio((char *) psource, (char *) (dimm_mmio),
 914                               window_size / 4);
 915                 psource += window_size;
 916                 size -= window_size;
 917                 idx ++;
 918         }
 919
 920         if (size) {
 921                 writel(0x01, mmio + PDC_GENERAL_CTLR);
 922                 readl(mmio + PDC_GENERAL_CTLR);
 923                 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
 924                 readl(mmio + PDC_DIMM_WINDOW_CTLR);
 925                 memcpy_fromio((char *) psource, (char *) (dimm_mmio),
 926                               size / 4);
 927         }
 928 }
 929 #endif
 930
 931
 932 static void pdc20621_put_to_dimm(struct ata_probe_ent *pe, void *psource,
 933                                  u32 offset, u32 size)
 934 {
 935         u32 window_size;
 936         u16 idx;
 937         u8 page_mask;
 938         long dist;
 939         void *mmio = pe->mmio_base;
 940         struct pdc_host_priv *hpriv = pe->private_data;
 941         void *dimm_mmio = hpriv->dimm_mmio;
 942
 943         /* hard-code chip #0 */
 944         mmio += PDC_CHIP0_OFS;
 945
 946         page_mask = 0x00;
 947         window_size = 0x2000 * 4;       /* 32K byte uchar size */
 948         idx = (u16) (offset / window_size);
 949
 950         writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
 951         readl(mmio + PDC_DIMM_WINDOW_CTLR);
 952         offset -= (idx * window_size);
 953         idx++;
 954         dist = ((long)(s32)(window_size - (offset + size))) >= 0 ? size :
 955                 (long) (window_size - offset);
 956         memcpy_toio((char *) (dimm_mmio + offset / 4), (char *) psource, dist);
 957         writel(0x01, mmio + PDC_GENERAL_CTLR);
 958         readl(mmio + PDC_GENERAL_CTLR);
 959
 960         psource += dist;
 961         size -= dist;
 962         for (; (long) size >= (long) window_size ;) {
 963                 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
 964                 readl(mmio + PDC_DIMM_WINDOW_CTLR);
 965                 memcpy_toio((char *) (dimm_mmio), (char *) psource,
 966                             window_size / 4);
 967                 writel(0x01, mmio + PDC_GENERAL_CTLR);
 968                 readl(mmio + PDC_GENERAL_CTLR);
 969                 psource += window_size;
 970                 size -= window_size;
 971                 idx ++;
 972         }
 973
 974         if (size) {
 975                 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
 976                 readl(mmio + PDC_DIMM_WINDOW_CTLR);
 977                 memcpy_toio((char *) (dimm_mmio), (char *) psource, size / 4);
 978                 writel(0x01, mmio + PDC_GENERAL_CTLR);
 979                 readl(mmio + PDC_GENERAL_CTLR);
 980         }
 981 }
 982
 983
 984 static unsigned int pdc20621_i2c_read(struct ata_probe_ent *pe, u32 device,
 985                                       u32 subaddr, u32 *pdata)
 986 {
 987         void *mmio = pe->mmio_base;
 988         u32 i2creg  = 0;
 989         u32 status;
 990         u32 count =0;
 991
 992         /* hard-code chip #0 */
 993         mmio += PDC_CHIP0_OFS;
 994
 995         i2creg |= device << 24;
 996         i2creg |= subaddr << 16;
 997
 998         /* Set the device and subaddress */
 999         writel(i2creg, mmio + PDC_I2C_ADDR_DATA_OFFSET);
1000         readl(mmio + PDC_I2C_ADDR_DATA_OFFSET);
1001
1002         /* Write Control to perform read operation, mask int */
1003         writel(PDC_I2C_READ | PDC_I2C_START | PDC_I2C_MASK_INT,
1004                mmio + PDC_I2C_CONTROL_OFFSET);
1005
1006         for (count = 0; count <= 1000; count ++) {
1007                 status = readl(mmio + PDC_I2C_CONTROL_OFFSET);
1008                 if (status & PDC_I2C_COMPLETE) {
1009                         status = readl(mmio + PDC_I2C_ADDR_DATA_OFFSET);
1010                         break;
1011                 } else if (count == 1000)
1012                         return 0;
1013         }
1014
1015         *pdata = (status >> 8) & 0x000000ff;
1016         return 1;
1017 }
1018
1019
1020 static int pdc20621_detect_dimm(struct ata_probe_ent *pe)
1021 {
1022         u32 data=0 ;
1023         if (pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1024                              PDC_DIMM_SPD_SYSTEM_FREQ, &data)) {
1025                 if (data == 100)
1026                         return 100;
1027         } else
1028                 return 0;
1029
1030         if (pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS, 9, &data)) {
1031                 if(data <= 0x75)
1032                         return 133;
1033         } else
1034                 return 0;
1035
1036         return 0;
1037 }
1038
1039
1040 static int pdc20621_prog_dimm0(struct ata_probe_ent *pe)
1041 {
1042         u32 spd0[50];
1043         u32 data = 0;
1044         int size, i;
1045         u8 bdimmsize;
1046         void *mmio = pe->mmio_base;
1047         static const struct {
1048                 unsigned int reg;
1049                 unsigned int ofs;
1050         } pdc_i2c_read_data [] = {
1051                 { PDC_DIMM_SPD_TYPE, 11 },
1052                 { PDC_DIMM_SPD_FRESH_RATE, 12 },
1053                 { PDC_DIMM_SPD_COLUMN_NUM, 4 },
1054                 { PDC_DIMM_SPD_ATTRIBUTE, 21 },
1055                 { PDC_DIMM_SPD_ROW_NUM, 3 },
1056                 { PDC_DIMM_SPD_BANK_NUM, 17 },
1057                 { PDC_DIMM_SPD_MODULE_ROW, 5 },
1058                 { PDC_DIMM_SPD_ROW_PRE_CHARGE, 27 },
1059                 { PDC_DIMM_SPD_ROW_ACTIVE_DELAY, 28 },
1060                 { PDC_DIMM_SPD_RAS_CAS_DELAY, 29 },
1061                 { PDC_DIMM_SPD_ACTIVE_PRECHARGE, 30 },
1062                 { PDC_DIMM_SPD_CAS_LATENCY, 18 },
1063         };
1064
1065         /* hard-code chip #0 */
1066         mmio += PDC_CHIP0_OFS;
1067
1068         for(i=0; i<ARRAY_SIZE(pdc_i2c_read_data); i++)
1069                 pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1070                                   pdc_i2c_read_data[i].reg,
1071                                   &spd0[pdc_i2c_read_data[i].ofs]);
1072
1073         data |= (spd0[4] - 8) | ((spd0[21] != 0) << 3) | ((spd0[3]-11) << 4);
1074         data |= ((spd0[17] / 4) << 6) | ((spd0[5] / 2) << 7) |
1075                 ((((spd0[27] + 9) / 10) - 1) << 8) ;
1076         data |= (((((spd0[29] > spd0[28])
1077                     ? spd0[29] : spd0[28]) + 9) / 10) - 1) << 10;
1078         data |= ((spd0[30] - spd0[29] + 9) / 10 - 2) << 12;
1079
1080         if (spd0[18] & 0x08)
1081                 data |= ((0x03) << 14);
1082         else if (spd0[18] & 0x04)
1083                 data |= ((0x02) << 14);
1084         else if (spd0[18] & 0x01)
1085                 data |= ((0x01) << 14);
1086         else
1087                 data |= (0 << 14);
1088
1089         /*
1090            Calculate the size of bDIMMSize (power of 2) and
1091            merge the DIMM size by program start/end address.
1092         */
1093
1094         bdimmsize = spd0[4] + (spd0[5] / 2) + spd0[3] + (spd0[17] / 2) + 3;
1095         size = (1 << bdimmsize) >> 20;  /* size = xxx(MB) */
1096         data |= (((size / 16) - 1) << 16);
1097         data |= (0 << 23);
1098         data |= 8;
1099         writel(data, mmio + PDC_DIMM0_CONTROL_OFFSET);
1100         readl(mmio + PDC_DIMM0_CONTROL_OFFSET);
1101         return size;
1102 }
1103
1104
1105 static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent *pe)
1106 {
1107         u32 data, spd0;
1108         int error, i;
1109         void *mmio = pe->mmio_base;
1110
1111         /* hard-code chip #0 */
1112         mmio += PDC_CHIP0_OFS;
1113
1114         /*
1115           Set To Default : DIMM Module Global Control Register (0x022259F1)
1116           DIMM Arbitration Disable (bit 20)
1117           DIMM Data/Control Output Driving Selection (bit12 - bit15)
1118           Refresh Enable (bit 17)
1119         */
1120
1121         data = 0x022259F1;
1122         writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
1123         readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
1124
1125         /* Turn on for ECC */
1126         pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1127                           PDC_DIMM_SPD_TYPE, &spd0);
1128         if (spd0 == 0x02) {
1129                 data |= (0x01 << 16);
1130                 writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
1131                 readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
1132                 printk(KERN_ERR "Local DIMM ECC Enabled\n");
1133         }
1134
1135         /* DIMM Initialization Select/Enable (bit 18/19) */
1136         data &= (~(1<<18));
1137         data |= (1<<19);
1138         writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
1139
1140         error = 1;
1141         for (i = 1; i <= 10; i++) {   /* polling ~5 secs */
1142                 data = readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
1143                 if (!(data & (1<<19))) {
1144                         error = 0;
1145                         break;
1146                 }
1147                 set_current_state(TASK_UNINTERRUPTIBLE);
1148                 schedule_timeout((i * 100) * HZ / 1000 + 1);
1149         }
1150         return error;
1151 }
1152
1153
1154 static unsigned int pdc20621_dimm_init(struct ata_probe_ent *pe)
1155 {
1156         int speed, size, length;
1157         u32 addr,spd0,pci_status;
1158         u32 tmp=0;
1159         u32 time_period=0;
1160         u32 tcount=0;
1161         u32 ticks=0;
1162         u32 clock=0;
1163         u32 fparam=0;
1164         void *mmio = pe->mmio_base;
1165
1166         /* hard-code chip #0 */
1167         mmio += PDC_CHIP0_OFS;
1168
1169         /* Initialize PLL based upon PCI Bus Frequency */
1170
1171         /* Initialize Time Period Register */
1172         writel(0xffffffff, mmio + PDC_TIME_PERIOD);
1173         time_period = readl(mmio + PDC_TIME_PERIOD);
1174         VPRINTK("Time Period Register (0x40): 0x%x\n", time_period);
1175
1176         /* Enable timer */
1177         writel(0x00001a0, mmio + PDC_TIME_CONTROL);
1178         readl(mmio + PDC_TIME_CONTROL);
1179
1180         /* Wait 3 seconds */
1181         set_current_state(TASK_UNINTERRUPTIBLE);
1182         schedule_timeout(3 * HZ);
1183
1184         /*
1185            When timer is enabled, counter is decreased every internal
1186            clock cycle.
1187         */
1188
1189         tcount = readl(mmio + PDC_TIME_COUNTER);
1190         VPRINTK("Time Counter Register (0x44): 0x%x\n", tcount);
1191
1192         /*
1193            If SX4 is on PCI-X bus, after 3 seconds, the timer counter
1194            register should be >= (0xffffffff - 3x10^8).
1195         */
1196         if(tcount >= PCI_X_TCOUNT) {
1197                 ticks = (time_period - tcount);
1198                 VPRINTK("Num counters 0x%x (%d)\n", ticks, ticks);
1199
1200                 clock = (ticks / 300000);
1201                 VPRINTK("10 * Internal clk = 0x%x (%d)\n", clock, clock);
1202
1203                 clock = (clock * 33);
1204                 VPRINTK("10 * Internal clk * 33 = 0x%x (%d)\n", clock, clock);
1205
1206                 /* PLL F Param (bit 22:16) */
1207                 fparam = (1400000 / clock) - 2;
1208                 VPRINTK("PLL F Param: 0x%x (%d)\n", fparam, fparam);
1209
1210                 /* OD param = 0x2 (bit 31:30), R param = 0x5 (bit 29:25) */
1211                 pci_status = (0x8a001824 | (fparam << 16));
1212         } else
1213                 pci_status = PCI_PLL_INIT;
1214
1215         /* Initialize PLL. */
1216         VPRINTK("pci_status: 0x%x\n", pci_status);
1217         writel(pci_status, mmio + PDC_CTL_STATUS);
1218         readl(mmio + PDC_CTL_STATUS);
1219
1220         /*
1221            Read SPD of DIMM by I2C interface,
1222            and program the DIMM Module Controller.
1223         */
1224         if (!(speed = pdc20621_detect_dimm(pe))) {
1225                 printk(KERN_ERR "Detect Local DIMM Fail\n");
1226                 return 1;       /* DIMM error */
1227         }
1228         VPRINTK("Local DIMM Speed = %d\n", speed);
1229
1230         /* Programming DIMM0 Module Control Register (index_CID0:80h) */
1231         size = pdc20621_prog_dimm0(pe);
1232         VPRINTK("Local DIMM Size = %dMB\n",size);
1233
1234         /* Programming DIMM Module Global Control Register (index_CID0:88h) */
1235         if (pdc20621_prog_dimm_global(pe)) {
1236                 printk(KERN_ERR "Programming DIMM Module Global Control Register Fail\n");
1237                 return 1;
1238         }
1239
1240 #ifdef ATA_VERBOSE_DEBUG
1241         {
1242                 u8 test_parttern1[40] = {0x55,0xAA,'P','r','o','m','i','s','e',' ',
1243                                 'N','o','t',' ','Y','e','t',' ','D','e','f','i','n','e','d',' ',
1244                                  '1','.','1','0',
1245                                 '9','8','0','3','1','6','1','2',0,0};
1246                 u8 test_parttern2[40] = {0};
1247
1248                 pdc20621_put_to_dimm(pe, (void *) test_parttern2, 0x10040, 40);
1249                 pdc20621_put_to_dimm(pe, (void *) test_parttern2, 0x40, 40);
1250
1251                 pdc20621_put_to_dimm(pe, (void *) test_parttern1, 0x10040, 40);
1252                 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x40, 40);
1253                 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1254                        test_parttern2[1], &(test_parttern2[2]));
1255                 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x10040,
1256                                        40);
1257                 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1258                        test_parttern2[1], &(test_parttern2[2]));
1259
1260                 pdc20621_put_to_dimm(pe, (void *) test_parttern1, 0x40, 40);
1261                 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x40, 40);
1262                 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1263                        test_parttern2[1], &(test_parttern2[2]));
1264         }
1265 #endif
1266
1267         /* ECC initiliazation. */
1268
1269         pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1270                           PDC_DIMM_SPD_TYPE, &spd0);
1271         if (spd0 == 0x02) {
1272                 VPRINTK("Start ECC initialization\n");
1273                 addr = 0;
1274                 length = size * 1024 * 1024;
1275                 while (addr < length) {
1276                         pdc20621_put_to_dimm(pe, (void *) &tmp, addr,
1277                                              sizeof(u32));
1278                         addr += sizeof(u32);
1279                 }
1280                 VPRINTK("Finish ECC initialization\n");
1281         }
1282         return 0;
1283 }
1284
1285
1286 static void pdc_20621_init(struct ata_probe_ent *pe)
1287 {
1288         u32 tmp;
1289         void *mmio = pe->mmio_base;
1290
1291         /* hard-code chip #0 */
1292         mmio += PDC_CHIP0_OFS;
1293
1294         /*
1295          * Select page 0x40 for our 32k DIMM window
1296          */
1297         tmp = readl(mmio + PDC_20621_DIMM_WINDOW) & 0xffff0000;
1298         tmp |= PDC_PAGE_WINDOW; /* page 40h; arbitrarily selected */
1299         writel(tmp, mmio + PDC_20621_DIMM_WINDOW);
1300
1301         /*
1302          * Reset Host DMA
1303          */
1304         tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1305         tmp |= PDC_RESET;
1306         writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1307         readl(mmio + PDC_HDMA_CTLSTAT);         /* flush */
1308
1309         udelay(10);
1310
1311         tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1312         tmp &= ~PDC_RESET;
1313         writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1314         readl(mmio + PDC_HDMA_CTLSTAT);         /* flush */
1315 }
1316
1317 static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1318 {
1319         static int printed_version;
1320         struct ata_probe_ent *probe_ent = NULL;
1321         unsigned long base;
1322         void *mmio_base, *dimm_mmio = NULL;
1323         struct pdc_host_priv *hpriv = NULL;
1324         unsigned int board_idx = (unsigned int) ent->driver_data;
1325         int rc;
1326
1327         if (!printed_version++)
1328                 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
1329
1330         /*
1331          * If this driver happens to only be useful on Apple's K2, then
1332          * we should check that here as it has a normal Serverworks ID
1333          */
1334         rc = pci_enable_device(pdev);
1335         if (rc)
1336                 return rc;
1337
1338         rc = pci_request_regions(pdev, DRV_NAME);
1339         if (rc)
1340                 goto err_out;
1341
1342         rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1343         if (rc)
1344                 goto err_out_regions;
1345         rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1346         if (rc)
1347                 goto err_out_regions;
1348
1349         probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1350         if (probe_ent == NULL) {
1351                 rc = -ENOMEM;
1352                 goto err_out_regions;
1353         }
1354
1355         memset(probe_ent, 0, sizeof(*probe_ent));
1356         probe_ent->pdev = pdev;
1357         INIT_LIST_HEAD(&probe_ent->node);
1358
1359         mmio_base = ioremap(pci_resource_start(pdev, 3),
1360                             pci_resource_len(pdev, 3));
1361         if (mmio_base == NULL) {
1362                 rc = -ENOMEM;
1363                 goto err_out_free_ent;
1364         }
1365         base = (unsigned long) mmio_base;
1366
1367         hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1368         if (!hpriv) {
1369                 rc = -ENOMEM;
1370                 goto err_out_iounmap;
1371         }
1372         memset(hpriv, 0, sizeof(*hpriv));
1373
1374         dimm_mmio = ioremap(pci_resource_start(pdev, 4),
1375                             pci_resource_len(pdev, 4));
1376         if (!dimm_mmio) {
1377                 kfree(hpriv);
1378                 rc = -ENOMEM;
1379                 goto err_out_iounmap;
1380         }
1381
1382         hpriv->dimm_mmio = dimm_mmio;
1383
1384         probe_ent->sht          = pdc_port_info[board_idx].sht;
1385         probe_ent->host_flags   = pdc_port_info[board_idx].host_flags;
1386         probe_ent->pio_mask     = pdc_port_info[board_idx].pio_mask;
1387         probe_ent->udma_mask    = pdc_port_info[board_idx].udma_mask;
1388         probe_ent->port_ops     = pdc_port_info[board_idx].port_ops;
1389
1390         probe_ent->irq = pdev->irq;
1391         probe_ent->irq_flags = SA_SHIRQ;
1392         probe_ent->mmio_base = mmio_base;
1393
1394         probe_ent->private_data = hpriv;
1395         base += PDC_CHIP0_OFS;
1396
1397         pdc_sata_setup_port(&probe_ent->port[0], base + 0x200);
1398         pdc_sata_setup_port(&probe_ent->port[1], base + 0x280);
1399
1400         /* notice 4-port boards */
1401         switch (board_idx) {
1402         case board_20621:
1403                 probe_ent->n_ports = 4;
1404
1405                 pdc_sata_setup_port(&probe_ent->port[2], base + 0x300);
1406                 pdc_sata_setup_port(&probe_ent->port[3], base + 0x380);
1407                 break;
1408         default:
1409                 BUG();
1410                 break;
1411         }
1412
1413         pci_set_master(pdev);
1414
1415         /* initialize adapter */
1416         /* initialize local dimm */
1417         if (pdc20621_dimm_init(probe_ent)) {
1418                 rc = -ENOMEM;
1419                 goto err_out_iounmap_dimm;
1420         }
1421         pdc_20621_init(probe_ent);
1422
1423         /* FIXME: check ata_device_add return value */
1424         ata_device_add(probe_ent);
1425         kfree(probe_ent);
1426
1427         return 0;
1428
1429 err_out_iounmap_dimm:           /* only get to this label if 20621 */
1430         kfree(hpriv);
1431         iounmap(dimm_mmio);
1432 err_out_iounmap:
1433         iounmap(mmio_base);
1434 err_out_free_ent:
1435         kfree(probe_ent);
1436 err_out_regions:
1437         pci_release_regions(pdev);
1438 err_out:
1439         pci_disable_device(pdev);
1440         return rc;
1441 }
1442
1443
1444 static int __init pdc_sata_init(void)
1445 {
1446         return pci_module_init(&pdc_sata_pci_driver);
1447 }
1448
1449
1450 static void __exit pdc_sata_exit(void)
1451 {
1452         pci_unregister_driver(&pdc_sata_pci_driver);
1453 }
1454
1455
1456 MODULE_AUTHOR("Jeff Garzik");
1457 MODULE_DESCRIPTION("Promise SATA low-level driver");
1458 MODULE_LICENSE("GPL");
1459 MODULE_DEVICE_TABLE(pci, pdc_sata_pci_tbl);
1460
1461 module_init(pdc_sata_init);
1462 module_exit(pdc_sata_exit);