1 /***********************************************************************
2 ;* File Name : TMSCSIM.H *
3 ;* TEKRAM DC-390(T) PCI SCSI Bus Master Host Adapter *
5 ;***********************************************************************/
6 /* $Id: tmscsim.h,v 2.15.2.3 2000/11/17 20:52:27 garloff Exp $ */
11 #include <linux/types.h>
12 #include <linux/config.h>
14 #define SCSI_IRQ_NONE 255
16 #define MAX_ADAPTER_NUM 4
17 #define MAX_SG_LIST_BUF 16 /* Not used */
18 #define MAX_CMD_PER_LUN 32
19 #define MAX_CMD_QUEUE MAX_CMD_PER_LUN+MAX_CMD_PER_LUN/2+1
21 #define MAX_SRB_CNT MAX_CMD_QUEUE+1 /* Max number of started commands */
23 #define SEL_TIMEOUT 153 /* 250 ms selection timeout (@ 40 MHz) */
27 #define pci_dma_lo32(a) (a & 0xffffffff)
29 typedef u8 UCHAR; /* 8 bits */
30 typedef u16 USHORT; /* 16 bits */
31 typedef u32 UINT; /* 32 bits */
32 typedef unsigned long ULONG; /* 32/64 bits */
34 typedef UCHAR *PUCHAR;
35 typedef USHORT *PUSHORT;
37 typedef ULONG *PULONG;
38 typedef Scsi_Host_Template *PSHT;
39 typedef struct Scsi_Host *PSH;
40 typedef Scsi_Device *PSCSIDEV;
41 typedef Scsi_Cmnd *PSCSICMD;
43 typedef struct scatterlist *PSGL, SGL;
46 /*;-----------------------------------------------------------------------*/
47 typedef struct _SyncMsg
55 /*;-----------------------------------------------------------------------*/
56 typedef struct _Capacity
61 /*;-----------------------------------------------------------------------*/
62 typedef struct _SGentry
68 typedef struct _SGentry1
76 ;-----------------------------------------------------------------------
78 ;-----------------------------------------------------------------------
84 struct _SRB *pNextSRB;
90 SGL Segmentx; /* make a one entry of S/G list table */
93 ULONG SGBusAddr; /*;a segment starting address as seen by AM53C974A*/
94 ULONG SGToBeXferLen; /*; to be xfer length */
95 ULONG TotalXferredLen;
101 UCHAR SRBFlag; /*; b0-AutoReqSense,b6-Read,b7-write */
102 /*; b4-settimeout,b5-Residual valid */
123 //UCHAR IORBFlag; /*;81h-Reset, 2-retry */
128 typedef struct _SRB DC390_SRB, *PSRB;
131 ;-----------------------------------------------------------------------
132 ; Device Control Block
133 ;-----------------------------------------------------------------------
137 struct _DCB *pNextDCB;
138 struct _ACB *pDCBACB;
140 /* Aborted Commands */
141 //PSCSICMD AboIORBhead;
142 //PSCSICMD AboIORBtail;
152 UCHAR WaitSRBCnt; /* Not used */
161 UCHAR TargetID; /*; SCSI Target ID (SCSI Only) */
162 UCHAR TargetLUN; /*; SCSI Log. Unit (SCSI Only) */
172 UCHAR SyncMode; /*; 0:async mode */
173 UCHAR NegoPeriod; /*;for nego. */
174 UCHAR SyncPeriod; /*;for reg. */
175 UCHAR SyncOffset; /*;for reg. and nego.(low nibble) */
178 //UCHAR InqDataBuf[8];
179 //UCHAR CapacityBuf[8];
183 typedef struct _DCB DC390_DCB, *PDCB;
185 ;-----------------------------------------------------------------------
186 ; Adapter Control Block
187 ;-----------------------------------------------------------------------
192 struct _ACB *pNextACB;
198 UCHAR AdapterIndex; /*; nth Adapter this driver */
218 UCHAR DCBmap[MAX_SCSI_ID];
223 #if defined(USE_SPINLOCKS) && USE_SPINLOCKS > 1 && (defined(CONFIG_SMP) || DEBUG_SPINLOCKS > 0)
230 UCHAR Ignore_IRQ; /* Not used */
232 PDEVDECL1; /* Pointer to PCI cfg. space */
241 struct timer_list Waiting_Timer;
245 DC390_SRB SRB_array[MAX_SRB_CNT]; /* 50 SRBs */
249 typedef struct _ACB DC390_ACB, *PACB;
251 /*;-----------------------------------------------------------------------*/
254 #define BIT31 0x80000000
255 #define BIT30 0x40000000
256 #define BIT29 0x20000000
257 #define BIT28 0x10000000
258 #define BIT27 0x08000000
259 #define BIT26 0x04000000
260 #define BIT25 0x02000000
261 #define BIT24 0x01000000
262 #define BIT23 0x00800000
263 #define BIT22 0x00400000
264 #define BIT21 0x00200000
265 #define BIT20 0x00100000
266 #define BIT19 0x00080000
267 #define BIT18 0x00040000
268 #define BIT17 0x00020000
269 #define BIT16 0x00010000
270 #define BIT15 0x00008000
271 #define BIT14 0x00004000
272 #define BIT13 0x00002000
273 #define BIT12 0x00001000
274 #define BIT11 0x00000800
275 #define BIT10 0x00000400
276 #define BIT9 0x00000200
277 #define BIT8 0x00000100
278 #define BIT7 0x00000080
279 #define BIT6 0x00000040
280 #define BIT5 0x00000020
281 #define BIT4 0x00000010
282 #define BIT3 0x00000008
283 #define BIT2 0x00000004
284 #define BIT1 0x00000002
285 #define BIT0 0x00000001
287 /*;---UnitCtrlFlag */
288 #define UNIT_ALLOCATED BIT0
289 #define UNIT_INFO_CHANGED BIT1
290 #define FORMATING_MEDIA BIT2
291 #define UNIT_RETRY BIT3
294 #define DASD_SUPPORT BIT0
295 #define SCSI_SUPPORT BIT1
296 #define ASPI_SUPPORT BIT2
298 /*;----SRBState machine definition */
300 #define SRB_WAIT BIT0
301 #define SRB_READY BIT1
302 #define SRB_MSGOUT BIT2 /*;arbitration+msg_out 1st byte*/
303 #define SRB_MSGIN BIT3
304 #define SRB_MSGIN_MULTI BIT4
305 #define SRB_COMMAND BIT5
306 #define SRB_START_ BIT6 /*;arbitration+msg_out+command_out*/
307 #define SRB_DISCONNECT BIT7
308 #define SRB_DATA_XFER BIT8
309 #define SRB_XFERPAD BIT9
310 #define SRB_STATUS BIT10
311 #define SRB_COMPLETED BIT11
312 #define SRB_ABORT_SENT BIT12
313 #define DO_SYNC_NEGO BIT13
314 #define SRB_UNEXPECT_RESEL BIT14
318 #define ABORTION BIT1
319 #define OVER_RUN BIT2
320 #define UNDER_RUN BIT3
321 #define PARITY_ERROR BIT4
322 #define SRB_ERROR BIT5
325 #define RESET_DEV BIT0
326 #define RESET_DETECT BIT1
327 #define RESET_DONE BIT2
330 #define ABORT_DEV_ BIT0
335 #define RESIDUAL_VALID BIT5
336 #define ENABLE_TIMER BIT4
337 #define RESET_DEV0 BIT2
338 #define ABORT_DEV BIT1
339 #define AUTO_REQSENSE BIT0
341 /*;---Adapter status */
342 #define H_STATUS_GOOD 0
343 #define H_SEL_TIMEOUT 0x11
344 #define H_OVER_UNDER_RUN 0x12
345 #define H_UNEXP_BUS_FREE 0x13
346 #define H_TARGET_PHASE_F 0x14
347 #define H_INVALID_CCB_OP 0x16
348 #define H_LINK_CCB_BAD 0x17
349 #define H_BAD_TARGET_DIR 0x18
350 #define H_DUPLICATE_CCB 0x19
351 #define H_BAD_CCB_OR_SG 0x1A
352 #define H_ABORT 0x0FF
354 /*; SCSI Status byte codes*/
355 /* The values defined in include/scsi/scsi.h, to be shifted << 1 */
357 #define SCSI_STAT_UNEXP_BUS_F 0xFD /*; Unexpect Bus Free */
358 #define SCSI_STAT_BUS_RST_DETECT 0xFE /*; Scsi Bus Reset detected */
359 #define SCSI_STAT_SEL_TIMEOUT 0xFF /*; Selection Time out */
362 #define RES_TARGET 0x000000FF /* Target State */
363 #define RES_TARGET_LNX STATUS_MASK /* Only official ... */
364 #define RES_ENDMSG 0x0000FF00 /* End Message */
365 #define RES_DID 0x00FF0000 /* DID_ codes */
366 #define RES_DRV 0xFF000000 /* DRIVER_ codes */
368 #define MK_RES(drv,did,msg,tgt) ((int)(drv)<<24 | (int)(did)<<16 | (int)(msg)<<8 | (int)(tgt))
369 #define MK_RES_LNX(drv,did,msg,tgt) ((int)(drv)<<24 | (int)(did)<<16 | (int)(msg)<<8 | (int)(tgt)<<1)
371 #define SET_RES_TARGET(who,tgt) { who &= ~RES_TARGET; who |= (int)(tgt); }
372 #define SET_RES_TARGET_LNX(who,tgt) { who &= ~RES_TARGET_LNX; who |= (int)(tgt) << 1; }
373 #define SET_RES_MSG(who,msg) { who &= ~RES_ENDMSG; who |= (int)(msg) << 8; }
374 #define SET_RES_DID(who,did) { who &= ~RES_DID; who |= (int)(did) << 16; }
375 #define SET_RES_DRV(who,drv) { who &= ~RES_DRV; who |= (int)(drv) << 24; }
378 #define SYNC_DISABLE 0
379 #define SYNC_ENABLE BIT0
380 #define SYNC_NEGO_DONE BIT1
381 #define WIDE_ENABLE BIT2 /* Not used ;-) */
382 #define WIDE_NEGO_DONE BIT3 /* Not used ;-) */
383 #define EN_TAG_QUEUEING BIT4
384 #define EN_ATN_STOP BIT5
386 #define SYNC_NEGO_OFFSET 15
388 /*;---SCSI bus phase*/
389 #define SCSI_DATA_OUT 0
390 #define SCSI_DATA_IN 1
391 #define SCSI_COMMAND 2
392 #define SCSI_STATUS_ 3
395 #define SCSI_MSG_OUT 6
396 #define SCSI_MSG_IN 7
398 /*;----SCSI MSG BYTE*/ /* see scsi/scsi.h */ /* One is missing ! */
399 #define ABORT_TAG 0x0d
405 dma_addr_t saved_dma_handle;
409 ** Inquiry Data format
412 typedef struct _SCSIInqData { /* INQUIRY */
414 UCHAR DevType; /* Periph Qualifier & Periph Dev Type*/
415 UCHAR RMB_TypeMod; /* rem media bit & Dev Type Modifier */
416 UCHAR Vers; /* ISO, ECMA, & ANSI versions */
417 UCHAR RDF; /* AEN, TRMIOP, & response data format*/
418 UCHAR AddLen; /* length of additional data */
419 UCHAR Res1; /* reserved */
420 UCHAR Res2; /* reserved */
421 UCHAR Flags; /* RelADr,Wbus32,Wbus16,Sync,etc. */
422 UCHAR VendorID[8]; /* Vendor Identification */
423 UCHAR ProductID[16]; /* Product Identification */
424 UCHAR ProductRev[4]; /* Product Revision */
427 } SCSI_INQDATA, *PSCSI_INQDATA;
430 /* Inquiry byte 0 masks */
433 #define SCSI_DEVTYPE 0x1F /* Peripheral Device Type */
434 #define SCSI_PERIPHQUAL 0xE0 /* Peripheral Qualifier */
435 #define TYPE_NODEV SCSI_DEVTYPE /* Unknown or no device type */
438 /* Inquiry byte 1 mask */
440 #define SCSI_REMOVABLE_MEDIA 0x80 /* Removable Media bit (1=removable) */
443 /* Peripheral Device Type definitions */
444 /* see include/scsi/scsi.h for the rest */
447 # define TYPE_PRINTER 0x02 /* Printer device */
450 # define TYPE_COMM 0x09 /* Communications device */
454 ** Inquiry flag definitions (Inq data byte 7)
457 #define SCSI_INQ_RELADR 0x80 /* device supports relative addressing*/
458 #define SCSI_INQ_WBUS32 0x40 /* device supports 32 bit data xfers */
459 #define SCSI_INQ_WBUS16 0x20 /* device supports 16 bit data xfers */
460 #define SCSI_INQ_SYNC 0x10 /* device supports synchronous xfer */
461 #define SCSI_INQ_LINKED 0x08 /* device supports linked commands */
462 #define SCSI_INQ_CMDQUEUE 0x02 /* device supports command queueing */
463 #define SCSI_INQ_SFTRE 0x01 /* device supports soft resets */
467 ;==========================================================
469 ;==========================================================
471 typedef struct _EEprom
479 #define REAL_EE_ADAPT_SCSI_ID 64
480 #define REAL_EE_MODE2 65
481 #define REAL_EE_DELAY 66
482 #define REAL_EE_TAG_CMD_NUM 67
484 #define EE_ADAPT_SCSI_ID 32
487 #define EE_TAG_CMD_NUM 35
491 /*; EE_MODE1 bits definition*/
492 #define PARITY_CHK_ BIT0
493 #define SYNC_NEGO_ BIT1
494 #define EN_DISCONNECT_ BIT2
495 #define SEND_START_ BIT3
496 #define TAG_QUEUEING_ BIT4
498 /*; EE_MODE2 bits definition*/
499 #define MORE2_DRV BIT0
500 #define GREATER_1G BIT1
501 #define RST_SCSI_BUS BIT2
502 #define ACTIVE_NEGATION BIT3
504 #define LUN_CHECK BIT5
508 #define EEPROM_READ 0x80
511 ;==========================================================
512 ; AMD 53C974 Registers bit Definition
513 ;==========================================================
516 ;====================
518 ;====================
521 /*; Command Reg.(+0CH) (rw) */
522 #define DMA_COMMAND BIT7
524 #define CLEAR_FIFO_CMD 1
525 #define RST_DEVICE_CMD 2
526 #define RST_SCSI_BUS_CMD 3
528 #define INFO_XFER_CMD 0x10
529 #define INITIATOR_CMD_CMPLTE 0x11
530 #define MSG_ACCEPTED_CMD 0x12
531 #define XFER_PAD_BYTE 0x18
532 #define SET_ATN_CMD 0x1A
533 #define RESET_ATN_CMD 0x1B
535 #define SEL_WO_ATN 0x41 /* currently not used */
536 #define SEL_W_ATN 0x42
537 #define SEL_W_ATN_STOP 0x43
538 #define SEL_W_ATN3 0x46
539 #define EN_SEL_RESEL 0x44
540 #define DIS_SEL_RESEL 0x45 /* currently not used */
541 #define RESEL 0x40 /* " */
542 #define RESEL_ATN3 0x47 /* " */
544 #define DATA_XFER_CMD INFO_XFER_CMD
547 /*; SCSI Status Reg.(+10H) (r) */
548 #define INTERRUPT BIT7
549 #define ILLEGAL_OP_ERR BIT6
550 #define PARITY_ERR BIT5
551 #define COUNT_2_ZERO BIT4
552 #define GROUP_CODE_VALID BIT3
553 #define SCSI_PHASE_MASK (BIT2+BIT1+BIT0)
554 /* BIT2: MSG phase; BIT1: C/D physe; BIT0: I/O phase */
556 /*; Interrupt Status Reg.(+14H) (r) */
557 #define SCSI_RESET BIT7
558 #define INVALID_CMD BIT6
559 #define DISCONNECTED BIT5
560 #define SERVICE_REQUEST BIT4
561 #define SUCCESSFUL_OP BIT3
562 #define RESELECTED BIT2
563 #define SEL_ATTENTION BIT1
564 #define SELECTED BIT0
566 /*; Internal State Reg.(+18H) (r) */
567 #define SYNC_OFFSET_FLAG BIT3
568 #define INTRN_STATE_MASK (BIT2+BIT1+BIT0)
569 /* 0x04: Sel. successful (w/o stop), 0x01: Sel. successful (w/ stop) */
571 /*; Clock Factor Reg.(+24H) (w) */
572 #define CLK_FREQ_40MHZ 0
573 #define CLK_FREQ_35MHZ (BIT2+BIT1+BIT0)
574 #define CLK_FREQ_30MHZ (BIT2+BIT1)
575 #define CLK_FREQ_25MHZ (BIT2+BIT0)
576 #define CLK_FREQ_20MHZ BIT2
577 #define CLK_FREQ_15MHZ (BIT1+BIT0)
578 #define CLK_FREQ_10MHZ BIT1
580 /*; Control Reg. 1(+20H) (rw) */
581 #define EXTENDED_TIMING BIT7
582 #define DIS_INT_ON_SCSI_RST BIT6
583 #define PARITY_ERR_REPO BIT4
584 #define SCSI_ID_ON_BUS (BIT2+BIT1+BIT0) /* host adapter ID */
586 /*; Control Reg. 2(+2CH) (rw) */
587 #define EN_FEATURE BIT6
588 #define EN_SCSI2_CMD BIT3
590 /*; Control Reg. 3(+30H) (rw) */
591 #define ID_MSG_CHECK BIT7
592 #define EN_QTAG_MSG BIT6
593 #define EN_GRP2_CMD BIT5
594 #define FAST_SCSI BIT4 /* ;10MB/SEC */
595 #define FAST_CLK BIT3 /* ;25 - 40 MHZ */
597 /*; Control Reg. 4(+34H) (rw) */
599 #define EATER_25NS BIT7
600 #define EATER_35NS BIT6
601 #define EATER_0NS (BIT7+BIT6)
602 #define REDUCED_POWER BIT5
603 #define CTRL4_RESERVED BIT4 /* must be 1 acc. to AM53C974.c */
604 #define NEGATE_REQACKDATA BIT2
605 #define NEGATE_REQACK BIT3
607 #define GLITCH_TO_NS(x) (((~x>>6 & 2) >> 1) | ((x>>6 & 1) << 1 ^ (x>>6 & 2)))
608 #define NS_TO_GLITCH(y) (((~y<<7) | ~((y<<6) ^ ((y<<5 & 1<<6) | ~0x40))) & 0xc0)
611 ;====================
613 ;====================
615 /*; DMA Command Reg.(+40H) (rw) */
616 #define READ_DIRECTION BIT7
617 #define WRITE_DIRECTION 0
618 #define EN_DMA_INT BIT6
619 #define EN_PAGE_INT BIT5 /* page transfer interrupt enable */
620 #define MAP_TO_MDL BIT4
621 #define DIAGNOSTIC BIT2
622 #define DMA_IDLE_CMD 0
623 #define DMA_BLAST_CMD BIT0
624 #define DMA_ABORT_CMD BIT1
625 #define DMA_START_CMD (BIT1+BIT0)
627 /*; DMA Status Reg.(+54H) (r) */
628 #define PCI_MS_ABORT BIT6
629 #define BLAST_COMPLETE BIT5
630 #define SCSI_INTERRUPT BIT4
631 #define DMA_XFER_DONE BIT3
632 #define DMA_XFER_ABORT BIT2
633 #define DMA_XFER_ERROR BIT1
634 #define POWER_DOWN BIT0
636 /*; DMA SCSI Bus and Ctrl.(+70H) */
637 #define EN_INT_ON_PCI_ABORT BIT25
638 #define WRT_ERASE_DMA_STAT BIT24
639 #define PW_DOWN_CTRL BIT21
640 #define SCSI_BUSY BIT20
643 #define SCSI_LINES 0x0003ffff
646 ;==========================================================
647 ; SCSI Chip register address offset
648 ;==========================================================
649 ;Registers are rw unless declared otherwise
651 #define CtcReg_Low 0x00 /* r curr. transfer count */
652 #define CtcReg_Mid 0x04 /* r */
653 #define CtcReg_High 0x38 /* r */
654 #define ScsiFifo 0x08
656 #define Scsi_Status 0x10 /* r */
657 #define INT_Status 0x14 /* r */
658 #define Sync_Period 0x18 /* w */
659 #define Sync_Offset 0x1C /* w */
660 #define Clk_Factor 0x24 /* w */
661 #define CtrlReg1 0x20
662 #define CtrlReg2 0x2C
663 #define CtrlReg3 0x30
664 #define CtrlReg4 0x34
666 #define DMA_XferCnt 0x44 /* rw starting transfer count (32 bit) */
667 #define DMA_XferAddr 0x48 /* rw starting physical address (32 bit) */
668 #define DMA_Wk_ByteCntr 0x4C /* r working byte counter */
669 #define DMA_Wk_AddrCntr 0x50 /* r working address counter */
670 #define DMA_Status 0x54 /* r */
671 #define DMA_MDL_Addr 0x58 /* rw starting MDL address */
672 #define DMA_Wk_MDL_Cntr 0x5C /* r working MDL counter */
673 #define DMA_ScsiBusCtrl 0x70 /* rw SCSI Bus, PCI/DMA Ctrl */
675 #define StcReg_Low CtcReg_Low /* w start transfer count */
676 #define StcReg_Mid CtcReg_Mid /* w */
677 #define StcReg_High CtcReg_High /* w */
678 #define Scsi_Dest_ID Scsi_Status /* w */
679 #define Scsi_TimeOut INT_Status /* w */
680 #define Intern_State Sync_Period /* r */
681 #define Current_Fifo Sync_Offset /* r Curr. FIFO / int. state */
684 #define DC390_read8(address) \
685 (inb (pACB->IOPortBase + (address)))
687 #define DC390_read8_(address, base) \
688 (inb ((USHORT)(base) + (address)))
690 #define DC390_read16(address) \
691 (inw (pACB->IOPortBase + (address)))
693 #define DC390_read32(address) \
694 (inl (pACB->IOPortBase + (address)))
696 #define DC390_write8(address,value) \
697 outb ((value), pACB->IOPortBase + (address))
699 #define DC390_write8_(address,value,base) \
700 outb ((value), (USHORT)(base) + (address))
702 #define DC390_write16(address,value) \
703 outw ((value), pACB->IOPortBase + (address))
705 #define DC390_write32(address,value) \
706 outl ((value), pACB->IOPortBase + (address))
709 #endif /* _TMSCSIM_H */