2 * linux/drivers/char/8250.c
4 * Driver for 8250/16550-type serial ports
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 * Copyright (C) 2001 Russell King.
10 * 2005/09/16: Enabled higher baud rates for 16C95x.
11 * (Mathias Adam <a2@adamis.de>)
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
18 * $Id: 8250.c,v 1.90 2002/07/28 10:03:27 rmk Exp $
20 * A note about mapbase / membase
22 * mapbase is the physical address of the IO port.
23 * membase is an 'ioremapped' cookie.
26 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
30 #include <linux/module.h>
31 #include <linux/moduleparam.h>
32 #include <linux/ioport.h>
33 #include <linux/init.h>
34 #include <linux/console.h>
35 #include <linux/sysrq.h>
36 #include <linux/delay.h>
37 #include <linux/platform_device.h>
38 #include <linux/tty.h>
39 #include <linux/tty_flip.h>
40 #include <linux/serial_reg.h>
41 #include <linux/serial_core.h>
42 #include <linux/serial.h>
43 #include <linux/serial_8250.h>
44 #include <linux/nmi.h>
45 #include <linux/mutex.h>
54 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
55 * is unsafe when used on edge-triggered interrupts.
57 static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
59 static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
65 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
67 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
71 #define DEBUG_INTR(fmt...) printk(fmt)
73 #define DEBUG_INTR(fmt...) do { } while (0)
76 #define PASS_LIMIT 256
79 * We default to IRQ0 for the "no irq" hack. Some
80 * machine types want others as well - they're free
81 * to redefine this in their header file.
83 #define is_real_interrupt(irq) ((irq) != 0)
85 #ifdef CONFIG_SERIAL_8250_DETECT_IRQ
86 #define CONFIG_SERIAL_DETECT_IRQ 1
88 #ifdef CONFIG_SERIAL_8250_MANY_PORTS
89 #define CONFIG_SERIAL_MANY_PORTS 1
93 * HUB6 is always on. This will be removed once the header
94 * files have been cleaned.
98 #include <asm/serial.h>
101 * SERIAL_PORT_DFNS tells us about built-in ports that have no
102 * standard enumeration mechanism. Platforms that can find all
103 * serial ports via mechanisms like ACPI or PCI need not supply it.
105 #ifndef SERIAL_PORT_DFNS
106 #define SERIAL_PORT_DFNS
109 static const struct old_serial_port old_serial_port[] = {
110 SERIAL_PORT_DFNS /* defined in asm/serial.h */
113 #define UART_NR CONFIG_SERIAL_8250_NR_UARTS
115 #ifdef CONFIG_SERIAL_8250_RSA
117 #define PORT_RSA_MAX 4
118 static unsigned long probe_rsa[PORT_RSA_MAX];
119 static unsigned int probe_rsa_count;
120 #endif /* CONFIG_SERIAL_8250_RSA */
122 struct uart_8250_port {
123 struct uart_port port;
124 struct timer_list timer; /* "no irq" timer */
125 struct list_head list; /* ports on this IRQ */
126 unsigned short capabilities; /* port capabilities */
127 unsigned short bugs; /* port bugs */
128 unsigned int tx_loadsz; /* transmit fifo load size */
133 unsigned char mcr_mask; /* mask of user bits */
134 unsigned char mcr_force; /* mask of forced bits */
135 unsigned char lsr_break_flag;
138 * We provide a per-port pm hook.
140 void (*pm)(struct uart_port *port,
141 unsigned int state, unsigned int old);
146 struct list_head *head;
149 static struct irq_info irq_lists[NR_IRQS];
152 * Here we define the default xmit fifo size used for each type of UART.
154 static const struct serial8250_config uart_config[] = {
179 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
180 .flags = UART_CAP_FIFO,
191 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
197 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
199 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
205 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
207 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
215 .name = "16C950/954",
218 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
219 .flags = UART_CAP_FIFO,
225 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
227 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
233 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
234 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
240 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
241 .flags = UART_CAP_FIFO,
247 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
248 .flags = UART_CAP_FIFO | UART_NATSEMI,
254 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
255 .flags = UART_CAP_FIFO | UART_CAP_UUE,
259 #ifdef CONFIG_SERIAL_8250_AU1X00
261 /* Au1x00 UART hardware has a weird register layout */
262 static const u8 au_io_in_map[] = {
272 static const u8 au_io_out_map[] = {
280 /* sane hardware needs no mapping */
281 static inline int map_8250_in_reg(struct uart_8250_port *up, int offset)
283 if (up->port.iotype != UPIO_AU)
285 return au_io_in_map[offset];
288 static inline int map_8250_out_reg(struct uart_8250_port *up, int offset)
290 if (up->port.iotype != UPIO_AU)
292 return au_io_out_map[offset];
297 /* sane hardware needs no mapping */
298 #define map_8250_in_reg(up, offset) (offset)
299 #define map_8250_out_reg(up, offset) (offset)
303 static unsigned int serial_in(struct uart_8250_port *up, int offset)
306 offset = map_8250_in_reg(up, offset) << up->port.regshift;
308 switch (up->port.iotype) {
310 outb(up->port.hub6 - 1 + offset, up->port.iobase);
311 return inb(up->port.iobase + 1);
314 return readb(up->port.membase + offset);
317 return readl(up->port.membase + offset);
319 #ifdef CONFIG_SERIAL_8250_AU1X00
321 return __raw_readl(up->port.membase + offset);
325 if (offset == UART_IIR) {
326 tmp = readl(up->port.membase + (UART_IIR & ~3));
327 return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */
329 return readb(up->port.membase + offset);
332 return inb(up->port.iobase + offset);
337 serial_out(struct uart_8250_port *up, int offset, int value)
339 offset = map_8250_out_reg(up, offset) << up->port.regshift;
341 switch (up->port.iotype) {
343 outb(up->port.hub6 - 1 + offset, up->port.iobase);
344 outb(value, up->port.iobase + 1);
348 writeb(value, up->port.membase + offset);
352 writel(value, up->port.membase + offset);
355 #ifdef CONFIG_SERIAL_8250_AU1X00
357 __raw_writel(value, up->port.membase + offset);
361 if (!((offset == UART_IER) && (value & UART_IER_UUE)))
362 writeb(value, up->port.membase + offset);
366 outb(value, up->port.iobase + offset);
371 * We used to support using pause I/O for certain machines. We
372 * haven't supported this for a while, but just in case it's badly
373 * needed for certain old 386 machines, I've left these #define's
376 #define serial_inp(up, offset) serial_in(up, offset)
377 #define serial_outp(up, offset, value) serial_out(up, offset, value)
379 /* Uart divisor latch read */
380 static inline int _serial_dl_read(struct uart_8250_port *up)
382 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
385 /* Uart divisor latch write */
386 static inline void _serial_dl_write(struct uart_8250_port *up, int value)
388 serial_outp(up, UART_DLL, value & 0xff);
389 serial_outp(up, UART_DLM, value >> 8 & 0xff);
392 #ifdef CONFIG_SERIAL_8250_AU1X00
393 /* Au1x00 haven't got a standard divisor latch */
394 static int serial_dl_read(struct uart_8250_port *up)
396 if (up->port.iotype == UPIO_AU)
397 return __raw_readl(up->port.membase + 0x28);
399 return _serial_dl_read(up);
402 static void serial_dl_write(struct uart_8250_port *up, int value)
404 if (up->port.iotype == UPIO_AU)
405 __raw_writel(value, up->port.membase + 0x28);
407 _serial_dl_write(up, value);
410 #define serial_dl_read(up) _serial_dl_read(up)
411 #define serial_dl_write(up, value) _serial_dl_write(up, value)
417 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
419 serial_out(up, UART_SCR, offset);
420 serial_out(up, UART_ICR, value);
423 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
427 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
428 serial_out(up, UART_SCR, offset);
429 value = serial_in(up, UART_ICR);
430 serial_icr_write(up, UART_ACR, up->acr);
438 static inline void serial8250_clear_fifos(struct uart_8250_port *p)
440 if (p->capabilities & UART_CAP_FIFO) {
441 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
442 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
443 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
444 serial_outp(p, UART_FCR, 0);
449 * IER sleep support. UARTs which have EFRs need the "extended
450 * capability" bit enabled. Note that on XR16C850s, we need to
451 * reset LCR to write to IER.
453 static inline void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
455 if (p->capabilities & UART_CAP_SLEEP) {
456 if (p->capabilities & UART_CAP_EFR) {
457 serial_outp(p, UART_LCR, 0xBF);
458 serial_outp(p, UART_EFR, UART_EFR_ECB);
459 serial_outp(p, UART_LCR, 0);
461 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
462 if (p->capabilities & UART_CAP_EFR) {
463 serial_outp(p, UART_LCR, 0xBF);
464 serial_outp(p, UART_EFR, 0);
465 serial_outp(p, UART_LCR, 0);
470 #ifdef CONFIG_SERIAL_8250_RSA
472 * Attempts to turn on the RSA FIFO. Returns zero on failure.
473 * We set the port uart clock rate if we succeed.
475 static int __enable_rsa(struct uart_8250_port *up)
480 mode = serial_inp(up, UART_RSA_MSR);
481 result = mode & UART_RSA_MSR_FIFO;
484 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
485 mode = serial_inp(up, UART_RSA_MSR);
486 result = mode & UART_RSA_MSR_FIFO;
490 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
495 static void enable_rsa(struct uart_8250_port *up)
497 if (up->port.type == PORT_RSA) {
498 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
499 spin_lock_irq(&up->port.lock);
501 spin_unlock_irq(&up->port.lock);
503 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
504 serial_outp(up, UART_RSA_FRR, 0);
509 * Attempts to turn off the RSA FIFO. Returns zero on failure.
510 * It is unknown why interrupts were disabled in here. However,
511 * the caller is expected to preserve this behaviour by grabbing
512 * the spinlock before calling this function.
514 static void disable_rsa(struct uart_8250_port *up)
519 if (up->port.type == PORT_RSA &&
520 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
521 spin_lock_irq(&up->port.lock);
523 mode = serial_inp(up, UART_RSA_MSR);
524 result = !(mode & UART_RSA_MSR_FIFO);
527 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
528 mode = serial_inp(up, UART_RSA_MSR);
529 result = !(mode & UART_RSA_MSR_FIFO);
533 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
534 spin_unlock_irq(&up->port.lock);
537 #endif /* CONFIG_SERIAL_8250_RSA */
540 * This is a quickie test to see how big the FIFO is.
541 * It doesn't work at all the time, more's the pity.
543 static int size_fifo(struct uart_8250_port *up)
545 unsigned char old_fcr, old_mcr, old_lcr;
546 unsigned short old_dl;
549 old_lcr = serial_inp(up, UART_LCR);
550 serial_outp(up, UART_LCR, 0);
551 old_fcr = serial_inp(up, UART_FCR);
552 old_mcr = serial_inp(up, UART_MCR);
553 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
554 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
555 serial_outp(up, UART_MCR, UART_MCR_LOOP);
556 serial_outp(up, UART_LCR, UART_LCR_DLAB);
557 old_dl = serial_dl_read(up);
558 serial_dl_write(up, 0x0001);
559 serial_outp(up, UART_LCR, 0x03);
560 for (count = 0; count < 256; count++)
561 serial_outp(up, UART_TX, count);
562 mdelay(20);/* FIXME - schedule_timeout */
563 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
564 (count < 256); count++)
565 serial_inp(up, UART_RX);
566 serial_outp(up, UART_FCR, old_fcr);
567 serial_outp(up, UART_MCR, old_mcr);
568 serial_outp(up, UART_LCR, UART_LCR_DLAB);
569 serial_dl_write(up, old_dl);
570 serial_outp(up, UART_LCR, old_lcr);
576 * Read UART ID using the divisor method - set DLL and DLM to zero
577 * and the revision will be in DLL and device type in DLM. We
578 * preserve the device state across this.
580 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
582 unsigned char old_dll, old_dlm, old_lcr;
585 old_lcr = serial_inp(p, UART_LCR);
586 serial_outp(p, UART_LCR, UART_LCR_DLAB);
588 old_dll = serial_inp(p, UART_DLL);
589 old_dlm = serial_inp(p, UART_DLM);
591 serial_outp(p, UART_DLL, 0);
592 serial_outp(p, UART_DLM, 0);
594 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
596 serial_outp(p, UART_DLL, old_dll);
597 serial_outp(p, UART_DLM, old_dlm);
598 serial_outp(p, UART_LCR, old_lcr);
604 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
605 * When this function is called we know it is at least a StarTech
606 * 16650 V2, but it might be one of several StarTech UARTs, or one of
607 * its clones. (We treat the broken original StarTech 16650 V1 as a
608 * 16550, and why not? Startech doesn't seem to even acknowledge its
611 * What evil have men's minds wrought...
613 static void autoconfig_has_efr(struct uart_8250_port *up)
615 unsigned int id1, id2, id3, rev;
618 * Everything with an EFR has SLEEP
620 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
623 * First we check to see if it's an Oxford Semiconductor UART.
625 * If we have to do this here because some non-National
626 * Semiconductor clone chips lock up if you try writing to the
627 * LSR register (which serial_icr_read does)
631 * Check for Oxford Semiconductor 16C950.
633 * EFR [4] must be set else this test fails.
635 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
636 * claims that it's needed for 952 dual UART's (which are not
637 * recommended for new designs).
640 serial_out(up, UART_LCR, 0xBF);
641 serial_out(up, UART_EFR, UART_EFR_ECB);
642 serial_out(up, UART_LCR, 0x00);
643 id1 = serial_icr_read(up, UART_ID1);
644 id2 = serial_icr_read(up, UART_ID2);
645 id3 = serial_icr_read(up, UART_ID3);
646 rev = serial_icr_read(up, UART_REV);
648 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
650 if (id1 == 0x16 && id2 == 0xC9 &&
651 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
652 up->port.type = PORT_16C950;
655 * Enable work around for the Oxford Semiconductor 952 rev B
656 * chip which causes it to seriously miscalculate baud rates
659 if (id3 == 0x52 && rev == 0x01)
660 up->bugs |= UART_BUG_QUOT;
665 * We check for a XR16C850 by setting DLL and DLM to 0, and then
666 * reading back DLL and DLM. The chip type depends on the DLM
668 * 0x10 - XR16C850 and the DLL contains the chip revision.
672 id1 = autoconfig_read_divisor_id(up);
673 DEBUG_AUTOCONF("850id=%04x ", id1);
676 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
677 up->port.type = PORT_16850;
682 * It wasn't an XR16C850.
684 * We distinguish between the '654 and the '650 by counting
685 * how many bytes are in the FIFO. I'm using this for now,
686 * since that's the technique that was sent to me in the
687 * serial driver update, but I'm not convinced this works.
688 * I've had problems doing this in the past. -TYT
690 if (size_fifo(up) == 64)
691 up->port.type = PORT_16654;
693 up->port.type = PORT_16650V2;
697 * We detected a chip without a FIFO. Only two fall into
698 * this category - the original 8250 and the 16450. The
699 * 16450 has a scratch register (accessible with LCR=0)
701 static void autoconfig_8250(struct uart_8250_port *up)
703 unsigned char scratch, status1, status2;
705 up->port.type = PORT_8250;
707 scratch = serial_in(up, UART_SCR);
708 serial_outp(up, UART_SCR, 0xa5);
709 status1 = serial_in(up, UART_SCR);
710 serial_outp(up, UART_SCR, 0x5a);
711 status2 = serial_in(up, UART_SCR);
712 serial_outp(up, UART_SCR, scratch);
714 if (status1 == 0xa5 && status2 == 0x5a)
715 up->port.type = PORT_16450;
718 static int broken_efr(struct uart_8250_port *up)
721 * Exar ST16C2550 "A2" devices incorrectly detect as
722 * having an EFR, and report an ID of 0x0201. See
723 * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf
725 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
732 * We know that the chip has FIFOs. Does it have an EFR? The
733 * EFR is located in the same register position as the IIR and
734 * we know the top two bits of the IIR are currently set. The
735 * EFR should contain zero. Try to read the EFR.
737 static void autoconfig_16550a(struct uart_8250_port *up)
739 unsigned char status1, status2;
740 unsigned int iersave;
742 up->port.type = PORT_16550A;
743 up->capabilities |= UART_CAP_FIFO;
746 * Check for presence of the EFR when DLAB is set.
747 * Only ST16C650V1 UARTs pass this test.
749 serial_outp(up, UART_LCR, UART_LCR_DLAB);
750 if (serial_in(up, UART_EFR) == 0) {
751 serial_outp(up, UART_EFR, 0xA8);
752 if (serial_in(up, UART_EFR) != 0) {
753 DEBUG_AUTOCONF("EFRv1 ");
754 up->port.type = PORT_16650;
755 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
757 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
759 serial_outp(up, UART_EFR, 0);
764 * Maybe it requires 0xbf to be written to the LCR.
765 * (other ST16C650V2 UARTs, TI16C752A, etc)
767 serial_outp(up, UART_LCR, 0xBF);
768 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
769 DEBUG_AUTOCONF("EFRv2 ");
770 autoconfig_has_efr(up);
775 * Check for a National Semiconductor SuperIO chip.
776 * Attempt to switch to bank 2, read the value of the LOOP bit
777 * from EXCR1. Switch back to bank 0, change it in MCR. Then
778 * switch back to bank 2, read it from EXCR1 again and check
779 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
781 serial_outp(up, UART_LCR, 0);
782 status1 = serial_in(up, UART_MCR);
783 serial_outp(up, UART_LCR, 0xE0);
784 status2 = serial_in(up, 0x02); /* EXCR1 */
786 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
787 serial_outp(up, UART_LCR, 0);
788 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
789 serial_outp(up, UART_LCR, 0xE0);
790 status2 = serial_in(up, 0x02); /* EXCR1 */
791 serial_outp(up, UART_LCR, 0);
792 serial_outp(up, UART_MCR, status1);
794 if ((status2 ^ status1) & UART_MCR_LOOP) {
797 serial_outp(up, UART_LCR, 0xE0);
799 quot = serial_dl_read(up);
802 status1 = serial_in(up, 0x04); /* EXCR1 */
803 status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
804 status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
805 serial_outp(up, 0x04, status1);
807 serial_dl_write(up, quot);
809 serial_outp(up, UART_LCR, 0);
811 up->port.uartclk = 921600*16;
812 up->port.type = PORT_NS16550A;
813 up->capabilities |= UART_NATSEMI;
819 * No EFR. Try to detect a TI16750, which only sets bit 5 of
820 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
821 * Try setting it with and without DLAB set. Cheap clones
822 * set bit 5 without DLAB set.
824 serial_outp(up, UART_LCR, 0);
825 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
826 status1 = serial_in(up, UART_IIR) >> 5;
827 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
828 serial_outp(up, UART_LCR, UART_LCR_DLAB);
829 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
830 status2 = serial_in(up, UART_IIR) >> 5;
831 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
832 serial_outp(up, UART_LCR, 0);
834 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
836 if (status1 == 6 && status2 == 7) {
837 up->port.type = PORT_16750;
838 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
843 * Try writing and reading the UART_IER_UUE bit (b6).
844 * If it works, this is probably one of the Xscale platform's
846 * We're going to explicitly set the UUE bit to 0 before
847 * trying to write and read a 1 just to make sure it's not
848 * already a 1 and maybe locked there before we even start start.
850 iersave = serial_in(up, UART_IER);
851 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
852 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
854 * OK it's in a known zero state, try writing and reading
855 * without disturbing the current state of the other bits.
857 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
858 if (serial_in(up, UART_IER) & UART_IER_UUE) {
861 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
863 DEBUG_AUTOCONF("Xscale ");
864 up->port.type = PORT_XSCALE;
865 up->capabilities |= UART_CAP_UUE;
870 * If we got here we couldn't force the IER_UUE bit to 0.
871 * Log it and continue.
873 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
875 serial_outp(up, UART_IER, iersave);
879 * This routine is called by rs_init() to initialize a specific serial
880 * port. It determines what type of UART chip this serial port is
881 * using: 8250, 16450, 16550, 16550A. The important question is
882 * whether or not this UART is a 16550A or not, since this will
883 * determine whether or not we can use its FIFO features or not.
885 static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
887 unsigned char status1, scratch, scratch2, scratch3;
888 unsigned char save_lcr, save_mcr;
891 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
894 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04x, 0x%p): ",
895 up->port.line, up->port.iobase, up->port.membase);
898 * We really do need global IRQs disabled here - we're going to
899 * be frobbing the chips IRQ enable register to see if it exists.
901 spin_lock_irqsave(&up->port.lock, flags);
902 // save_flags(flags); cli();
904 up->capabilities = 0;
907 if (!(up->port.flags & UPF_BUGGY_UART)) {
909 * Do a simple existence test first; if we fail this,
910 * there's no point trying anything else.
912 * 0x80 is used as a nonsense port to prevent against
913 * false positives due to ISA bus float. The
914 * assumption is that 0x80 is a non-existent port;
915 * which should be safe since include/asm/io.h also
916 * makes this assumption.
918 * Note: this is safe as long as MCR bit 4 is clear
919 * and the device is in "PC" mode.
921 scratch = serial_inp(up, UART_IER);
922 serial_outp(up, UART_IER, 0);
926 scratch2 = serial_inp(up, UART_IER);
927 serial_outp(up, UART_IER, 0x0F);
931 scratch3 = serial_inp(up, UART_IER);
932 serial_outp(up, UART_IER, scratch);
933 if (scratch2 != 0 || scratch3 != 0x0F) {
935 * We failed; there's nothing here
937 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
943 save_mcr = serial_in(up, UART_MCR);
944 save_lcr = serial_in(up, UART_LCR);
947 * Check to see if a UART is really there. Certain broken
948 * internal modems based on the Rockwell chipset fail this
949 * test, because they apparently don't implement the loopback
950 * test mode. So this test is skipped on the COM 1 through
951 * COM 4 ports. This *should* be safe, since no board
952 * manufacturer would be stupid enough to design a board
953 * that conflicts with COM 1-4 --- we hope!
955 if (!(up->port.flags & UPF_SKIP_TEST)) {
956 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
957 status1 = serial_inp(up, UART_MSR) & 0xF0;
958 serial_outp(up, UART_MCR, save_mcr);
959 if (status1 != 0x90) {
960 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
967 * We're pretty sure there's a port here. Lets find out what
968 * type of port it is. The IIR top two bits allows us to find
969 * out if it's 8250 or 16450, 16550, 16550A or later. This
970 * determines what we test for next.
972 * We also initialise the EFR (if any) to zero for later. The
973 * EFR occupies the same register location as the FCR and IIR.
975 serial_outp(up, UART_LCR, 0xBF);
976 serial_outp(up, UART_EFR, 0);
977 serial_outp(up, UART_LCR, 0);
979 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
980 scratch = serial_in(up, UART_IIR) >> 6;
982 DEBUG_AUTOCONF("iir=%d ", scratch);
989 up->port.type = PORT_UNKNOWN;
992 up->port.type = PORT_16550;
995 autoconfig_16550a(up);
999 #ifdef CONFIG_SERIAL_8250_RSA
1001 * Only probe for RSA ports if we got the region.
1003 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1006 for (i = 0 ; i < probe_rsa_count; ++i) {
1007 if (probe_rsa[i] == up->port.iobase &&
1009 up->port.type = PORT_RSA;
1016 #ifdef CONFIG_SERIAL_8250_AU1X00
1017 /* if access method is AU, it is a 16550 with a quirk */
1018 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
1019 up->bugs |= UART_BUG_NOMSR;
1022 serial_outp(up, UART_LCR, save_lcr);
1024 if (up->capabilities != uart_config[up->port.type].flags) {
1026 "ttyS%d: detected caps %08x should be %08x\n",
1027 up->port.line, up->capabilities,
1028 uart_config[up->port.type].flags);
1031 up->port.fifosize = uart_config[up->port.type].fifo_size;
1032 up->capabilities = uart_config[up->port.type].flags;
1033 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1035 if (up->port.type == PORT_UNKNOWN)
1041 #ifdef CONFIG_SERIAL_8250_RSA
1042 if (up->port.type == PORT_RSA)
1043 serial_outp(up, UART_RSA_FRR, 0);
1045 serial_outp(up, UART_MCR, save_mcr);
1046 serial8250_clear_fifos(up);
1047 (void)serial_in(up, UART_RX);
1048 if (up->capabilities & UART_CAP_UUE)
1049 serial_outp(up, UART_IER, UART_IER_UUE);
1051 serial_outp(up, UART_IER, 0);
1054 spin_unlock_irqrestore(&up->port.lock, flags);
1055 // restore_flags(flags);
1056 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1059 static void autoconfig_irq(struct uart_8250_port *up)
1061 unsigned char save_mcr, save_ier;
1062 unsigned char save_ICP = 0;
1063 unsigned int ICP = 0;
1067 if (up->port.flags & UPF_FOURPORT) {
1068 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1069 save_ICP = inb_p(ICP);
1074 /* forget possible initially masked and pending IRQ */
1075 probe_irq_off(probe_irq_on());
1076 save_mcr = serial_inp(up, UART_MCR);
1077 save_ier = serial_inp(up, UART_IER);
1078 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1080 irqs = probe_irq_on();
1081 serial_outp(up, UART_MCR, 0);
1083 if (up->port.flags & UPF_FOURPORT) {
1084 serial_outp(up, UART_MCR,
1085 UART_MCR_DTR | UART_MCR_RTS);
1087 serial_outp(up, UART_MCR,
1088 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1090 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1091 (void)serial_inp(up, UART_LSR);
1092 (void)serial_inp(up, UART_RX);
1093 (void)serial_inp(up, UART_IIR);
1094 (void)serial_inp(up, UART_MSR);
1095 serial_outp(up, UART_TX, 0xFF);
1097 irq = probe_irq_off(irqs);
1099 serial_outp(up, UART_MCR, save_mcr);
1100 serial_outp(up, UART_IER, save_ier);
1102 if (up->port.flags & UPF_FOURPORT)
1103 outb_p(save_ICP, ICP);
1105 up->port.irq = (irq > 0) ? irq : 0;
1108 static inline void __stop_tx(struct uart_8250_port *p)
1110 if (p->ier & UART_IER_THRI) {
1111 p->ier &= ~UART_IER_THRI;
1112 serial_out(p, UART_IER, p->ier);
1116 static void serial8250_stop_tx(struct uart_port *port)
1118 struct uart_8250_port *up = (struct uart_8250_port *)port;
1123 * We really want to stop the transmitter from sending.
1125 if (up->port.type == PORT_16C950) {
1126 up->acr |= UART_ACR_TXDIS;
1127 serial_icr_write(up, UART_ACR, up->acr);
1131 static void transmit_chars(struct uart_8250_port *up);
1133 static void serial8250_start_tx(struct uart_port *port)
1135 struct uart_8250_port *up = (struct uart_8250_port *)port;
1137 if (!(up->ier & UART_IER_THRI)) {
1138 up->ier |= UART_IER_THRI;
1139 serial_out(up, UART_IER, up->ier);
1141 if (up->bugs & UART_BUG_TXEN) {
1142 unsigned char lsr, iir;
1143 lsr = serial_in(up, UART_LSR);
1144 iir = serial_in(up, UART_IIR);
1145 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT)
1151 * Re-enable the transmitter if we disabled it.
1153 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1154 up->acr &= ~UART_ACR_TXDIS;
1155 serial_icr_write(up, UART_ACR, up->acr);
1159 static void serial8250_stop_rx(struct uart_port *port)
1161 struct uart_8250_port *up = (struct uart_8250_port *)port;
1163 up->ier &= ~UART_IER_RLSI;
1164 up->port.read_status_mask &= ~UART_LSR_DR;
1165 serial_out(up, UART_IER, up->ier);
1168 static void serial8250_enable_ms(struct uart_port *port)
1170 struct uart_8250_port *up = (struct uart_8250_port *)port;
1172 /* no MSR capabilities */
1173 if (up->bugs & UART_BUG_NOMSR)
1176 up->ier |= UART_IER_MSI;
1177 serial_out(up, UART_IER, up->ier);
1181 receive_chars(struct uart_8250_port *up, int *status)
1183 struct tty_struct *tty = up->port.info->tty;
1184 unsigned char ch, lsr = *status;
1185 int max_count = 256;
1189 ch = serial_inp(up, UART_RX);
1191 up->port.icount.rx++;
1193 #ifdef CONFIG_SERIAL_8250_CONSOLE
1195 * Recover the break flag from console xmit
1197 if (up->port.line == up->port.cons->index) {
1198 lsr |= up->lsr_break_flag;
1199 up->lsr_break_flag = 0;
1203 if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE |
1204 UART_LSR_FE | UART_LSR_OE))) {
1206 * For statistics only
1208 if (lsr & UART_LSR_BI) {
1209 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1210 up->port.icount.brk++;
1212 * We do the SysRQ and SAK checking
1213 * here because otherwise the break
1214 * may get masked by ignore_status_mask
1215 * or read_status_mask.
1217 if (uart_handle_break(&up->port))
1219 } else if (lsr & UART_LSR_PE)
1220 up->port.icount.parity++;
1221 else if (lsr & UART_LSR_FE)
1222 up->port.icount.frame++;
1223 if (lsr & UART_LSR_OE)
1224 up->port.icount.overrun++;
1227 * Mask off conditions which should be ignored.
1229 lsr &= up->port.read_status_mask;
1231 if (lsr & UART_LSR_BI) {
1232 DEBUG_INTR("handling break....");
1234 } else if (lsr & UART_LSR_PE)
1236 else if (lsr & UART_LSR_FE)
1239 if (uart_handle_sysrq_char(&up->port, ch))
1242 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1245 lsr = serial_inp(up, UART_LSR);
1246 } while ((lsr & UART_LSR_DR) && (max_count-- > 0));
1247 spin_unlock(&up->port.lock);
1248 tty_flip_buffer_push(tty);
1249 spin_lock(&up->port.lock);
1253 static void transmit_chars(struct uart_8250_port *up)
1255 struct circ_buf *xmit = &up->port.info->xmit;
1258 if (up->port.x_char) {
1259 serial_outp(up, UART_TX, up->port.x_char);
1260 up->port.icount.tx++;
1261 up->port.x_char = 0;
1264 if (uart_tx_stopped(&up->port)) {
1265 serial8250_stop_tx(&up->port);
1268 if (uart_circ_empty(xmit)) {
1273 count = up->tx_loadsz;
1275 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1276 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1277 up->port.icount.tx++;
1278 if (uart_circ_empty(xmit))
1280 } while (--count > 0);
1282 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1283 uart_write_wakeup(&up->port);
1285 DEBUG_INTR("THRE...");
1287 if (uart_circ_empty(xmit))
1291 static unsigned int check_modem_status(struct uart_8250_port *up)
1293 unsigned int status = serial_in(up, UART_MSR);
1295 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1296 up->port.info != NULL) {
1297 if (status & UART_MSR_TERI)
1298 up->port.icount.rng++;
1299 if (status & UART_MSR_DDSR)
1300 up->port.icount.dsr++;
1301 if (status & UART_MSR_DDCD)
1302 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1303 if (status & UART_MSR_DCTS)
1304 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1306 wake_up_interruptible(&up->port.info->delta_msr_wait);
1313 * This handles the interrupt from one port.
1316 serial8250_handle_port(struct uart_8250_port *up)
1318 unsigned int status;
1320 spin_lock(&up->port.lock);
1322 status = serial_inp(up, UART_LSR);
1324 DEBUG_INTR("status = %x...", status);
1326 if (status & UART_LSR_DR)
1327 receive_chars(up, &status);
1328 check_modem_status(up);
1329 if (status & UART_LSR_THRE)
1332 spin_unlock(&up->port.lock);
1336 * This is the serial driver's interrupt routine.
1338 * Arjan thinks the old way was overly complex, so it got simplified.
1339 * Alan disagrees, saying that need the complexity to handle the weird
1340 * nature of ISA shared interrupts. (This is a special exception.)
1342 * In order to handle ISA shared interrupts properly, we need to check
1343 * that all ports have been serviced, and therefore the ISA interrupt
1344 * line has been de-asserted.
1346 * This means we need to loop through all ports. checking that they
1347 * don't have an interrupt pending.
1349 static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1351 struct irq_info *i = dev_id;
1352 struct list_head *l, *end = NULL;
1353 int pass_counter = 0, handled = 0;
1355 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1357 spin_lock(&i->lock);
1361 struct uart_8250_port *up;
1364 up = list_entry(l, struct uart_8250_port, list);
1366 iir = serial_in(up, UART_IIR);
1367 if (!(iir & UART_IIR_NO_INT)) {
1368 serial8250_handle_port(up);
1373 } else if (end == NULL)
1378 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1379 /* If we hit this, we're dead. */
1380 printk(KERN_ERR "serial8250: too much work for "
1386 spin_unlock(&i->lock);
1388 DEBUG_INTR("end.\n");
1390 return IRQ_RETVAL(handled);
1394 * To support ISA shared interrupts, we need to have one interrupt
1395 * handler that ensures that the IRQ line has been deasserted
1396 * before returning. Failing to do this will result in the IRQ
1397 * line being stuck active, and, since ISA irqs are edge triggered,
1398 * no more IRQs will be seen.
1400 static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1402 spin_lock_irq(&i->lock);
1404 if (!list_empty(i->head)) {
1405 if (i->head == &up->list)
1406 i->head = i->head->next;
1407 list_del(&up->list);
1409 BUG_ON(i->head != &up->list);
1413 spin_unlock_irq(&i->lock);
1416 static int serial_link_irq_chain(struct uart_8250_port *up)
1418 struct irq_info *i = irq_lists + up->port.irq;
1419 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1421 spin_lock_irq(&i->lock);
1424 list_add(&up->list, i->head);
1425 spin_unlock_irq(&i->lock);
1429 INIT_LIST_HEAD(&up->list);
1430 i->head = &up->list;
1431 spin_unlock_irq(&i->lock);
1433 ret = request_irq(up->port.irq, serial8250_interrupt,
1434 irq_flags, "serial", i);
1436 serial_do_unlink(i, up);
1442 static void serial_unlink_irq_chain(struct uart_8250_port *up)
1444 struct irq_info *i = irq_lists + up->port.irq;
1446 BUG_ON(i->head == NULL);
1448 if (list_empty(i->head))
1449 free_irq(up->port.irq, i);
1451 serial_do_unlink(i, up);
1455 * This function is used to handle ports that do not have an
1456 * interrupt. This doesn't work very well for 16450's, but gives
1457 * barely passable results for a 16550A. (Although at the expense
1458 * of much CPU overhead).
1460 static void serial8250_timeout(unsigned long data)
1462 struct uart_8250_port *up = (struct uart_8250_port *)data;
1463 unsigned int timeout;
1466 iir = serial_in(up, UART_IIR);
1467 if (!(iir & UART_IIR_NO_INT))
1468 serial8250_handle_port(up);
1470 timeout = up->port.timeout;
1471 timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
1472 mod_timer(&up->timer, jiffies + timeout);
1475 static unsigned int serial8250_tx_empty(struct uart_port *port)
1477 struct uart_8250_port *up = (struct uart_8250_port *)port;
1478 unsigned long flags;
1481 spin_lock_irqsave(&up->port.lock, flags);
1482 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
1483 spin_unlock_irqrestore(&up->port.lock, flags);
1488 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1490 struct uart_8250_port *up = (struct uart_8250_port *)port;
1491 unsigned int status;
1494 status = check_modem_status(up);
1497 if (status & UART_MSR_DCD)
1499 if (status & UART_MSR_RI)
1501 if (status & UART_MSR_DSR)
1503 if (status & UART_MSR_CTS)
1508 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1510 struct uart_8250_port *up = (struct uart_8250_port *)port;
1511 unsigned char mcr = 0;
1513 if (mctrl & TIOCM_RTS)
1514 mcr |= UART_MCR_RTS;
1515 if (mctrl & TIOCM_DTR)
1516 mcr |= UART_MCR_DTR;
1517 if (mctrl & TIOCM_OUT1)
1518 mcr |= UART_MCR_OUT1;
1519 if (mctrl & TIOCM_OUT2)
1520 mcr |= UART_MCR_OUT2;
1521 if (mctrl & TIOCM_LOOP)
1522 mcr |= UART_MCR_LOOP;
1524 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1526 serial_out(up, UART_MCR, mcr);
1529 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1531 struct uart_8250_port *up = (struct uart_8250_port *)port;
1532 unsigned long flags;
1534 spin_lock_irqsave(&up->port.lock, flags);
1535 if (break_state == -1)
1536 up->lcr |= UART_LCR_SBC;
1538 up->lcr &= ~UART_LCR_SBC;
1539 serial_out(up, UART_LCR, up->lcr);
1540 spin_unlock_irqrestore(&up->port.lock, flags);
1543 static int serial8250_startup(struct uart_port *port)
1545 struct uart_8250_port *up = (struct uart_8250_port *)port;
1546 unsigned long flags;
1547 unsigned char lsr, iir;
1550 up->capabilities = uart_config[up->port.type].flags;
1553 if (up->port.type == PORT_16C950) {
1554 /* Wake up and initialize UART */
1556 serial_outp(up, UART_LCR, 0xBF);
1557 serial_outp(up, UART_EFR, UART_EFR_ECB);
1558 serial_outp(up, UART_IER, 0);
1559 serial_outp(up, UART_LCR, 0);
1560 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1561 serial_outp(up, UART_LCR, 0xBF);
1562 serial_outp(up, UART_EFR, UART_EFR_ECB);
1563 serial_outp(up, UART_LCR, 0);
1566 #ifdef CONFIG_SERIAL_8250_RSA
1568 * If this is an RSA port, see if we can kick it up to the
1569 * higher speed clock.
1575 * Clear the FIFO buffers and disable them.
1576 * (they will be reenabled in set_termios())
1578 serial8250_clear_fifos(up);
1581 * Clear the interrupt registers.
1583 (void) serial_inp(up, UART_LSR);
1584 (void) serial_inp(up, UART_RX);
1585 (void) serial_inp(up, UART_IIR);
1586 (void) serial_inp(up, UART_MSR);
1589 * At this point, there's no way the LSR could still be 0xff;
1590 * if it is, then bail out, because there's likely no UART
1593 if (!(up->port.flags & UPF_BUGGY_UART) &&
1594 (serial_inp(up, UART_LSR) == 0xff)) {
1595 printk("ttyS%d: LSR safety check engaged!\n", up->port.line);
1600 * For a XR16C850, we need to set the trigger levels
1602 if (up->port.type == PORT_16850) {
1605 serial_outp(up, UART_LCR, 0xbf);
1607 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
1608 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
1609 serial_outp(up, UART_TRG, UART_TRG_96);
1610 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
1611 serial_outp(up, UART_TRG, UART_TRG_96);
1613 serial_outp(up, UART_LCR, 0);
1617 * If the "interrupt" for this port doesn't correspond with any
1618 * hardware interrupt, we use a timer-based system. The original
1619 * driver used to do this with IRQ0.
1621 if (!is_real_interrupt(up->port.irq)) {
1622 unsigned int timeout = up->port.timeout;
1624 timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
1626 up->timer.data = (unsigned long)up;
1627 mod_timer(&up->timer, jiffies + timeout);
1629 retval = serial_link_irq_chain(up);
1635 * Now, initialize the UART
1637 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
1639 spin_lock_irqsave(&up->port.lock, flags);
1640 if (up->port.flags & UPF_FOURPORT) {
1641 if (!is_real_interrupt(up->port.irq))
1642 up->port.mctrl |= TIOCM_OUT1;
1645 * Most PC uarts need OUT2 raised to enable interrupts.
1647 if (is_real_interrupt(up->port.irq))
1648 up->port.mctrl |= TIOCM_OUT2;
1650 serial8250_set_mctrl(&up->port, up->port.mctrl);
1653 * Do a quick test to see if we receive an
1654 * interrupt when we enable the TX irq.
1656 serial_outp(up, UART_IER, UART_IER_THRI);
1657 lsr = serial_in(up, UART_LSR);
1658 iir = serial_in(up, UART_IIR);
1659 serial_outp(up, UART_IER, 0);
1661 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
1662 if (!(up->bugs & UART_BUG_TXEN)) {
1663 up->bugs |= UART_BUG_TXEN;
1664 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
1668 up->bugs &= ~UART_BUG_TXEN;
1671 spin_unlock_irqrestore(&up->port.lock, flags);
1674 * Finally, enable interrupts. Note: Modem status interrupts
1675 * are set via set_termios(), which will be occurring imminently
1676 * anyway, so we don't enable them here.
1678 up->ier = UART_IER_RLSI | UART_IER_RDI;
1679 serial_outp(up, UART_IER, up->ier);
1681 if (up->port.flags & UPF_FOURPORT) {
1684 * Enable interrupts on the AST Fourport board
1686 icp = (up->port.iobase & 0xfe0) | 0x01f;
1692 * And clear the interrupt registers again for luck.
1694 (void) serial_inp(up, UART_LSR);
1695 (void) serial_inp(up, UART_RX);
1696 (void) serial_inp(up, UART_IIR);
1697 (void) serial_inp(up, UART_MSR);
1702 static void serial8250_shutdown(struct uart_port *port)
1704 struct uart_8250_port *up = (struct uart_8250_port *)port;
1705 unsigned long flags;
1708 * Disable interrupts from this port
1711 serial_outp(up, UART_IER, 0);
1713 spin_lock_irqsave(&up->port.lock, flags);
1714 if (up->port.flags & UPF_FOURPORT) {
1715 /* reset interrupts on the AST Fourport board */
1716 inb((up->port.iobase & 0xfe0) | 0x1f);
1717 up->port.mctrl |= TIOCM_OUT1;
1719 up->port.mctrl &= ~TIOCM_OUT2;
1721 serial8250_set_mctrl(&up->port, up->port.mctrl);
1722 spin_unlock_irqrestore(&up->port.lock, flags);
1725 * Disable break condition and FIFOs
1727 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
1728 serial8250_clear_fifos(up);
1730 #ifdef CONFIG_SERIAL_8250_RSA
1732 * Reset the RSA board back to 115kbps compat mode.
1738 * Read data port to reset things, and then unlink from
1741 (void) serial_in(up, UART_RX);
1743 if (!is_real_interrupt(up->port.irq))
1744 del_timer_sync(&up->timer);
1746 serial_unlink_irq_chain(up);
1749 static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
1754 * Handle magic divisors for baud rates above baud_base on
1755 * SMSC SuperIO chips.
1757 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
1758 baud == (port->uartclk/4))
1760 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
1761 baud == (port->uartclk/8))
1764 * For 16C950s UART_TCR is used in combination with divisor==1
1765 * to achieve baud rates up to baud_base*4.
1767 else if ((port->type == PORT_16C950) &&
1768 baud > (port->uartclk/16))
1772 quot = uart_get_divisor(port, baud);
1778 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
1779 struct ktermios *old)
1781 struct uart_8250_port *up = (struct uart_8250_port *)port;
1782 unsigned char cval, fcr = 0;
1783 unsigned long flags;
1784 unsigned int baud, quot, max_baud;
1786 switch (termios->c_cflag & CSIZE) {
1788 cval = UART_LCR_WLEN5;
1791 cval = UART_LCR_WLEN6;
1794 cval = UART_LCR_WLEN7;
1798 cval = UART_LCR_WLEN8;
1802 if (termios->c_cflag & CSTOPB)
1803 cval |= UART_LCR_STOP;
1804 if (termios->c_cflag & PARENB)
1805 cval |= UART_LCR_PARITY;
1806 if (!(termios->c_cflag & PARODD))
1807 cval |= UART_LCR_EPAR;
1809 if (termios->c_cflag & CMSPAR)
1810 cval |= UART_LCR_SPAR;
1814 * Ask the core to calculate the divisor for us.
1816 max_baud = (up->port.type == PORT_16C950 ? port->uartclk/4 : port->uartclk/16);
1817 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1818 quot = serial8250_get_divisor(port, baud);
1821 * Oxford Semi 952 rev B workaround
1823 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
1826 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
1828 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
1830 fcr = uart_config[up->port.type].fcr;
1834 * MCR-based auto flow control. When AFE is enabled, RTS will be
1835 * deasserted when the receive FIFO contains more characters than
1836 * the trigger, or the MCR RTS bit is cleared. In the case where
1837 * the remote UART is not using CTS auto flow control, we must
1838 * have sufficient FIFO entries for the latency of the remote
1839 * UART to respond. IOW, at least 32 bytes of FIFO.
1841 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
1842 up->mcr &= ~UART_MCR_AFE;
1843 if (termios->c_cflag & CRTSCTS)
1844 up->mcr |= UART_MCR_AFE;
1848 * Ok, we're now changing the port state. Do it with
1849 * interrupts disabled.
1851 spin_lock_irqsave(&up->port.lock, flags);
1854 * 16C950 supports additional prescaler ratios between 1:16 and 1:4
1855 * thus increasing max baud rate to uartclk/4.
1857 if (up->port.type == PORT_16C950) {
1858 if (baud == port->uartclk/4)
1859 serial_icr_write(up, UART_TCR, 0x4);
1860 else if (baud == port->uartclk/8)
1861 serial_icr_write(up, UART_TCR, 0x8);
1863 serial_icr_write(up, UART_TCR, 0);
1867 * Update the per-port timeout.
1869 uart_update_timeout(port, termios->c_cflag, baud);
1871 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
1872 if (termios->c_iflag & INPCK)
1873 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
1874 if (termios->c_iflag & (BRKINT | PARMRK))
1875 up->port.read_status_mask |= UART_LSR_BI;
1878 * Characteres to ignore
1880 up->port.ignore_status_mask = 0;
1881 if (termios->c_iflag & IGNPAR)
1882 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
1883 if (termios->c_iflag & IGNBRK) {
1884 up->port.ignore_status_mask |= UART_LSR_BI;
1886 * If we're ignoring parity and break indicators,
1887 * ignore overruns too (for real raw support).
1889 if (termios->c_iflag & IGNPAR)
1890 up->port.ignore_status_mask |= UART_LSR_OE;
1894 * ignore all characters if CREAD is not set
1896 if ((termios->c_cflag & CREAD) == 0)
1897 up->port.ignore_status_mask |= UART_LSR_DR;
1900 * CTS flow control flag and modem status interrupts
1902 up->ier &= ~UART_IER_MSI;
1903 if (!(up->bugs & UART_BUG_NOMSR) &&
1904 UART_ENABLE_MS(&up->port, termios->c_cflag))
1905 up->ier |= UART_IER_MSI;
1906 if (up->capabilities & UART_CAP_UUE)
1907 up->ier |= UART_IER_UUE | UART_IER_RTOIE;
1909 serial_out(up, UART_IER, up->ier);
1911 if (up->capabilities & UART_CAP_EFR) {
1912 unsigned char efr = 0;
1914 * TI16C752/Startech hardware flow control. FIXME:
1915 * - TI16C752 requires control thresholds to be set.
1916 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
1918 if (termios->c_cflag & CRTSCTS)
1919 efr |= UART_EFR_CTS;
1921 serial_outp(up, UART_LCR, 0xBF);
1922 serial_outp(up, UART_EFR, efr);
1925 #ifdef CONFIG_ARCH_OMAP15XX
1926 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
1927 if (cpu_is_omap1510() && is_omap_port((unsigned int)up->port.membase)) {
1928 if (baud == 115200) {
1930 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
1932 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
1936 if (up->capabilities & UART_NATSEMI) {
1937 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
1938 serial_outp(up, UART_LCR, 0xe0);
1940 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
1943 serial_dl_write(up, quot);
1946 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
1947 * is written without DLAB set, this mode will be disabled.
1949 if (up->port.type == PORT_16750)
1950 serial_outp(up, UART_FCR, fcr);
1952 serial_outp(up, UART_LCR, cval); /* reset DLAB */
1953 up->lcr = cval; /* Save LCR */
1954 if (up->port.type != PORT_16750) {
1955 if (fcr & UART_FCR_ENABLE_FIFO) {
1956 /* emulated UARTs (Lucent Venus 167x) need two steps */
1957 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1959 serial_outp(up, UART_FCR, fcr); /* set fcr */
1961 serial8250_set_mctrl(&up->port, up->port.mctrl);
1962 spin_unlock_irqrestore(&up->port.lock, flags);
1966 serial8250_pm(struct uart_port *port, unsigned int state,
1967 unsigned int oldstate)
1969 struct uart_8250_port *p = (struct uart_8250_port *)port;
1971 serial8250_set_sleep(p, state != 0);
1974 p->pm(port, state, oldstate);
1978 * Resource handling.
1980 static int serial8250_request_std_resource(struct uart_8250_port *up)
1982 unsigned int size = 8 << up->port.regshift;
1985 switch (up->port.iotype) {
1992 if (!up->port.mapbase)
1995 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2000 if (up->port.flags & UPF_IOREMAP) {
2001 up->port.membase = ioremap(up->port.mapbase, size);
2002 if (!up->port.membase) {
2003 release_mem_region(up->port.mapbase, size);
2011 if (!request_region(up->port.iobase, size, "serial"))
2018 static void serial8250_release_std_resource(struct uart_8250_port *up)
2020 unsigned int size = 8 << up->port.regshift;
2022 switch (up->port.iotype) {
2029 if (!up->port.mapbase)
2032 if (up->port.flags & UPF_IOREMAP) {
2033 iounmap(up->port.membase);
2034 up->port.membase = NULL;
2037 release_mem_region(up->port.mapbase, size);
2042 release_region(up->port.iobase, size);
2047 static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2049 unsigned long start = UART_RSA_BASE << up->port.regshift;
2050 unsigned int size = 8 << up->port.regshift;
2053 switch (up->port.iotype) {
2056 start += up->port.iobase;
2057 if (request_region(start, size, "serial-rsa"))
2067 static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2069 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2070 unsigned int size = 8 << up->port.regshift;
2072 switch (up->port.iotype) {
2075 release_region(up->port.iobase + offset, size);
2080 static void serial8250_release_port(struct uart_port *port)
2082 struct uart_8250_port *up = (struct uart_8250_port *)port;
2084 serial8250_release_std_resource(up);
2085 if (up->port.type == PORT_RSA)
2086 serial8250_release_rsa_resource(up);
2089 static int serial8250_request_port(struct uart_port *port)
2091 struct uart_8250_port *up = (struct uart_8250_port *)port;
2094 ret = serial8250_request_std_resource(up);
2095 if (ret == 0 && up->port.type == PORT_RSA) {
2096 ret = serial8250_request_rsa_resource(up);
2098 serial8250_release_std_resource(up);
2104 static void serial8250_config_port(struct uart_port *port, int flags)
2106 struct uart_8250_port *up = (struct uart_8250_port *)port;
2107 int probeflags = PROBE_ANY;
2111 * Find the region that we can probe for. This in turn
2112 * tells us whether we can probe for the type of port.
2114 ret = serial8250_request_std_resource(up);
2118 ret = serial8250_request_rsa_resource(up);
2120 probeflags &= ~PROBE_RSA;
2122 if (flags & UART_CONFIG_TYPE)
2123 autoconfig(up, probeflags);
2124 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2127 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2128 serial8250_release_rsa_resource(up);
2129 if (up->port.type == PORT_UNKNOWN)
2130 serial8250_release_std_resource(up);
2134 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2136 if (ser->irq >= NR_IRQS || ser->irq < 0 ||
2137 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2138 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2139 ser->type == PORT_STARTECH)
2145 serial8250_type(struct uart_port *port)
2147 int type = port->type;
2149 if (type >= ARRAY_SIZE(uart_config))
2151 return uart_config[type].name;
2154 static struct uart_ops serial8250_pops = {
2155 .tx_empty = serial8250_tx_empty,
2156 .set_mctrl = serial8250_set_mctrl,
2157 .get_mctrl = serial8250_get_mctrl,
2158 .stop_tx = serial8250_stop_tx,
2159 .start_tx = serial8250_start_tx,
2160 .stop_rx = serial8250_stop_rx,
2161 .enable_ms = serial8250_enable_ms,
2162 .break_ctl = serial8250_break_ctl,
2163 .startup = serial8250_startup,
2164 .shutdown = serial8250_shutdown,
2165 .set_termios = serial8250_set_termios,
2166 .pm = serial8250_pm,
2167 .type = serial8250_type,
2168 .release_port = serial8250_release_port,
2169 .request_port = serial8250_request_port,
2170 .config_port = serial8250_config_port,
2171 .verify_port = serial8250_verify_port,
2174 static struct uart_8250_port serial8250_ports[UART_NR];
2176 static void __init serial8250_isa_init_ports(void)
2178 struct uart_8250_port *up;
2179 static int first = 1;
2186 for (i = 0; i < nr_uarts; i++) {
2187 struct uart_8250_port *up = &serial8250_ports[i];
2190 spin_lock_init(&up->port.lock);
2192 init_timer(&up->timer);
2193 up->timer.function = serial8250_timeout;
2196 * ALPHA_KLUDGE_MCR needs to be killed.
2198 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2199 up->mcr_force = ALPHA_KLUDGE_MCR;
2201 up->port.ops = &serial8250_pops;
2204 for (i = 0, up = serial8250_ports;
2205 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2207 up->port.iobase = old_serial_port[i].port;
2208 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2209 up->port.uartclk = old_serial_port[i].baud_base * 16;
2210 up->port.flags = old_serial_port[i].flags;
2211 up->port.hub6 = old_serial_port[i].hub6;
2212 up->port.membase = old_serial_port[i].iomem_base;
2213 up->port.iotype = old_serial_port[i].io_type;
2214 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2216 up->port.flags |= UPF_SHARE_IRQ;
2221 serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2225 serial8250_isa_init_ports();
2227 for (i = 0; i < nr_uarts; i++) {
2228 struct uart_8250_port *up = &serial8250_ports[i];
2231 uart_add_one_port(drv, &up->port);
2235 #ifdef CONFIG_SERIAL_8250_CONSOLE
2237 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
2240 * Wait for transmitter & holding register to empty
2242 static inline void wait_for_xmitr(struct uart_8250_port *up, int bits)
2244 unsigned int status, tmout = 10000;
2246 /* Wait up to 10ms for the character(s) to be sent. */
2248 status = serial_in(up, UART_LSR);
2250 if (status & UART_LSR_BI)
2251 up->lsr_break_flag = UART_LSR_BI;
2256 } while ((status & bits) != bits);
2258 /* Wait up to 1s for flow control if necessary */
2259 if (up->port.flags & UPF_CONS_FLOW) {
2261 while (!(serial_in(up, UART_MSR) & UART_MSR_CTS) && --tmout) {
2263 touch_nmi_watchdog();
2268 static void serial8250_console_putchar(struct uart_port *port, int ch)
2270 struct uart_8250_port *up = (struct uart_8250_port *)port;
2272 wait_for_xmitr(up, UART_LSR_THRE);
2273 serial_out(up, UART_TX, ch);
2277 * Print a string to the serial port trying not to disturb
2278 * any possible real use of the port...
2280 * The console_lock must be held when we get here.
2283 serial8250_console_write(struct console *co, const char *s, unsigned int count)
2285 struct uart_8250_port *up = &serial8250_ports[co->index];
2286 unsigned long flags;
2290 touch_nmi_watchdog();
2292 local_irq_save(flags);
2293 if (up->port.sysrq) {
2294 /* serial8250_handle_port() already took the lock */
2296 } else if (oops_in_progress) {
2297 locked = spin_trylock(&up->port.lock);
2299 spin_lock(&up->port.lock);
2302 * First save the IER then disable the interrupts
2304 ier = serial_in(up, UART_IER);
2306 if (up->capabilities & UART_CAP_UUE)
2307 serial_out(up, UART_IER, UART_IER_UUE);
2309 serial_out(up, UART_IER, 0);
2311 uart_console_write(&up->port, s, count, serial8250_console_putchar);
2314 * Finally, wait for transmitter to become empty
2315 * and restore the IER
2317 wait_for_xmitr(up, BOTH_EMPTY);
2318 serial_out(up, UART_IER, ier);
2321 spin_unlock(&up->port.lock);
2322 local_irq_restore(flags);
2325 static int __init serial8250_console_setup(struct console *co, char *options)
2327 struct uart_port *port;
2334 * Check whether an invalid uart number has been specified, and
2335 * if so, search for the first available port that does have
2338 if (co->index >= nr_uarts)
2340 port = &serial8250_ports[co->index].port;
2341 if (!port->iobase && !port->membase)
2345 uart_parse_options(options, &baud, &parity, &bits, &flow);
2347 return uart_set_options(port, co, baud, parity, bits, flow);
2350 static struct uart_driver serial8250_reg;
2351 static struct console serial8250_console = {
2353 .write = serial8250_console_write,
2354 .device = uart_console_device,
2355 .setup = serial8250_console_setup,
2356 .flags = CON_PRINTBUFFER,
2358 .data = &serial8250_reg,
2361 static int __init serial8250_console_init(void)
2363 serial8250_isa_init_ports();
2364 register_console(&serial8250_console);
2367 console_initcall(serial8250_console_init);
2369 static int __init find_port(struct uart_port *p)
2372 struct uart_port *port;
2374 for (line = 0; line < nr_uarts; line++) {
2375 port = &serial8250_ports[line].port;
2376 if (uart_match_port(p, port))
2382 int __init serial8250_start_console(struct uart_port *port, char *options)
2386 line = find_port(port);
2390 add_preferred_console("ttyS", line, options);
2391 printk("Adding console on ttyS%d at %s 0x%lx (options '%s')\n",
2392 line, port->iotype == UPIO_MEM ? "MMIO" : "I/O port",
2393 port->iotype == UPIO_MEM ? (unsigned long) port->mapbase :
2394 (unsigned long) port->iobase, options);
2395 if (!(serial8250_console.flags & CON_ENABLED)) {
2396 serial8250_console.flags &= ~CON_PRINTBUFFER;
2397 register_console(&serial8250_console);
2402 #define SERIAL8250_CONSOLE &serial8250_console
2404 #define SERIAL8250_CONSOLE NULL
2407 static struct uart_driver serial8250_reg = {
2408 .owner = THIS_MODULE,
2409 .driver_name = "serial",
2414 .cons = SERIAL8250_CONSOLE,
2418 * early_serial_setup - early registration for 8250 ports
2420 * Setup an 8250 port structure prior to console initialisation. Use
2421 * after console initialisation will cause undefined behaviour.
2423 int __init early_serial_setup(struct uart_port *port)
2425 if (port->line >= ARRAY_SIZE(serial8250_ports))
2428 serial8250_isa_init_ports();
2429 serial8250_ports[port->line].port = *port;
2430 serial8250_ports[port->line].port.ops = &serial8250_pops;
2435 * serial8250_suspend_port - suspend one serial port
2436 * @line: serial line number
2438 * Suspend one serial port.
2440 void serial8250_suspend_port(int line)
2442 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2446 * serial8250_resume_port - resume one serial port
2447 * @line: serial line number
2449 * Resume one serial port.
2451 void serial8250_resume_port(int line)
2453 uart_resume_port(&serial8250_reg, &serial8250_ports[line].port);
2457 * Register a set of serial devices attached to a platform device. The
2458 * list is terminated with a zero flags entry, which means we expect
2459 * all entries to have at least UPF_BOOT_AUTOCONF set.
2461 static int __devinit serial8250_probe(struct platform_device *dev)
2463 struct plat_serial8250_port *p = dev->dev.platform_data;
2464 struct uart_port port;
2467 memset(&port, 0, sizeof(struct uart_port));
2469 for (i = 0; p && p->flags != 0; p++, i++) {
2470 port.iobase = p->iobase;
2471 port.membase = p->membase;
2473 port.uartclk = p->uartclk;
2474 port.regshift = p->regshift;
2475 port.iotype = p->iotype;
2476 port.flags = p->flags;
2477 port.mapbase = p->mapbase;
2478 port.hub6 = p->hub6;
2479 port.dev = &dev->dev;
2481 port.flags |= UPF_SHARE_IRQ;
2482 ret = serial8250_register_port(&port);
2484 dev_err(&dev->dev, "unable to register port at index %d "
2485 "(IO%lx MEM%lx IRQ%d): %d\n", i,
2486 p->iobase, p->mapbase, p->irq, ret);
2493 * Remove serial ports registered against a platform device.
2495 static int __devexit serial8250_remove(struct platform_device *dev)
2499 for (i = 0; i < nr_uarts; i++) {
2500 struct uart_8250_port *up = &serial8250_ports[i];
2502 if (up->port.dev == &dev->dev)
2503 serial8250_unregister_port(i);
2508 static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
2512 for (i = 0; i < UART_NR; i++) {
2513 struct uart_8250_port *up = &serial8250_ports[i];
2515 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
2516 uart_suspend_port(&serial8250_reg, &up->port);
2522 static int serial8250_resume(struct platform_device *dev)
2526 for (i = 0; i < UART_NR; i++) {
2527 struct uart_8250_port *up = &serial8250_ports[i];
2529 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
2530 uart_resume_port(&serial8250_reg, &up->port);
2536 static struct platform_driver serial8250_isa_driver = {
2537 .probe = serial8250_probe,
2538 .remove = __devexit_p(serial8250_remove),
2539 .suspend = serial8250_suspend,
2540 .resume = serial8250_resume,
2542 .name = "serial8250",
2543 .owner = THIS_MODULE,
2548 * This "device" covers _all_ ISA 8250-compatible serial devices listed
2549 * in the table in include/asm/serial.h
2551 static struct platform_device *serial8250_isa_devs;
2554 * serial8250_register_port and serial8250_unregister_port allows for
2555 * 16x50 serial ports to be configured at run-time, to support PCMCIA
2556 * modems and PCI multiport cards.
2558 static DEFINE_MUTEX(serial_mutex);
2560 static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
2565 * First, find a port entry which matches.
2567 for (i = 0; i < nr_uarts; i++)
2568 if (uart_match_port(&serial8250_ports[i].port, port))
2569 return &serial8250_ports[i];
2572 * We didn't find a matching entry, so look for the first
2573 * free entry. We look for one which hasn't been previously
2574 * used (indicated by zero iobase).
2576 for (i = 0; i < nr_uarts; i++)
2577 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
2578 serial8250_ports[i].port.iobase == 0)
2579 return &serial8250_ports[i];
2582 * That also failed. Last resort is to find any entry which
2583 * doesn't have a real port associated with it.
2585 for (i = 0; i < nr_uarts; i++)
2586 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
2587 return &serial8250_ports[i];
2593 * serial8250_register_port - register a serial port
2594 * @port: serial port template
2596 * Configure the serial port specified by the request. If the
2597 * port exists and is in use, it is hung up and unregistered
2600 * The port is then probed and if necessary the IRQ is autodetected
2601 * If this fails an error is returned.
2603 * On success the port is ready to use and the line number is returned.
2605 int serial8250_register_port(struct uart_port *port)
2607 struct uart_8250_port *uart;
2610 if (port->uartclk == 0)
2613 mutex_lock(&serial_mutex);
2615 uart = serial8250_find_match_or_unused(port);
2617 uart_remove_one_port(&serial8250_reg, &uart->port);
2619 uart->port.iobase = port->iobase;
2620 uart->port.membase = port->membase;
2621 uart->port.irq = port->irq;
2622 uart->port.uartclk = port->uartclk;
2623 uart->port.fifosize = port->fifosize;
2624 uart->port.regshift = port->regshift;
2625 uart->port.iotype = port->iotype;
2626 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
2627 uart->port.mapbase = port->mapbase;
2629 uart->port.dev = port->dev;
2631 ret = uart_add_one_port(&serial8250_reg, &uart->port);
2633 ret = uart->port.line;
2635 mutex_unlock(&serial_mutex);
2639 EXPORT_SYMBOL(serial8250_register_port);
2642 * serial8250_unregister_port - remove a 16x50 serial port at runtime
2643 * @line: serial line number
2645 * Remove one serial port. This may not be called from interrupt
2646 * context. We hand the port back to the our control.
2648 void serial8250_unregister_port(int line)
2650 struct uart_8250_port *uart = &serial8250_ports[line];
2652 mutex_lock(&serial_mutex);
2653 uart_remove_one_port(&serial8250_reg, &uart->port);
2654 if (serial8250_isa_devs) {
2655 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
2656 uart->port.type = PORT_UNKNOWN;
2657 uart->port.dev = &serial8250_isa_devs->dev;
2658 uart_add_one_port(&serial8250_reg, &uart->port);
2660 uart->port.dev = NULL;
2662 mutex_unlock(&serial_mutex);
2664 EXPORT_SYMBOL(serial8250_unregister_port);
2666 static int __init serial8250_init(void)
2670 if (nr_uarts > UART_NR)
2673 printk(KERN_INFO "Serial: 8250/16550 driver $Revision: 1.90 $ "
2674 "%d ports, IRQ sharing %sabled\n", nr_uarts,
2675 share_irqs ? "en" : "dis");
2677 for (i = 0; i < NR_IRQS; i++)
2678 spin_lock_init(&irq_lists[i].lock);
2680 ret = uart_register_driver(&serial8250_reg);
2684 serial8250_isa_devs = platform_device_alloc("serial8250",
2685 PLAT8250_DEV_LEGACY);
2686 if (!serial8250_isa_devs) {
2688 goto unreg_uart_drv;
2691 ret = platform_device_add(serial8250_isa_devs);
2695 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
2697 ret = platform_driver_register(&serial8250_isa_driver);
2701 platform_device_del(serial8250_isa_devs);
2703 platform_device_put(serial8250_isa_devs);
2705 uart_unregister_driver(&serial8250_reg);
2710 static void __exit serial8250_exit(void)
2712 struct platform_device *isa_dev = serial8250_isa_devs;
2715 * This tells serial8250_unregister_port() not to re-register
2716 * the ports (thereby making serial8250_isa_driver permanently
2719 serial8250_isa_devs = NULL;
2721 platform_driver_unregister(&serial8250_isa_driver);
2722 platform_device_unregister(isa_dev);
2724 uart_unregister_driver(&serial8250_reg);
2727 module_init(serial8250_init);
2728 module_exit(serial8250_exit);
2730 EXPORT_SYMBOL(serial8250_suspend_port);
2731 EXPORT_SYMBOL(serial8250_resume_port);
2733 MODULE_LICENSE("GPL");
2734 MODULE_DESCRIPTION("Generic 8250/16x50 serial driver $Revision: 1.90 $");
2736 module_param(share_irqs, uint, 0644);
2737 MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
2740 module_param(nr_uarts, uint, 0644);
2741 MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
2743 #ifdef CONFIG_SERIAL_8250_RSA
2744 module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
2745 MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
2747 MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);