2 * linux/drivers/char/8250.c
4 * Driver for 8250/16550-type serial ports
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 * Copyright (C) 2001 Russell King.
10 * 2005/09/16: Enabled higher baud rates for 16C95x.
11 * (Mathias Adam <a2@adamis.de>)
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
18 * $Id: 8250.c,v 1.90 2002/07/28 10:03:27 rmk Exp $
20 * A note about mapbase / membase
22 * mapbase is the physical address of the IO port.
23 * membase is an 'ioremapped' cookie.
25 #include <linux/config.h>
27 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
31 #include <linux/module.h>
32 #include <linux/moduleparam.h>
33 #include <linux/ioport.h>
34 #include <linux/init.h>
35 #include <linux/console.h>
36 #include <linux/sysrq.h>
37 #include <linux/delay.h>
38 #include <linux/platform_device.h>
39 #include <linux/tty.h>
40 #include <linux/tty_flip.h>
41 #include <linux/serial_reg.h>
42 #include <linux/serial_core.h>
43 #include <linux/serial.h>
44 #include <linux/serial_8250.h>
45 #include <linux/nmi.h>
46 #include <linux/mutex.h>
55 * share_irqs - whether we pass SA_SHIRQ to request_irq(). This option
56 * is unsafe when used on edge-triggered interrupts.
58 static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
60 static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
66 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
68 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
72 #define DEBUG_INTR(fmt...) printk(fmt)
74 #define DEBUG_INTR(fmt...) do { } while (0)
77 #define PASS_LIMIT 256
80 * We default to IRQ0 for the "no irq" hack. Some
81 * machine types want others as well - they're free
82 * to redefine this in their header file.
84 #define is_real_interrupt(irq) ((irq) != 0)
86 #ifdef CONFIG_SERIAL_8250_DETECT_IRQ
87 #define CONFIG_SERIAL_DETECT_IRQ 1
89 #ifdef CONFIG_SERIAL_8250_MANY_PORTS
90 #define CONFIG_SERIAL_MANY_PORTS 1
94 * HUB6 is always on. This will be removed once the header
95 * files have been cleaned.
99 #include <asm/serial.h>
102 * SERIAL_PORT_DFNS tells us about built-in ports that have no
103 * standard enumeration mechanism. Platforms that can find all
104 * serial ports via mechanisms like ACPI or PCI need not supply it.
106 #ifndef SERIAL_PORT_DFNS
107 #define SERIAL_PORT_DFNS
110 static const struct old_serial_port old_serial_port[] = {
111 SERIAL_PORT_DFNS /* defined in asm/serial.h */
114 #define UART_NR CONFIG_SERIAL_8250_NR_UARTS
116 #ifdef CONFIG_SERIAL_8250_RSA
118 #define PORT_RSA_MAX 4
119 static unsigned long probe_rsa[PORT_RSA_MAX];
120 static unsigned int probe_rsa_count;
121 #endif /* CONFIG_SERIAL_8250_RSA */
123 struct uart_8250_port {
124 struct uart_port port;
125 struct timer_list timer; /* "no irq" timer */
126 struct list_head list; /* ports on this IRQ */
127 unsigned short capabilities; /* port capabilities */
128 unsigned short bugs; /* port bugs */
129 unsigned int tx_loadsz; /* transmit fifo load size */
134 unsigned char mcr_mask; /* mask of user bits */
135 unsigned char mcr_force; /* mask of forced bits */
136 unsigned char lsr_break_flag;
139 * We provide a per-port pm hook.
141 void (*pm)(struct uart_port *port,
142 unsigned int state, unsigned int old);
147 struct list_head *head;
150 static struct irq_info irq_lists[NR_IRQS];
153 * Here we define the default xmit fifo size used for each type of UART.
155 static const struct serial8250_config uart_config[] = {
180 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
181 .flags = UART_CAP_FIFO,
192 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
198 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
200 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
206 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
208 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
216 .name = "16C950/954",
219 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
220 .flags = UART_CAP_FIFO,
226 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
228 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
234 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
235 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
241 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
242 .flags = UART_CAP_FIFO,
248 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
249 .flags = UART_CAP_FIFO | UART_NATSEMI,
255 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
256 .flags = UART_CAP_FIFO | UART_CAP_UUE,
260 #ifdef CONFIG_SERIAL_8250_AU1X00
262 /* Au1x00 UART hardware has a weird register layout */
263 static const u8 au_io_in_map[] = {
273 static const u8 au_io_out_map[] = {
281 /* sane hardware needs no mapping */
282 static inline int map_8250_in_reg(struct uart_8250_port *up, int offset)
284 if (up->port.iotype != UPIO_AU)
286 return au_io_in_map[offset];
289 static inline int map_8250_out_reg(struct uart_8250_port *up, int offset)
291 if (up->port.iotype != UPIO_AU)
293 return au_io_out_map[offset];
298 /* sane hardware needs no mapping */
299 #define map_8250_in_reg(up, offset) (offset)
300 #define map_8250_out_reg(up, offset) (offset)
304 static unsigned int serial_in(struct uart_8250_port *up, int offset)
306 offset = map_8250_in_reg(up, offset) << up->port.regshift;
308 switch (up->port.iotype) {
310 outb(up->port.hub6 - 1 + offset, up->port.iobase);
311 return inb(up->port.iobase + 1);
314 return readb(up->port.membase + offset);
317 return readl(up->port.membase + offset);
319 #ifdef CONFIG_SERIAL_8250_AU1X00
321 return __raw_readl(up->port.membase + offset);
325 return inb(up->port.iobase + offset);
330 serial_out(struct uart_8250_port *up, int offset, int value)
332 offset = map_8250_out_reg(up, offset) << up->port.regshift;
334 switch (up->port.iotype) {
336 outb(up->port.hub6 - 1 + offset, up->port.iobase);
337 outb(value, up->port.iobase + 1);
341 writeb(value, up->port.membase + offset);
345 writel(value, up->port.membase + offset);
348 #ifdef CONFIG_SERIAL_8250_AU1X00
350 __raw_writel(value, up->port.membase + offset);
355 outb(value, up->port.iobase + offset);
360 * We used to support using pause I/O for certain machines. We
361 * haven't supported this for a while, but just in case it's badly
362 * needed for certain old 386 machines, I've left these #define's
365 #define serial_inp(up, offset) serial_in(up, offset)
366 #define serial_outp(up, offset, value) serial_out(up, offset, value)
368 /* Uart divisor latch read */
369 static inline int _serial_dl_read(struct uart_8250_port *up)
371 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
374 /* Uart divisor latch write */
375 static inline void _serial_dl_write(struct uart_8250_port *up, int value)
377 serial_outp(up, UART_DLL, value & 0xff);
378 serial_outp(up, UART_DLM, value >> 8 & 0xff);
381 #ifdef CONFIG_SERIAL_8250_AU1X00
382 /* Au1x00 haven't got a standard divisor latch */
383 static int serial_dl_read(struct uart_8250_port *up)
385 if (up->port.iotype == UPIO_AU)
386 return __raw_readl(up->port.membase + 0x28);
388 return _serial_dl_read(up);
391 static void serial_dl_write(struct uart_8250_port *up, int value)
393 if (up->port.iotype == UPIO_AU)
394 __raw_writel(value, up->port.membase + 0x28);
396 _serial_dl_write(up, value);
399 #define serial_dl_read(up) _serial_dl_read(up)
400 #define serial_dl_write(up, value) _serial_dl_write(up, value)
406 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
408 serial_out(up, UART_SCR, offset);
409 serial_out(up, UART_ICR, value);
412 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
416 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
417 serial_out(up, UART_SCR, offset);
418 value = serial_in(up, UART_ICR);
419 serial_icr_write(up, UART_ACR, up->acr);
427 static inline void serial8250_clear_fifos(struct uart_8250_port *p)
429 if (p->capabilities & UART_CAP_FIFO) {
430 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
431 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
432 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
433 serial_outp(p, UART_FCR, 0);
438 * IER sleep support. UARTs which have EFRs need the "extended
439 * capability" bit enabled. Note that on XR16C850s, we need to
440 * reset LCR to write to IER.
442 static inline void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
444 if (p->capabilities & UART_CAP_SLEEP) {
445 if (p->capabilities & UART_CAP_EFR) {
446 serial_outp(p, UART_LCR, 0xBF);
447 serial_outp(p, UART_EFR, UART_EFR_ECB);
448 serial_outp(p, UART_LCR, 0);
450 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
451 if (p->capabilities & UART_CAP_EFR) {
452 serial_outp(p, UART_LCR, 0xBF);
453 serial_outp(p, UART_EFR, 0);
454 serial_outp(p, UART_LCR, 0);
459 #ifdef CONFIG_SERIAL_8250_RSA
461 * Attempts to turn on the RSA FIFO. Returns zero on failure.
462 * We set the port uart clock rate if we succeed.
464 static int __enable_rsa(struct uart_8250_port *up)
469 mode = serial_inp(up, UART_RSA_MSR);
470 result = mode & UART_RSA_MSR_FIFO;
473 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
474 mode = serial_inp(up, UART_RSA_MSR);
475 result = mode & UART_RSA_MSR_FIFO;
479 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
484 static void enable_rsa(struct uart_8250_port *up)
486 if (up->port.type == PORT_RSA) {
487 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
488 spin_lock_irq(&up->port.lock);
490 spin_unlock_irq(&up->port.lock);
492 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
493 serial_outp(up, UART_RSA_FRR, 0);
498 * Attempts to turn off the RSA FIFO. Returns zero on failure.
499 * It is unknown why interrupts were disabled in here. However,
500 * the caller is expected to preserve this behaviour by grabbing
501 * the spinlock before calling this function.
503 static void disable_rsa(struct uart_8250_port *up)
508 if (up->port.type == PORT_RSA &&
509 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
510 spin_lock_irq(&up->port.lock);
512 mode = serial_inp(up, UART_RSA_MSR);
513 result = !(mode & UART_RSA_MSR_FIFO);
516 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
517 mode = serial_inp(up, UART_RSA_MSR);
518 result = !(mode & UART_RSA_MSR_FIFO);
522 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
523 spin_unlock_irq(&up->port.lock);
526 #endif /* CONFIG_SERIAL_8250_RSA */
529 * This is a quickie test to see how big the FIFO is.
530 * It doesn't work at all the time, more's the pity.
532 static int size_fifo(struct uart_8250_port *up)
534 unsigned char old_fcr, old_mcr, old_lcr;
535 unsigned short old_dl;
538 old_lcr = serial_inp(up, UART_LCR);
539 serial_outp(up, UART_LCR, 0);
540 old_fcr = serial_inp(up, UART_FCR);
541 old_mcr = serial_inp(up, UART_MCR);
542 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
543 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
544 serial_outp(up, UART_MCR, UART_MCR_LOOP);
545 serial_outp(up, UART_LCR, UART_LCR_DLAB);
546 old_dl = serial_dl_read(up);
547 serial_dl_write(up, 0x0001);
548 serial_outp(up, UART_LCR, 0x03);
549 for (count = 0; count < 256; count++)
550 serial_outp(up, UART_TX, count);
551 mdelay(20);/* FIXME - schedule_timeout */
552 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
553 (count < 256); count++)
554 serial_inp(up, UART_RX);
555 serial_outp(up, UART_FCR, old_fcr);
556 serial_outp(up, UART_MCR, old_mcr);
557 serial_outp(up, UART_LCR, UART_LCR_DLAB);
558 serial_dl_write(up, old_dl);
559 serial_outp(up, UART_LCR, old_lcr);
565 * Read UART ID using the divisor method - set DLL and DLM to zero
566 * and the revision will be in DLL and device type in DLM. We
567 * preserve the device state across this.
569 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
571 unsigned char old_dll, old_dlm, old_lcr;
574 old_lcr = serial_inp(p, UART_LCR);
575 serial_outp(p, UART_LCR, UART_LCR_DLAB);
577 old_dll = serial_inp(p, UART_DLL);
578 old_dlm = serial_inp(p, UART_DLM);
580 serial_outp(p, UART_DLL, 0);
581 serial_outp(p, UART_DLM, 0);
583 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
585 serial_outp(p, UART_DLL, old_dll);
586 serial_outp(p, UART_DLM, old_dlm);
587 serial_outp(p, UART_LCR, old_lcr);
593 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
594 * When this function is called we know it is at least a StarTech
595 * 16650 V2, but it might be one of several StarTech UARTs, or one of
596 * its clones. (We treat the broken original StarTech 16650 V1 as a
597 * 16550, and why not? Startech doesn't seem to even acknowledge its
600 * What evil have men's minds wrought...
602 static void autoconfig_has_efr(struct uart_8250_port *up)
604 unsigned int id1, id2, id3, rev;
607 * Everything with an EFR has SLEEP
609 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
612 * First we check to see if it's an Oxford Semiconductor UART.
614 * If we have to do this here because some non-National
615 * Semiconductor clone chips lock up if you try writing to the
616 * LSR register (which serial_icr_read does)
620 * Check for Oxford Semiconductor 16C950.
622 * EFR [4] must be set else this test fails.
624 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
625 * claims that it's needed for 952 dual UART's (which are not
626 * recommended for new designs).
629 serial_out(up, UART_LCR, 0xBF);
630 serial_out(up, UART_EFR, UART_EFR_ECB);
631 serial_out(up, UART_LCR, 0x00);
632 id1 = serial_icr_read(up, UART_ID1);
633 id2 = serial_icr_read(up, UART_ID2);
634 id3 = serial_icr_read(up, UART_ID3);
635 rev = serial_icr_read(up, UART_REV);
637 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
639 if (id1 == 0x16 && id2 == 0xC9 &&
640 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
641 up->port.type = PORT_16C950;
644 * Enable work around for the Oxford Semiconductor 952 rev B
645 * chip which causes it to seriously miscalculate baud rates
648 if (id3 == 0x52 && rev == 0x01)
649 up->bugs |= UART_BUG_QUOT;
654 * We check for a XR16C850 by setting DLL and DLM to 0, and then
655 * reading back DLL and DLM. The chip type depends on the DLM
657 * 0x10 - XR16C850 and the DLL contains the chip revision.
661 id1 = autoconfig_read_divisor_id(up);
662 DEBUG_AUTOCONF("850id=%04x ", id1);
665 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
666 up->port.type = PORT_16850;
671 * It wasn't an XR16C850.
673 * We distinguish between the '654 and the '650 by counting
674 * how many bytes are in the FIFO. I'm using this for now,
675 * since that's the technique that was sent to me in the
676 * serial driver update, but I'm not convinced this works.
677 * I've had problems doing this in the past. -TYT
679 if (size_fifo(up) == 64)
680 up->port.type = PORT_16654;
682 up->port.type = PORT_16650V2;
686 * We detected a chip without a FIFO. Only two fall into
687 * this category - the original 8250 and the 16450. The
688 * 16450 has a scratch register (accessible with LCR=0)
690 static void autoconfig_8250(struct uart_8250_port *up)
692 unsigned char scratch, status1, status2;
694 up->port.type = PORT_8250;
696 scratch = serial_in(up, UART_SCR);
697 serial_outp(up, UART_SCR, 0xa5);
698 status1 = serial_in(up, UART_SCR);
699 serial_outp(up, UART_SCR, 0x5a);
700 status2 = serial_in(up, UART_SCR);
701 serial_outp(up, UART_SCR, scratch);
703 if (status1 == 0xa5 && status2 == 0x5a)
704 up->port.type = PORT_16450;
707 static int broken_efr(struct uart_8250_port *up)
710 * Exar ST16C2550 "A2" devices incorrectly detect as
711 * having an EFR, and report an ID of 0x0201. See
712 * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf
714 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
721 * We know that the chip has FIFOs. Does it have an EFR? The
722 * EFR is located in the same register position as the IIR and
723 * we know the top two bits of the IIR are currently set. The
724 * EFR should contain zero. Try to read the EFR.
726 static void autoconfig_16550a(struct uart_8250_port *up)
728 unsigned char status1, status2;
729 unsigned int iersave;
731 up->port.type = PORT_16550A;
732 up->capabilities |= UART_CAP_FIFO;
735 * Check for presence of the EFR when DLAB is set.
736 * Only ST16C650V1 UARTs pass this test.
738 serial_outp(up, UART_LCR, UART_LCR_DLAB);
739 if (serial_in(up, UART_EFR) == 0) {
740 serial_outp(up, UART_EFR, 0xA8);
741 if (serial_in(up, UART_EFR) != 0) {
742 DEBUG_AUTOCONF("EFRv1 ");
743 up->port.type = PORT_16650;
744 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
746 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
748 serial_outp(up, UART_EFR, 0);
753 * Maybe it requires 0xbf to be written to the LCR.
754 * (other ST16C650V2 UARTs, TI16C752A, etc)
756 serial_outp(up, UART_LCR, 0xBF);
757 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
758 DEBUG_AUTOCONF("EFRv2 ");
759 autoconfig_has_efr(up);
764 * Check for a National Semiconductor SuperIO chip.
765 * Attempt to switch to bank 2, read the value of the LOOP bit
766 * from EXCR1. Switch back to bank 0, change it in MCR. Then
767 * switch back to bank 2, read it from EXCR1 again and check
768 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
770 serial_outp(up, UART_LCR, 0);
771 status1 = serial_in(up, UART_MCR);
772 serial_outp(up, UART_LCR, 0xE0);
773 status2 = serial_in(up, 0x02); /* EXCR1 */
775 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
776 serial_outp(up, UART_LCR, 0);
777 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
778 serial_outp(up, UART_LCR, 0xE0);
779 status2 = serial_in(up, 0x02); /* EXCR1 */
780 serial_outp(up, UART_LCR, 0);
781 serial_outp(up, UART_MCR, status1);
783 if ((status2 ^ status1) & UART_MCR_LOOP) {
786 serial_outp(up, UART_LCR, 0xE0);
788 quot = serial_dl_read(up);
791 status1 = serial_in(up, 0x04); /* EXCR1 */
792 status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
793 status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
794 serial_outp(up, 0x04, status1);
796 serial_dl_write(up, quot);
798 serial_outp(up, UART_LCR, 0);
800 up->port.uartclk = 921600*16;
801 up->port.type = PORT_NS16550A;
802 up->capabilities |= UART_NATSEMI;
808 * No EFR. Try to detect a TI16750, which only sets bit 5 of
809 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
810 * Try setting it with and without DLAB set. Cheap clones
811 * set bit 5 without DLAB set.
813 serial_outp(up, UART_LCR, 0);
814 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
815 status1 = serial_in(up, UART_IIR) >> 5;
816 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
817 serial_outp(up, UART_LCR, UART_LCR_DLAB);
818 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
819 status2 = serial_in(up, UART_IIR) >> 5;
820 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
821 serial_outp(up, UART_LCR, 0);
823 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
825 if (status1 == 6 && status2 == 7) {
826 up->port.type = PORT_16750;
827 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
832 * Try writing and reading the UART_IER_UUE bit (b6).
833 * If it works, this is probably one of the Xscale platform's
835 * We're going to explicitly set the UUE bit to 0 before
836 * trying to write and read a 1 just to make sure it's not
837 * already a 1 and maybe locked there before we even start start.
839 iersave = serial_in(up, UART_IER);
840 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
841 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
843 * OK it's in a known zero state, try writing and reading
844 * without disturbing the current state of the other bits.
846 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
847 if (serial_in(up, UART_IER) & UART_IER_UUE) {
850 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
852 DEBUG_AUTOCONF("Xscale ");
853 up->port.type = PORT_XSCALE;
854 up->capabilities |= UART_CAP_UUE;
859 * If we got here we couldn't force the IER_UUE bit to 0.
860 * Log it and continue.
862 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
864 serial_outp(up, UART_IER, iersave);
868 * This routine is called by rs_init() to initialize a specific serial
869 * port. It determines what type of UART chip this serial port is
870 * using: 8250, 16450, 16550, 16550A. The important question is
871 * whether or not this UART is a 16550A or not, since this will
872 * determine whether or not we can use its FIFO features or not.
874 static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
876 unsigned char status1, scratch, scratch2, scratch3;
877 unsigned char save_lcr, save_mcr;
880 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
883 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04x, 0x%p): ",
884 up->port.line, up->port.iobase, up->port.membase);
887 * We really do need global IRQs disabled here - we're going to
888 * be frobbing the chips IRQ enable register to see if it exists.
890 spin_lock_irqsave(&up->port.lock, flags);
891 // save_flags(flags); cli();
893 up->capabilities = 0;
896 if (!(up->port.flags & UPF_BUGGY_UART)) {
898 * Do a simple existence test first; if we fail this,
899 * there's no point trying anything else.
901 * 0x80 is used as a nonsense port to prevent against
902 * false positives due to ISA bus float. The
903 * assumption is that 0x80 is a non-existent port;
904 * which should be safe since include/asm/io.h also
905 * makes this assumption.
907 * Note: this is safe as long as MCR bit 4 is clear
908 * and the device is in "PC" mode.
910 scratch = serial_inp(up, UART_IER);
911 serial_outp(up, UART_IER, 0);
915 scratch2 = serial_inp(up, UART_IER);
916 serial_outp(up, UART_IER, 0x0F);
920 scratch3 = serial_inp(up, UART_IER);
921 serial_outp(up, UART_IER, scratch);
922 if (scratch2 != 0 || scratch3 != 0x0F) {
924 * We failed; there's nothing here
926 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
932 save_mcr = serial_in(up, UART_MCR);
933 save_lcr = serial_in(up, UART_LCR);
936 * Check to see if a UART is really there. Certain broken
937 * internal modems based on the Rockwell chipset fail this
938 * test, because they apparently don't implement the loopback
939 * test mode. So this test is skipped on the COM 1 through
940 * COM 4 ports. This *should* be safe, since no board
941 * manufacturer would be stupid enough to design a board
942 * that conflicts with COM 1-4 --- we hope!
944 if (!(up->port.flags & UPF_SKIP_TEST)) {
945 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
946 status1 = serial_inp(up, UART_MSR) & 0xF0;
947 serial_outp(up, UART_MCR, save_mcr);
948 if (status1 != 0x90) {
949 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
956 * We're pretty sure there's a port here. Lets find out what
957 * type of port it is. The IIR top two bits allows us to find
958 * out if it's 8250 or 16450, 16550, 16550A or later. This
959 * determines what we test for next.
961 * We also initialise the EFR (if any) to zero for later. The
962 * EFR occupies the same register location as the FCR and IIR.
964 serial_outp(up, UART_LCR, 0xBF);
965 serial_outp(up, UART_EFR, 0);
966 serial_outp(up, UART_LCR, 0);
968 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
969 scratch = serial_in(up, UART_IIR) >> 6;
971 DEBUG_AUTOCONF("iir=%d ", scratch);
978 up->port.type = PORT_UNKNOWN;
981 up->port.type = PORT_16550;
984 autoconfig_16550a(up);
988 #ifdef CONFIG_SERIAL_8250_RSA
990 * Only probe for RSA ports if we got the region.
992 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
995 for (i = 0 ; i < probe_rsa_count; ++i) {
996 if (probe_rsa[i] == up->port.iobase &&
998 up->port.type = PORT_RSA;
1005 #ifdef CONFIG_SERIAL_8250_AU1X00
1006 /* if access method is AU, it is a 16550 with a quirk */
1007 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
1008 up->bugs |= UART_BUG_NOMSR;
1011 serial_outp(up, UART_LCR, save_lcr);
1013 if (up->capabilities != uart_config[up->port.type].flags) {
1015 "ttyS%d: detected caps %08x should be %08x\n",
1016 up->port.line, up->capabilities,
1017 uart_config[up->port.type].flags);
1020 up->port.fifosize = uart_config[up->port.type].fifo_size;
1021 up->capabilities = uart_config[up->port.type].flags;
1022 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1024 if (up->port.type == PORT_UNKNOWN)
1030 #ifdef CONFIG_SERIAL_8250_RSA
1031 if (up->port.type == PORT_RSA)
1032 serial_outp(up, UART_RSA_FRR, 0);
1034 serial_outp(up, UART_MCR, save_mcr);
1035 serial8250_clear_fifos(up);
1036 (void)serial_in(up, UART_RX);
1037 if (up->capabilities & UART_CAP_UUE)
1038 serial_outp(up, UART_IER, UART_IER_UUE);
1040 serial_outp(up, UART_IER, 0);
1043 spin_unlock_irqrestore(&up->port.lock, flags);
1044 // restore_flags(flags);
1045 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1048 static void autoconfig_irq(struct uart_8250_port *up)
1050 unsigned char save_mcr, save_ier;
1051 unsigned char save_ICP = 0;
1052 unsigned int ICP = 0;
1056 if (up->port.flags & UPF_FOURPORT) {
1057 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1058 save_ICP = inb_p(ICP);
1063 /* forget possible initially masked and pending IRQ */
1064 probe_irq_off(probe_irq_on());
1065 save_mcr = serial_inp(up, UART_MCR);
1066 save_ier = serial_inp(up, UART_IER);
1067 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1069 irqs = probe_irq_on();
1070 serial_outp(up, UART_MCR, 0);
1072 if (up->port.flags & UPF_FOURPORT) {
1073 serial_outp(up, UART_MCR,
1074 UART_MCR_DTR | UART_MCR_RTS);
1076 serial_outp(up, UART_MCR,
1077 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1079 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1080 (void)serial_inp(up, UART_LSR);
1081 (void)serial_inp(up, UART_RX);
1082 (void)serial_inp(up, UART_IIR);
1083 (void)serial_inp(up, UART_MSR);
1084 serial_outp(up, UART_TX, 0xFF);
1086 irq = probe_irq_off(irqs);
1088 serial_outp(up, UART_MCR, save_mcr);
1089 serial_outp(up, UART_IER, save_ier);
1091 if (up->port.flags & UPF_FOURPORT)
1092 outb_p(save_ICP, ICP);
1094 up->port.irq = (irq > 0) ? irq : 0;
1097 static inline void __stop_tx(struct uart_8250_port *p)
1099 if (p->ier & UART_IER_THRI) {
1100 p->ier &= ~UART_IER_THRI;
1101 serial_out(p, UART_IER, p->ier);
1105 static void serial8250_stop_tx(struct uart_port *port)
1107 struct uart_8250_port *up = (struct uart_8250_port *)port;
1112 * We really want to stop the transmitter from sending.
1114 if (up->port.type == PORT_16C950) {
1115 up->acr |= UART_ACR_TXDIS;
1116 serial_icr_write(up, UART_ACR, up->acr);
1120 static void transmit_chars(struct uart_8250_port *up);
1122 static void serial8250_start_tx(struct uart_port *port)
1124 struct uart_8250_port *up = (struct uart_8250_port *)port;
1126 if (!(up->ier & UART_IER_THRI)) {
1127 up->ier |= UART_IER_THRI;
1128 serial_out(up, UART_IER, up->ier);
1130 if (up->bugs & UART_BUG_TXEN) {
1131 unsigned char lsr, iir;
1132 lsr = serial_in(up, UART_LSR);
1133 iir = serial_in(up, UART_IIR);
1134 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT)
1140 * Re-enable the transmitter if we disabled it.
1142 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1143 up->acr &= ~UART_ACR_TXDIS;
1144 serial_icr_write(up, UART_ACR, up->acr);
1148 static void serial8250_stop_rx(struct uart_port *port)
1150 struct uart_8250_port *up = (struct uart_8250_port *)port;
1152 up->ier &= ~UART_IER_RLSI;
1153 up->port.read_status_mask &= ~UART_LSR_DR;
1154 serial_out(up, UART_IER, up->ier);
1157 static void serial8250_enable_ms(struct uart_port *port)
1159 struct uart_8250_port *up = (struct uart_8250_port *)port;
1161 /* no MSR capabilities */
1162 if (up->bugs & UART_BUG_NOMSR)
1165 up->ier |= UART_IER_MSI;
1166 serial_out(up, UART_IER, up->ier);
1170 receive_chars(struct uart_8250_port *up, int *status, struct pt_regs *regs)
1172 struct tty_struct *tty = up->port.info->tty;
1173 unsigned char ch, lsr = *status;
1174 int max_count = 256;
1178 ch = serial_inp(up, UART_RX);
1180 up->port.icount.rx++;
1182 #ifdef CONFIG_SERIAL_8250_CONSOLE
1184 * Recover the break flag from console xmit
1186 if (up->port.line == up->port.cons->index) {
1187 lsr |= up->lsr_break_flag;
1188 up->lsr_break_flag = 0;
1192 if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE |
1193 UART_LSR_FE | UART_LSR_OE))) {
1195 * For statistics only
1197 if (lsr & UART_LSR_BI) {
1198 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1199 up->port.icount.brk++;
1201 * We do the SysRQ and SAK checking
1202 * here because otherwise the break
1203 * may get masked by ignore_status_mask
1204 * or read_status_mask.
1206 if (uart_handle_break(&up->port))
1208 } else if (lsr & UART_LSR_PE)
1209 up->port.icount.parity++;
1210 else if (lsr & UART_LSR_FE)
1211 up->port.icount.frame++;
1212 if (lsr & UART_LSR_OE)
1213 up->port.icount.overrun++;
1216 * Mask off conditions which should be ignored.
1218 lsr &= up->port.read_status_mask;
1220 if (lsr & UART_LSR_BI) {
1221 DEBUG_INTR("handling break....");
1223 } else if (lsr & UART_LSR_PE)
1225 else if (lsr & UART_LSR_FE)
1228 if (uart_handle_sysrq_char(&up->port, ch, regs))
1231 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1234 lsr = serial_inp(up, UART_LSR);
1235 } while ((lsr & UART_LSR_DR) && (max_count-- > 0));
1236 spin_unlock(&up->port.lock);
1237 tty_flip_buffer_push(tty);
1238 spin_lock(&up->port.lock);
1242 static void transmit_chars(struct uart_8250_port *up)
1244 struct circ_buf *xmit = &up->port.info->xmit;
1247 if (up->port.x_char) {
1248 serial_outp(up, UART_TX, up->port.x_char);
1249 up->port.icount.tx++;
1250 up->port.x_char = 0;
1253 if (uart_tx_stopped(&up->port)) {
1254 serial8250_stop_tx(&up->port);
1257 if (uart_circ_empty(xmit)) {
1262 count = up->tx_loadsz;
1264 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1265 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1266 up->port.icount.tx++;
1267 if (uart_circ_empty(xmit))
1269 } while (--count > 0);
1271 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1272 uart_write_wakeup(&up->port);
1274 DEBUG_INTR("THRE...");
1276 if (uart_circ_empty(xmit))
1280 static unsigned int check_modem_status(struct uart_8250_port *up)
1282 unsigned int status = serial_in(up, UART_MSR);
1284 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI) {
1285 if (status & UART_MSR_TERI)
1286 up->port.icount.rng++;
1287 if (status & UART_MSR_DDSR)
1288 up->port.icount.dsr++;
1289 if (status & UART_MSR_DDCD)
1290 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1291 if (status & UART_MSR_DCTS)
1292 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1294 wake_up_interruptible(&up->port.info->delta_msr_wait);
1301 * This handles the interrupt from one port.
1304 serial8250_handle_port(struct uart_8250_port *up, struct pt_regs *regs)
1306 unsigned int status;
1308 spin_lock(&up->port.lock);
1310 status = serial_inp(up, UART_LSR);
1312 DEBUG_INTR("status = %x...", status);
1314 if (status & UART_LSR_DR)
1315 receive_chars(up, &status, regs);
1316 check_modem_status(up);
1317 if (status & UART_LSR_THRE)
1320 spin_unlock(&up->port.lock);
1324 * This is the serial driver's interrupt routine.
1326 * Arjan thinks the old way was overly complex, so it got simplified.
1327 * Alan disagrees, saying that need the complexity to handle the weird
1328 * nature of ISA shared interrupts. (This is a special exception.)
1330 * In order to handle ISA shared interrupts properly, we need to check
1331 * that all ports have been serviced, and therefore the ISA interrupt
1332 * line has been de-asserted.
1334 * This means we need to loop through all ports. checking that they
1335 * don't have an interrupt pending.
1337 static irqreturn_t serial8250_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1339 struct irq_info *i = dev_id;
1340 struct list_head *l, *end = NULL;
1341 int pass_counter = 0, handled = 0;
1343 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1345 spin_lock(&i->lock);
1349 struct uart_8250_port *up;
1352 up = list_entry(l, struct uart_8250_port, list);
1354 iir = serial_in(up, UART_IIR);
1355 if (!(iir & UART_IIR_NO_INT)) {
1356 serial8250_handle_port(up, regs);
1361 } else if (end == NULL)
1366 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1367 /* If we hit this, we're dead. */
1368 printk(KERN_ERR "serial8250: too much work for "
1374 spin_unlock(&i->lock);
1376 DEBUG_INTR("end.\n");
1378 return IRQ_RETVAL(handled);
1382 * To support ISA shared interrupts, we need to have one interrupt
1383 * handler that ensures that the IRQ line has been deasserted
1384 * before returning. Failing to do this will result in the IRQ
1385 * line being stuck active, and, since ISA irqs are edge triggered,
1386 * no more IRQs will be seen.
1388 static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1390 spin_lock_irq(&i->lock);
1392 if (!list_empty(i->head)) {
1393 if (i->head == &up->list)
1394 i->head = i->head->next;
1395 list_del(&up->list);
1397 BUG_ON(i->head != &up->list);
1401 spin_unlock_irq(&i->lock);
1404 static int serial_link_irq_chain(struct uart_8250_port *up)
1406 struct irq_info *i = irq_lists + up->port.irq;
1407 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? SA_SHIRQ : 0;
1409 spin_lock_irq(&i->lock);
1412 list_add(&up->list, i->head);
1413 spin_unlock_irq(&i->lock);
1417 INIT_LIST_HEAD(&up->list);
1418 i->head = &up->list;
1419 spin_unlock_irq(&i->lock);
1421 ret = request_irq(up->port.irq, serial8250_interrupt,
1422 irq_flags, "serial", i);
1424 serial_do_unlink(i, up);
1430 static void serial_unlink_irq_chain(struct uart_8250_port *up)
1432 struct irq_info *i = irq_lists + up->port.irq;
1434 BUG_ON(i->head == NULL);
1436 if (list_empty(i->head))
1437 free_irq(up->port.irq, i);
1439 serial_do_unlink(i, up);
1443 * This function is used to handle ports that do not have an
1444 * interrupt. This doesn't work very well for 16450's, but gives
1445 * barely passable results for a 16550A. (Although at the expense
1446 * of much CPU overhead).
1448 static void serial8250_timeout(unsigned long data)
1450 struct uart_8250_port *up = (struct uart_8250_port *)data;
1451 unsigned int timeout;
1454 iir = serial_in(up, UART_IIR);
1455 if (!(iir & UART_IIR_NO_INT))
1456 serial8250_handle_port(up, NULL);
1458 timeout = up->port.timeout;
1459 timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
1460 mod_timer(&up->timer, jiffies + timeout);
1463 static unsigned int serial8250_tx_empty(struct uart_port *port)
1465 struct uart_8250_port *up = (struct uart_8250_port *)port;
1466 unsigned long flags;
1469 spin_lock_irqsave(&up->port.lock, flags);
1470 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
1471 spin_unlock_irqrestore(&up->port.lock, flags);
1476 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1478 struct uart_8250_port *up = (struct uart_8250_port *)port;
1479 unsigned int status;
1482 status = check_modem_status(up);
1485 if (status & UART_MSR_DCD)
1487 if (status & UART_MSR_RI)
1489 if (status & UART_MSR_DSR)
1491 if (status & UART_MSR_CTS)
1496 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1498 struct uart_8250_port *up = (struct uart_8250_port *)port;
1499 unsigned char mcr = 0;
1501 if (mctrl & TIOCM_RTS)
1502 mcr |= UART_MCR_RTS;
1503 if (mctrl & TIOCM_DTR)
1504 mcr |= UART_MCR_DTR;
1505 if (mctrl & TIOCM_OUT1)
1506 mcr |= UART_MCR_OUT1;
1507 if (mctrl & TIOCM_OUT2)
1508 mcr |= UART_MCR_OUT2;
1509 if (mctrl & TIOCM_LOOP)
1510 mcr |= UART_MCR_LOOP;
1512 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1514 serial_out(up, UART_MCR, mcr);
1517 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1519 struct uart_8250_port *up = (struct uart_8250_port *)port;
1520 unsigned long flags;
1522 spin_lock_irqsave(&up->port.lock, flags);
1523 if (break_state == -1)
1524 up->lcr |= UART_LCR_SBC;
1526 up->lcr &= ~UART_LCR_SBC;
1527 serial_out(up, UART_LCR, up->lcr);
1528 spin_unlock_irqrestore(&up->port.lock, flags);
1531 static int serial8250_startup(struct uart_port *port)
1533 struct uart_8250_port *up = (struct uart_8250_port *)port;
1534 unsigned long flags;
1535 unsigned char lsr, iir;
1538 up->capabilities = uart_config[up->port.type].flags;
1541 if (up->port.type == PORT_16C950) {
1542 /* Wake up and initialize UART */
1544 serial_outp(up, UART_LCR, 0xBF);
1545 serial_outp(up, UART_EFR, UART_EFR_ECB);
1546 serial_outp(up, UART_IER, 0);
1547 serial_outp(up, UART_LCR, 0);
1548 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1549 serial_outp(up, UART_LCR, 0xBF);
1550 serial_outp(up, UART_EFR, UART_EFR_ECB);
1551 serial_outp(up, UART_LCR, 0);
1554 #ifdef CONFIG_SERIAL_8250_RSA
1556 * If this is an RSA port, see if we can kick it up to the
1557 * higher speed clock.
1563 * Clear the FIFO buffers and disable them.
1564 * (they will be reenabled in set_termios())
1566 serial8250_clear_fifos(up);
1569 * Clear the interrupt registers.
1571 (void) serial_inp(up, UART_LSR);
1572 (void) serial_inp(up, UART_RX);
1573 (void) serial_inp(up, UART_IIR);
1574 (void) serial_inp(up, UART_MSR);
1577 * At this point, there's no way the LSR could still be 0xff;
1578 * if it is, then bail out, because there's likely no UART
1581 if (!(up->port.flags & UPF_BUGGY_UART) &&
1582 (serial_inp(up, UART_LSR) == 0xff)) {
1583 printk("ttyS%d: LSR safety check engaged!\n", up->port.line);
1588 * For a XR16C850, we need to set the trigger levels
1590 if (up->port.type == PORT_16850) {
1593 serial_outp(up, UART_LCR, 0xbf);
1595 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
1596 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
1597 serial_outp(up, UART_TRG, UART_TRG_96);
1598 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
1599 serial_outp(up, UART_TRG, UART_TRG_96);
1601 serial_outp(up, UART_LCR, 0);
1605 * If the "interrupt" for this port doesn't correspond with any
1606 * hardware interrupt, we use a timer-based system. The original
1607 * driver used to do this with IRQ0.
1609 if (!is_real_interrupt(up->port.irq)) {
1610 unsigned int timeout = up->port.timeout;
1612 timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
1614 up->timer.data = (unsigned long)up;
1615 mod_timer(&up->timer, jiffies + timeout);
1617 retval = serial_link_irq_chain(up);
1623 * Now, initialize the UART
1625 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
1627 spin_lock_irqsave(&up->port.lock, flags);
1628 if (up->port.flags & UPF_FOURPORT) {
1629 if (!is_real_interrupt(up->port.irq))
1630 up->port.mctrl |= TIOCM_OUT1;
1633 * Most PC uarts need OUT2 raised to enable interrupts.
1635 if (is_real_interrupt(up->port.irq))
1636 up->port.mctrl |= TIOCM_OUT2;
1638 serial8250_set_mctrl(&up->port, up->port.mctrl);
1641 * Do a quick test to see if we receive an
1642 * interrupt when we enable the TX irq.
1644 serial_outp(up, UART_IER, UART_IER_THRI);
1645 lsr = serial_in(up, UART_LSR);
1646 iir = serial_in(up, UART_IIR);
1647 serial_outp(up, UART_IER, 0);
1649 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
1650 if (!(up->bugs & UART_BUG_TXEN)) {
1651 up->bugs |= UART_BUG_TXEN;
1652 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
1656 up->bugs &= ~UART_BUG_TXEN;
1659 spin_unlock_irqrestore(&up->port.lock, flags);
1662 * Finally, enable interrupts. Note: Modem status interrupts
1663 * are set via set_termios(), which will be occurring imminently
1664 * anyway, so we don't enable them here.
1666 up->ier = UART_IER_RLSI | UART_IER_RDI;
1667 serial_outp(up, UART_IER, up->ier);
1669 if (up->port.flags & UPF_FOURPORT) {
1672 * Enable interrupts on the AST Fourport board
1674 icp = (up->port.iobase & 0xfe0) | 0x01f;
1680 * And clear the interrupt registers again for luck.
1682 (void) serial_inp(up, UART_LSR);
1683 (void) serial_inp(up, UART_RX);
1684 (void) serial_inp(up, UART_IIR);
1685 (void) serial_inp(up, UART_MSR);
1690 static void serial8250_shutdown(struct uart_port *port)
1692 struct uart_8250_port *up = (struct uart_8250_port *)port;
1693 unsigned long flags;
1696 * Disable interrupts from this port
1699 serial_outp(up, UART_IER, 0);
1701 spin_lock_irqsave(&up->port.lock, flags);
1702 if (up->port.flags & UPF_FOURPORT) {
1703 /* reset interrupts on the AST Fourport board */
1704 inb((up->port.iobase & 0xfe0) | 0x1f);
1705 up->port.mctrl |= TIOCM_OUT1;
1707 up->port.mctrl &= ~TIOCM_OUT2;
1709 serial8250_set_mctrl(&up->port, up->port.mctrl);
1710 spin_unlock_irqrestore(&up->port.lock, flags);
1713 * Disable break condition and FIFOs
1715 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
1716 serial8250_clear_fifos(up);
1718 #ifdef CONFIG_SERIAL_8250_RSA
1720 * Reset the RSA board back to 115kbps compat mode.
1726 * Read data port to reset things, and then unlink from
1729 (void) serial_in(up, UART_RX);
1731 if (!is_real_interrupt(up->port.irq))
1732 del_timer_sync(&up->timer);
1734 serial_unlink_irq_chain(up);
1737 static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
1742 * Handle magic divisors for baud rates above baud_base on
1743 * SMSC SuperIO chips.
1745 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
1746 baud == (port->uartclk/4))
1748 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
1749 baud == (port->uartclk/8))
1752 * For 16C950s UART_TCR is used in combination with divisor==1
1753 * to achieve baud rates up to baud_base*4.
1755 else if ((port->type == PORT_16C950) &&
1756 baud > (port->uartclk/16))
1760 quot = uart_get_divisor(port, baud);
1766 serial8250_set_termios(struct uart_port *port, struct termios *termios,
1767 struct termios *old)
1769 struct uart_8250_port *up = (struct uart_8250_port *)port;
1770 unsigned char cval, fcr = 0;
1771 unsigned long flags;
1772 unsigned int baud, quot, max_baud;
1774 switch (termios->c_cflag & CSIZE) {
1776 cval = UART_LCR_WLEN5;
1779 cval = UART_LCR_WLEN6;
1782 cval = UART_LCR_WLEN7;
1786 cval = UART_LCR_WLEN8;
1790 if (termios->c_cflag & CSTOPB)
1791 cval |= UART_LCR_STOP;
1792 if (termios->c_cflag & PARENB)
1793 cval |= UART_LCR_PARITY;
1794 if (!(termios->c_cflag & PARODD))
1795 cval |= UART_LCR_EPAR;
1797 if (termios->c_cflag & CMSPAR)
1798 cval |= UART_LCR_SPAR;
1802 * Ask the core to calculate the divisor for us.
1804 max_baud = (up->port.type == PORT_16C950 ? port->uartclk/4 : port->uartclk/16);
1805 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1806 quot = serial8250_get_divisor(port, baud);
1809 * Oxford Semi 952 rev B workaround
1811 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
1814 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
1816 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
1818 fcr = uart_config[up->port.type].fcr;
1822 * MCR-based auto flow control. When AFE is enabled, RTS will be
1823 * deasserted when the receive FIFO contains more characters than
1824 * the trigger, or the MCR RTS bit is cleared. In the case where
1825 * the remote UART is not using CTS auto flow control, we must
1826 * have sufficient FIFO entries for the latency of the remote
1827 * UART to respond. IOW, at least 32 bytes of FIFO.
1829 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
1830 up->mcr &= ~UART_MCR_AFE;
1831 if (termios->c_cflag & CRTSCTS)
1832 up->mcr |= UART_MCR_AFE;
1836 * Ok, we're now changing the port state. Do it with
1837 * interrupts disabled.
1839 spin_lock_irqsave(&up->port.lock, flags);
1842 * 16C950 supports additional prescaler ratios between 1:16 and 1:4
1843 * thus increasing max baud rate to uartclk/4.
1845 if (up->port.type == PORT_16C950) {
1846 if (baud == port->uartclk/4)
1847 serial_icr_write(up, UART_TCR, 0x4);
1848 else if (baud == port->uartclk/8)
1849 serial_icr_write(up, UART_TCR, 0x8);
1851 serial_icr_write(up, UART_TCR, 0);
1855 * Update the per-port timeout.
1857 uart_update_timeout(port, termios->c_cflag, baud);
1859 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
1860 if (termios->c_iflag & INPCK)
1861 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
1862 if (termios->c_iflag & (BRKINT | PARMRK))
1863 up->port.read_status_mask |= UART_LSR_BI;
1866 * Characteres to ignore
1868 up->port.ignore_status_mask = 0;
1869 if (termios->c_iflag & IGNPAR)
1870 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
1871 if (termios->c_iflag & IGNBRK) {
1872 up->port.ignore_status_mask |= UART_LSR_BI;
1874 * If we're ignoring parity and break indicators,
1875 * ignore overruns too (for real raw support).
1877 if (termios->c_iflag & IGNPAR)
1878 up->port.ignore_status_mask |= UART_LSR_OE;
1882 * ignore all characters if CREAD is not set
1884 if ((termios->c_cflag & CREAD) == 0)
1885 up->port.ignore_status_mask |= UART_LSR_DR;
1888 * CTS flow control flag and modem status interrupts
1890 up->ier &= ~UART_IER_MSI;
1891 if (!(up->bugs & UART_BUG_NOMSR) &&
1892 UART_ENABLE_MS(&up->port, termios->c_cflag))
1893 up->ier |= UART_IER_MSI;
1894 if (up->capabilities & UART_CAP_UUE)
1895 up->ier |= UART_IER_UUE | UART_IER_RTOIE;
1897 serial_out(up, UART_IER, up->ier);
1899 if (up->capabilities & UART_CAP_EFR) {
1900 unsigned char efr = 0;
1902 * TI16C752/Startech hardware flow control. FIXME:
1903 * - TI16C752 requires control thresholds to be set.
1904 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
1906 if (termios->c_cflag & CRTSCTS)
1907 efr |= UART_EFR_CTS;
1909 serial_outp(up, UART_LCR, 0xBF);
1910 serial_outp(up, UART_EFR, efr);
1913 if (up->capabilities & UART_NATSEMI) {
1914 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
1915 serial_outp(up, UART_LCR, 0xe0);
1917 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
1920 serial_dl_write(up, quot);
1923 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
1924 * is written without DLAB set, this mode will be disabled.
1926 if (up->port.type == PORT_16750)
1927 serial_outp(up, UART_FCR, fcr);
1929 serial_outp(up, UART_LCR, cval); /* reset DLAB */
1930 up->lcr = cval; /* Save LCR */
1931 if (up->port.type != PORT_16750) {
1932 if (fcr & UART_FCR_ENABLE_FIFO) {
1933 /* emulated UARTs (Lucent Venus 167x) need two steps */
1934 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1936 serial_outp(up, UART_FCR, fcr); /* set fcr */
1938 serial8250_set_mctrl(&up->port, up->port.mctrl);
1939 spin_unlock_irqrestore(&up->port.lock, flags);
1943 serial8250_pm(struct uart_port *port, unsigned int state,
1944 unsigned int oldstate)
1946 struct uart_8250_port *p = (struct uart_8250_port *)port;
1948 serial8250_set_sleep(p, state != 0);
1951 p->pm(port, state, oldstate);
1955 * Resource handling.
1957 static int serial8250_request_std_resource(struct uart_8250_port *up)
1959 unsigned int size = 8 << up->port.regshift;
1962 switch (up->port.iotype) {
1967 if (!up->port.mapbase)
1970 if (!request_mem_region(up->port.mapbase, size, "serial")) {
1975 if (up->port.flags & UPF_IOREMAP) {
1976 up->port.membase = ioremap(up->port.mapbase, size);
1977 if (!up->port.membase) {
1978 release_mem_region(up->port.mapbase, size);
1986 if (!request_region(up->port.iobase, size, "serial"))
1993 static void serial8250_release_std_resource(struct uart_8250_port *up)
1995 unsigned int size = 8 << up->port.regshift;
1997 switch (up->port.iotype) {
2002 if (!up->port.mapbase)
2005 if (up->port.flags & UPF_IOREMAP) {
2006 iounmap(up->port.membase);
2007 up->port.membase = NULL;
2010 release_mem_region(up->port.mapbase, size);
2015 release_region(up->port.iobase, size);
2020 static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2022 unsigned long start = UART_RSA_BASE << up->port.regshift;
2023 unsigned int size = 8 << up->port.regshift;
2026 switch (up->port.iotype) {
2033 start += up->port.iobase;
2034 if (!request_region(start, size, "serial-rsa"))
2042 static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2044 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2045 unsigned int size = 8 << up->port.regshift;
2047 switch (up->port.iotype) {
2053 release_region(up->port.iobase + offset, size);
2058 static void serial8250_release_port(struct uart_port *port)
2060 struct uart_8250_port *up = (struct uart_8250_port *)port;
2062 serial8250_release_std_resource(up);
2063 if (up->port.type == PORT_RSA)
2064 serial8250_release_rsa_resource(up);
2067 static int serial8250_request_port(struct uart_port *port)
2069 struct uart_8250_port *up = (struct uart_8250_port *)port;
2072 ret = serial8250_request_std_resource(up);
2073 if (ret == 0 && up->port.type == PORT_RSA) {
2074 ret = serial8250_request_rsa_resource(up);
2076 serial8250_release_std_resource(up);
2082 static void serial8250_config_port(struct uart_port *port, int flags)
2084 struct uart_8250_port *up = (struct uart_8250_port *)port;
2085 int probeflags = PROBE_ANY;
2089 * Find the region that we can probe for. This in turn
2090 * tells us whether we can probe for the type of port.
2092 ret = serial8250_request_std_resource(up);
2096 ret = serial8250_request_rsa_resource(up);
2098 probeflags &= ~PROBE_RSA;
2100 if (flags & UART_CONFIG_TYPE)
2101 autoconfig(up, probeflags);
2102 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2105 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2106 serial8250_release_rsa_resource(up);
2107 if (up->port.type == PORT_UNKNOWN)
2108 serial8250_release_std_resource(up);
2112 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2114 if (ser->irq >= NR_IRQS || ser->irq < 0 ||
2115 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2116 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2117 ser->type == PORT_STARTECH)
2123 serial8250_type(struct uart_port *port)
2125 int type = port->type;
2127 if (type >= ARRAY_SIZE(uart_config))
2129 return uart_config[type].name;
2132 static struct uart_ops serial8250_pops = {
2133 .tx_empty = serial8250_tx_empty,
2134 .set_mctrl = serial8250_set_mctrl,
2135 .get_mctrl = serial8250_get_mctrl,
2136 .stop_tx = serial8250_stop_tx,
2137 .start_tx = serial8250_start_tx,
2138 .stop_rx = serial8250_stop_rx,
2139 .enable_ms = serial8250_enable_ms,
2140 .break_ctl = serial8250_break_ctl,
2141 .startup = serial8250_startup,
2142 .shutdown = serial8250_shutdown,
2143 .set_termios = serial8250_set_termios,
2144 .pm = serial8250_pm,
2145 .type = serial8250_type,
2146 .release_port = serial8250_release_port,
2147 .request_port = serial8250_request_port,
2148 .config_port = serial8250_config_port,
2149 .verify_port = serial8250_verify_port,
2152 static struct uart_8250_port serial8250_ports[UART_NR];
2154 static void __init serial8250_isa_init_ports(void)
2156 struct uart_8250_port *up;
2157 static int first = 1;
2164 for (i = 0; i < nr_uarts; i++) {
2165 struct uart_8250_port *up = &serial8250_ports[i];
2168 spin_lock_init(&up->port.lock);
2170 init_timer(&up->timer);
2171 up->timer.function = serial8250_timeout;
2174 * ALPHA_KLUDGE_MCR needs to be killed.
2176 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2177 up->mcr_force = ALPHA_KLUDGE_MCR;
2179 up->port.ops = &serial8250_pops;
2182 for (i = 0, up = serial8250_ports;
2183 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2185 up->port.iobase = old_serial_port[i].port;
2186 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2187 up->port.uartclk = old_serial_port[i].baud_base * 16;
2188 up->port.flags = old_serial_port[i].flags;
2189 up->port.hub6 = old_serial_port[i].hub6;
2190 up->port.membase = old_serial_port[i].iomem_base;
2191 up->port.iotype = old_serial_port[i].io_type;
2192 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2194 up->port.flags |= UPF_SHARE_IRQ;
2199 serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2203 serial8250_isa_init_ports();
2205 for (i = 0; i < nr_uarts; i++) {
2206 struct uart_8250_port *up = &serial8250_ports[i];
2209 uart_add_one_port(drv, &up->port);
2213 #ifdef CONFIG_SERIAL_8250_CONSOLE
2215 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
2218 * Wait for transmitter & holding register to empty
2220 static inline void wait_for_xmitr(struct uart_8250_port *up, int bits)
2222 unsigned int status, tmout = 10000;
2224 /* Wait up to 10ms for the character(s) to be sent. */
2226 status = serial_in(up, UART_LSR);
2228 if (status & UART_LSR_BI)
2229 up->lsr_break_flag = UART_LSR_BI;
2234 } while ((status & bits) != bits);
2236 /* Wait up to 1s for flow control if necessary */
2237 if (up->port.flags & UPF_CONS_FLOW) {
2239 while (!(serial_in(up, UART_MSR) & UART_MSR_CTS) && --tmout) {
2241 if ((tmout % 1000) == 0)
2242 touch_nmi_watchdog();
2247 static void serial8250_console_putchar(struct uart_port *port, int ch)
2249 struct uart_8250_port *up = (struct uart_8250_port *)port;
2251 wait_for_xmitr(up, UART_LSR_THRE);
2252 serial_out(up, UART_TX, ch);
2256 * Print a string to the serial port trying not to disturb
2257 * any possible real use of the port...
2259 * The console_lock must be held when we get here.
2262 serial8250_console_write(struct console *co, const char *s, unsigned int count)
2264 struct uart_8250_port *up = &serial8250_ports[co->index];
2265 unsigned long flags;
2269 touch_nmi_watchdog();
2271 local_irq_save(flags);
2272 if (up->port.sysrq) {
2273 /* serial8250_handle_port() already took the lock */
2275 } else if (oops_in_progress) {
2276 locked = spin_trylock(&up->port.lock);
2278 spin_lock(&up->port.lock);
2281 * First save the IER then disable the interrupts
2283 ier = serial_in(up, UART_IER);
2285 if (up->capabilities & UART_CAP_UUE)
2286 serial_out(up, UART_IER, UART_IER_UUE);
2288 serial_out(up, UART_IER, 0);
2290 uart_console_write(&up->port, s, count, serial8250_console_putchar);
2293 * Finally, wait for transmitter to become empty
2294 * and restore the IER
2296 wait_for_xmitr(up, BOTH_EMPTY);
2297 serial_out(up, UART_IER, ier);
2300 spin_unlock(&up->port.lock);
2301 local_irq_restore(flags);
2304 static int serial8250_console_setup(struct console *co, char *options)
2306 struct uart_port *port;
2313 * Check whether an invalid uart number has been specified, and
2314 * if so, search for the first available port that does have
2317 if (co->index >= nr_uarts)
2319 port = &serial8250_ports[co->index].port;
2320 if (!port->iobase && !port->membase)
2324 uart_parse_options(options, &baud, &parity, &bits, &flow);
2326 return uart_set_options(port, co, baud, parity, bits, flow);
2329 static struct uart_driver serial8250_reg;
2330 static struct console serial8250_console = {
2332 .write = serial8250_console_write,
2333 .device = uart_console_device,
2334 .setup = serial8250_console_setup,
2335 .flags = CON_PRINTBUFFER,
2337 .data = &serial8250_reg,
2340 static int __init serial8250_console_init(void)
2342 serial8250_isa_init_ports();
2343 register_console(&serial8250_console);
2346 console_initcall(serial8250_console_init);
2348 static int __init find_port(struct uart_port *p)
2351 struct uart_port *port;
2353 for (line = 0; line < nr_uarts; line++) {
2354 port = &serial8250_ports[line].port;
2355 if (uart_match_port(p, port))
2361 int __init serial8250_start_console(struct uart_port *port, char *options)
2365 line = find_port(port);
2369 add_preferred_console("ttyS", line, options);
2370 printk("Adding console on ttyS%d at %s 0x%lx (options '%s')\n",
2371 line, port->iotype == UPIO_MEM ? "MMIO" : "I/O port",
2372 port->iotype == UPIO_MEM ? (unsigned long) port->mapbase :
2373 (unsigned long) port->iobase, options);
2374 if (!(serial8250_console.flags & CON_ENABLED)) {
2375 serial8250_console.flags &= ~CON_PRINTBUFFER;
2376 register_console(&serial8250_console);
2381 #define SERIAL8250_CONSOLE &serial8250_console
2383 #define SERIAL8250_CONSOLE NULL
2386 static struct uart_driver serial8250_reg = {
2387 .owner = THIS_MODULE,
2388 .driver_name = "serial",
2389 .devfs_name = "tts/",
2394 .cons = SERIAL8250_CONSOLE,
2398 * early_serial_setup - early registration for 8250 ports
2400 * Setup an 8250 port structure prior to console initialisation. Use
2401 * after console initialisation will cause undefined behaviour.
2403 int __init early_serial_setup(struct uart_port *port)
2405 if (port->line >= ARRAY_SIZE(serial8250_ports))
2408 serial8250_isa_init_ports();
2409 serial8250_ports[port->line].port = *port;
2410 serial8250_ports[port->line].port.ops = &serial8250_pops;
2415 * serial8250_suspend_port - suspend one serial port
2416 * @line: serial line number
2417 * @level: the level of port suspension, as per uart_suspend_port
2419 * Suspend one serial port.
2421 void serial8250_suspend_port(int line)
2423 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2427 * serial8250_resume_port - resume one serial port
2428 * @line: serial line number
2429 * @level: the level of port resumption, as per uart_resume_port
2431 * Resume one serial port.
2433 void serial8250_resume_port(int line)
2435 uart_resume_port(&serial8250_reg, &serial8250_ports[line].port);
2439 * Register a set of serial devices attached to a platform device. The
2440 * list is terminated with a zero flags entry, which means we expect
2441 * all entries to have at least UPF_BOOT_AUTOCONF set.
2443 static int __devinit serial8250_probe(struct platform_device *dev)
2445 struct plat_serial8250_port *p = dev->dev.platform_data;
2446 struct uart_port port;
2449 memset(&port, 0, sizeof(struct uart_port));
2451 for (i = 0; p && p->flags != 0; p++, i++) {
2452 port.iobase = p->iobase;
2453 port.membase = p->membase;
2455 port.uartclk = p->uartclk;
2456 port.regshift = p->regshift;
2457 port.iotype = p->iotype;
2458 port.flags = p->flags;
2459 port.mapbase = p->mapbase;
2460 port.hub6 = p->hub6;
2461 port.dev = &dev->dev;
2463 port.flags |= UPF_SHARE_IRQ;
2464 ret = serial8250_register_port(&port);
2466 dev_err(&dev->dev, "unable to register port at index %d "
2467 "(IO%lx MEM%lx IRQ%d): %d\n", i,
2468 p->iobase, p->mapbase, p->irq, ret);
2475 * Remove serial ports registered against a platform device.
2477 static int __devexit serial8250_remove(struct platform_device *dev)
2481 for (i = 0; i < nr_uarts; i++) {
2482 struct uart_8250_port *up = &serial8250_ports[i];
2484 if (up->port.dev == &dev->dev)
2485 serial8250_unregister_port(i);
2490 static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
2494 for (i = 0; i < UART_NR; i++) {
2495 struct uart_8250_port *up = &serial8250_ports[i];
2497 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
2498 uart_suspend_port(&serial8250_reg, &up->port);
2504 static int serial8250_resume(struct platform_device *dev)
2508 for (i = 0; i < UART_NR; i++) {
2509 struct uart_8250_port *up = &serial8250_ports[i];
2511 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
2512 uart_resume_port(&serial8250_reg, &up->port);
2518 static struct platform_driver serial8250_isa_driver = {
2519 .probe = serial8250_probe,
2520 .remove = __devexit_p(serial8250_remove),
2521 .suspend = serial8250_suspend,
2522 .resume = serial8250_resume,
2524 .name = "serial8250",
2525 .owner = THIS_MODULE,
2530 * This "device" covers _all_ ISA 8250-compatible serial devices listed
2531 * in the table in include/asm/serial.h
2533 static struct platform_device *serial8250_isa_devs;
2536 * serial8250_register_port and serial8250_unregister_port allows for
2537 * 16x50 serial ports to be configured at run-time, to support PCMCIA
2538 * modems and PCI multiport cards.
2540 static DEFINE_MUTEX(serial_mutex);
2542 static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
2547 * First, find a port entry which matches.
2549 for (i = 0; i < nr_uarts; i++)
2550 if (uart_match_port(&serial8250_ports[i].port, port))
2551 return &serial8250_ports[i];
2554 * We didn't find a matching entry, so look for the first
2555 * free entry. We look for one which hasn't been previously
2556 * used (indicated by zero iobase).
2558 for (i = 0; i < nr_uarts; i++)
2559 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
2560 serial8250_ports[i].port.iobase == 0)
2561 return &serial8250_ports[i];
2564 * That also failed. Last resort is to find any entry which
2565 * doesn't have a real port associated with it.
2567 for (i = 0; i < nr_uarts; i++)
2568 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
2569 return &serial8250_ports[i];
2575 * serial8250_register_port - register a serial port
2576 * @port: serial port template
2578 * Configure the serial port specified by the request. If the
2579 * port exists and is in use, it is hung up and unregistered
2582 * The port is then probed and if necessary the IRQ is autodetected
2583 * If this fails an error is returned.
2585 * On success the port is ready to use and the line number is returned.
2587 int serial8250_register_port(struct uart_port *port)
2589 struct uart_8250_port *uart;
2592 if (port->uartclk == 0)
2595 mutex_lock(&serial_mutex);
2597 uart = serial8250_find_match_or_unused(port);
2599 uart_remove_one_port(&serial8250_reg, &uart->port);
2601 uart->port.iobase = port->iobase;
2602 uart->port.membase = port->membase;
2603 uart->port.irq = port->irq;
2604 uart->port.uartclk = port->uartclk;
2605 uart->port.fifosize = port->fifosize;
2606 uart->port.regshift = port->regshift;
2607 uart->port.iotype = port->iotype;
2608 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
2609 uart->port.mapbase = port->mapbase;
2611 uart->port.dev = port->dev;
2613 ret = uart_add_one_port(&serial8250_reg, &uart->port);
2615 ret = uart->port.line;
2617 mutex_unlock(&serial_mutex);
2621 EXPORT_SYMBOL(serial8250_register_port);
2624 * serial8250_unregister_port - remove a 16x50 serial port at runtime
2625 * @line: serial line number
2627 * Remove one serial port. This may not be called from interrupt
2628 * context. We hand the port back to the our control.
2630 void serial8250_unregister_port(int line)
2632 struct uart_8250_port *uart = &serial8250_ports[line];
2634 mutex_lock(&serial_mutex);
2635 uart_remove_one_port(&serial8250_reg, &uart->port);
2636 if (serial8250_isa_devs) {
2637 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
2638 uart->port.type = PORT_UNKNOWN;
2639 uart->port.dev = &serial8250_isa_devs->dev;
2640 uart_add_one_port(&serial8250_reg, &uart->port);
2642 uart->port.dev = NULL;
2644 mutex_unlock(&serial_mutex);
2646 EXPORT_SYMBOL(serial8250_unregister_port);
2648 static int __init serial8250_init(void)
2652 if (nr_uarts > UART_NR)
2655 printk(KERN_INFO "Serial: 8250/16550 driver $Revision: 1.90 $ "
2656 "%d ports, IRQ sharing %sabled\n", nr_uarts,
2657 share_irqs ? "en" : "dis");
2659 for (i = 0; i < NR_IRQS; i++)
2660 spin_lock_init(&irq_lists[i].lock);
2662 ret = uart_register_driver(&serial8250_reg);
2666 serial8250_isa_devs = platform_device_alloc("serial8250",
2667 PLAT8250_DEV_LEGACY);
2668 if (!serial8250_isa_devs) {
2670 goto unreg_uart_drv;
2673 ret = platform_device_add(serial8250_isa_devs);
2677 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
2679 ret = platform_driver_register(&serial8250_isa_driver);
2683 platform_device_del(serial8250_isa_devs);
2685 platform_device_put(serial8250_isa_devs);
2687 uart_unregister_driver(&serial8250_reg);
2692 static void __exit serial8250_exit(void)
2694 struct platform_device *isa_dev = serial8250_isa_devs;
2697 * This tells serial8250_unregister_port() not to re-register
2698 * the ports (thereby making serial8250_isa_driver permanently
2701 serial8250_isa_devs = NULL;
2703 platform_driver_unregister(&serial8250_isa_driver);
2704 platform_device_unregister(isa_dev);
2706 uart_unregister_driver(&serial8250_reg);
2709 module_init(serial8250_init);
2710 module_exit(serial8250_exit);
2712 EXPORT_SYMBOL(serial8250_suspend_port);
2713 EXPORT_SYMBOL(serial8250_resume_port);
2715 MODULE_LICENSE("GPL");
2716 MODULE_DESCRIPTION("Generic 8250/16x50 serial driver $Revision: 1.90 $");
2718 module_param(share_irqs, uint, 0644);
2719 MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
2722 module_param(nr_uarts, uint, 0644);
2723 MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
2725 #ifdef CONFIG_SERIAL_8250_RSA
2726 module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
2727 MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
2729 MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);