drivers/serial/8250_pci.c

   1 /*
   2  *  linux/drivers/char/8250_pci.c
   3  *
   4  *  Probe module for 8250/16550-type PCI serial ports.
   5  *
   6  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   7  *
   8  *  Copyright (C) 2001 Russell King, All Rights Reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License.
  13  *
  14  *  $Id: 8250_pci.c,v 1.28 2002/11/02 11:14:18 rmk Exp $
  15  */
  16 #include <linux/module.h>
  17 #include <linux/init.h>
  18 #include <linux/pci.h>
  19 #include <linux/sched.h>
  20 #include <linux/string.h>
  21 #include <linux/kernel.h>
  22 #include <linux/slab.h>
  23 #include <linux/delay.h>
  24 #include <linux/tty.h>
  25 #include <linux/serial.h>
  26 #include <linux/serial_core.h>
  27 #include <linux/8250_pci.h>
  28
  29 #include <asm/bitops.h>
  30 #include <asm/byteorder.h>
  31 #include <asm/io.h>
  32
  33 #include "8250.h"
  34
  35 /*
  36  * Definitions for PCI support.
  37  */
  38 #define FL_BASE_MASK            0x0007
  39 #define FL_BASE0                0x0000
  40 #define FL_BASE1                0x0001
  41 #define FL_BASE2                0x0002
  42 #define FL_BASE3                0x0003
  43 #define FL_BASE4                0x0004
  44 #define FL_GET_BASE(x)          (x & FL_BASE_MASK)
  45
  46 /* Use successive BARs (PCI base address registers),
  47    else use offset into some specified BAR */
  48 #define FL_BASE_BARS            0x0008
  49
  50 /* do not assign an irq */
  51 #define FL_NOIRQ                0x0080
  52
  53 /* Use the Base address register size to cap number of ports */
  54 #define FL_REGION_SZ_CAP        0x0100
  55
  56 struct pci_board {
  57         unsigned int flags;
  58         unsigned int num_ports;
  59         unsigned int base_baud;
  60         unsigned int uart_offset;
  61         unsigned int reg_shift;
  62         unsigned int first_offset;
  63 };
  64
  65 /*
  66  * init function returns:
  67  *  > 0 - number of ports
  68  *  = 0 - use board->num_ports
  69  *  < 0 - error
  70  */
  71 struct pci_serial_quirk {
  72         u32     vendor;
  73         u32     device;
  74         u32     subvendor;
  75         u32     subdevice;
  76         int     (*init)(struct pci_dev *dev);
  77         int     (*setup)(struct pci_dev *dev, struct pci_board *board,
  78                          struct serial_struct *req, int idx);
  79         void    (*exit)(struct pci_dev *dev);
  80 };
  81
  82 #define PCI_NUM_BAR_RESOURCES   6
  83
  84 struct serial_private {
  85         unsigned int            nr;
  86         void                    *remapped_bar[PCI_NUM_BAR_RESOURCES];
  87         struct pci_serial_quirk *quirk;
  88         int                     line[0];
  89 };
  90
  91 static void moan_device(const char *str, struct pci_dev *dev)
  92 {
  93         printk(KERN_WARNING "%s: %s\n"
  94                KERN_WARNING "Please send the output of lspci -vv, this\n"
  95                KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
  96                KERN_WARNING "manufacturer and name of serial board or\n"
  97                KERN_WARNING "modem board to rmk+serial@arm.linux.org.uk.\n",
  98                pci_name(dev), str, dev->vendor, dev->device,
  99                dev->subsystem_vendor, dev->subsystem_device);
 100 }
 101
 102 static int
 103 setup_port(struct pci_dev *dev, struct serial_struct *req,
 104            int bar, int offset, int regshift)
 105 {
 106         struct serial_private *priv = pci_get_drvdata(dev);
 107         unsigned long port, len;
 108
 109         if (bar >= PCI_NUM_BAR_RESOURCES)
 110                 return -EINVAL;
 111
 112         if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
 113                 port = pci_resource_start(dev, bar);
 114                 len =  pci_resource_len(dev, bar);
 115
 116                 if (!priv->remapped_bar[bar])
 117                         priv->remapped_bar[bar] = ioremap(port, len);
 118                 if (!priv->remapped_bar[bar])
 119                         return -ENOMEM;
 120
 121                 req->io_type = UPIO_MEM;
 122                 req->iomap_base = port + offset;
 123                 req->iomem_base = priv->remapped_bar[bar] + offset;
 124                 req->iomem_reg_shift = regshift;
 125         } else {
 126                 port = pci_resource_start(dev, bar) + offset;
 127                 req->io_type = UPIO_PORT;
 128                 req->port = port;
 129                 if (HIGH_BITS_OFFSET)
 130                         req->port_high = port >> HIGH_BITS_OFFSET;
 131         }
 132         return 0;
 133 }
 134
 135 /*
 136  * AFAVLAB uses a different mixture of BARs and offsets
 137  * Not that ugly ;) -- HW
 138  */
 139 static int
 140 afavlab_setup(struct pci_dev *dev, struct pci_board *board,
 141               struct serial_struct *req, int idx)
 142 {
 143         unsigned int bar, offset = board->first_offset;
 144
 145         bar = FL_GET_BASE(board->flags);
 146         if (idx < 4)
 147                 bar += idx;
 148         else {
 149                 bar = 4;
 150                 offset += (idx - 4) * board->uart_offset;
 151         }
 152
 153         return setup_port(dev, req, bar, offset, board->reg_shift);
 154 }
 155
 156 /*
 157  * HP's Remote Management Console.  The Diva chip came in several
 158  * different versions.  N-class, L2000 and A500 have two Diva chips, each
 159  * with 3 UARTs (the third UART on the second chip is unused).  Superdome
 160  * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
 161  * one Diva chip, but it has been expanded to 5 UARTs.
 162  */
 163 static int __devinit pci_hp_diva_init(struct pci_dev *dev)
 164 {
 165         int rc = 0;
 166
 167         switch (dev->subsystem_device) {
 168         case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
 169         case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
 170         case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
 171         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 172                 rc = 3;
 173                 break;
 174         case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
 175                 rc = 2;
 176                 break;
 177         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 178                 rc = 4;
 179                 break;
 180         case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
 181                 rc = 1;
 182                 break;
 183         }
 184
 185         return rc;
 186 }
 187
 188 /*
 189  * HP's Diva chip puts the 4th/5th serial port further out, and
 190  * some serial ports are supposed to be hidden on certain models.
 191  */
 192 static int
 193 pci_hp_diva_setup(struct pci_dev *dev, struct pci_board *board,
 194               struct serial_struct *req, int idx)
 195 {
 196         unsigned int offset = board->first_offset;
 197         unsigned int bar = FL_GET_BASE(board->flags);
 198
 199         switch (dev->subsystem_device) {
 200         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 201                 if (idx == 3)
 202                         idx++;
 203                 break;
 204         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 205                 if (idx > 0)
 206                         idx++;
 207                 if (idx > 2)
 208                         idx++;
 209                 break;
 210         }
 211         if (idx > 2)
 212                 offset = 0x18;
 213
 214         offset += idx * board->uart_offset;
 215
 216         return setup_port(dev, req, bar, offset, board->reg_shift);
 217 }
 218
 219 /*
 220  * Added for EKF Intel i960 serial boards
 221  */
 222 static int __devinit pci_inteli960ni_init(struct pci_dev *dev)
 223 {
 224         unsigned long oldval;
 225
 226         if (!(dev->subsystem_device & 0x1000))
 227                 return -ENODEV;
 228
 229         /* is firmware started? */
 230         pci_read_config_dword(dev, 0x44, (void*) &oldval);
 231         if (oldval == 0x00001000L) { /* RESET value */
 232                 printk(KERN_DEBUG "Local i960 firmware missing");
 233                 return -ENODEV;
 234         }
 235         return 0;
 236 }
 237
 238 /*
 239  * Some PCI serial cards using the PLX 9050 PCI interface chip require
 240  * that the card interrupt be explicitly enabled or disabled.  This
 241  * seems to be mainly needed on card using the PLX which also use I/O
 242  * mapped memory.
 243  */
 244 static int __devinit pci_plx9050_init(struct pci_dev *dev)
 245 {
 246         u8 *p, irq_config;
 247
 248         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
 249                 moan_device("no memory in bar 0", dev);
 250                 return 0;
 251         }
 252
 253         irq_config = 0x41;
 254         if (dev->vendor == PCI_VENDOR_ID_PANACOM)
 255                 irq_config = 0x43;
 256         if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
 257             (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) {
 258                 /*
 259                  * As the megawolf cards have the int pins active
 260                  * high, and have 2 UART chips, both ints must be
 261                  * enabled on the 9050. Also, the UARTS are set in
 262                  * 16450 mode by default, so we have to enable the
 263                  * 16C950 'enhanced' mode so that we can use the
 264                  * deep FIFOs
 265                  */
 266                 irq_config = 0x5b;
 267         }
 268
 269         /*
 270          * enable/disable interrupts
 271          */
 272         p = ioremap(pci_resource_start(dev, 0), 0x80);
 273         if (p == NULL)
 274                 return -ENOMEM;
 275         writel(irq_config, (unsigned long)p + 0x4c);
 276
 277         /*
 278          * Read the register back to ensure that it took effect.
 279          */
 280         readl((unsigned long)p + 0x4c);
 281         iounmap(p);
 282
 283         return 0;
 284 }
 285
 286 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
 287 {
 288         u8 *p;
 289
 290         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
 291                 return;
 292
 293         /*
 294          * disable interrupts
 295          */
 296         p = ioremap(pci_resource_start(dev, 0), 0x80);
 297         if (p != NULL) {
 298                 writel(0, p + 0x4c);
 299
 300                 /*
 301                  * Read the register back to ensure that it took effect.
 302                  */
 303                 readl(p + 0x4c);
 304                 iounmap(p);
 305         }
 306 }
 307
 308 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
 309 static int
 310 sbs_setup(struct pci_dev *dev, struct pci_board *board,
 311                 struct serial_struct *req, int idx)
 312 {
 313         unsigned int bar, offset = board->first_offset;
 314
 315         bar = 0;
 316
 317         if (idx < 4) {
 318                 /* first four channels map to 0, 0x100, 0x200, 0x300 */
 319                 offset += idx * board->uart_offset;
 320         } else if (idx < 8) {
 321                 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
 322                 offset += idx * board->uart_offset + 0xC00;
 323         } else /* we have only 8 ports on PMC-OCTALPRO */
 324                 return 1;
 325
 326         return setup_port(dev, req, bar, offset, board->reg_shift);
 327 }
 328
 329 /*
 330 * This does initialization for PMC OCTALPRO cards:
 331 * maps the device memory, resets the UARTs (needed, bc
 332 * if the module is removed and inserted again, the card
 333 * is in the sleep mode) and enables global interrupt.
 334 */
 335
 336 /* global control register offset for SBS PMC-OctalPro */
 337 #define OCT_REG_CR_OFF          0x500
 338
 339 static int __devinit sbs_init(struct pci_dev *dev)
 340 {
 341         u8 * p;
 342
 343         p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
 344
 345         if (p == NULL)
 346                 return -ENOMEM;
 347         /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
 348         writeb(0x10,p + OCT_REG_CR_OFF);
 349         udelay(50);
 350         writeb(0x0,p + OCT_REG_CR_OFF);
 351
 352         /* Set bit-2 (INTENABLE) of Control Register */
 353         writeb(0x4, p + OCT_REG_CR_OFF);
 354         iounmap(p);
 355
 356         return 0;
 357 }
 358
 359 /*
 360  * Disables the global interrupt of PMC-OctalPro
 361  */
 362
 363 static void __devexit sbs_exit(struct pci_dev *dev)
 364 {
 365         u8 * p;
 366
 367         p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
 368         if (p != NULL) {
 369                 writeb(0, p + OCT_REG_CR_OFF);
 370         }
 371         iounmap(p);
 372 }
 373
 374 /*
 375  * SIIG serial cards have an PCI interface chip which also controls
 376  * the UART clocking frequency. Each UART can be clocked independently
 377  * (except cards equiped with 4 UARTs) and initial clocking settings
 378  * are stored in the EEPROM chip. It can cause problems because this
 379  * version of serial driver doesn't support differently clocked UART's
 380  * on single PCI card. To prevent this, initialization functions set
 381  * high frequency clocking for all UART's on given card. It is safe (I
 382  * hope) because it doesn't touch EEPROM settings to prevent conflicts
 383  * with other OSes (like M$ DOS).
 384  *
 385  *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
 386  *
 387  * There is two family of SIIG serial cards with different PCI
 388  * interface chip and different configuration methods:
 389  *     - 10x cards have control registers in IO and/or memory space;
 390  *     - 20x cards have control registers in standard PCI configuration space.
 391  *
 392  * Note: some SIIG cards are probed by the parport_serial object.
 393  */
 394
 395 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
 396 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
 397
 398 static int pci_siig10x_init(struct pci_dev *dev)
 399 {
 400         u16 data, *p;
 401
 402         switch (dev->device & 0xfff8) {
 403         case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
 404                 data = 0xffdf;
 405                 break;
 406         case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
 407                 data = 0xf7ff;
 408                 break;
 409         default:                        /* 1S1P, 4S */
 410                 data = 0xfffb;
 411                 break;
 412         }
 413
 414         p = ioremap(pci_resource_start(dev, 0), 0x80);
 415         if (p == NULL)
 416                 return -ENOMEM;
 417
 418         writew(readw((unsigned long) p + 0x28) & data, (unsigned long) p + 0x28);
 419         readw((unsigned long)p + 0x28);
 420         iounmap(p);
 421         return 0;
 422 }
 423
 424 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
 425 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
 426
 427 static int pci_siig20x_init(struct pci_dev *dev)
 428 {
 429         u8 data;
 430
 431         /* Change clock frequency for the first UART. */
 432         pci_read_config_byte(dev, 0x6f, &data);
 433         pci_write_config_byte(dev, 0x6f, data & 0xef);
 434
 435         /* If this card has 2 UART, we have to do the same with second UART. */
 436         if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
 437             ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
 438                 pci_read_config_byte(dev, 0x73, &data);
 439                 pci_write_config_byte(dev, 0x73, data & 0xef);
 440         }
 441         return 0;
 442 }
 443
 444 int pci_siig10x_fn(struct pci_dev *dev, int enable)
 445 {
 446         int ret = 0;
 447         if (enable)
 448                 ret = pci_siig10x_init(dev);
 449         return ret;
 450 }
 451
 452 int pci_siig20x_fn(struct pci_dev *dev, int enable)
 453 {
 454         int ret = 0;
 455         if (enable)
 456                 ret = pci_siig20x_init(dev);
 457         return ret;
 458 }
 459
 460 EXPORT_SYMBOL(pci_siig10x_fn);
 461 EXPORT_SYMBOL(pci_siig20x_fn);
 462
 463 /*
 464  * Timedia has an explosion of boards, and to avoid the PCI table from
 465  * growing *huge*, we use this function to collapse some 70 entries
 466  * in the PCI table into one, for sanity's and compactness's sake.
 467  */
 468 static unsigned short timedia_single_port[] = {
 469         0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
 470 };
 471
 472 static unsigned short timedia_dual_port[] = {
 473         0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
 474         0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
 475         0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
 476         0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
 477         0xD079, 0
 478 };
 479
 480 static unsigned short timedia_quad_port[] = {
 481         0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
 482         0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
 483         0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
 484         0xB157, 0
 485 };
 486
 487 static unsigned short timedia_eight_port[] = {
 488         0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
 489         0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
 490 };
 491
 492 static struct timedia_struct {
 493         int num;
 494         unsigned short *ids;
 495 } timedia_data[] = {
 496         { 1, timedia_single_port },
 497         { 2, timedia_dual_port },
 498         { 4, timedia_quad_port },
 499         { 8, timedia_eight_port },
 500         { 0, NULL }
 501 };
 502
 503 static int __devinit pci_timedia_init(struct pci_dev *dev)
 504 {
 505         unsigned short *ids;
 506         int i, j;
 507
 508         for (i = 0; timedia_data[i].num; i++) {
 509                 ids = timedia_data[i].ids;
 510                 for (j = 0; ids[j]; j++)
 511                         if (dev->subsystem_device == ids[j])
 512                                 return timedia_data[i].num;
 513         }
 514         return 0;
 515 }
 516
 517 /*
 518  * Timedia/SUNIX uses a mixture of BARs and offsets
 519  * Ugh, this is ugly as all hell --- TYT
 520  */
 521 static int
 522 pci_timedia_setup(struct pci_dev *dev, struct pci_board *board,
 523                   struct serial_struct *req, int idx)
 524 {
 525         unsigned int bar = 0, offset = board->first_offset;
 526
 527         switch (idx) {
 528         case 0:
 529                 bar = 0;
 530                 break;
 531         case 1:
 532                 offset = board->uart_offset;
 533                 bar = 0;
 534                 break;
 535         case 2:
 536                 bar = 1;
 537                 break;
 538         case 3:
 539                 offset = board->uart_offset;
 540                 bar = 1;
 541         case 4: /* BAR 2 */
 542         case 5: /* BAR 3 */
 543         case 6: /* BAR 4 */
 544         case 7: /* BAR 5 */
 545                 bar = idx - 2;
 546         }
 547
 548         return setup_port(dev, req, bar, offset, board->reg_shift);
 549 }
 550
 551 /*
 552  * Some Titan cards are also a little weird
 553  */
 554 static int
 555 titan_400l_800l_setup(struct pci_dev *dev, struct pci_board *board,
 556                       struct serial_struct *req, int idx)
 557 {
 558         unsigned int bar, offset = board->first_offset;
 559
 560         switch (idx) {
 561         case 0:
 562                 bar = 1;
 563                 break;
 564         case 1:
 565                 bar = 2;
 566                 break;
 567         default:
 568                 bar = 4;
 569                 offset = (idx - 2) * board->uart_offset;
 570         }
 571
 572         return setup_port(dev, req, bar, offset, board->reg_shift);
 573 }
 574
 575 static int __devinit pci_xircom_init(struct pci_dev *dev)
 576 {
 577         msleep(100);
 578         return 0;
 579 }
 580
 581 static int
 582 pci_default_setup(struct pci_dev *dev, struct pci_board *board,
 583                   struct serial_struct *req, int idx)
 584 {
 585         unsigned int bar, offset = board->first_offset, maxnr;
 586
 587         bar = FL_GET_BASE(board->flags);
 588         if (board->flags & FL_BASE_BARS)
 589                 bar += idx;
 590         else
 591                 offset += idx * board->uart_offset;
 592
 593         maxnr = (pci_resource_len(dev, bar) - board->first_offset) /
 594                 (8 << board->reg_shift);
 595
 596         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
 597                 return 1;
 598
 599         return setup_port(dev, req, bar, offset, board->reg_shift);
 600 }
 601
 602 /* This should be in linux/pci_ids.h */
 603 #define PCI_VENDOR_ID_SBSMODULARIO      0x124B
 604 #define PCI_SUBVENDOR_ID_SBSMODULARIO   0x124B
 605 #define PCI_DEVICE_ID_OCTPRO            0x0001
 606 #define PCI_SUBDEVICE_ID_OCTPRO232      0x0108
 607 #define PCI_SUBDEVICE_ID_OCTPRO422      0x0208
 608 #define PCI_SUBDEVICE_ID_POCTAL232      0x0308
 609 #define PCI_SUBDEVICE_ID_POCTAL422      0x0408
 610
 611 /*
 612  * Master list of serial port init/setup/exit quirks.
 613  * This does not describe the general nature of the port.
 614  * (ie, baud base, number and location of ports, etc)
 615  *
 616  * This list is ordered alphabetically by vendor then device.
 617  * Specific entries must come before more generic entries.
 618  */
 619 static struct pci_serial_quirk pci_serial_quirks[] = {
 620         /*
 621          * AFAVLAB cards.
 622          *  It is not clear whether this applies to all products.
 623          */
 624         {
 625                 .vendor         = PCI_VENDOR_ID_AFAVLAB,
 626                 .device         = PCI_ANY_ID,
 627                 .subvendor      = PCI_ANY_ID,
 628                 .subdevice      = PCI_ANY_ID,
 629                 .setup          = afavlab_setup,
 630         },
 631         /*
 632          * HP Diva
 633          */
 634         {
 635                 .vendor         = PCI_VENDOR_ID_HP,
 636                 .device         = PCI_DEVICE_ID_HP_DIVA,
 637                 .subvendor      = PCI_ANY_ID,
 638                 .subdevice      = PCI_ANY_ID,
 639                 .init           = pci_hp_diva_init,
 640                 .setup          = pci_hp_diva_setup,
 641         },
 642         /*
 643          * Intel
 644          */
 645         {
 646                 .vendor         = PCI_VENDOR_ID_INTEL,
 647                 .device         = PCI_DEVICE_ID_INTEL_80960_RP,
 648                 .subvendor      = 0xe4bf,
 649                 .subdevice      = PCI_ANY_ID,
 650                 .init           = pci_inteli960ni_init,
 651                 .setup          = pci_default_setup,
 652         },
 653         /*
 654          * Panacom
 655          */
 656         {
 657                 .vendor         = PCI_VENDOR_ID_PANACOM,
 658                 .device         = PCI_DEVICE_ID_PANACOM_QUADMODEM,
 659                 .subvendor      = PCI_ANY_ID,
 660                 .subdevice      = PCI_ANY_ID,
 661                 .init           = pci_plx9050_init,
 662                 .setup          = pci_default_setup,
 663                 .exit           = __devexit_p(pci_plx9050_exit),
 664         },
 665         {
 666                 .vendor         = PCI_VENDOR_ID_PANACOM,
 667                 .device         = PCI_DEVICE_ID_PANACOM_DUALMODEM,
 668                 .subvendor      = PCI_ANY_ID,
 669                 .subdevice      = PCI_ANY_ID,
 670                 .init           = pci_plx9050_init,
 671                 .setup          = pci_default_setup,
 672                 .exit           = __devexit_p(pci_plx9050_exit),
 673         },
 674         /*
 675          * PLX
 676          */
 677         {
 678                 .vendor         = PCI_VENDOR_ID_PLX,
 679                 .device         = PCI_DEVICE_ID_PLX_9050,
 680                 .subvendor      = PCI_SUBVENDOR_ID_KEYSPAN,
 681                 .subdevice      = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
 682                 .init           = pci_plx9050_init,
 683                 .setup          = pci_default_setup,
 684                 .exit           = __devexit_p(pci_plx9050_exit),
 685         },
 686         {
 687                 .vendor         = PCI_VENDOR_ID_PLX,
 688                 .device         = PCI_DEVICE_ID_PLX_ROMULUS,
 689                 .subvendor      = PCI_VENDOR_ID_PLX,
 690                 .subdevice      = PCI_DEVICE_ID_PLX_ROMULUS,
 691                 .init           = pci_plx9050_init,
 692                 .setup          = pci_default_setup,
 693                 .exit           = __devexit_p(pci_plx9050_exit),
 694         },
 695         /*
 696          * SBS Technologies, Inc., PMC-OCTALPRO 232
 697          */
 698         {
 699                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 700                 .device         = PCI_DEVICE_ID_OCTPRO,
 701                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 702                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO232,
 703                 .init           = sbs_init,
 704                 .setup          = sbs_setup,
 705                 .exit           = __devexit_p(sbs_exit),
 706         },
 707         /*
 708          * SBS Technologies, Inc., PMC-OCTALPRO 422
 709          */
 710         {
 711                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 712                 .device         = PCI_DEVICE_ID_OCTPRO,
 713                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 714                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO422,
 715                 .init           = sbs_init,
 716                 .setup          = sbs_setup,
 717                 .exit           = __devexit_p(sbs_exit),
 718         },
 719         /*
 720          * SBS Technologies, Inc., P-Octal 232
 721          */
 722         {
 723                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 724                 .device         = PCI_DEVICE_ID_OCTPRO,
 725                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 726                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL232,
 727                 .init           = sbs_init,
 728                 .setup          = sbs_setup,
 729                 .exit           = __devexit_p(sbs_exit),
 730         },
 731         /*
 732          * SBS Technologies, Inc., P-Octal 422
 733          */
 734         {
 735                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 736                 .device         = PCI_DEVICE_ID_OCTPRO,
 737                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 738                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL422,
 739                 .init           = sbs_init,
 740                 .setup          = sbs_setup,
 741                 .exit           = __devexit_p(sbs_exit),
 742         },
 743
 744         /*
 745          * SIIG cards.
 746          *  It is not clear whether these could be collapsed.
 747          */
 748         {
 749                 .vendor         = PCI_VENDOR_ID_SIIG,
 750                 .device         = PCI_DEVICE_ID_SIIG_1S_10x_550,
 751                 .subvendor      = PCI_ANY_ID,
 752                 .subdevice      = PCI_ANY_ID,
 753                 .init           = pci_siig10x_init,
 754                 .setup          = pci_default_setup,
 755         },
 756         {
 757                 .vendor         = PCI_VENDOR_ID_SIIG,
 758                 .device         = PCI_DEVICE_ID_SIIG_1S_10x_650,
 759                 .subvendor      = PCI_ANY_ID,
 760                 .subdevice      = PCI_ANY_ID,
 761                 .init           = pci_siig10x_init,
 762                 .setup          = pci_default_setup,
 763         },
 764         {
 765                 .vendor         = PCI_VENDOR_ID_SIIG,
 766                 .device         = PCI_DEVICE_ID_SIIG_1S_10x_850,
 767                 .subvendor      = PCI_ANY_ID,
 768                 .subdevice      = PCI_ANY_ID,
 769                 .init           = pci_siig10x_init,
 770                 .setup          = pci_default_setup,
 771         },
 772         {
 773                 .vendor         = PCI_VENDOR_ID_SIIG,
 774                 .device         = PCI_DEVICE_ID_SIIG_2S_10x_550,
 775                 .subvendor      = PCI_ANY_ID,
 776                 .subdevice      = PCI_ANY_ID,
 777                 .init           = pci_siig10x_init,
 778                 .setup          = pci_default_setup,
 779         },
 780         {
 781                 .vendor         = PCI_VENDOR_ID_SIIG,
 782                 .device         = PCI_DEVICE_ID_SIIG_2S_10x_650,
 783                 .subvendor      = PCI_ANY_ID,
 784                 .subdevice      = PCI_ANY_ID,
 785                 .init           = pci_siig10x_init,
 786                 .setup          = pci_default_setup,
 787         },
 788         {
 789                 .vendor         = PCI_VENDOR_ID_SIIG,
 790                 .device         = PCI_DEVICE_ID_SIIG_2S_10x_850,
 791                 .subvendor      = PCI_ANY_ID,
 792                 .subdevice      = PCI_ANY_ID,
 793                 .init           = pci_siig10x_init,
 794                 .setup          = pci_default_setup,
 795         },
 796         {
 797                 .vendor         = PCI_VENDOR_ID_SIIG,
 798                 .device         = PCI_DEVICE_ID_SIIG_4S_10x_550,
 799                 .subvendor      = PCI_ANY_ID,
 800                 .subdevice      = PCI_ANY_ID,
 801                 .init           = pci_siig10x_init,
 802                 .setup          = pci_default_setup,
 803         },
 804         {
 805                 .vendor         = PCI_VENDOR_ID_SIIG,
 806                 .device         = PCI_DEVICE_ID_SIIG_4S_10x_650,
 807                 .subvendor      = PCI_ANY_ID,
 808                 .subdevice      = PCI_ANY_ID,
 809                 .init           = pci_siig10x_init,
 810                 .setup          = pci_default_setup,
 811         },
 812         {
 813                 .vendor         = PCI_VENDOR_ID_SIIG,
 814                 .device         = PCI_DEVICE_ID_SIIG_4S_10x_850,
 815                 .subvendor      = PCI_ANY_ID,
 816                 .subdevice      = PCI_ANY_ID,
 817                 .init           = pci_siig10x_init,
 818                 .setup          = pci_default_setup,
 819         },
 820         {
 821                 .vendor         = PCI_VENDOR_ID_SIIG,
 822                 .device         = PCI_DEVICE_ID_SIIG_1S_20x_550,
 823                 .subvendor      = PCI_ANY_ID,
 824                 .subdevice      = PCI_ANY_ID,
 825                 .init           = pci_siig20x_init,
 826                 .setup          = pci_default_setup,
 827         },
 828         {
 829                 .vendor         = PCI_VENDOR_ID_SIIG,
 830                 .device         = PCI_DEVICE_ID_SIIG_1S_20x_650,
 831                 .subvendor      = PCI_ANY_ID,
 832                 .subdevice      = PCI_ANY_ID,
 833                 .init           = pci_siig20x_init,
 834                 .setup          = pci_default_setup,
 835         },
 836         {
 837                 .vendor         = PCI_VENDOR_ID_SIIG,
 838                 .device         = PCI_DEVICE_ID_SIIG_1S_20x_850,
 839                 .subvendor      = PCI_ANY_ID,
 840                 .subdevice      = PCI_ANY_ID,
 841                 .init           = pci_siig20x_init,
 842                 .setup          = pci_default_setup,
 843         },
 844         {
 845                 .vendor         = PCI_VENDOR_ID_SIIG,
 846                 .device         = PCI_DEVICE_ID_SIIG_2S_20x_550,
 847                 .subvendor      = PCI_ANY_ID,
 848                 .subdevice      = PCI_ANY_ID,
 849                 .init           = pci_siig20x_init,
 850                 .setup          = pci_default_setup,
 851         },
 852         {       .vendor         = PCI_VENDOR_ID_SIIG,
 853                 .device         = PCI_DEVICE_ID_SIIG_2S_20x_650,
 854                 .subvendor      = PCI_ANY_ID,
 855                 .subdevice      = PCI_ANY_ID,
 856                 .init           = pci_siig20x_init,
 857                 .setup          = pci_default_setup,
 858         },
 859         {
 860                 .vendor         = PCI_VENDOR_ID_SIIG,
 861                 .device         = PCI_DEVICE_ID_SIIG_2S_20x_850,
 862                 .subvendor      = PCI_ANY_ID,
 863                 .subdevice      = PCI_ANY_ID,
 864                 .init           = pci_siig20x_init,
 865                 .setup          = pci_default_setup,
 866         },
 867         {
 868                 .vendor         = PCI_VENDOR_ID_SIIG,
 869                 .device         = PCI_DEVICE_ID_SIIG_4S_20x_550,
 870                 .subvendor      = PCI_ANY_ID,
 871                 .subdevice      = PCI_ANY_ID,
 872                 .init           = pci_siig20x_init,
 873                 .setup          = pci_default_setup,
 874         },
 875         {
 876                 .vendor         = PCI_VENDOR_ID_SIIG,
 877                 .device         = PCI_DEVICE_ID_SIIG_4S_20x_650,
 878                 .subvendor      = PCI_ANY_ID,
 879                 .subdevice      = PCI_ANY_ID,
 880                 .init           = pci_siig20x_init,
 881                 .setup          = pci_default_setup,
 882         },
 883         {
 884                 .vendor         = PCI_VENDOR_ID_SIIG,
 885                 .device         = PCI_DEVICE_ID_SIIG_4S_20x_850,
 886                 .subvendor      = PCI_ANY_ID,
 887                 .subdevice      = PCI_ANY_ID,
 888                 .init           = pci_siig20x_init,
 889                 .setup          = pci_default_setup,
 890         },
 891         /*
 892          * Titan cards
 893          */
 894         {
 895                 .vendor         = PCI_VENDOR_ID_TITAN,
 896                 .device         = PCI_DEVICE_ID_TITAN_400L,
 897                 .subvendor      = PCI_ANY_ID,
 898                 .subdevice      = PCI_ANY_ID,
 899                 .setup          = titan_400l_800l_setup,
 900         },
 901         {
 902                 .vendor         = PCI_VENDOR_ID_TITAN,
 903                 .device         = PCI_DEVICE_ID_TITAN_800L,
 904                 .subvendor      = PCI_ANY_ID,
 905                 .subdevice      = PCI_ANY_ID,
 906                 .setup          = titan_400l_800l_setup,
 907         },
 908         /*
 909          * Timedia cards
 910          */
 911         {
 912                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
 913                 .device         = PCI_DEVICE_ID_TIMEDIA_1889,
 914                 .subvendor      = PCI_VENDOR_ID_TIMEDIA,
 915                 .subdevice      = PCI_ANY_ID,
 916                 .init           = pci_timedia_init,
 917                 .setup          = pci_timedia_setup,
 918         },
 919         {
 920                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
 921                 .device         = PCI_ANY_ID,
 922                 .subvendor      = PCI_ANY_ID,
 923                 .subdevice      = PCI_ANY_ID,
 924                 .setup          = pci_timedia_setup,
 925         },
 926         /*
 927          * Xircom cards
 928          */
 929         {
 930                 .vendor         = PCI_VENDOR_ID_XIRCOM,
 931                 .device         = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
 932                 .subvendor      = PCI_ANY_ID,
 933                 .subdevice      = PCI_ANY_ID,
 934                 .init           = pci_xircom_init,
 935                 .setup          = pci_default_setup,
 936         },
 937         /*
 938          * Default "match everything" terminator entry
 939          */
 940         {
 941                 .vendor         = PCI_ANY_ID,
 942                 .device         = PCI_ANY_ID,
 943                 .subvendor      = PCI_ANY_ID,
 944                 .subdevice      = PCI_ANY_ID,
 945                 .setup          = pci_default_setup,
 946         }
 947 };
 948
 949 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
 950 {
 951         return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
 952 }
 953
 954 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
 955 {
 956         struct pci_serial_quirk *quirk;
 957
 958         for (quirk = pci_serial_quirks; ; quirk++)
 959                 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
 960                     quirk_id_matches(quirk->device, dev->device) &&
 961                     quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
 962                     quirk_id_matches(quirk->subdevice, dev->subsystem_device))
 963                         break;
 964         return quirk;
 965 }
 966
 967 static _INLINE_ int
 968 get_pci_irq(struct pci_dev *dev, struct pci_board *board, int idx)
 969 {
 970         if (board->flags & FL_NOIRQ)
 971                 return 0;
 972         else
 973                 return dev->irq;
 974 }
 975
 976 /*
 977  * This is the configuration table for all of the PCI serial boards
 978  * which we support.  It is directly indexed by the pci_board_num_t enum
 979  * value, which is encoded in the pci_device_id PCI probe table's
 980  * driver_data member.
 981  *
 982  * The makeup of these names are:
 983  *  pbn_bn{_bt}_n_baud
 984  *
 985  *  bn   = PCI BAR number
 986  *  bt   = Index using PCI BARs
 987  *  n    = number of serial ports
 988  *  baud = baud rate
 989  *
 990  * Please note: in theory if n = 1, _bt infix should make no difference.
 991  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
 992  */
 993 enum pci_board_num_t {
 994         pbn_default = 0,
 995
 996         pbn_b0_1_115200,
 997         pbn_b0_2_115200,
 998         pbn_b0_4_115200,
 999         pbn_b0_5_115200,
1000
1001         pbn_b0_1_921600,
1002         pbn_b0_2_921600,
1003         pbn_b0_4_921600,
1004
1005         pbn_b0_bt_1_115200,
1006         pbn_b0_bt_2_115200,
1007         pbn_b0_bt_8_115200,
1008
1009         pbn_b0_bt_1_460800,
1010         pbn_b0_bt_2_460800,
1011         pbn_b0_bt_4_460800,
1012
1013         pbn_b0_bt_1_921600,
1014         pbn_b0_bt_2_921600,
1015         pbn_b0_bt_4_921600,
1016         pbn_b0_bt_8_921600,
1017
1018         pbn_b1_1_115200,
1019         pbn_b1_2_115200,
1020         pbn_b1_4_115200,
1021         pbn_b1_8_115200,
1022
1023         pbn_b1_1_921600,
1024         pbn_b1_2_921600,
1025         pbn_b1_4_921600,
1026         pbn_b1_8_921600,
1027
1028         pbn_b1_bt_2_921600,
1029
1030         pbn_b1_2_1382400,
1031         pbn_b1_4_1382400,
1032         pbn_b1_8_1382400,
1033
1034         pbn_b2_1_115200,
1035         pbn_b2_8_115200,
1036
1037         pbn_b2_1_460800,
1038         pbn_b2_4_460800,
1039         pbn_b2_8_460800,
1040         pbn_b2_16_460800,
1041
1042         pbn_b2_1_921600,
1043         pbn_b2_4_921600,
1044         pbn_b2_8_921600,
1045
1046         pbn_b2_bt_1_115200,
1047         pbn_b2_bt_2_115200,
1048         pbn_b2_bt_4_115200,
1049
1050         pbn_b2_bt_2_921600,
1051         pbn_b2_bt_4_921600,
1052
1053         pbn_b3_4_115200,
1054         pbn_b3_8_115200,
1055
1056         /*
1057          * Board-specific versions.
1058          */
1059         pbn_panacom,
1060         pbn_panacom2,
1061         pbn_panacom4,
1062         pbn_plx_romulus,
1063         pbn_oxsemi,
1064         pbn_intel_i960,
1065         pbn_sgi_ioc3,
1066         pbn_nec_nile4,
1067         pbn_computone_4,
1068         pbn_computone_6,
1069         pbn_computone_8,
1070         pbn_sbsxrsio,
1071 };
1072
1073 /*
1074  * uart_offset - the space between channels
1075  * reg_shift   - describes how the UART registers are mapped
1076  *               to PCI memory by the card.
1077  * For example IER register on SBS, Inc. PMC-OctPro is located at
1078  * offset 0x10 from the UART base, while UART_IER is defined as 1
1079  * in include/linux/serial_reg.h,
1080  * see first lines of serial_in() and serial_out() in 8250.c
1081 */
1082
1083 static struct pci_board pci_boards[] __devinitdata = {
1084         [pbn_default] = {
1085                 .flags          = FL_BASE0,
1086                 .num_ports      = 1,
1087                 .base_baud      = 115200,
1088                 .uart_offset    = 8,
1089         },
1090         [pbn_b0_1_115200] = {
1091                 .flags          = FL_BASE0,
1092                 .num_ports      = 1,
1093                 .base_baud      = 115200,
1094                 .uart_offset    = 8,
1095         },
1096         [pbn_b0_2_115200] = {
1097                 .flags          = FL_BASE0,
1098                 .num_ports      = 2,
1099                 .base_baud      = 115200,
1100                 .uart_offset    = 8,
1101         },
1102         [pbn_b0_4_115200] = {
1103                 .flags          = FL_BASE0,
1104                 .num_ports      = 4,
1105                 .base_baud      = 115200,
1106                 .uart_offset    = 8,
1107         },
1108         [pbn_b0_5_115200] = {
1109                 .flags          = FL_BASE0,
1110                 .num_ports      = 5,
1111                 .base_baud      = 115200,
1112                 .uart_offset    = 8,
1113         },
1114
1115         [pbn_b0_1_921600] = {
1116                 .flags          = FL_BASE0,
1117                 .num_ports      = 1,
1118                 .base_baud      = 921600,
1119                 .uart_offset    = 8,
1120         },
1121         [pbn_b0_2_921600] = {
1122                 .flags          = FL_BASE0,
1123                 .num_ports      = 2,
1124                 .base_baud      = 921600,
1125                 .uart_offset    = 8,
1126         },
1127         [pbn_b0_4_921600] = {
1128                 .flags          = FL_BASE0,
1129                 .num_ports      = 4,
1130                 .base_baud      = 921600,
1131                 .uart_offset    = 8,
1132         },
1133
1134         [pbn_b0_bt_1_115200] = {
1135                 .flags          = FL_BASE0|FL_BASE_BARS,
1136                 .num_ports      = 1,
1137                 .base_baud      = 115200,
1138                 .uart_offset    = 8,
1139         },
1140         [pbn_b0_bt_2_115200] = {
1141                 .flags          = FL_BASE0|FL_BASE_BARS,
1142                 .num_ports      = 2,
1143                 .base_baud      = 115200,
1144                 .uart_offset    = 8,
1145         },
1146         [pbn_b0_bt_8_115200] = {
1147                 .flags          = FL_BASE0|FL_BASE_BARS,
1148                 .num_ports      = 8,
1149                 .base_baud      = 115200,
1150                 .uart_offset    = 8,
1151         },
1152
1153         [pbn_b0_bt_1_460800] = {
1154                 .flags          = FL_BASE0|FL_BASE_BARS,
1155                 .num_ports      = 1,
1156                 .base_baud      = 460800,
1157                 .uart_offset    = 8,
1158         },
1159         [pbn_b0_bt_2_460800] = {
1160                 .flags          = FL_BASE0|FL_BASE_BARS,
1161                 .num_ports      = 2,
1162                 .base_baud      = 460800,
1163                 .uart_offset    = 8,
1164         },
1165         [pbn_b0_bt_4_460800] = {
1166                 .flags          = FL_BASE0|FL_BASE_BARS,
1167                 .num_ports      = 4,
1168                 .base_baud      = 460800,
1169                 .uart_offset    = 8,
1170         },
1171
1172         [pbn_b0_bt_1_921600] = {
1173                 .flags          = FL_BASE0|FL_BASE_BARS,
1174                 .num_ports      = 1,
1175                 .base_baud      = 921600,
1176                 .uart_offset    = 8,
1177         },
1178         [pbn_b0_bt_2_921600] = {
1179                 .flags          = FL_BASE0|FL_BASE_BARS,
1180                 .num_ports      = 2,
1181                 .base_baud      = 921600,
1182                 .uart_offset    = 8,
1183         },
1184         [pbn_b0_bt_4_921600] = {
1185                 .flags          = FL_BASE0|FL_BASE_BARS,
1186                 .num_ports      = 4,
1187                 .base_baud      = 921600,
1188                 .uart_offset    = 8,
1189         },
1190         [pbn_b0_bt_8_921600] = {
1191                 .flags          = FL_BASE0|FL_BASE_BARS,
1192                 .num_ports      = 8,
1193                 .base_baud      = 921600,
1194                 .uart_offset    = 8,
1195         },
1196
1197         [pbn_b1_1_115200] = {
1198                 .flags          = FL_BASE1,
1199                 .num_ports      = 1,
1200                 .base_baud      = 115200,
1201                 .uart_offset    = 8,
1202         },
1203         [pbn_b1_2_115200] = {
1204                 .flags          = FL_BASE1,
1205                 .num_ports      = 2,
1206                 .base_baud      = 115200,
1207                 .uart_offset    = 8,
1208         },
1209         [pbn_b1_4_115200] = {
1210                 .flags          = FL_BASE1,
1211                 .num_ports      = 4,
1212                 .base_baud      = 115200,
1213                 .uart_offset    = 8,
1214         },
1215         [pbn_b1_8_115200] = {
1216                 .flags          = FL_BASE1,
1217                 .num_ports      = 8,
1218                 .base_baud      = 115200,
1219                 .uart_offset    = 8,
1220         },
1221
1222         [pbn_b1_1_921600] = {
1223                 .flags          = FL_BASE1,
1224                 .num_ports      = 1,
1225                 .base_baud      = 921600,
1226                 .uart_offset    = 8,
1227         },
1228         [pbn_b1_2_921600] = {
1229                 .flags          = FL_BASE1,
1230                 .num_ports      = 2,
1231                 .base_baud      = 921600,
1232                 .uart_offset    = 8,
1233         },
1234         [pbn_b1_4_921600] = {
1235                 .flags          = FL_BASE1,
1236                 .num_ports      = 4,
1237                 .base_baud      = 921600,
1238                 .uart_offset    = 8,
1239         },
1240         [pbn_b1_8_921600] = {
1241                 .flags          = FL_BASE1,
1242                 .num_ports      = 8,
1243                 .base_baud      = 921600,
1244                 .uart_offset    = 8,
1245         },
1246
1247         [pbn_b1_bt_2_921600] = {
1248                 .flags          = FL_BASE1|FL_BASE_BARS,
1249                 .num_ports      = 2,
1250                 .base_baud      = 921600,
1251                 .uart_offset    = 8,
1252         },
1253
1254         [pbn_b1_2_1382400] = {
1255                 .flags          = FL_BASE1,
1256                 .num_ports      = 2,
1257                 .base_baud      = 1382400,
1258                 .uart_offset    = 8,
1259         },
1260         [pbn_b1_4_1382400] = {
1261                 .flags          = FL_BASE1,
1262                 .num_ports      = 4,
1263                 .base_baud      = 1382400,
1264                 .uart_offset    = 8,
1265         },
1266         [pbn_b1_8_1382400] = {
1267                 .flags          = FL_BASE1,
1268                 .num_ports      = 8,
1269                 .base_baud      = 1382400,
1270                 .uart_offset    = 8,
1271         },
1272
1273         [pbn_b2_1_115200] = {
1274                 .flags          = FL_BASE2,
1275                 .num_ports      = 1,
1276                 .base_baud      = 115200,
1277                 .uart_offset    = 8,
1278         },
1279         [pbn_b2_8_115200] = {
1280                 .flags          = FL_BASE2,
1281                 .num_ports      = 8,
1282                 .base_baud      = 115200,
1283                 .uart_offset    = 8,
1284         },
1285
1286         [pbn_b2_1_460800] = {
1287                 .flags          = FL_BASE2,
1288                 .num_ports      = 1,
1289                 .base_baud      = 460800,
1290                 .uart_offset    = 8,
1291         },
1292         [pbn_b2_4_460800] = {
1293                 .flags          = FL_BASE2,
1294                 .num_ports      = 4,
1295                 .base_baud      = 460800,
1296                 .uart_offset    = 8,
1297         },
1298         [pbn_b2_8_460800] = {
1299                 .flags          = FL_BASE2,
1300                 .num_ports      = 8,
1301                 .base_baud      = 460800,
1302                 .uart_offset    = 8,
1303         },
1304         [pbn_b2_16_460800] = {
1305                 .flags          = FL_BASE2,
1306                 .num_ports      = 16,
1307                 .base_baud      = 460800,
1308                 .uart_offset    = 8,
1309          },
1310
1311         [pbn_b2_1_921600] = {
1312                 .flags          = FL_BASE2,
1313                 .num_ports      = 1,
1314                 .base_baud      = 921600,
1315                 .uart_offset    = 8,
1316         },
1317         [pbn_b2_4_921600] = {
1318                 .flags          = FL_BASE2,
1319                 .num_ports      = 4,
1320                 .base_baud      = 921600,
1321                 .uart_offset    = 8,
1322         },
1323         [pbn_b2_8_921600] = {
1324                 .flags          = FL_BASE2,
1325                 .num_ports      = 8,
1326                 .base_baud      = 921600,
1327                 .uart_offset    = 8,
1328         },
1329
1330         [pbn_b2_bt_1_115200] = {
1331                 .flags          = FL_BASE2|FL_BASE_BARS,
1332                 .num_ports      = 1,
1333                 .base_baud      = 115200,
1334                 .uart_offset    = 8,
1335         },
1336         [pbn_b2_bt_2_115200] = {
1337                 .flags          = FL_BASE2|FL_BASE_BARS,
1338                 .num_ports      = 2,
1339                 .base_baud      = 115200,
1340                 .uart_offset    = 8,
1341         },
1342         [pbn_b2_bt_4_115200] = {
1343                 .flags          = FL_BASE2|FL_BASE_BARS,
1344                 .num_ports      = 4,
1345                 .base_baud      = 115200,
1346                 .uart_offset    = 8,
1347         },
1348
1349         [pbn_b2_bt_2_921600] = {
1350                 .flags          = FL_BASE2|FL_BASE_BARS,
1351                 .num_ports      = 2,
1352                 .base_baud      = 921600,
1353                 .uart_offset    = 8,
1354         },
1355         [pbn_b2_bt_4_921600] = {
1356                 .flags          = FL_BASE2|FL_BASE_BARS,
1357                 .num_ports      = 4,
1358                 .base_baud      = 921600,
1359                 .uart_offset    = 8,
1360         },
1361
1362         [pbn_b3_4_115200] = {
1363                 .flags          = FL_BASE3,
1364                 .num_ports      = 4,
1365                 .base_baud      = 115200,
1366                 .uart_offset    = 8,
1367         },
1368         [pbn_b3_8_115200] = {
1369                 .flags          = FL_BASE3,
1370                 .num_ports      = 8,
1371                 .base_baud      = 115200,
1372                 .uart_offset    = 8,
1373         },
1374
1375         /*
1376          * Entries following this are board-specific.
1377          */
1378
1379         /*
1380          * Panacom - IOMEM
1381          */
1382         [pbn_panacom] = {
1383                 .flags          = FL_BASE2,
1384                 .num_ports      = 2,
1385                 .base_baud      = 921600,
1386                 .uart_offset    = 0x400,
1387                 .reg_shift      = 7,
1388         },
1389         [pbn_panacom2] = {
1390                 .flags          = FL_BASE2|FL_BASE_BARS,
1391                 .num_ports      = 2,
1392                 .base_baud      = 921600,
1393                 .uart_offset    = 0x400,
1394                 .reg_shift      = 7,
1395         },
1396         [pbn_panacom4] = {
1397                 .flags          = FL_BASE2|FL_BASE_BARS,
1398                 .num_ports      = 4,
1399                 .base_baud      = 921600,
1400                 .uart_offset    = 0x400,
1401                 .reg_shift      = 7,
1402         },
1403
1404         /* I think this entry is broken - the first_offset looks wrong --rmk */
1405         [pbn_plx_romulus] = {
1406                 .flags          = FL_BASE2,
1407                 .num_ports      = 4,
1408                 .base_baud      = 921600,
1409                 .uart_offset    = 8 << 2,
1410                 .reg_shift      = 2,
1411                 .first_offset   = 0x03,
1412         },
1413
1414         /*
1415          * This board uses the size of PCI Base region 0 to
1416          * signal now many ports are available
1417          */
1418         [pbn_oxsemi] = {
1419                 .flags          = FL_BASE0|FL_REGION_SZ_CAP,
1420                 .num_ports      = 32,
1421                 .base_baud      = 115200,
1422                 .uart_offset    = 8,
1423         },
1424
1425         /*
1426          * EKF addition for i960 Boards form EKF with serial port.
1427          * Max 256 ports.
1428          */
1429         [pbn_intel_i960] = {
1430                 .flags          = FL_BASE0,
1431                 .num_ports      = 32,
1432                 .base_baud      = 921600,
1433                 .uart_offset    = 8 << 2,
1434                 .reg_shift      = 2,
1435                 .first_offset   = 0x10000,
1436         },
1437         [pbn_sgi_ioc3] = {
1438                 .flags          = FL_BASE0|FL_NOIRQ,
1439                 .num_ports      = 1,
1440                 .base_baud      = 458333,
1441                 .uart_offset    = 8,
1442                 .reg_shift      = 0,
1443                 .first_offset   = 0x20178,
1444         },
1445
1446         /*
1447          * NEC Vrc-5074 (Nile 4) builtin UART.
1448          */
1449         [pbn_nec_nile4] = {
1450                 .flags          = FL_BASE0,
1451                 .num_ports      = 1,
1452                 .base_baud      = 520833,
1453                 .uart_offset    = 8 << 3,
1454                 .reg_shift      = 3,
1455                 .first_offset   = 0x300,
1456         },
1457
1458         /*
1459          * Computone - uses IOMEM.
1460          */
1461         [pbn_computone_4] = {
1462                 .flags          = FL_BASE0,
1463                 .num_ports      = 4,
1464                 .base_baud      = 921600,
1465                 .uart_offset    = 0x40,
1466                 .reg_shift      = 2,
1467                 .first_offset   = 0x200,
1468         },
1469         [pbn_computone_6] = {
1470                 .flags          = FL_BASE0,
1471                 .num_ports      = 6,
1472                 .base_baud      = 921600,
1473                 .uart_offset    = 0x40,
1474                 .reg_shift      = 2,
1475                 .first_offset   = 0x200,
1476         },
1477         [pbn_computone_8] = {
1478                 .flags          = FL_BASE0,
1479                 .num_ports      = 8,
1480                 .base_baud      = 921600,
1481                 .uart_offset    = 0x40,
1482                 .reg_shift      = 2,
1483                 .first_offset   = 0x200,
1484         },
1485         [pbn_sbsxrsio] = {
1486                 .flags          = FL_BASE0,
1487                 .num_ports      = 8,
1488                 .base_baud      = 460800,
1489                 .uart_offset    = 256,
1490                 .reg_shift      = 4,
1491         }
1492 };
1493
1494 /*
1495  * Given a complete unknown PCI device, try to use some heuristics to
1496  * guess what the configuration might be, based on the pitiful PCI
1497  * serial specs.  Returns 0 on success, 1 on failure.
1498  */
1499 static int __devinit
1500 serial_pci_guess_board(struct pci_dev *dev, struct pci_board *board)
1501 {
1502         int num_iomem, num_port, first_port = -1, i;
1503
1504         /*
1505          * If it is not a communications device or the programming
1506          * interface is greater than 6, give up.
1507          *
1508          * (Should we try to make guesses for multiport serial devices
1509          * later?)
1510          */
1511         if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
1512              ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
1513             (dev->class & 0xff) > 6)
1514                 return -ENODEV;
1515
1516         num_iomem = num_port = 0;
1517         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1518                 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
1519                         num_port++;
1520                         if (first_port == -1)
1521                                 first_port = i;
1522                 }
1523                 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
1524                         num_iomem++;
1525         }
1526
1527         /*
1528          * If there is 1 or 0 iomem regions, and exactly one port,
1529          * use it.  We guess the number of ports based on the IO
1530          * region size.
1531          */
1532         if (num_iomem <= 1 && num_port == 1) {
1533                 board->flags = first_port;
1534                 board->num_ports = pci_resource_len(dev, first_port) / 8;
1535                 return 0;
1536         }
1537
1538         /*
1539          * Now guess if we've got a board which indexes by BARs.
1540          * Each IO BAR should be 8 bytes, and they should follow
1541          * consecutively.
1542          */
1543         first_port = -1;
1544         num_port = 0;
1545         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1546                 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
1547                     pci_resource_len(dev, i) == 8 &&
1548                     (first_port == -1 || (first_port + num_port) == i)) {
1549                         num_port++;
1550                         if (first_port == -1)
1551                                 first_port = i;
1552                 }
1553         }
1554
1555         if (num_port > 1) {
1556                 board->flags = first_port | FL_BASE_BARS;
1557                 board->num_ports = num_port;
1558                 return 0;
1559         }
1560
1561         return -ENODEV;
1562 }
1563
1564 static inline int
1565 serial_pci_matches(struct pci_board *board, struct pci_board *guessed)
1566 {
1567         return
1568             board->num_ports == guessed->num_ports &&
1569             board->base_baud == guessed->base_baud &&
1570             board->uart_offset == guessed->uart_offset &&
1571             board->reg_shift == guessed->reg_shift &&
1572             board->first_offset == guessed->first_offset;
1573 }
1574
1575 /*
1576  * Probe one serial board.  Unfortunately, there is no rhyme nor reason
1577  * to the arrangement of serial ports on a PCI card.
1578  */
1579 static int __devinit
1580 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
1581 {
1582         struct serial_private *priv;
1583         struct pci_board *board, tmp;
1584         struct pci_serial_quirk *quirk;
1585         struct serial_struct serial_req;
1586         int rc, nr_ports, i;
1587
1588         if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
1589                 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
1590                         ent->driver_data);
1591                 return -EINVAL;
1592         }
1593
1594         board = &pci_boards[ent->driver_data];
1595
1596         rc = pci_enable_device(dev);
1597         if (rc)
1598                 return rc;
1599
1600         if (ent->driver_data == pbn_default) {
1601                 /*
1602                  * Use a copy of the pci_board entry for this;
1603                  * avoid changing entries in the table.
1604                  */
1605                 memcpy(&tmp, board, sizeof(struct pci_board));
1606                 board = &tmp;
1607
1608                 /*
1609                  * We matched one of our class entries.  Try to
1610                  * determine the parameters of this board.
1611                  */
1612                 rc = serial_pci_guess_board(dev, board);
1613                 if (rc)
1614                         goto disable;
1615         } else {
1616                 /*
1617                  * We matched an explicit entry.  If we are able to
1618                  * detect this boards settings with our heuristic,
1619                  * then we no longer need this entry.
1620                  */
1621                 memcpy(&tmp, &pci_boards[pbn_default], sizeof(struct pci_board));
1622                 rc = serial_pci_guess_board(dev, &tmp);
1623                 if (rc == 0 && serial_pci_matches(board, &tmp))
1624                         moan_device("Redundant entry in serial pci_table.",
1625                                     dev);
1626         }
1627
1628         nr_ports = board->num_ports;
1629
1630         /*
1631          * Find an init and setup quirks.
1632          */
1633         quirk = find_quirk(dev);
1634
1635         /*
1636          * Run the new-style initialization function.
1637          * The initialization function returns:
1638          *  <0  - error
1639          *   0  - use board->num_ports
1640          *  >0  - number of ports
1641          */
1642         if (quirk->init) {
1643                 rc = quirk->init(dev);
1644                 if (rc < 0)
1645                         goto disable;
1646                 if (rc)
1647                         nr_ports = rc;
1648         }
1649
1650         priv = kmalloc(sizeof(struct serial_private) +
1651                        sizeof(unsigned int) * nr_ports,
1652                        GFP_KERNEL);
1653         if (!priv) {
1654                 rc = -ENOMEM;
1655                 goto deinit;
1656         }
1657
1658         memset(priv, 0, sizeof(struct serial_private) +
1659                         sizeof(unsigned int) * nr_ports);
1660
1661         priv->quirk = quirk;
1662         pci_set_drvdata(dev, priv);
1663
1664         for (i = 0; i < nr_ports; i++) {
1665                 memset(&serial_req, 0, sizeof(serial_req));
1666                 serial_req.flags = UPF_SKIP_TEST | UPF_AUTOPROBE |
1667                                    UPF_SHARE_IRQ;
1668                 serial_req.baud_base = board->base_baud;
1669                 serial_req.irq = get_pci_irq(dev, board, i);
1670                 if (quirk->setup(dev, board, &serial_req, i))
1671                         break;
1672 #ifdef SERIAL_DEBUG_PCI
1673                 printk("Setup PCI port: port %x, irq %d, type %d\n",
1674                        serial_req.port, serial_req.irq, serial_req.io_type);
1675 #endif
1676
1677                 priv->line[i] = register_serial(&serial_req);
1678                 if (priv->line[i] < 0) {
1679                         printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
1680                         break;
1681                 }
1682         }
1683
1684         priv->nr = i;
1685
1686         return 0;
1687
1688  deinit:
1689         if (quirk->exit)
1690                 quirk->exit(dev);
1691  disable:
1692         pci_disable_device(dev);
1693         return rc;
1694 }
1695
1696 static void __devexit pciserial_remove_one(struct pci_dev *dev)
1697 {
1698         struct serial_private *priv = pci_get_drvdata(dev);
1699
1700         pci_set_drvdata(dev, NULL);
1701
1702         if (priv) {
1703                 struct pci_serial_quirk *quirk;
1704                 int i;
1705
1706                 for (i = 0; i < priv->nr; i++)
1707                         unregister_serial(priv->line[i]);
1708
1709                 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1710                         if (priv->remapped_bar[i])
1711                                 iounmap(priv->remapped_bar[i]);
1712                         priv->remapped_bar[i] = NULL;
1713                 }
1714
1715                 /*
1716                  * Find the exit quirks.
1717                  */
1718                 quirk = find_quirk(dev);
1719                 if (quirk->exit)
1720                         quirk->exit(dev);
1721
1722                 pci_disable_device(dev);
1723
1724                 kfree(priv);
1725         }
1726 }
1727
1728 static int pciserial_suspend_one(struct pci_dev *dev, u32 state)
1729 {
1730         struct serial_private *priv = pci_get_drvdata(dev);
1731
1732         if (priv) {
1733                 int i;
1734
1735                 for (i = 0; i < priv->nr; i++)
1736                         serial8250_suspend_port(priv->line[i]);
1737         }
1738         return 0;
1739 }
1740
1741 static int pciserial_resume_one(struct pci_dev *dev)
1742 {
1743         struct serial_private *priv = pci_get_drvdata(dev);
1744
1745         if (priv) {
1746                 int i;
1747
1748                 /*
1749                  * Ensure that the board is correctly configured.
1750                  */
1751                 if (priv->quirk->init)
1752                         priv->quirk->init(dev);
1753
1754                 for (i = 0; i < priv->nr; i++)
1755                         serial8250_resume_port(priv->line[i]);
1756         }
1757         return 0;
1758 }
1759
1760 static struct pci_device_id serial_pci_tbl[] = {
1761         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1762                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1763                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1764                 pbn_b1_8_1382400 },
1765         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1766                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1767                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1768                 pbn_b1_4_1382400 },
1769         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1770                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1771                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1772                 pbn_b1_2_1382400 },
1773         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1774                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1775                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1776                 pbn_b1_8_1382400 },
1777         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1778                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1779                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1780                 pbn_b1_4_1382400 },
1781         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1782                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1783                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1784                 pbn_b1_2_1382400 },
1785         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1786                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1787                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
1788                 pbn_b1_8_921600 },
1789         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1790                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1791                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
1792                 pbn_b1_8_921600 },
1793         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1794                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1795                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
1796                 pbn_b1_4_921600 },
1797         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1798                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1799                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
1800                 pbn_b1_4_921600 },
1801         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1802                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1803                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
1804                 pbn_b1_2_921600 },
1805         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1806                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1807                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
1808                 pbn_b1_8_921600 },
1809         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1810                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1811                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
1812                 pbn_b1_8_921600 },
1813         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1814                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1815                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
1816                 pbn_b1_4_921600 },
1817
1818         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
1819                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1820                 pbn_b2_bt_1_115200 },
1821         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
1822                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1823                 pbn_b2_bt_2_115200 },
1824         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
1825                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1826                 pbn_b2_bt_4_115200 },
1827         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
1828                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1829                 pbn_b2_bt_2_115200 },
1830         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
1831                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1832                 pbn_b2_bt_4_115200 },
1833         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
1834                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1835                 pbn_b2_8_115200 },
1836
1837         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
1838                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1839                 pbn_b2_bt_2_115200 },
1840         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
1841                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1842                 pbn_b2_bt_2_921600 },
1843         /*
1844          * VScom SPCOM800, from sl@s.pl
1845          */
1846         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
1847                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1848                 pbn_b2_8_921600 },
1849         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
1850                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1851                 pbn_b2_4_921600 },
1852         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1853                 PCI_SUBVENDOR_ID_KEYSPAN,
1854                 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
1855                 pbn_panacom },
1856         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
1857                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1858                 pbn_panacom4 },
1859         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
1860                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1861                 pbn_panacom2 },
1862         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1863                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1864                 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
1865                 pbn_b2_4_460800 },
1866         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1867                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1868                 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
1869                 pbn_b2_8_460800 },
1870         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1871                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1872                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
1873                 pbn_b2_16_460800 },
1874         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1875                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1876                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
1877                 pbn_b2_16_460800 },
1878         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1879                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
1880                 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
1881                 pbn_b2_4_460800 },
1882         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1883                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
1884                 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
1885                 pbn_b2_8_460800 },
1886         /*
1887          * Megawolf Romulus PCI Serial Card, from Mike Hudson
1888          * (Exoray@isys.ca)
1889          */
1890         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
1891                 0x10b5, 0x106a, 0, 0,
1892                 pbn_plx_romulus },
1893         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
1894                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1895                 pbn_b1_4_115200 },
1896         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
1897                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1898                 pbn_b1_2_115200 },
1899         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
1900                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1901                 pbn_b1_8_115200 },
1902         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
1903                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1904                 pbn_b1_8_115200 },
1905         {       PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
1906                 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 0, 0,
1907                 pbn_b0_4_921600 },
1908         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1909                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1910                 pbn_b0_4_115200 },
1911         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
1912                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1913                 pbn_b0_bt_2_921600 },
1914
1915         /*
1916          * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
1917          * from skokodyn@yahoo.com
1918          */
1919         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1920                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
1921                 pbn_sbsxrsio },
1922         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1923                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
1924                 pbn_sbsxrsio },
1925         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1926                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
1927                 pbn_sbsxrsio },
1928         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1929                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
1930                 pbn_sbsxrsio },
1931
1932         /*
1933          * Digitan DS560-558, from jimd@esoft.com
1934          */
1935         {       PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
1936                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1937                 pbn_b1_1_115200 },
1938
1939         /*
1940          * Titan Electronic cards
1941          *  The 400L and 800L have a custom setup quirk.
1942          */
1943         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
1944                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1945                 pbn_b0_1_921600 },
1946         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
1947                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1948                 pbn_b0_2_921600 },
1949         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
1950                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1951                 pbn_b0_4_921600 },
1952         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
1953                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1954                 pbn_b0_4_921600 },
1955         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
1956                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1957                 pbn_b1_1_921600 },
1958         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
1959                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1960                 pbn_b1_bt_2_921600 },
1961         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
1962                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1963                 pbn_b0_bt_4_921600 },
1964         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
1965                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1966                 pbn_b0_bt_8_921600 },
1967
1968         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
1969                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1970                 pbn_b2_1_460800 },
1971         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
1972                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1973                 pbn_b2_1_460800 },
1974         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
1975                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1976                 pbn_b2_1_460800 },
1977         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
1978                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1979                 pbn_b2_bt_2_921600 },
1980         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
1981                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1982                 pbn_b2_bt_2_921600 },
1983         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
1984                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1985                 pbn_b2_bt_2_921600 },
1986         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
1987                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1988                 pbn_b2_bt_4_921600 },
1989         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
1990                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1991                 pbn_b2_bt_4_921600 },
1992         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
1993                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1994                 pbn_b2_bt_4_921600 },
1995         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
1996                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1997                 pbn_b0_1_921600 },
1998         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
1999                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2000                 pbn_b0_1_921600 },
2001         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
2002                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2003                 pbn_b0_1_921600 },
2004         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
2005                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2006                 pbn_b0_bt_2_921600 },
2007         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
2008                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2009                 pbn_b0_bt_2_921600 },
2010         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
2011                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2012                 pbn_b0_bt_2_921600 },
2013         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
2014                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2015                 pbn_b0_bt_4_921600 },
2016         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
2017                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2018                 pbn_b0_bt_4_921600 },
2019         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
2020                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2021                 pbn_b0_bt_4_921600 },
2022
2023         /*
2024          * Computone devices submitted by Doug McNash dmcnash@computone.com
2025          */
2026         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2027                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
2028                 0, 0, pbn_computone_4 },
2029         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2030                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
2031                 0, 0, pbn_computone_8 },
2032         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2033                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
2034                 0, 0, pbn_computone_6 },
2035
2036         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
2037                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2038                 pbn_oxsemi },
2039         {       PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
2040                 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
2041                 pbn_b0_bt_1_921600 },
2042
2043         /*
2044          * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
2045          */
2046         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
2047                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2048                 pbn_b0_bt_8_115200 },
2049         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
2050                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2051                 pbn_b0_bt_8_115200 },
2052
2053         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
2054                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2055                 pbn_b0_bt_2_115200 },
2056         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
2057                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2058                 pbn_b0_bt_2_115200 },
2059         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
2060                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2061                 pbn_b0_bt_2_115200 },
2062         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
2063                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2064                 pbn_b0_bt_4_460800 },
2065         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
2066                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2067                 pbn_b0_bt_4_460800 },
2068         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
2069                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2070                 pbn_b0_bt_2_460800 },
2071         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
2072                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2073                 pbn_b0_bt_2_460800 },
2074         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
2075                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2076                 pbn_b0_bt_2_460800 },
2077         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
2078                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2079                 pbn_b0_bt_1_115200 },
2080         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
2081                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2082                 pbn_b0_bt_1_460800 },
2083
2084         /*
2085          * RAStel 2 port modem, gerg@moreton.com.au
2086          */
2087         {       PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
2088                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2089                 pbn_b2_bt_2_115200 },
2090
2091         /*
2092          * EKF addition for i960 Boards form EKF with serial port
2093          */
2094         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
2095                 0xE4BF, PCI_ANY_ID, 0, 0,
2096                 pbn_intel_i960 },
2097
2098         /*
2099          * Xircom Cardbus/Ethernet combos
2100          */
2101         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2102                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2103                 pbn_b0_1_115200 },
2104         /*
2105          * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
2106          */
2107         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
2108                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2109                 pbn_b0_1_115200 },
2110
2111         /*
2112          * Untested PCI modems, sent in from various folks...
2113          */
2114
2115         /*
2116          * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
2117          */
2118         {       PCI_VENDOR_ID_ROCKWELL, 0x1004,
2119                 0x1048, 0x1500, 0, 0,
2120                 pbn_b1_1_115200 },
2121
2122         {       PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
2123                 0xFF00, 0, 0, 0,
2124                 pbn_sgi_ioc3 },
2125
2126         /*
2127          * HP Diva card
2128          */
2129         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2130                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2131                 pbn_b0_5_115200 },
2132         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
2133                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2134                 pbn_b2_1_115200 },
2135
2136         /*
2137          * NEC Vrc-5074 (Nile 4) builtin UART.
2138          */
2139         {       PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_NILE4,
2140                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2141                 pbn_nec_nile4 },
2142
2143         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
2144                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2145                 pbn_b3_4_115200 },
2146         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
2147                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2148                 pbn_b3_8_115200 },
2149
2150         /*
2151          * These entries match devices with class COMMUNICATION_SERIAL,
2152          * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
2153          */
2154         {       PCI_ANY_ID, PCI_ANY_ID,
2155                 PCI_ANY_ID, PCI_ANY_ID,
2156                 PCI_CLASS_COMMUNICATION_SERIAL << 8,
2157                 0xffff00, pbn_default },
2158         {       PCI_ANY_ID, PCI_ANY_ID,
2159                 PCI_ANY_ID, PCI_ANY_ID,
2160                 PCI_CLASS_COMMUNICATION_MODEM << 8,
2161                 0xffff00, pbn_default },
2162         {       PCI_ANY_ID, PCI_ANY_ID,
2163                 PCI_ANY_ID, PCI_ANY_ID,
2164                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
2165                 0xffff00, pbn_default },
2166         { 0, }
2167 };
2168
2169 static struct pci_driver serial_pci_driver = {
2170         .name           = "serial",
2171         .probe          = pciserial_init_one,
2172         .remove         = __devexit_p(pciserial_remove_one),
2173         .suspend        = pciserial_suspend_one,
2174         .resume         = pciserial_resume_one,
2175         .id_table       = serial_pci_tbl,
2176 };
2177
2178 static int __init serial8250_pci_init(void)
2179 {
2180         return pci_module_init(&serial_pci_driver);
2181 }
2182
2183 static void __exit serial8250_pci_exit(void)
2184 {
2185         pci_unregister_driver(&serial_pci_driver);
2186 }
2187
2188 module_init(serial8250_pci_init);
2189 module_exit(serial8250_pci_exit);
2190
2191 MODULE_LICENSE("GPL");
2192 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
2193 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);