drivers/serial/8250_pci.c

   1 /*
   2  *  linux/drivers/char/8250_pci.c
   3  *
   4  *  Probe module for 8250/16550-type PCI serial ports.
   5  *
   6  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   7  *
   8  *  Copyright (C) 2001 Russell King, All Rights Reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License.
  13  *
  14  *  $Id: 8250_pci.c,v 1.28 2002/11/02 11:14:18 rmk Exp $
  15  */
  16 #include <linux/module.h>
  17 #include <linux/init.h>
  18 #include <linux/pci.h>
  19 #include <linux/sched.h>
  20 #include <linux/string.h>
  21 #include <linux/kernel.h>
  22 #include <linux/slab.h>
  23 #include <linux/delay.h>
  24 #include <linux/tty.h>
  25 #include <linux/serial.h>
  26 #include <linux/serial_core.h>
  27 #include <linux/8250_pci.h>
  28
  29 #include <asm/bitops.h>
  30 #include <asm/byteorder.h>
  31 #include <asm/io.h>
  32
  33 #include "8250.h"
  34
  35 /*
  36  * Definitions for PCI support.
  37  */
  38 #define FL_BASE_MASK            0x0007
  39 #define FL_BASE0                0x0000
  40 #define FL_BASE1                0x0001
  41 #define FL_BASE2                0x0002
  42 #define FL_BASE3                0x0003
  43 #define FL_BASE4                0x0004
  44 #define FL_GET_BASE(x)          (x & FL_BASE_MASK)
  45
  46 /* Use successive BARs (PCI base address registers),
  47    else use offset into some specified BAR */
  48 #define FL_BASE_BARS            0x0008
  49
  50 /* do not assign an irq */
  51 #define FL_NOIRQ                0x0080
  52
  53 /* Use the Base address register size to cap number of ports */
  54 #define FL_REGION_SZ_CAP        0x0100
  55
  56 struct pci_board {
  57         unsigned int flags;
  58         unsigned int num_ports;
  59         unsigned int base_baud;
  60         unsigned int uart_offset;
  61         unsigned int reg_shift;
  62         unsigned int first_offset;
  63 };
  64
  65 /*
  66  * init function returns:
  67  *  > 0 - number of ports
  68  *  = 0 - use board->num_ports
  69  *  < 0 - error
  70  */
  71 struct pci_serial_quirk {
  72         u32     vendor;
  73         u32     device;
  74         u32     subvendor;
  75         u32     subdevice;
  76         int     (*init)(struct pci_dev *dev);
  77         int     (*setup)(struct pci_dev *dev, struct pci_board *board,
  78                          struct serial_struct *req, int idx);
  79         void    (*exit)(struct pci_dev *dev);
  80 };
  81
  82 #define PCI_NUM_BAR_RESOURCES   6
  83
  84 struct serial_private {
  85         unsigned int            nr;
  86         void                    *remapped_bar[PCI_NUM_BAR_RESOURCES];
  87         struct pci_serial_quirk *quirk;
  88         int                     line[0];
  89 };
  90
  91 static void moan_device(const char *str, struct pci_dev *dev)
  92 {
  93         printk(KERN_WARNING "%s: %s\n"
  94                KERN_WARNING "Please send the output of lspci -vv, this\n"
  95                KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
  96                KERN_WARNING "manufacturer and name of serial board or\n"
  97                KERN_WARNING "modem board to rmk+serial@arm.linux.org.uk.\n",
  98                pci_name(dev), str, dev->vendor, dev->device,
  99                dev->subsystem_vendor, dev->subsystem_device);
 100 }
 101
 102 static int
 103 setup_port(struct pci_dev *dev, struct serial_struct *req,
 104            int bar, int offset, int regshift)
 105 {
 106         struct serial_private *priv = pci_get_drvdata(dev);
 107         unsigned long port, len;
 108
 109         if (bar >= PCI_NUM_BAR_RESOURCES)
 110                 return -EINVAL;
 111
 112         if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
 113                 port = pci_resource_start(dev, bar);
 114                 len =  pci_resource_len(dev, bar);
 115
 116                 if (!priv->remapped_bar[bar])
 117                         priv->remapped_bar[bar] = ioremap(port, len);
 118                 if (!priv->remapped_bar[bar])
 119                         return -ENOMEM;
 120
 121                 req->io_type = UPIO_MEM;
 122                 req->iomap_base = port + offset;
 123                 req->iomem_base = priv->remapped_bar[bar] + offset;
 124                 req->iomem_reg_shift = regshift;
 125         } else {
 126                 port = pci_resource_start(dev, bar) + offset;
 127                 req->io_type = UPIO_PORT;
 128                 req->port = port;
 129                 if (HIGH_BITS_OFFSET)
 130                         req->port_high = port >> HIGH_BITS_OFFSET;
 131         }
 132         return 0;
 133 }
 134
 135 /*
 136  * AFAVLAB uses a different mixture of BARs and offsets
 137  * Not that ugly ;) -- HW
 138  */
 139 static int
 140 afavlab_setup(struct pci_dev *dev, struct pci_board *board,
 141               struct serial_struct *req, int idx)
 142 {
 143         unsigned int bar, offset = board->first_offset;
 144
 145         bar = FL_GET_BASE(board->flags);
 146         if (idx < 4)
 147                 bar += idx;
 148         else {
 149                 bar = 4;
 150                 offset += (idx - 4) * board->uart_offset;
 151         }
 152
 153         return setup_port(dev, req, bar, offset, board->reg_shift);
 154 }
 155
 156 /*
 157  * HP's Remote Management Console.  The Diva chip came in several
 158  * different versions.  N-class, L2000 and A500 have two Diva chips, each
 159  * with 3 UARTs (the third UART on the second chip is unused).  Superdome
 160  * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
 161  * one Diva chip, but it has been expanded to 5 UARTs.
 162  */
 163 static int __devinit pci_hp_diva_init(struct pci_dev *dev)
 164 {
 165         int rc = 0;
 166
 167         switch (dev->subsystem_device) {
 168         case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
 169         case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
 170         case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
 171         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 172                 rc = 3;
 173                 break;
 174         case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
 175                 rc = 2;
 176                 break;
 177         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 178                 rc = 4;
 179                 break;
 180         case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
 181                 rc = 1;
 182                 break;
 183         }
 184
 185         return rc;
 186 }
 187
 188 /*
 189  * HP's Diva chip puts the 4th/5th serial port further out, and
 190  * some serial ports are supposed to be hidden on certain models.
 191  */
 192 static int
 193 pci_hp_diva_setup(struct pci_dev *dev, struct pci_board *board,
 194               struct serial_struct *req, int idx)
 195 {
 196         unsigned int offset = board->first_offset;
 197         unsigned int bar = FL_GET_BASE(board->flags);
 198
 199         switch (dev->subsystem_device) {
 200         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 201                 if (idx == 3)
 202                         idx++;
 203                 break;
 204         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 205                 if (idx > 0)
 206                         idx++;
 207                 if (idx > 2)
 208                         idx++;
 209                 break;
 210         }
 211         if (idx > 2)
 212                 offset = 0x18;
 213
 214         offset += idx * board->uart_offset;
 215
 216         return setup_port(dev, req, bar, offset, board->reg_shift);
 217 }
 218
 219 /*
 220  * Added for EKF Intel i960 serial boards
 221  */
 222 static int __devinit pci_inteli960ni_init(struct pci_dev *dev)
 223 {
 224         unsigned long oldval;
 225
 226         if (!(dev->subsystem_device & 0x1000))
 227                 return -ENODEV;
 228
 229         /* is firmware started? */
 230         pci_read_config_dword(dev, 0x44, (void*) &oldval);
 231         if (oldval == 0x00001000L) { /* RESET value */
 232                 printk(KERN_DEBUG "Local i960 firmware missing");
 233                 return -ENODEV;
 234         }
 235         return 0;
 236 }
 237
 238 /*
 239  * Some PCI serial cards using the PLX 9050 PCI interface chip require
 240  * that the card interrupt be explicitly enabled or disabled.  This
 241  * seems to be mainly needed on card using the PLX which also use I/O
 242  * mapped memory.
 243  */
 244 static int __devinit pci_plx9050_init(struct pci_dev *dev)
 245 {
 246         u8 *p, irq_config;
 247
 248         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
 249                 moan_device("no memory in bar 0", dev);
 250                 return 0;
 251         }
 252
 253         irq_config = 0x41;
 254         if (dev->vendor == PCI_VENDOR_ID_PANACOM)
 255                 irq_config = 0x43;
 256         if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
 257             (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) {
 258                 /*
 259                  * As the megawolf cards have the int pins active
 260                  * high, and have 2 UART chips, both ints must be
 261                  * enabled on the 9050. Also, the UARTS are set in
 262                  * 16450 mode by default, so we have to enable the
 263                  * 16C950 'enhanced' mode so that we can use the
 264                  * deep FIFOs
 265                  */
 266                 irq_config = 0x5b;
 267         }
 268
 269         /*
 270          * enable/disable interrupts
 271          */
 272         p = ioremap(pci_resource_start(dev, 0), 0x80);
 273         if (p == NULL)
 274                 return -ENOMEM;
 275         writel(irq_config, (unsigned long)p + 0x4c);
 276
 277         /*
 278          * Read the register back to ensure that it took effect.
 279          */
 280         readl((unsigned long)p + 0x4c);
 281         iounmap(p);
 282
 283         return 0;
 284 }
 285
 286 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
 287 {
 288         u8 *p;
 289
 290         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
 291                 return;
 292
 293         /*
 294          * disable interrupts
 295          */
 296         p = ioremap(pci_resource_start(dev, 0), 0x80);
 297         if (p != NULL) {
 298                 writel(0, p + 0x4c);
 299
 300                 /*
 301                  * Read the register back to ensure that it took effect.
 302                  */
 303                 readl(p + 0x4c);
 304                 iounmap(p);
 305         }
 306 }
 307
 308 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
 309 static int
 310 sbs_setup(struct pci_dev *dev, struct pci_board *board,
 311                 struct serial_struct *req, int idx)
 312 {
 313         unsigned int bar, offset = board->first_offset;
 314
 315         bar = 0;
 316
 317         if (idx < 4) {
 318                 /* first four channels map to 0, 0x100, 0x200, 0x300 */
 319                 offset += idx * board->uart_offset;
 320         } else if (idx < 8) {
 321                 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
 322                 offset += idx * board->uart_offset + 0xC00;
 323         } else /* we have only 8 ports on PMC-OCTALPRO */
 324                 return 1;
 325
 326         return setup_port(dev, req, bar, offset, board->reg_shift);
 327 }
 328
 329 /*
 330 * This does initialization for PMC OCTALPRO cards:
 331 * maps the device memory, resets the UARTs (needed, bc
 332 * if the module is removed and inserted again, the card
 333 * is in the sleep mode) and enables global interrupt.
 334 */
 335
 336 /* global control register offset for SBS PMC-OctalPro */
 337 #define OCT_REG_CR_OFF          0x500
 338
 339 static int __devinit sbs_init(struct pci_dev *dev)
 340 {
 341         u8 * p;
 342
 343         p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
 344
 345         if (p == NULL)
 346                 return -ENOMEM;
 347         /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
 348         writeb(0x10,p + OCT_REG_CR_OFF);
 349         udelay(50);
 350         writeb(0x0,p + OCT_REG_CR_OFF);
 351
 352         /* Set bit-2 (INTENABLE) of Control Register */
 353         writeb(0x4, p + OCT_REG_CR_OFF);
 354         iounmap(p);
 355
 356         return 0;
 357 }
 358
 359 /*
 360  * Disables the global interrupt of PMC-OctalPro
 361  */
 362
 363 static void __devexit sbs_exit(struct pci_dev *dev)
 364 {
 365         u8 * p;
 366
 367         p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
 368         if (p != NULL) {
 369                 writeb(0, p + OCT_REG_CR_OFF);
 370         }
 371         iounmap(p);
 372 }
 373
 374 /*
 375  * SIIG serial cards have an PCI interface chip which also controls
 376  * the UART clocking frequency. Each UART can be clocked independently
 377  * (except cards equiped with 4 UARTs) and initial clocking settings
 378  * are stored in the EEPROM chip. It can cause problems because this
 379  * version of serial driver doesn't support differently clocked UART's
 380  * on single PCI card. To prevent this, initialization functions set
 381  * high frequency clocking for all UART's on given card. It is safe (I
 382  * hope) because it doesn't touch EEPROM settings to prevent conflicts
 383  * with other OSes (like M$ DOS).
 384  *
 385  *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
 386  *
 387  * There is two family of SIIG serial cards with different PCI
 388  * interface chip and different configuration methods:
 389  *     - 10x cards have control registers in IO and/or memory space;
 390  *     - 20x cards have control registers in standard PCI configuration space.
 391  *
 392  * Note: some SIIG cards are probed by the parport_serial object.
 393  */
 394
 395 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
 396 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
 397
 398 static int pci_siig10x_init(struct pci_dev *dev)
 399 {
 400         u16 data, *p;
 401
 402         switch (dev->device & 0xfff8) {
 403         case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
 404                 data = 0xffdf;
 405                 break;
 406         case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
 407                 data = 0xf7ff;
 408                 break;
 409         default:                        /* 1S1P, 4S */
 410                 data = 0xfffb;
 411                 break;
 412         }
 413
 414         p = ioremap(pci_resource_start(dev, 0), 0x80);
 415         if (p == NULL)
 416                 return -ENOMEM;
 417
 418         writew(readw((unsigned long) p + 0x28) & data, (unsigned long) p + 0x28);
 419         readw((unsigned long)p + 0x28);
 420         iounmap(p);
 421         return 0;
 422 }
 423
 424 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
 425 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
 426
 427 static int pci_siig20x_init(struct pci_dev *dev)
 428 {
 429         u8 data;
 430
 431         /* Change clock frequency for the first UART. */
 432         pci_read_config_byte(dev, 0x6f, &data);
 433         pci_write_config_byte(dev, 0x6f, data & 0xef);
 434
 435         /* If this card has 2 UART, we have to do the same with second UART. */
 436         if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
 437             ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
 438                 pci_read_config_byte(dev, 0x73, &data);
 439                 pci_write_config_byte(dev, 0x73, data & 0xef);
 440         }
 441         return 0;
 442 }
 443
 444 int pci_siig10x_fn(struct pci_dev *dev, int enable)
 445 {
 446         int ret = 0;
 447         if (enable)
 448                 ret = pci_siig10x_init(dev);
 449         return ret;
 450 }
 451
 452 int pci_siig20x_fn(struct pci_dev *dev, int enable)
 453 {
 454         int ret = 0;
 455         if (enable)
 456                 ret = pci_siig20x_init(dev);
 457         return ret;
 458 }
 459
 460 EXPORT_SYMBOL(pci_siig10x_fn);
 461 EXPORT_SYMBOL(pci_siig20x_fn);
 462
 463 /*
 464  * Timedia has an explosion of boards, and to avoid the PCI table from
 465  * growing *huge*, we use this function to collapse some 70 entries
 466  * in the PCI table into one, for sanity's and compactness's sake.
 467  */
 468 static unsigned short timedia_single_port[] = {
 469         0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
 470 };
 471
 472 static unsigned short timedia_dual_port[] = {
 473         0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
 474         0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
 475         0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
 476         0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
 477         0xD079, 0
 478 };
 479
 480 static unsigned short timedia_quad_port[] = {
 481         0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
 482         0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
 483         0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
 484         0xB157, 0
 485 };
 486
 487 static unsigned short timedia_eight_port[] = {
 488         0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
 489         0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
 490 };
 491
 492 static struct timedia_struct {
 493         int num;
 494         unsigned short *ids;
 495 } timedia_data[] = {
 496         { 1, timedia_single_port },
 497         { 2, timedia_dual_port },
 498         { 4, timedia_quad_port },
 499         { 8, timedia_eight_port },
 500         { 0, 0 }
 501 };
 502
 503 static int __devinit pci_timedia_init(struct pci_dev *dev)
 504 {
 505         unsigned short *ids;
 506         int i, j;
 507
 508         for (i = 0; timedia_data[i].num; i++) {
 509                 ids = timedia_data[i].ids;
 510                 for (j = 0; ids[j]; j++)
 511                         if (dev->subsystem_device == ids[j])
 512                                 return timedia_data[i].num;
 513         }
 514         return 0;
 515 }
 516
 517 /*
 518  * Timedia/SUNIX uses a mixture of BARs and offsets
 519  * Ugh, this is ugly as all hell --- TYT
 520  */
 521 static int
 522 pci_timedia_setup(struct pci_dev *dev, struct pci_board *board,
 523                   struct serial_struct *req, int idx)
 524 {
 525         unsigned int bar = 0, offset = board->first_offset;
 526
 527         switch (idx) {
 528         case 0:
 529                 bar = 0;
 530                 break;
 531         case 1:
 532                 offset = board->uart_offset;
 533                 bar = 0;
 534                 break;
 535         case 2:
 536                 bar = 1;
 537                 break;
 538         case 3:
 539                 offset = board->uart_offset;
 540                 bar = 1;
 541         case 4: /* BAR 2 */
 542         case 5: /* BAR 3 */
 543         case 6: /* BAR 4 */
 544         case 7: /* BAR 5 */
 545                 bar = idx - 2;
 546         }
 547
 548         return setup_port(dev, req, bar, offset, board->reg_shift);
 549 }
 550
 551 /*
 552  * Some Titan cards are also a little weird
 553  */
 554 static int
 555 titan_400l_800l_setup(struct pci_dev *dev, struct pci_board *board,
 556                       struct serial_struct *req, int idx)
 557 {
 558         unsigned int bar, offset = board->first_offset;
 559
 560         switch (idx) {
 561         case 0:
 562                 bar = 1;
 563                 break;
 564         case 1:
 565                 bar = 2;
 566                 break;
 567         default:
 568                 bar = 4;
 569                 offset = (idx - 2) * board->uart_offset;
 570         }
 571
 572         return setup_port(dev, req, bar, offset, board->reg_shift);
 573 }
 574
 575 static int __devinit pci_xircom_init(struct pci_dev *dev)
 576 {
 577         __set_current_state(TASK_UNINTERRUPTIBLE);
 578         schedule_timeout(HZ/10);
 579         return 0;
 580 }
 581
 582 static int
 583 pci_default_setup(struct pci_dev *dev, struct pci_board *board,
 584                   struct serial_struct *req, int idx)
 585 {
 586         unsigned int bar, offset = board->first_offset, maxnr;
 587
 588         bar = FL_GET_BASE(board->flags);
 589         if (board->flags & FL_BASE_BARS)
 590                 bar += idx;
 591         else
 592                 offset += idx * board->uart_offset;
 593
 594         maxnr = (pci_resource_len(dev, bar) - board->first_offset) /
 595                 (8 << board->reg_shift);
 596
 597         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
 598                 return 1;
 599
 600         return setup_port(dev, req, bar, offset, board->reg_shift);
 601 }
 602
 603 /* This should be in linux/pci_ids.h */
 604 #define PCI_VENDOR_ID_SBSMODULARIO      0x124B
 605 #define PCI_SUBVENDOR_ID_SBSMODULARIO   0x124B
 606 #define PCI_DEVICE_ID_OCTPRO            0x0001
 607 #define PCI_SUBDEVICE_ID_OCTPRO232      0x0108
 608 #define PCI_SUBDEVICE_ID_OCTPRO422      0x0208
 609 #define PCI_SUBDEVICE_ID_POCTAL232      0x0308
 610 #define PCI_SUBDEVICE_ID_POCTAL422      0x0408
 611
 612 /*
 613  * Master list of serial port init/setup/exit quirks.
 614  * This does not describe the general nature of the port.
 615  * (ie, baud base, number and location of ports, etc)
 616  *
 617  * This list is ordered alphabetically by vendor then device.
 618  * Specific entries must come before more generic entries.
 619  */
 620 static struct pci_serial_quirk pci_serial_quirks[] = {
 621         /*
 622          * AFAVLAB cards.
 623          *  It is not clear whether this applies to all products.
 624          */
 625         {
 626                 .vendor         = PCI_VENDOR_ID_AFAVLAB,
 627                 .device         = PCI_ANY_ID,
 628                 .subvendor      = PCI_ANY_ID,
 629                 .subdevice      = PCI_ANY_ID,
 630                 .setup          = afavlab_setup,
 631         },
 632         /*
 633          * HP Diva
 634          */
 635         {
 636                 .vendor         = PCI_VENDOR_ID_HP,
 637                 .device         = PCI_DEVICE_ID_HP_DIVA,
 638                 .subvendor      = PCI_ANY_ID,
 639                 .subdevice      = PCI_ANY_ID,
 640                 .init           = pci_hp_diva_init,
 641                 .setup          = pci_hp_diva_setup,
 642         },
 643         /*
 644          * Intel
 645          */
 646         {
 647                 .vendor         = PCI_VENDOR_ID_INTEL,
 648                 .device         = PCI_DEVICE_ID_INTEL_80960_RP,
 649                 .subvendor      = 0xe4bf,
 650                 .subdevice      = PCI_ANY_ID,
 651                 .init           = pci_inteli960ni_init,
 652                 .setup          = pci_default_setup,
 653         },
 654         /*
 655          * Panacom
 656          */
 657         {
 658                 .vendor         = PCI_VENDOR_ID_PANACOM,
 659                 .device         = PCI_DEVICE_ID_PANACOM_QUADMODEM,
 660                 .subvendor      = PCI_ANY_ID,
 661                 .subdevice      = PCI_ANY_ID,
 662                 .init           = pci_plx9050_init,
 663                 .setup          = pci_default_setup,
 664                 .exit           = __devexit_p(pci_plx9050_exit),
 665         },
 666         {
 667                 .vendor         = PCI_VENDOR_ID_PANACOM,
 668                 .device         = PCI_DEVICE_ID_PANACOM_DUALMODEM,
 669                 .subvendor      = PCI_ANY_ID,
 670                 .subdevice      = PCI_ANY_ID,
 671                 .init           = pci_plx9050_init,
 672                 .setup          = pci_default_setup,
 673                 .exit           = __devexit_p(pci_plx9050_exit),
 674         },
 675         /*
 676          * PLX
 677          */
 678         {
 679                 .vendor         = PCI_VENDOR_ID_PLX,
 680                 .device         = PCI_DEVICE_ID_PLX_9050,
 681                 .subvendor      = PCI_SUBVENDOR_ID_KEYSPAN,
 682                 .subdevice      = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
 683                 .init           = pci_plx9050_init,
 684                 .setup          = pci_default_setup,
 685                 .exit           = __devexit_p(pci_plx9050_exit),
 686         },
 687         {
 688                 .vendor         = PCI_VENDOR_ID_PLX,
 689                 .device         = PCI_DEVICE_ID_PLX_ROMULUS,
 690                 .subvendor      = PCI_VENDOR_ID_PLX,
 691                 .subdevice      = PCI_DEVICE_ID_PLX_ROMULUS,
 692                 .init           = pci_plx9050_init,
 693                 .setup          = pci_default_setup,
 694                 .exit           = __devexit_p(pci_plx9050_exit),
 695         },
 696         /*
 697          * SBS Technologies, Inc., PMC-OCTALPRO 232
 698          */
 699         {
 700                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 701                 .device         = PCI_DEVICE_ID_OCTPRO,
 702                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 703                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO232,
 704                 .init           = sbs_init,
 705                 .setup          = sbs_setup,
 706                 .exit           = __devexit_p(sbs_exit),
 707         },
 708         /*
 709          * SBS Technologies, Inc., PMC-OCTALPRO 422
 710          */
 711         {
 712                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 713                 .device         = PCI_DEVICE_ID_OCTPRO,
 714                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 715                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO422,
 716                 .init           = sbs_init,
 717                 .setup          = sbs_setup,
 718                 .exit           = __devexit_p(sbs_exit),
 719         },
 720         /*
 721          * SBS Technologies, Inc., P-Octal 232
 722          */
 723         {
 724                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 725                 .device         = PCI_DEVICE_ID_OCTPRO,
 726                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 727                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL232,
 728                 .init           = sbs_init,
 729                 .setup          = sbs_setup,
 730                 .exit           = __devexit_p(sbs_exit),
 731         },
 732         /*
 733          * SBS Technologies, Inc., P-Octal 422
 734          */
 735         {
 736                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 737                 .device         = PCI_DEVICE_ID_OCTPRO,
 738                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 739                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL422,
 740                 .init           = sbs_init,
 741                 .setup          = sbs_setup,
 742                 .exit           = __devexit_p(sbs_exit),
 743         },
 744
 745         /*
 746          * SIIG cards.
 747          *  It is not clear whether these could be collapsed.
 748          */
 749         {
 750                 .vendor         = PCI_VENDOR_ID_SIIG,
 751                 .device         = PCI_DEVICE_ID_SIIG_1S_10x_550,
 752                 .subvendor      = PCI_ANY_ID,
 753                 .subdevice      = PCI_ANY_ID,
 754                 .init           = pci_siig10x_init,
 755                 .setup          = pci_default_setup,
 756         },
 757         {
 758                 .vendor         = PCI_VENDOR_ID_SIIG,
 759                 .device         = PCI_DEVICE_ID_SIIG_1S_10x_650,
 760                 .subvendor      = PCI_ANY_ID,
 761                 .subdevice      = PCI_ANY_ID,
 762                 .init           = pci_siig10x_init,
 763                 .setup          = pci_default_setup,
 764         },
 765         {
 766                 .vendor         = PCI_VENDOR_ID_SIIG,
 767                 .device         = PCI_DEVICE_ID_SIIG_1S_10x_850,
 768                 .subvendor      = PCI_ANY_ID,
 769                 .subdevice      = PCI_ANY_ID,
 770                 .init           = pci_siig10x_init,
 771                 .setup          = pci_default_setup,
 772         },
 773         {
 774                 .vendor         = PCI_VENDOR_ID_SIIG,
 775                 .device         = PCI_DEVICE_ID_SIIG_2S_10x_550,
 776                 .subvendor      = PCI_ANY_ID,
 777                 .subdevice      = PCI_ANY_ID,
 778                 .init           = pci_siig10x_init,
 779                 .setup          = pci_default_setup,
 780         },
 781         {
 782                 .vendor         = PCI_VENDOR_ID_SIIG,
 783                 .device         = PCI_DEVICE_ID_SIIG_2S_10x_650,
 784                 .subvendor      = PCI_ANY_ID,
 785                 .subdevice      = PCI_ANY_ID,
 786                 .init           = pci_siig10x_init,
 787                 .setup          = pci_default_setup,
 788         },
 789         {
 790                 .vendor         = PCI_VENDOR_ID_SIIG,
 791                 .device         = PCI_DEVICE_ID_SIIG_2S_10x_850,
 792                 .subvendor      = PCI_ANY_ID,
 793                 .subdevice      = PCI_ANY_ID,
 794                 .init           = pci_siig10x_init,
 795                 .setup          = pci_default_setup,
 796         },
 797         {
 798                 .vendor         = PCI_VENDOR_ID_SIIG,
 799                 .device         = PCI_DEVICE_ID_SIIG_4S_10x_550,
 800                 .subvendor      = PCI_ANY_ID,
 801                 .subdevice      = PCI_ANY_ID,
 802                 .init           = pci_siig10x_init,
 803                 .setup          = pci_default_setup,
 804         },
 805         {
 806                 .vendor         = PCI_VENDOR_ID_SIIG,
 807                 .device         = PCI_DEVICE_ID_SIIG_4S_10x_650,
 808                 .subvendor      = PCI_ANY_ID,
 809                 .subdevice      = PCI_ANY_ID,
 810                 .init           = pci_siig10x_init,
 811                 .setup          = pci_default_setup,
 812         },
 813         {
 814                 .vendor         = PCI_VENDOR_ID_SIIG,
 815                 .device         = PCI_DEVICE_ID_SIIG_4S_10x_850,
 816                 .subvendor      = PCI_ANY_ID,
 817                 .subdevice      = PCI_ANY_ID,
 818                 .init           = pci_siig10x_init,
 819                 .setup          = pci_default_setup,
 820         },
 821         {
 822                 .vendor         = PCI_VENDOR_ID_SIIG,
 823                 .device         = PCI_DEVICE_ID_SIIG_1S_20x_550,
 824                 .subvendor      = PCI_ANY_ID,
 825                 .subdevice      = PCI_ANY_ID,
 826                 .init           = pci_siig20x_init,
 827                 .setup          = pci_default_setup,
 828         },
 829         {
 830                 .vendor         = PCI_VENDOR_ID_SIIG,
 831                 .device         = PCI_DEVICE_ID_SIIG_1S_20x_650,
 832                 .subvendor      = PCI_ANY_ID,
 833                 .subdevice      = PCI_ANY_ID,
 834                 .init           = pci_siig20x_init,
 835                 .setup          = pci_default_setup,
 836         },
 837         {
 838                 .vendor         = PCI_VENDOR_ID_SIIG,
 839                 .device         = PCI_DEVICE_ID_SIIG_1S_20x_850,
 840                 .subvendor      = PCI_ANY_ID,
 841                 .subdevice      = PCI_ANY_ID,
 842                 .init           = pci_siig20x_init,
 843                 .setup          = pci_default_setup,
 844         },
 845         {
 846                 .vendor         = PCI_VENDOR_ID_SIIG,
 847                 .device         = PCI_DEVICE_ID_SIIG_2S_20x_550,
 848                 .subvendor      = PCI_ANY_ID,
 849                 .subdevice      = PCI_ANY_ID,
 850                 .init           = pci_siig20x_init,
 851                 .setup          = pci_default_setup,
 852         },
 853         {       .vendor         = PCI_VENDOR_ID_SIIG,
 854                 .device         = PCI_DEVICE_ID_SIIG_2S_20x_650,
 855                 .subvendor      = PCI_ANY_ID,
 856                 .subdevice      = PCI_ANY_ID,
 857                 .init           = pci_siig20x_init,
 858                 .setup          = pci_default_setup,
 859         },
 860         {
 861                 .vendor         = PCI_VENDOR_ID_SIIG,
 862                 .device         = PCI_DEVICE_ID_SIIG_2S_20x_850,
 863                 .subvendor      = PCI_ANY_ID,
 864                 .subdevice      = PCI_ANY_ID,
 865                 .init           = pci_siig20x_init,
 866                 .setup          = pci_default_setup,
 867         },
 868         {
 869                 .vendor         = PCI_VENDOR_ID_SIIG,
 870                 .device         = PCI_DEVICE_ID_SIIG_4S_20x_550,
 871                 .subvendor      = PCI_ANY_ID,
 872                 .subdevice      = PCI_ANY_ID,
 873                 .init           = pci_siig20x_init,
 874                 .setup          = pci_default_setup,
 875         },
 876         {
 877                 .vendor         = PCI_VENDOR_ID_SIIG,
 878                 .device         = PCI_DEVICE_ID_SIIG_4S_20x_650,
 879                 .subvendor      = PCI_ANY_ID,
 880                 .subdevice      = PCI_ANY_ID,
 881                 .init           = pci_siig20x_init,
 882                 .setup          = pci_default_setup,
 883         },
 884         {
 885                 .vendor         = PCI_VENDOR_ID_SIIG,
 886                 .device         = PCI_DEVICE_ID_SIIG_4S_20x_850,
 887                 .subvendor      = PCI_ANY_ID,
 888                 .subdevice      = PCI_ANY_ID,
 889                 .init           = pci_siig20x_init,
 890                 .setup          = pci_default_setup,
 891         },
 892         /*
 893          * Titan cards
 894          */
 895         {
 896                 .vendor         = PCI_VENDOR_ID_TITAN,
 897                 .device         = PCI_DEVICE_ID_TITAN_400L,
 898                 .subvendor      = PCI_ANY_ID,
 899                 .subdevice      = PCI_ANY_ID,
 900                 .setup          = titan_400l_800l_setup,
 901         },
 902         {
 903                 .vendor         = PCI_VENDOR_ID_TITAN,
 904                 .device         = PCI_DEVICE_ID_TITAN_800L,
 905                 .subvendor      = PCI_ANY_ID,
 906                 .subdevice      = PCI_ANY_ID,
 907                 .setup          = titan_400l_800l_setup,
 908         },
 909         /*
 910          * Timedia cards
 911          */
 912         {
 913                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
 914                 .device         = PCI_DEVICE_ID_TIMEDIA_1889,
 915                 .subvendor      = PCI_VENDOR_ID_TIMEDIA,
 916                 .subdevice      = PCI_ANY_ID,
 917                 .init           = pci_timedia_init,
 918                 .setup          = pci_timedia_setup,
 919         },
 920         {
 921                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
 922                 .device         = PCI_ANY_ID,
 923                 .subvendor      = PCI_ANY_ID,
 924                 .subdevice      = PCI_ANY_ID,
 925                 .setup          = pci_timedia_setup,
 926         },
 927         /*
 928          * Xircom cards
 929          */
 930         {
 931                 .vendor         = PCI_VENDOR_ID_XIRCOM,
 932                 .device         = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
 933                 .subvendor      = PCI_ANY_ID,
 934                 .subdevice      = PCI_ANY_ID,
 935                 .init           = pci_xircom_init,
 936                 .setup          = pci_default_setup,
 937         },
 938         /*
 939          * Default "match everything" terminator entry
 940          */
 941         {
 942                 .vendor         = PCI_ANY_ID,
 943                 .device         = PCI_ANY_ID,
 944                 .subvendor      = PCI_ANY_ID,
 945                 .subdevice      = PCI_ANY_ID,
 946                 .setup          = pci_default_setup,
 947         }
 948 };
 949
 950 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
 951 {
 952         return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
 953 }
 954
 955 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
 956 {
 957         struct pci_serial_quirk *quirk;
 958
 959         for (quirk = pci_serial_quirks; ; quirk++)
 960                 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
 961                     quirk_id_matches(quirk->device, dev->device) &&
 962                     quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
 963                     quirk_id_matches(quirk->subdevice, dev->subsystem_device))
 964                         break;
 965         return quirk;
 966 }
 967
 968 static _INLINE_ int
 969 get_pci_irq(struct pci_dev *dev, struct pci_board *board, int idx)
 970 {
 971         if (board->flags & FL_NOIRQ)
 972                 return 0;
 973         else
 974                 return dev->irq;
 975 }
 976
 977 /*
 978  * This is the configuration table for all of the PCI serial boards
 979  * which we support.  It is directly indexed by the pci_board_num_t enum
 980  * value, which is encoded in the pci_device_id PCI probe table's
 981  * driver_data member.
 982  *
 983  * The makeup of these names are:
 984  *  pbn_bn{_bt}_n_baud
 985  *
 986  *  bn   = PCI BAR number
 987  *  bt   = Index using PCI BARs
 988  *  n    = number of serial ports
 989  *  baud = baud rate
 990  *
 991  * Please note: in theory if n = 1, _bt infix should make no difference.
 992  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
 993  */
 994 enum pci_board_num_t {
 995         pbn_default = 0,
 996
 997         pbn_b0_1_115200,
 998         pbn_b0_2_115200,
 999         pbn_b0_4_115200,
1000         pbn_b0_5_115200,
1001
1002         pbn_b0_1_921600,
1003         pbn_b0_2_921600,
1004         pbn_b0_4_921600,
1005
1006         pbn_b0_bt_1_115200,
1007         pbn_b0_bt_2_115200,
1008         pbn_b0_bt_8_115200,
1009
1010         pbn_b0_bt_1_460800,
1011         pbn_b0_bt_2_460800,
1012         pbn_b0_bt_4_460800,
1013
1014         pbn_b0_bt_1_921600,
1015         pbn_b0_bt_2_921600,
1016         pbn_b0_bt_4_921600,
1017         pbn_b0_bt_8_921600,
1018
1019         pbn_b1_1_115200,
1020         pbn_b1_2_115200,
1021         pbn_b1_4_115200,
1022         pbn_b1_8_115200,
1023
1024         pbn_b1_1_921600,
1025         pbn_b1_2_921600,
1026         pbn_b1_4_921600,
1027         pbn_b1_8_921600,
1028
1029         pbn_b1_bt_2_921600,
1030
1031         pbn_b1_2_1382400,
1032         pbn_b1_4_1382400,
1033         pbn_b1_8_1382400,
1034
1035         pbn_b2_1_115200,
1036         pbn_b2_8_115200,
1037
1038         pbn_b2_1_460800,
1039         pbn_b2_4_460800,
1040         pbn_b2_8_460800,
1041         pbn_b2_16_460800,
1042
1043         pbn_b2_1_921600,
1044         pbn_b2_4_921600,
1045         pbn_b2_8_921600,
1046
1047         pbn_b2_bt_1_115200,
1048         pbn_b2_bt_2_115200,
1049         pbn_b2_bt_4_115200,
1050
1051         pbn_b2_bt_2_921600,
1052         pbn_b2_bt_4_921600,
1053
1054         pbn_b3_4_115200,
1055         pbn_b3_8_115200,
1056
1057         /*
1058          * Board-specific versions.
1059          */
1060         pbn_panacom,
1061         pbn_panacom2,
1062         pbn_panacom4,
1063         pbn_plx_romulus,
1064         pbn_oxsemi,
1065         pbn_intel_i960,
1066         pbn_sgi_ioc3,
1067         pbn_nec_nile4,
1068         pbn_computone_4,
1069         pbn_computone_6,
1070         pbn_computone_8,
1071         pbn_sbsxrsio,
1072 };
1073
1074 /*
1075  * uart_offset - the space between channels
1076  * reg_shift   - describes how the UART registers are mapped
1077  *               to PCI memory by the card.
1078  * For example IER register on SBS, Inc. PMC-OctPro is located at
1079  * offset 0x10 from the UART base, while UART_IER is defined as 1
1080  * in include/linux/serial_reg.h,
1081  * see first lines of serial_in() and serial_out() in 8250.c
1082 */
1083
1084 static struct pci_board pci_boards[] __devinitdata = {
1085         [pbn_default] = {
1086                 .flags          = FL_BASE0,
1087                 .num_ports      = 1,
1088                 .base_baud      = 115200,
1089                 .uart_offset    = 8,
1090         },
1091         [pbn_b0_1_115200] = {
1092                 .flags          = FL_BASE0,
1093                 .num_ports      = 1,
1094                 .base_baud      = 115200,
1095                 .uart_offset    = 8,
1096         },
1097         [pbn_b0_2_115200] = {
1098                 .flags          = FL_BASE0,
1099                 .num_ports      = 2,
1100                 .base_baud      = 115200,
1101                 .uart_offset    = 8,
1102         },
1103         [pbn_b0_4_115200] = {
1104                 .flags          = FL_BASE0,
1105                 .num_ports      = 4,
1106                 .base_baud      = 115200,
1107                 .uart_offset    = 8,
1108         },
1109         [pbn_b0_5_115200] = {
1110                 .flags          = FL_BASE0,
1111                 .num_ports      = 5,
1112                 .base_baud      = 115200,
1113                 .uart_offset    = 8,
1114         },
1115
1116         [pbn_b0_1_921600] = {
1117                 .flags          = FL_BASE0,
1118                 .num_ports      = 1,
1119                 .base_baud      = 921600,
1120                 .uart_offset    = 8,
1121         },
1122         [pbn_b0_2_921600] = {
1123                 .flags          = FL_BASE0,
1124                 .num_ports      = 2,
1125                 .base_baud      = 921600,
1126                 .uart_offset    = 8,
1127         },
1128         [pbn_b0_4_921600] = {
1129                 .flags          = FL_BASE0,
1130                 .num_ports      = 4,
1131                 .base_baud      = 921600,
1132                 .uart_offset    = 8,
1133         },
1134
1135         [pbn_b0_bt_1_115200] = {
1136                 .flags          = FL_BASE0|FL_BASE_BARS,
1137                 .num_ports      = 1,
1138                 .base_baud      = 115200,
1139                 .uart_offset    = 8,
1140         },
1141         [pbn_b0_bt_2_115200] = {
1142                 .flags          = FL_BASE0|FL_BASE_BARS,
1143                 .num_ports      = 2,
1144                 .base_baud      = 115200,
1145                 .uart_offset    = 8,
1146         },
1147         [pbn_b0_bt_8_115200] = {
1148                 .flags          = FL_BASE0|FL_BASE_BARS,
1149                 .num_ports      = 8,
1150                 .base_baud      = 115200,
1151                 .uart_offset    = 8,
1152         },
1153
1154         [pbn_b0_bt_1_460800] = {
1155                 .flags          = FL_BASE0|FL_BASE_BARS,
1156                 .num_ports      = 1,
1157                 .base_baud      = 460800,
1158                 .uart_offset    = 8,
1159         },
1160         [pbn_b0_bt_2_460800] = {
1161                 .flags          = FL_BASE0|FL_BASE_BARS,
1162                 .num_ports      = 2,
1163                 .base_baud      = 460800,
1164                 .uart_offset    = 8,
1165         },
1166         [pbn_b0_bt_4_460800] = {
1167                 .flags          = FL_BASE0|FL_BASE_BARS,
1168                 .num_ports      = 4,
1169                 .base_baud      = 460800,
1170                 .uart_offset    = 8,
1171         },
1172
1173         [pbn_b0_bt_1_921600] = {
1174                 .flags          = FL_BASE0|FL_BASE_BARS,
1175                 .num_ports      = 1,
1176                 .base_baud      = 921600,
1177                 .uart_offset    = 8,
1178         },
1179         [pbn_b0_bt_2_921600] = {
1180                 .flags          = FL_BASE0|FL_BASE_BARS,
1181                 .num_ports      = 2,
1182                 .base_baud      = 921600,
1183                 .uart_offset    = 8,
1184         },
1185         [pbn_b0_bt_4_921600] = {
1186                 .flags          = FL_BASE0|FL_BASE_BARS,
1187                 .num_ports      = 4,
1188                 .base_baud      = 921600,
1189                 .uart_offset    = 8,
1190         },
1191         [pbn_b0_bt_8_921600] = {
1192                 .flags          = FL_BASE0|FL_BASE_BARS,
1193                 .num_ports      = 8,
1194                 .base_baud      = 921600,
1195                 .uart_offset    = 8,
1196         },
1197
1198         [pbn_b1_1_115200] = {
1199                 .flags          = FL_BASE1,
1200                 .num_ports      = 1,
1201                 .base_baud      = 115200,
1202                 .uart_offset    = 8,
1203         },
1204         [pbn_b1_2_115200] = {
1205                 .flags          = FL_BASE1,
1206                 .num_ports      = 2,
1207                 .base_baud      = 115200,
1208                 .uart_offset    = 8,
1209         },
1210         [pbn_b1_4_115200] = {
1211                 .flags          = FL_BASE1,
1212                 .num_ports      = 4,
1213                 .base_baud      = 115200,
1214                 .uart_offset    = 8,
1215         },
1216         [pbn_b1_8_115200] = {
1217                 .flags          = FL_BASE1,
1218                 .num_ports      = 8,
1219                 .base_baud      = 115200,
1220                 .uart_offset    = 8,
1221         },
1222
1223         [pbn_b1_1_921600] = {
1224                 .flags          = FL_BASE1,
1225                 .num_ports      = 1,
1226                 .base_baud      = 921600,
1227                 .uart_offset    = 8,
1228         },
1229         [pbn_b1_2_921600] = {
1230                 .flags          = FL_BASE1,
1231                 .num_ports      = 2,
1232                 .base_baud      = 921600,
1233                 .uart_offset    = 8,
1234         },
1235         [pbn_b1_4_921600] = {
1236                 .flags          = FL_BASE1,
1237                 .num_ports      = 4,
1238                 .base_baud      = 921600,
1239                 .uart_offset    = 8,
1240         },
1241         [pbn_b1_8_921600] = {
1242                 .flags          = FL_BASE1,
1243                 .num_ports      = 8,
1244                 .base_baud      = 921600,
1245                 .uart_offset    = 8,
1246         },
1247
1248         [pbn_b1_bt_2_921600] = {
1249                 .flags          = FL_BASE1|FL_BASE_BARS,
1250                 .num_ports      = 2,
1251                 .base_baud      = 921600,
1252                 .uart_offset    = 8,
1253         },
1254
1255         [pbn_b1_2_1382400] = {
1256                 .flags          = FL_BASE1,
1257                 .num_ports      = 2,
1258                 .base_baud      = 1382400,
1259                 .uart_offset    = 8,
1260         },
1261         [pbn_b1_4_1382400] = {
1262                 .flags          = FL_BASE1,
1263                 .num_ports      = 4,
1264                 .base_baud      = 1382400,
1265                 .uart_offset    = 8,
1266         },
1267         [pbn_b1_8_1382400] = {
1268                 .flags          = FL_BASE1,
1269                 .num_ports      = 8,
1270                 .base_baud      = 1382400,
1271                 .uart_offset    = 8,
1272         },
1273
1274         [pbn_b2_1_115200] = {
1275                 .flags          = FL_BASE2,
1276                 .num_ports      = 1,
1277                 .base_baud      = 115200,
1278                 .uart_offset    = 8,
1279         },
1280         [pbn_b2_8_115200] = {
1281                 .flags          = FL_BASE2,
1282                 .num_ports      = 8,
1283                 .base_baud      = 115200,
1284                 .uart_offset    = 8,
1285         },
1286
1287         [pbn_b2_1_460800] = {
1288                 .flags          = FL_BASE2,
1289                 .num_ports      = 1,
1290                 .base_baud      = 460800,
1291                 .uart_offset    = 8,
1292         },
1293         [pbn_b2_4_460800] = {
1294                 .flags          = FL_BASE2,
1295                 .num_ports      = 4,
1296                 .base_baud      = 460800,
1297                 .uart_offset    = 8,
1298         },
1299         [pbn_b2_8_460800] = {
1300                 .flags          = FL_BASE2,
1301                 .num_ports      = 8,
1302                 .base_baud      = 460800,
1303                 .uart_offset    = 8,
1304         },
1305         [pbn_b2_16_460800] = {
1306                 .flags          = FL_BASE2,
1307                 .num_ports      = 16,
1308                 .base_baud      = 460800,
1309                 .uart_offset    = 8,
1310          },
1311
1312         [pbn_b2_1_921600] = {
1313                 .flags          = FL_BASE2,
1314                 .num_ports      = 1,
1315                 .base_baud      = 921600,
1316                 .uart_offset    = 8,
1317         },
1318         [pbn_b2_4_921600] = {
1319                 .flags          = FL_BASE2,
1320                 .num_ports      = 4,
1321                 .base_baud      = 921600,
1322                 .uart_offset    = 8,
1323         },
1324         [pbn_b2_8_921600] = {
1325                 .flags          = FL_BASE2,
1326                 .num_ports      = 8,
1327                 .base_baud      = 921600,
1328                 .uart_offset    = 8,
1329         },
1330
1331         [pbn_b2_bt_1_115200] = {
1332                 .flags          = FL_BASE2|FL_BASE_BARS,
1333                 .num_ports      = 1,
1334                 .base_baud      = 115200,
1335                 .uart_offset    = 8,
1336         },
1337         [pbn_b2_bt_2_115200] = {
1338                 .flags          = FL_BASE2|FL_BASE_BARS,
1339                 .num_ports      = 2,
1340                 .base_baud      = 115200,
1341                 .uart_offset    = 8,
1342         },
1343         [pbn_b2_bt_4_115200] = {
1344                 .flags          = FL_BASE2|FL_BASE_BARS,
1345                 .num_ports      = 4,
1346                 .base_baud      = 115200,
1347                 .uart_offset    = 8,
1348         },
1349
1350         [pbn_b2_bt_2_921600] = {
1351                 .flags          = FL_BASE2|FL_BASE_BARS,
1352                 .num_ports      = 2,
1353                 .base_baud      = 921600,
1354                 .uart_offset    = 8,
1355         },
1356         [pbn_b2_bt_4_921600] = {
1357                 .flags          = FL_BASE2|FL_BASE_BARS,
1358                 .num_ports      = 4,
1359                 .base_baud      = 921600,
1360                 .uart_offset    = 8,
1361         },
1362
1363         [pbn_b3_4_115200] = {
1364                 .flags          = FL_BASE3,
1365                 .num_ports      = 4,
1366                 .base_baud      = 115200,
1367                 .uart_offset    = 8,
1368         },
1369         [pbn_b3_8_115200] = {
1370                 .flags          = FL_BASE3,
1371                 .num_ports      = 8,
1372                 .base_baud      = 115200,
1373                 .uart_offset    = 8,
1374         },
1375
1376         /*
1377          * Entries following this are board-specific.
1378          */
1379
1380         /*
1381          * Panacom - IOMEM
1382          */
1383         [pbn_panacom] = {
1384                 .flags          = FL_BASE2,
1385                 .num_ports      = 2,
1386                 .base_baud      = 921600,
1387                 .uart_offset    = 0x400,
1388                 .reg_shift      = 7,
1389         },
1390         [pbn_panacom2] = {
1391                 .flags          = FL_BASE2|FL_BASE_BARS,
1392                 .num_ports      = 2,
1393                 .base_baud      = 921600,
1394                 .uart_offset    = 0x400,
1395                 .reg_shift      = 7,
1396         },
1397         [pbn_panacom4] = {
1398                 .flags          = FL_BASE2|FL_BASE_BARS,
1399                 .num_ports      = 4,
1400                 .base_baud      = 921600,
1401                 .uart_offset    = 0x400,
1402                 .reg_shift      = 7,
1403         },
1404
1405         /* I think this entry is broken - the first_offset looks wrong --rmk */
1406         [pbn_plx_romulus] = {
1407                 .flags          = FL_BASE2,
1408                 .num_ports      = 4,
1409                 .base_baud      = 921600,
1410                 .uart_offset    = 8 << 2,
1411                 .reg_shift      = 2,
1412                 .first_offset   = 0x03,
1413         },
1414
1415         /*
1416          * This board uses the size of PCI Base region 0 to
1417          * signal now many ports are available
1418          */
1419         [pbn_oxsemi] = {
1420                 .flags          = FL_BASE0|FL_REGION_SZ_CAP,
1421                 .num_ports      = 32,
1422                 .base_baud      = 115200,
1423                 .uart_offset    = 8,
1424         },
1425
1426         /*
1427          * EKF addition for i960 Boards form EKF with serial port.
1428          * Max 256 ports.
1429          */
1430         [pbn_intel_i960] = {
1431                 .flags          = FL_BASE0,
1432                 .num_ports      = 32,
1433                 .base_baud      = 921600,
1434                 .uart_offset    = 8 << 2,
1435                 .reg_shift      = 2,
1436                 .first_offset   = 0x10000,
1437         },
1438         [pbn_sgi_ioc3] = {
1439                 .flags          = FL_BASE0|FL_NOIRQ,
1440                 .num_ports      = 1,
1441                 .base_baud      = 458333,
1442                 .uart_offset    = 8,
1443                 .reg_shift      = 0,
1444                 .first_offset   = 0x20178,
1445         },
1446
1447         /*
1448          * NEC Vrc-5074 (Nile 4) builtin UART.
1449          */
1450         [pbn_nec_nile4] = {
1451                 .flags          = FL_BASE0,
1452                 .num_ports      = 1,
1453                 .base_baud      = 520833,
1454                 .uart_offset    = 8 << 3,
1455                 .reg_shift      = 3,
1456                 .first_offset   = 0x300,
1457         },
1458
1459         /*
1460          * Computone - uses IOMEM.
1461          */
1462         [pbn_computone_4] = {
1463                 .flags          = FL_BASE0,
1464                 .num_ports      = 4,
1465                 .base_baud      = 921600,
1466                 .uart_offset    = 0x40,
1467                 .reg_shift      = 2,
1468                 .first_offset   = 0x200,
1469         },
1470         [pbn_computone_6] = {
1471                 .flags          = FL_BASE0,
1472                 .num_ports      = 6,
1473                 .base_baud      = 921600,
1474                 .uart_offset    = 0x40,
1475                 .reg_shift      = 2,
1476                 .first_offset   = 0x200,
1477         },
1478         [pbn_computone_8] = {
1479                 .flags          = FL_BASE0,
1480                 .num_ports      = 8,
1481                 .base_baud      = 921600,
1482                 .uart_offset    = 0x40,
1483                 .reg_shift      = 2,
1484                 .first_offset   = 0x200,
1485         },
1486         [pbn_sbsxrsio] = {
1487                 .flags          = FL_BASE0,
1488                 .num_ports      = 8,
1489                 .base_baud      = 460800,
1490                 .uart_offset    = 256,
1491                 .reg_shift      = 4,
1492         }
1493 };
1494
1495 /*
1496  * Given a complete unknown PCI device, try to use some heuristics to
1497  * guess what the configuration might be, based on the pitiful PCI
1498  * serial specs.  Returns 0 on success, 1 on failure.
1499  */
1500 static int __devinit
1501 serial_pci_guess_board(struct pci_dev *dev, struct pci_board *board)
1502 {
1503         int num_iomem, num_port, first_port = -1, i;
1504
1505         /*
1506          * If it is not a communications device or the programming
1507          * interface is greater than 6, give up.
1508          *
1509          * (Should we try to make guesses for multiport serial devices
1510          * later?)
1511          */
1512         if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
1513              ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
1514             (dev->class & 0xff) > 6)
1515                 return -ENODEV;
1516
1517         num_iomem = num_port = 0;
1518         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1519                 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
1520                         num_port++;
1521                         if (first_port == -1)
1522                                 first_port = i;
1523                 }
1524                 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
1525                         num_iomem++;
1526         }
1527
1528         /*
1529          * If there is 1 or 0 iomem regions, and exactly one port,
1530          * use it.  We guess the number of ports based on the IO
1531          * region size.
1532          */
1533         if (num_iomem <= 1 && num_port == 1) {
1534                 board->flags = first_port;
1535                 board->num_ports = pci_resource_len(dev, first_port) / 8;
1536                 return 0;
1537         }
1538
1539         /*
1540          * Now guess if we've got a board which indexes by BARs.
1541          * Each IO BAR should be 8 bytes, and they should follow
1542          * consecutively.
1543          */
1544         first_port = -1;
1545         num_port = 0;
1546         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1547                 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
1548                     pci_resource_len(dev, i) == 8 &&
1549                     (first_port == -1 || (first_port + num_port) == i)) {
1550                         num_port++;
1551                         if (first_port == -1)
1552                                 first_port = i;
1553                 }
1554         }
1555
1556         if (num_port > 1) {
1557                 board->flags = first_port | FL_BASE_BARS;
1558                 board->num_ports = num_port;
1559                 return 0;
1560         }
1561
1562         return -ENODEV;
1563 }
1564
1565 static inline int
1566 serial_pci_matches(struct pci_board *board, struct pci_board *guessed)
1567 {
1568         return
1569             board->num_ports == guessed->num_ports &&
1570             board->base_baud == guessed->base_baud &&
1571             board->uart_offset == guessed->uart_offset &&
1572             board->reg_shift == guessed->reg_shift &&
1573             board->first_offset == guessed->first_offset;
1574 }
1575
1576 /*
1577  * Probe one serial board.  Unfortunately, there is no rhyme nor reason
1578  * to the arrangement of serial ports on a PCI card.
1579  */
1580 static int __devinit
1581 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
1582 {
1583         struct serial_private *priv;
1584         struct pci_board *board, tmp;
1585         struct pci_serial_quirk *quirk;
1586         struct serial_struct serial_req;
1587         int rc, nr_ports, i;
1588
1589         if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
1590                 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
1591                         ent->driver_data);
1592                 return -EINVAL;
1593         }
1594
1595         board = &pci_boards[ent->driver_data];
1596
1597         rc = pci_enable_device(dev);
1598         if (rc)
1599                 return rc;
1600
1601         if (ent->driver_data == pbn_default) {
1602                 /*
1603                  * Use a copy of the pci_board entry for this;
1604                  * avoid changing entries in the table.
1605                  */
1606                 memcpy(&tmp, board, sizeof(struct pci_board));
1607                 board = &tmp;
1608
1609                 /*
1610                  * We matched one of our class entries.  Try to
1611                  * determine the parameters of this board.
1612                  */
1613                 rc = serial_pci_guess_board(dev, board);
1614                 if (rc)
1615                         goto disable;
1616         } else {
1617                 /*
1618                  * We matched an explicit entry.  If we are able to
1619                  * detect this boards settings with our heuristic,
1620                  * then we no longer need this entry.
1621                  */
1622                 memcpy(&tmp, &pci_boards[pbn_default], sizeof(struct pci_board));
1623                 rc = serial_pci_guess_board(dev, &tmp);
1624                 if (rc == 0 && serial_pci_matches(board, &tmp))
1625                         moan_device("Redundant entry in serial pci_table.",
1626                                     dev);
1627         }
1628
1629         nr_ports = board->num_ports;
1630
1631         /*
1632          * Find an init and setup quirks.
1633          */
1634         quirk = find_quirk(dev);
1635
1636         /*
1637          * Run the new-style initialization function.
1638          * The initialization function returns:
1639          *  <0  - error
1640          *   0  - use board->num_ports
1641          *  >0  - number of ports
1642          */
1643         if (quirk->init) {
1644                 rc = quirk->init(dev);
1645                 if (rc < 0)
1646                         goto disable;
1647                 if (rc)
1648                         nr_ports = rc;
1649         }
1650
1651         priv = kmalloc(sizeof(struct serial_private) +
1652                        sizeof(unsigned int) * nr_ports,
1653                        GFP_KERNEL);
1654         if (!priv) {
1655                 rc = -ENOMEM;
1656                 goto deinit;
1657         }
1658
1659         memset(priv, 0, sizeof(struct serial_private) +
1660                         sizeof(unsigned int) * nr_ports);
1661
1662         priv->quirk = quirk;
1663         pci_set_drvdata(dev, priv);
1664
1665         for (i = 0; i < nr_ports; i++) {
1666                 memset(&serial_req, 0, sizeof(serial_req));
1667                 serial_req.flags = UPF_SKIP_TEST | UPF_AUTOPROBE |
1668                                    UPF_RESOURCES | UPF_SHARE_IRQ;
1669                 serial_req.baud_base = board->base_baud;
1670                 serial_req.irq = get_pci_irq(dev, board, i);
1671                 if (quirk->setup(dev, board, &serial_req, i))
1672                         break;
1673 #ifdef SERIAL_DEBUG_PCI
1674                 printk("Setup PCI port: port %x, irq %d, type %d\n",
1675                        serial_req.port, serial_req.irq, serial_req.io_type);
1676 #endif
1677
1678                 priv->line[i] = register_serial(&serial_req);
1679                 if (priv->line[i] < 0) {
1680                         printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
1681                         break;
1682                 }
1683         }
1684
1685         priv->nr = i;
1686
1687         return 0;
1688
1689  deinit:
1690         if (quirk->exit)
1691                 quirk->exit(dev);
1692  disable:
1693         pci_disable_device(dev);
1694         return rc;
1695 }
1696
1697 static void __devexit pciserial_remove_one(struct pci_dev *dev)
1698 {
1699         struct serial_private *priv = pci_get_drvdata(dev);
1700
1701         pci_set_drvdata(dev, NULL);
1702
1703         if (priv) {
1704                 struct pci_serial_quirk *quirk;
1705                 int i;
1706
1707                 for (i = 0; i < priv->nr; i++)
1708                         unregister_serial(priv->line[i]);
1709
1710                 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1711                         if (priv->remapped_bar[i])
1712                                 iounmap(priv->remapped_bar[i]);
1713                         priv->remapped_bar[i] = NULL;
1714                 }
1715
1716                 /*
1717                  * Find the exit quirks.
1718                  */
1719                 quirk = find_quirk(dev);
1720                 if (quirk->exit)
1721                         quirk->exit(dev);
1722
1723                 pci_disable_device(dev);
1724
1725                 kfree(priv);
1726         }
1727 }
1728
1729 static int pciserial_suspend_one(struct pci_dev *dev, u32 state)
1730 {
1731         struct serial_private *priv = pci_get_drvdata(dev);
1732
1733         if (priv) {
1734                 int i;
1735
1736                 for (i = 0; i < priv->nr; i++)
1737                         serial8250_suspend_port(priv->line[i]);
1738         }
1739         return 0;
1740 }
1741
1742 static int pciserial_resume_one(struct pci_dev *dev)
1743 {
1744         struct serial_private *priv = pci_get_drvdata(dev);
1745
1746         if (priv) {
1747                 int i;
1748
1749                 /*
1750                  * Ensure that the board is correctly configured.
1751                  */
1752                 if (priv->quirk->init)
1753                         priv->quirk->init(dev);
1754
1755                 for (i = 0; i < priv->nr; i++)
1756                         serial8250_resume_port(priv->line[i]);
1757         }
1758         return 0;
1759 }
1760
1761 static struct pci_device_id serial_pci_tbl[] = {
1762         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1763                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1764                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1765                 pbn_b1_8_1382400 },
1766         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1767                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1768                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1769                 pbn_b1_4_1382400 },
1770         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1771                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1772                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1773                 pbn_b1_2_1382400 },
1774         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1775                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1776                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1777                 pbn_b1_8_1382400 },
1778         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1779                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1780                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1781                 pbn_b1_4_1382400 },
1782         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1783                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1784                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1785                 pbn_b1_2_1382400 },
1786         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1787                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1788                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
1789                 pbn_b1_8_921600 },
1790         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1791                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1792                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
1793                 pbn_b1_8_921600 },
1794         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1795                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1796                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
1797                 pbn_b1_4_921600 },
1798         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1799                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1800                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
1801                 pbn_b1_4_921600 },
1802         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1803                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1804                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
1805                 pbn_b1_2_921600 },
1806         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1807                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1808                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
1809                 pbn_b1_8_921600 },
1810         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1811                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1812                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
1813                 pbn_b1_8_921600 },
1814         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1815                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1816                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
1817                 pbn_b1_4_921600 },
1818
1819         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
1820                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1821                 pbn_b2_bt_1_115200 },
1822         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
1823                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1824                 pbn_b2_bt_2_115200 },
1825         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
1826                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1827                 pbn_b2_bt_4_115200 },
1828         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
1829                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1830                 pbn_b2_bt_2_115200 },
1831         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
1832                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1833                 pbn_b2_bt_4_115200 },
1834         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
1835                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1836                 pbn_b2_8_115200 },
1837
1838         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
1839                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1840                 pbn_b2_bt_2_115200 },
1841         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
1842                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1843                 pbn_b2_bt_2_921600 },
1844         /*
1845          * VScom SPCOM800, from sl@s.pl
1846          */
1847         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
1848                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1849                 pbn_b2_8_921600 },
1850         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
1851                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1852                 pbn_b2_4_921600 },
1853         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1854                 PCI_SUBVENDOR_ID_KEYSPAN,
1855                 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
1856                 pbn_panacom },
1857         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
1858                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1859                 pbn_panacom4 },
1860         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
1861                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1862                 pbn_panacom2 },
1863         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1864                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1865                 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
1866                 pbn_b2_4_460800 },
1867         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1868                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1869                 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
1870                 pbn_b2_8_460800 },
1871         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1872                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1873                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
1874                 pbn_b2_16_460800 },
1875         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1876                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1877                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
1878                 pbn_b2_16_460800 },
1879         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1880                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
1881                 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
1882                 pbn_b2_4_460800 },
1883         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1884                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
1885                 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
1886                 pbn_b2_8_460800 },
1887         /*
1888          * Megawolf Romulus PCI Serial Card, from Mike Hudson
1889          * (Exoray@isys.ca)
1890          */
1891         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
1892                 0x10b5, 0x106a, 0, 0,
1893                 pbn_plx_romulus },
1894         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
1895                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1896                 pbn_b1_4_115200 },
1897         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
1898                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1899                 pbn_b1_2_115200 },
1900         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
1901                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1902                 pbn_b1_8_115200 },
1903         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
1904                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1905                 pbn_b1_8_115200 },
1906         {       PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
1907                 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 0, 0,
1908                 pbn_b0_4_921600 },
1909         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1910                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1911                 pbn_b0_4_115200 },
1912         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
1913                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1914                 pbn_b0_bt_2_921600 },
1915
1916         /*
1917          * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
1918          * from skokodyn@yahoo.com
1919          */
1920         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1921                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
1922                 pbn_sbsxrsio },
1923         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1924                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
1925                 pbn_sbsxrsio },
1926         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1927                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
1928                 pbn_sbsxrsio },
1929         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1930                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
1931                 pbn_sbsxrsio },
1932
1933         /*
1934          * Digitan DS560-558, from jimd@esoft.com
1935          */
1936         {       PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
1937                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1938                 pbn_b1_1_115200 },
1939
1940         /*
1941          * Titan Electronic cards
1942          *  The 400L and 800L have a custom setup quirk.
1943          */
1944         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
1945                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1946                 pbn_b0_1_921600 },
1947         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
1948                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1949                 pbn_b0_2_921600 },
1950         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
1951                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1952                 pbn_b0_4_921600 },
1953         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
1954                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1955                 pbn_b0_4_921600 },
1956         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
1957                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1958                 pbn_b1_1_921600 },
1959         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
1960                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1961                 pbn_b1_bt_2_921600 },
1962         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
1963                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1964                 pbn_b0_bt_4_921600 },
1965         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
1966                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1967                 pbn_b0_bt_8_921600 },
1968
1969         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
1970                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1971                 pbn_b2_1_460800 },
1972         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
1973                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1974                 pbn_b2_1_460800 },
1975         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
1976                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1977                 pbn_b2_1_460800 },
1978         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
1979                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1980                 pbn_b2_bt_2_921600 },
1981         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
1982                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1983                 pbn_b2_bt_2_921600 },
1984         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
1985                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1986                 pbn_b2_bt_2_921600 },
1987         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
1988                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1989                 pbn_b2_bt_4_921600 },
1990         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
1991                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1992                 pbn_b2_bt_4_921600 },
1993         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
1994                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1995                 pbn_b2_bt_4_921600 },
1996         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
1997                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1998                 pbn_b0_1_921600 },
1999         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
2000                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2001                 pbn_b0_1_921600 },
2002         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
2003                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2004                 pbn_b0_1_921600 },
2005         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
2006                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2007                 pbn_b0_bt_2_921600 },
2008         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
2009                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2010                 pbn_b0_bt_2_921600 },
2011         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
2012                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2013                 pbn_b0_bt_2_921600 },
2014         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
2015                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2016                 pbn_b0_bt_4_921600 },
2017         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
2018                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2019                 pbn_b0_bt_4_921600 },
2020         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
2021                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2022                 pbn_b0_bt_4_921600 },
2023
2024         /*
2025          * Computone devices submitted by Doug McNash dmcnash@computone.com
2026          */
2027         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2028                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
2029                 0, 0, pbn_computone_4 },
2030         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2031                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
2032                 0, 0, pbn_computone_8 },
2033         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2034                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
2035                 0, 0, pbn_computone_6 },
2036
2037         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
2038                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2039                 pbn_oxsemi },
2040         {       PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
2041                 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
2042                 pbn_b0_bt_1_921600 },
2043
2044         /*
2045          * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
2046          */
2047         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
2048                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2049                 pbn_b0_bt_8_115200 },
2050         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
2051                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2052                 pbn_b0_bt_8_115200 },
2053
2054         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
2055                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2056                 pbn_b0_bt_2_115200 },
2057         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
2058                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2059                 pbn_b0_bt_2_115200 },
2060         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
2061                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2062                 pbn_b0_bt_2_115200 },
2063         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
2064                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2065                 pbn_b0_bt_4_460800 },
2066         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
2067                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2068                 pbn_b0_bt_4_460800 },
2069         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
2070                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2071                 pbn_b0_bt_2_460800 },
2072         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
2073                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2074                 pbn_b0_bt_2_460800 },
2075         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
2076                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2077                 pbn_b0_bt_2_460800 },
2078         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
2079                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2080                 pbn_b0_bt_1_115200 },
2081         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
2082                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2083                 pbn_b0_bt_1_460800 },
2084
2085         /*
2086          * RAStel 2 port modem, gerg@moreton.com.au
2087          */
2088         {       PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
2089                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2090                 pbn_b2_bt_2_115200 },
2091
2092         /*
2093          * EKF addition for i960 Boards form EKF with serial port
2094          */
2095         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
2096                 0xE4BF, PCI_ANY_ID, 0, 0,
2097                 pbn_intel_i960 },
2098
2099         /*
2100          * Xircom Cardbus/Ethernet combos
2101          */
2102         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2103                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2104                 pbn_b0_1_115200 },
2105         /*
2106          * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
2107          */
2108         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
2109                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2110                 pbn_b0_1_115200 },
2111
2112         /*
2113          * Untested PCI modems, sent in from various folks...
2114          */
2115
2116         /*
2117          * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
2118          */
2119         {       PCI_VENDOR_ID_ROCKWELL, 0x1004,
2120                 0x1048, 0x1500, 0, 0,
2121                 pbn_b1_1_115200 },
2122
2123         {       PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
2124                 0xFF00, 0, 0, 0,
2125                 pbn_sgi_ioc3 },
2126
2127         /*
2128          * HP Diva card
2129          */
2130         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2131                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2132                 pbn_b0_5_115200 },
2133         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
2134                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2135                 pbn_b2_1_115200 },
2136
2137         /*
2138          * NEC Vrc-5074 (Nile 4) builtin UART.
2139          */
2140         {       PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_NILE4,
2141                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2142                 pbn_nec_nile4 },
2143
2144         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
2145                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2146                 pbn_b3_4_115200 },
2147         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
2148                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2149                 pbn_b3_8_115200 },
2150
2151         /*
2152          * These entries match devices with class COMMUNICATION_SERIAL,
2153          * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
2154          */
2155         {       PCI_ANY_ID, PCI_ANY_ID,
2156                 PCI_ANY_ID, PCI_ANY_ID,
2157                 PCI_CLASS_COMMUNICATION_SERIAL << 8,
2158                 0xffff00, pbn_default },
2159         {       PCI_ANY_ID, PCI_ANY_ID,
2160                 PCI_ANY_ID, PCI_ANY_ID,
2161                 PCI_CLASS_COMMUNICATION_MODEM << 8,
2162                 0xffff00, pbn_default },
2163         {       PCI_ANY_ID, PCI_ANY_ID,
2164                 PCI_ANY_ID, PCI_ANY_ID,
2165                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
2166                 0xffff00, pbn_default },
2167         { 0, }
2168 };
2169
2170 static struct pci_driver serial_pci_driver = {
2171         .name           = "serial",
2172         .probe          = pciserial_init_one,
2173         .remove         = __devexit_p(pciserial_remove_one),
2174         .suspend        = pciserial_suspend_one,
2175         .resume         = pciserial_resume_one,
2176         .id_table       = serial_pci_tbl,
2177 };
2178
2179 static int __init serial8250_pci_init(void)
2180 {
2181         return pci_module_init(&serial_pci_driver);
2182 }
2183
2184 static void __exit serial8250_pci_exit(void)
2185 {
2186         pci_unregister_driver(&serial_pci_driver);
2187 }
2188
2189 module_init(serial8250_pci_init);
2190 module_exit(serial8250_pci_exit);
2191
2192 MODULE_LICENSE("GPL");
2193 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
2194 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);