drivers/serial/8250_pci.c

   1 /*
   2  *  linux/drivers/char/8250_pci.c
   3  *
   4  *  Probe module for 8250/16550-type PCI serial ports.
   5  *
   6  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   7  *
   8  *  Copyright (C) 2001 Russell King, All Rights Reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License.
  13  *
  14  *  $Id: 8250_pci.c,v 1.28 2002/11/02 11:14:18 rmk Exp $
  15  */
  16 #include <linux/module.h>
  17 #include <linux/init.h>
  18 #include <linux/pci.h>
  19 #include <linux/sched.h>
  20 #include <linux/string.h>
  21 #include <linux/kernel.h>
  22 #include <linux/slab.h>
  23 #include <linux/delay.h>
  24 #include <linux/tty.h>
  25 #include <linux/serial.h>
  26 #include <linux/serial_core.h>
  27 #include <linux/8250_pci.h>
  28
  29 #include <asm/bitops.h>
  30 #include <asm/byteorder.h>
  31 #include <asm/serial.h>
  32 #include <asm/io.h>
  33
  34 #include "8250.h"
  35
  36 /*
  37  * Definitions for PCI support.
  38  */
  39 #define FL_BASE_MASK            0x0007
  40 #define FL_BASE0                0x0000
  41 #define FL_BASE1                0x0001
  42 #define FL_BASE2                0x0002
  43 #define FL_BASE3                0x0003
  44 #define FL_BASE4                0x0004
  45 #define FL_GET_BASE(x)          (x & FL_BASE_MASK)
  46
  47 /* Use successive BARs (PCI base address registers),
  48    else use offset into some specified BAR */
  49 #define FL_BASE_BARS            0x0008
  50
  51 /* do not assign an irq */
  52 #define FL_NOIRQ                0x0080
  53
  54 /* Use the Base address register size to cap number of ports */
  55 #define FL_REGION_SZ_CAP        0x0100
  56
  57 struct pci_board {
  58         unsigned int flags;
  59         unsigned int num_ports;
  60         unsigned int base_baud;
  61         unsigned int uart_offset;
  62         unsigned int reg_shift;
  63         unsigned int first_offset;
  64 };
  65
  66 /*
  67  * init function returns:
  68  *  > 0 - number of ports
  69  *  = 0 - use board->num_ports
  70  *  < 0 - error
  71  */
  72 struct pci_serial_quirk {
  73         u32     vendor;
  74         u32     device;
  75         u32     subvendor;
  76         u32     subdevice;
  77         int     (*init)(struct pci_dev *dev);
  78         int     (*setup)(struct pci_dev *dev, struct pci_board *board,
  79                          struct serial_struct *req, int idx);
  80         void    (*exit)(struct pci_dev *dev);
  81 };
  82
  83 #define PCI_NUM_BAR_RESOURCES   6
  84
  85 struct serial_private {
  86         unsigned int            nr;
  87         void                    *remapped_bar[PCI_NUM_BAR_RESOURCES];
  88         struct pci_serial_quirk *quirk;
  89         int                     line[0];
  90 };
  91
  92 static void moan_device(const char *str, struct pci_dev *dev)
  93 {
  94         printk(KERN_WARNING "%s: %s\n"
  95                KERN_WARNING "Please send the output of lspci -vv, this\n"
  96                KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
  97                KERN_WARNING "manufacturer and name of serial board or\n"
  98                KERN_WARNING "modem board to rmk+serial@arm.linux.org.uk.\n",
  99                pci_name(dev), str, dev->vendor, dev->device,
 100                dev->subsystem_vendor, dev->subsystem_device);
 101 }
 102
 103 static int
 104 setup_port(struct pci_dev *dev, struct serial_struct *req,
 105            int bar, int offset, int regshift)
 106 {
 107         struct serial_private *priv = pci_get_drvdata(dev);
 108         unsigned long port, len;
 109
 110         if (bar >= PCI_NUM_BAR_RESOURCES)
 111                 return -EINVAL;
 112
 113         if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
 114                 port = pci_resource_start(dev, bar);
 115                 len =  pci_resource_len(dev, bar);
 116
 117                 if (!priv->remapped_bar[bar])
 118                         priv->remapped_bar[bar] = ioremap(port, len);
 119                 if (!priv->remapped_bar[bar])
 120                         return -ENOMEM;
 121
 122                 req->io_type = UPIO_MEM;
 123                 req->iomap_base = port + offset;
 124                 req->iomem_base = priv->remapped_bar[bar] + offset;
 125                 req->iomem_reg_shift = regshift;
 126         } else {
 127                 port = pci_resource_start(dev, bar) + offset;
 128                 req->io_type = UPIO_PORT;
 129                 req->port = port;
 130                 if (HIGH_BITS_OFFSET)
 131                         req->port_high = port >> HIGH_BITS_OFFSET;
 132         }
 133         return 0;
 134 }
 135
 136 /*
 137  * AFAVLAB uses a different mixture of BARs and offsets
 138  * Not that ugly ;) -- HW
 139  */
 140 static int
 141 afavlab_setup(struct pci_dev *dev, struct pci_board *board,
 142               struct serial_struct *req, int idx)
 143 {
 144         unsigned int bar, offset = board->first_offset;
 145
 146         bar = FL_GET_BASE(board->flags);
 147         if (idx < 4)
 148                 bar += idx;
 149         else {
 150                 bar = 4;
 151                 offset += (idx - 4) * board->uart_offset;
 152         }
 153
 154         return setup_port(dev, req, bar, offset, board->reg_shift);
 155 }
 156
 157 /*
 158  * HP's Remote Management Console.  The Diva chip came in several
 159  * different versions.  N-class, L2000 and A500 have two Diva chips, each
 160  * with 3 UARTs (the third UART on the second chip is unused).  Superdome
 161  * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
 162  * one Diva chip, but it has been expanded to 5 UARTs.
 163  */
 164 static int __devinit pci_hp_diva_init(struct pci_dev *dev)
 165 {
 166         int rc = 0;
 167
 168         switch (dev->subsystem_device) {
 169         case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
 170         case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
 171         case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
 172         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 173                 rc = 3;
 174                 break;
 175         case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
 176                 rc = 2;
 177                 break;
 178         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 179                 rc = 4;
 180                 break;
 181         case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
 182                 rc = 1;
 183                 break;
 184         }
 185
 186         return rc;
 187 }
 188
 189 /*
 190  * HP's Diva chip puts the 4th/5th serial port further out, and
 191  * some serial ports are supposed to be hidden on certain models.
 192  */
 193 static int
 194 pci_hp_diva_setup(struct pci_dev *dev, struct pci_board *board,
 195               struct serial_struct *req, int idx)
 196 {
 197         unsigned int offset = board->first_offset;
 198         unsigned int bar = FL_GET_BASE(board->flags);
 199
 200         switch (dev->subsystem_device) {
 201         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 202                 if (idx == 3)
 203                         idx++;
 204                 break;
 205         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 206                 if (idx > 0)
 207                         idx++;
 208                 if (idx > 2)
 209                         idx++;
 210                 break;
 211         }
 212         if (idx > 2)
 213                 offset = 0x18;
 214
 215         offset += idx * board->uart_offset;
 216
 217         return setup_port(dev, req, bar, offset, board->reg_shift);
 218 }
 219
 220 /*
 221  * Added for EKF Intel i960 serial boards
 222  */
 223 static int __devinit pci_inteli960ni_init(struct pci_dev *dev)
 224 {
 225         unsigned long oldval;
 226
 227         if (!(dev->subsystem_device & 0x1000))
 228                 return -ENODEV;
 229
 230         /* is firmware started? */
 231         pci_read_config_dword(dev, 0x44, (void*) &oldval);
 232         if (oldval == 0x00001000L) { /* RESET value */
 233                 printk(KERN_DEBUG "Local i960 firmware missing");
 234                 return -ENODEV;
 235         }
 236         return 0;
 237 }
 238
 239 /*
 240  * Some PCI serial cards using the PLX 9050 PCI interface chip require
 241  * that the card interrupt be explicitly enabled or disabled.  This
 242  * seems to be mainly needed on card using the PLX which also use I/O
 243  * mapped memory.
 244  */
 245 static int __devinit pci_plx9050_init(struct pci_dev *dev)
 246 {
 247         u8 *p, irq_config;
 248
 249         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
 250                 moan_device("no memory in bar 0", dev);
 251                 return 0;
 252         }
 253
 254         irq_config = 0x41;
 255         if (dev->vendor == PCI_VENDOR_ID_PANACOM)
 256                 irq_config = 0x43;
 257         if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
 258             (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) {
 259                 /*
 260                  * As the megawolf cards have the int pins active
 261                  * high, and have 2 UART chips, both ints must be
 262                  * enabled on the 9050. Also, the UARTS are set in
 263                  * 16450 mode by default, so we have to enable the
 264                  * 16C950 'enhanced' mode so that we can use the
 265                  * deep FIFOs
 266                  */
 267                 irq_config = 0x5b;
 268         }
 269
 270         /*
 271          * enable/disable interrupts
 272          */
 273         p = ioremap(pci_resource_start(dev, 0), 0x80);
 274         if (p == NULL)
 275                 return -ENOMEM;
 276         writel(irq_config, (unsigned long)p + 0x4c);
 277
 278         /*
 279          * Read the register back to ensure that it took effect.
 280          */
 281         readl((unsigned long)p + 0x4c);
 282         iounmap(p);
 283
 284         return 0;
 285 }
 286
 287 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
 288 {
 289         u8 *p;
 290
 291         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
 292                 return;
 293
 294         /*
 295          * disable interrupts
 296          */
 297         p = ioremap(pci_resource_start(dev, 0), 0x80);
 298         if (p != NULL) {
 299                 writel(0, p + 0x4c);
 300
 301                 /*
 302                  * Read the register back to ensure that it took effect.
 303                  */
 304                 readl(p + 0x4c);
 305                 iounmap(p);
 306         }
 307 }
 308
 309 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
 310 static int
 311 sbs_setup(struct pci_dev *dev, struct pci_board *board,
 312                 struct serial_struct *req, int idx)
 313 {
 314         unsigned int bar, offset = board->first_offset;
 315
 316         bar = 0;
 317
 318         if (idx < 4) {
 319                 /* first four channels map to 0, 0x100, 0x200, 0x300 */
 320                 offset += idx * board->uart_offset;
 321         } else if (idx < 8) {
 322                 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
 323                 offset += idx * board->uart_offset + 0xC00;
 324         } else /* we have only 8 ports on PMC-OCTALPRO */
 325                 return 1;
 326
 327         return setup_port(dev, req, bar, offset, board->reg_shift);
 328 }
 329
 330 /*
 331 * This does initialization for PMC OCTALPRO cards:
 332 * maps the device memory, resets the UARTs (needed, bc
 333 * if the module is removed and inserted again, the card
 334 * is in the sleep mode) and enables global interrupt.
 335 */
 336
 337 /* global control register offset for SBS PMC-OctalPro */
 338 #define OCT_REG_CR_OFF          0x500
 339
 340 static int __devinit sbs_init(struct pci_dev *dev)
 341 {
 342         u8 * p;
 343
 344         p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
 345
 346         if (p == NULL)
 347                 return -ENOMEM;
 348         /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
 349         writeb(0x10,p + OCT_REG_CR_OFF);
 350         udelay(50);
 351         writeb(0x0,p + OCT_REG_CR_OFF);
 352
 353         /* Set bit-2 (INTENABLE) of Control Register */
 354         writeb(0x4, p + OCT_REG_CR_OFF);
 355         iounmap(p);
 356
 357         return 0;
 358 }
 359
 360 /*
 361  * Disables the global interrupt of PMC-OctalPro
 362  */
 363
 364 static void __devexit sbs_exit(struct pci_dev *dev)
 365 {
 366         u8 * p;
 367
 368         p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
 369         if (p != NULL) {
 370                 writeb(0, p + OCT_REG_CR_OFF);
 371         }
 372         iounmap(p);
 373 }
 374
 375 /*
 376  * SIIG serial cards have an PCI interface chip which also controls
 377  * the UART clocking frequency. Each UART can be clocked independently
 378  * (except cards equiped with 4 UARTs) and initial clocking settings
 379  * are stored in the EEPROM chip. It can cause problems because this
 380  * version of serial driver doesn't support differently clocked UART's
 381  * on single PCI card. To prevent this, initialization functions set
 382  * high frequency clocking for all UART's on given card. It is safe (I
 383  * hope) because it doesn't touch EEPROM settings to prevent conflicts
 384  * with other OSes (like M$ DOS).
 385  *
 386  *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
 387  *
 388  * There is two family of SIIG serial cards with different PCI
 389  * interface chip and different configuration methods:
 390  *     - 10x cards have control registers in IO and/or memory space;
 391  *     - 20x cards have control registers in standard PCI configuration space.
 392  *
 393  * Note: some SIIG cards are probed by the parport_serial object.
 394  */
 395
 396 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
 397 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
 398
 399 static int pci_siig10x_init(struct pci_dev *dev)
 400 {
 401         u16 data, *p;
 402
 403         switch (dev->device & 0xfff8) {
 404         case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
 405                 data = 0xffdf;
 406                 break;
 407         case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
 408                 data = 0xf7ff;
 409                 break;
 410         default:                        /* 1S1P, 4S */
 411                 data = 0xfffb;
 412                 break;
 413         }
 414
 415         p = ioremap(pci_resource_start(dev, 0), 0x80);
 416         if (p == NULL)
 417                 return -ENOMEM;
 418
 419         writew(readw((unsigned long) p + 0x28) & data, (unsigned long) p + 0x28);
 420         readw((unsigned long)p + 0x28);
 421         iounmap(p);
 422         return 0;
 423 }
 424
 425 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
 426 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
 427
 428 static int pci_siig20x_init(struct pci_dev *dev)
 429 {
 430         u8 data;
 431
 432         /* Change clock frequency for the first UART. */
 433         pci_read_config_byte(dev, 0x6f, &data);
 434         pci_write_config_byte(dev, 0x6f, data & 0xef);
 435
 436         /* If this card has 2 UART, we have to do the same with second UART. */
 437         if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
 438             ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
 439                 pci_read_config_byte(dev, 0x73, &data);
 440                 pci_write_config_byte(dev, 0x73, data & 0xef);
 441         }
 442         return 0;
 443 }
 444
 445 int pci_siig10x_fn(struct pci_dev *dev, int enable)
 446 {
 447         int ret = 0;
 448         if (enable)
 449                 ret = pci_siig10x_init(dev);
 450         return ret;
 451 }
 452
 453 int pci_siig20x_fn(struct pci_dev *dev, int enable)
 454 {
 455         int ret = 0;
 456         if (enable)
 457                 ret = pci_siig20x_init(dev);
 458         return ret;
 459 }
 460
 461 EXPORT_SYMBOL(pci_siig10x_fn);
 462 EXPORT_SYMBOL(pci_siig20x_fn);
 463
 464 /*
 465  * Timedia has an explosion of boards, and to avoid the PCI table from
 466  * growing *huge*, we use this function to collapse some 70 entries
 467  * in the PCI table into one, for sanity's and compactness's sake.
 468  */
 469 static unsigned short timedia_single_port[] = {
 470         0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
 471 };
 472
 473 static unsigned short timedia_dual_port[] = {
 474         0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
 475         0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
 476         0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
 477         0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
 478         0xD079, 0
 479 };
 480
 481 static unsigned short timedia_quad_port[] = {
 482         0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
 483         0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
 484         0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
 485         0xB157, 0
 486 };
 487
 488 static unsigned short timedia_eight_port[] = {
 489         0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
 490         0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
 491 };
 492
 493 static struct timedia_struct {
 494         int num;
 495         unsigned short *ids;
 496 } timedia_data[] = {
 497         { 1, timedia_single_port },
 498         { 2, timedia_dual_port },
 499         { 4, timedia_quad_port },
 500         { 8, timedia_eight_port },
 501         { 0, 0 }
 502 };
 503
 504 static int __devinit pci_timedia_init(struct pci_dev *dev)
 505 {
 506         unsigned short *ids;
 507         int i, j;
 508
 509         for (i = 0; timedia_data[i].num; i++) {
 510                 ids = timedia_data[i].ids;
 511                 for (j = 0; ids[j]; j++)
 512                         if (dev->subsystem_device == ids[j])
 513                                 return timedia_data[i].num;
 514         }
 515         return 0;
 516 }
 517
 518 /*
 519  * Timedia/SUNIX uses a mixture of BARs and offsets
 520  * Ugh, this is ugly as all hell --- TYT
 521  */
 522 static int
 523 pci_timedia_setup(struct pci_dev *dev, struct pci_board *board,
 524                   struct serial_struct *req, int idx)
 525 {
 526         unsigned int bar = 0, offset = board->first_offset;
 527
 528         switch (idx) {
 529         case 0:
 530                 bar = 0;
 531                 break;
 532         case 1:
 533                 offset = board->uart_offset;
 534                 bar = 0;
 535                 break;
 536         case 2:
 537                 bar = 1;
 538                 break;
 539         case 3:
 540                 offset = board->uart_offset;
 541                 bar = 1;
 542         case 4: /* BAR 2 */
 543         case 5: /* BAR 3 */
 544         case 6: /* BAR 4 */
 545         case 7: /* BAR 5 */
 546                 bar = idx - 2;
 547         }
 548
 549         return setup_port(dev, req, bar, offset, board->reg_shift);
 550 }
 551
 552 /*
 553  * Some Titan cards are also a little weird
 554  */
 555 static int
 556 titan_400l_800l_setup(struct pci_dev *dev, struct pci_board *board,
 557                       struct serial_struct *req, int idx)
 558 {
 559         unsigned int bar, offset = board->first_offset;
 560
 561         switch (idx) {
 562         case 0:
 563                 bar = 1;
 564                 break;
 565         case 1:
 566                 bar = 2;
 567                 break;
 568         default:
 569                 bar = 4;
 570                 offset = (idx - 2) * board->uart_offset;
 571         }
 572
 573         return setup_port(dev, req, bar, offset, board->reg_shift);
 574 }
 575
 576 static int __devinit pci_xircom_init(struct pci_dev *dev)
 577 {
 578         __set_current_state(TASK_UNINTERRUPTIBLE);
 579         schedule_timeout(HZ/10);
 580         return 0;
 581 }
 582
 583 static int
 584 pci_default_setup(struct pci_dev *dev, struct pci_board *board,
 585                   struct serial_struct *req, int idx)
 586 {
 587         unsigned int bar, offset = board->first_offset, maxnr;
 588
 589         bar = FL_GET_BASE(board->flags);
 590         if (board->flags & FL_BASE_BARS)
 591                 bar += idx;
 592         else
 593                 offset += idx * board->uart_offset;
 594
 595         maxnr = (pci_resource_len(dev, bar) - board->first_offset) /
 596                 (8 << board->reg_shift);
 597
 598         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
 599                 return 1;
 600
 601         return setup_port(dev, req, bar, offset, board->reg_shift);
 602 }
 603
 604 /* This should be in linux/pci_ids.h */
 605 #define PCI_VENDOR_ID_SBSMODULARIO      0x124B
 606 #define PCI_SUBVENDOR_ID_SBSMODULARIO   0x124B
 607 #define PCI_DEVICE_ID_OCTPRO            0x0001
 608 #define PCI_SUBDEVICE_ID_OCTPRO232      0x0108
 609 #define PCI_SUBDEVICE_ID_OCTPRO422      0x0208
 610 #define PCI_SUBDEVICE_ID_POCTAL232      0x0308
 611 #define PCI_SUBDEVICE_ID_POCTAL422      0x0408
 612
 613 /*
 614  * Master list of serial port init/setup/exit quirks.
 615  * This does not describe the general nature of the port.
 616  * (ie, baud base, number and location of ports, etc)
 617  *
 618  * This list is ordered alphabetically by vendor then device.
 619  * Specific entries must come before more generic entries.
 620  */
 621 static struct pci_serial_quirk pci_serial_quirks[] = {
 622         /*
 623          * AFAVLAB cards.
 624          *  It is not clear whether this applies to all products.
 625          */
 626         {
 627                 .vendor         = PCI_VENDOR_ID_AFAVLAB,
 628                 .device         = PCI_ANY_ID,
 629                 .subvendor      = PCI_ANY_ID,
 630                 .subdevice      = PCI_ANY_ID,
 631                 .setup          = afavlab_setup,
 632         },
 633         /*
 634          * HP Diva
 635          */
 636         {
 637                 .vendor         = PCI_VENDOR_ID_HP,
 638                 .device         = PCI_DEVICE_ID_HP_DIVA,
 639                 .subvendor      = PCI_ANY_ID,
 640                 .subdevice      = PCI_ANY_ID,
 641                 .init           = pci_hp_diva_init,
 642                 .setup          = pci_hp_diva_setup,
 643         },
 644         /*
 645          * Intel
 646          */
 647         {
 648                 .vendor         = PCI_VENDOR_ID_INTEL,
 649                 .device         = PCI_DEVICE_ID_INTEL_80960_RP,
 650                 .subvendor      = 0xe4bf,
 651                 .subdevice      = PCI_ANY_ID,
 652                 .init           = pci_inteli960ni_init,
 653                 .setup          = pci_default_setup,
 654         },
 655         /*
 656          * Panacom
 657          */
 658         {
 659                 .vendor         = PCI_VENDOR_ID_PANACOM,
 660                 .device         = PCI_DEVICE_ID_PANACOM_QUADMODEM,
 661                 .subvendor      = PCI_ANY_ID,
 662                 .subdevice      = PCI_ANY_ID,
 663                 .init           = pci_plx9050_init,
 664                 .setup          = pci_default_setup,
 665                 .exit           = __devexit_p(pci_plx9050_exit),
 666         },
 667         {
 668                 .vendor         = PCI_VENDOR_ID_PANACOM,
 669                 .device         = PCI_DEVICE_ID_PANACOM_DUALMODEM,
 670                 .subvendor      = PCI_ANY_ID,
 671                 .subdevice      = PCI_ANY_ID,
 672                 .init           = pci_plx9050_init,
 673                 .setup          = pci_default_setup,
 674                 .exit           = __devexit_p(pci_plx9050_exit),
 675         },
 676         /*
 677          * PLX
 678          */
 679         {
 680                 .vendor         = PCI_VENDOR_ID_PLX,
 681                 .device         = PCI_DEVICE_ID_PLX_9050,
 682                 .subvendor      = PCI_SUBVENDOR_ID_KEYSPAN,
 683                 .subdevice      = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
 684                 .init           = pci_plx9050_init,
 685                 .setup          = pci_default_setup,
 686                 .exit           = __devexit_p(pci_plx9050_exit),
 687         },
 688         {
 689                 .vendor         = PCI_VENDOR_ID_PLX,
 690                 .device         = PCI_DEVICE_ID_PLX_ROMULUS,
 691                 .subvendor      = PCI_VENDOR_ID_PLX,
 692                 .subdevice      = PCI_DEVICE_ID_PLX_ROMULUS,
 693                 .init           = pci_plx9050_init,
 694                 .setup          = pci_default_setup,
 695                 .exit           = __devexit_p(pci_plx9050_exit),
 696         },
 697         /*
 698          * SBS Technologies, Inc., PMC-OCTALPRO 232
 699          */
 700         {
 701                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 702                 .device         = PCI_DEVICE_ID_OCTPRO,
 703                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 704                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO232,
 705                 .init           = sbs_init,
 706                 .setup          = sbs_setup,
 707                 .exit           = sbs_exit
 708         },
 709         /*
 710          * SBS Technologies, Inc., PMC-OCTALPRO 422
 711          */
 712         {
 713                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 714                 .device         = PCI_DEVICE_ID_OCTPRO,
 715                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 716                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO422,
 717                 .init           = sbs_init,
 718                 .setup          = sbs_setup,
 719                 .exit           = sbs_exit
 720         },
 721         /*
 722          * SBS Technologies, Inc., P-Octal 232
 723          */
 724         {
 725                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 726                 .device         = PCI_DEVICE_ID_OCTPRO,
 727                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 728                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL232,
 729                 .init           = sbs_init,
 730                 .setup          = sbs_setup,
 731                 .exit           = sbs_exit
 732         },
 733         /*
 734          * SBS Technologies, Inc., P-Octal 422
 735          */
 736         {
 737                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 738                 .device         = PCI_DEVICE_ID_OCTPRO,
 739                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 740                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL422,
 741                 .init           = sbs_init,
 742                 .setup          = sbs_setup,
 743                 .exit           = sbs_exit
 744         },
 745
 746         /*
 747          * SIIG cards.
 748          *  It is not clear whether these could be collapsed.
 749          */
 750         {
 751                 .vendor         = PCI_VENDOR_ID_SIIG,
 752                 .device         = PCI_DEVICE_ID_SIIG_1S_10x_550,
 753                 .subvendor      = PCI_ANY_ID,
 754                 .subdevice      = PCI_ANY_ID,
 755                 .init           = pci_siig10x_init,
 756                 .setup          = pci_default_setup,
 757         },
 758         {
 759                 .vendor         = PCI_VENDOR_ID_SIIG,
 760                 .device         = PCI_DEVICE_ID_SIIG_1S_10x_650,
 761                 .subvendor      = PCI_ANY_ID,
 762                 .subdevice      = PCI_ANY_ID,
 763                 .init           = pci_siig10x_init,
 764                 .setup          = pci_default_setup,
 765         },
 766         {
 767                 .vendor         = PCI_VENDOR_ID_SIIG,
 768                 .device         = PCI_DEVICE_ID_SIIG_1S_10x_850,
 769                 .subvendor      = PCI_ANY_ID,
 770                 .subdevice      = PCI_ANY_ID,
 771                 .init           = pci_siig10x_init,
 772                 .setup          = pci_default_setup,
 773         },
 774         {
 775                 .vendor         = PCI_VENDOR_ID_SIIG,
 776                 .device         = PCI_DEVICE_ID_SIIG_2S_10x_550,
 777                 .subvendor      = PCI_ANY_ID,
 778                 .subdevice      = PCI_ANY_ID,
 779                 .init           = pci_siig10x_init,
 780                 .setup          = pci_default_setup,
 781         },
 782         {
 783                 .vendor         = PCI_VENDOR_ID_SIIG,
 784                 .device         = PCI_DEVICE_ID_SIIG_2S_10x_650,
 785                 .subvendor      = PCI_ANY_ID,
 786                 .subdevice      = PCI_ANY_ID,
 787                 .init           = pci_siig10x_init,
 788                 .setup          = pci_default_setup,
 789         },
 790         {
 791                 .vendor         = PCI_VENDOR_ID_SIIG,
 792                 .device         = PCI_DEVICE_ID_SIIG_2S_10x_850,
 793                 .subvendor      = PCI_ANY_ID,
 794                 .subdevice      = PCI_ANY_ID,
 795                 .init           = pci_siig10x_init,
 796                 .setup          = pci_default_setup,
 797         },
 798         {
 799                 .vendor         = PCI_VENDOR_ID_SIIG,
 800                 .device         = PCI_DEVICE_ID_SIIG_4S_10x_550,
 801                 .subvendor      = PCI_ANY_ID,
 802                 .subdevice      = PCI_ANY_ID,
 803                 .init           = pci_siig10x_init,
 804                 .setup          = pci_default_setup,
 805         },
 806         {
 807                 .vendor         = PCI_VENDOR_ID_SIIG,
 808                 .device         = PCI_DEVICE_ID_SIIG_4S_10x_650,
 809                 .subvendor      = PCI_ANY_ID,
 810                 .subdevice      = PCI_ANY_ID,
 811                 .init           = pci_siig10x_init,
 812                 .setup          = pci_default_setup,
 813         },
 814         {
 815                 .vendor         = PCI_VENDOR_ID_SIIG,
 816                 .device         = PCI_DEVICE_ID_SIIG_4S_10x_850,
 817                 .subvendor      = PCI_ANY_ID,
 818                 .subdevice      = PCI_ANY_ID,
 819                 .init           = pci_siig10x_init,
 820                 .setup          = pci_default_setup,
 821         },
 822         {
 823                 .vendor         = PCI_VENDOR_ID_SIIG,
 824                 .device         = PCI_DEVICE_ID_SIIG_1S_20x_550,
 825                 .subvendor      = PCI_ANY_ID,
 826                 .subdevice      = PCI_ANY_ID,
 827                 .init           = pci_siig20x_init,
 828                 .setup          = pci_default_setup,
 829         },
 830         {
 831                 .vendor         = PCI_VENDOR_ID_SIIG,
 832                 .device         = PCI_DEVICE_ID_SIIG_1S_20x_650,
 833                 .subvendor      = PCI_ANY_ID,
 834                 .subdevice      = PCI_ANY_ID,
 835                 .init           = pci_siig20x_init,
 836                 .setup          = pci_default_setup,
 837         },
 838         {
 839                 .vendor         = PCI_VENDOR_ID_SIIG,
 840                 .device         = PCI_DEVICE_ID_SIIG_1S_20x_850,
 841                 .subvendor      = PCI_ANY_ID,
 842                 .subdevice      = PCI_ANY_ID,
 843                 .init           = pci_siig20x_init,
 844                 .setup          = pci_default_setup,
 845         },
 846         {
 847                 .vendor         = PCI_VENDOR_ID_SIIG,
 848                 .device         = PCI_DEVICE_ID_SIIG_2S_20x_550,
 849                 .subvendor      = PCI_ANY_ID,
 850                 .subdevice      = PCI_ANY_ID,
 851                 .init           = pci_siig20x_init,
 852                 .setup          = pci_default_setup,
 853         },
 854         {       .vendor         = PCI_VENDOR_ID_SIIG,
 855                 .device         = PCI_DEVICE_ID_SIIG_2S_20x_650,
 856                 .subvendor      = PCI_ANY_ID,
 857                 .subdevice      = PCI_ANY_ID,
 858                 .init           = pci_siig20x_init,
 859                 .setup          = pci_default_setup,
 860         },
 861         {
 862                 .vendor         = PCI_VENDOR_ID_SIIG,
 863                 .device         = PCI_DEVICE_ID_SIIG_2S_20x_850,
 864                 .subvendor      = PCI_ANY_ID,
 865                 .subdevice      = PCI_ANY_ID,
 866                 .init           = pci_siig20x_init,
 867                 .setup          = pci_default_setup,
 868         },
 869         {
 870                 .vendor         = PCI_VENDOR_ID_SIIG,
 871                 .device         = PCI_DEVICE_ID_SIIG_4S_20x_550,
 872                 .subvendor      = PCI_ANY_ID,
 873                 .subdevice      = PCI_ANY_ID,
 874                 .init           = pci_siig20x_init,
 875                 .setup          = pci_default_setup,
 876         },
 877         {
 878                 .vendor         = PCI_VENDOR_ID_SIIG,
 879                 .device         = PCI_DEVICE_ID_SIIG_4S_20x_650,
 880                 .subvendor      = PCI_ANY_ID,
 881                 .subdevice      = PCI_ANY_ID,
 882                 .init           = pci_siig20x_init,
 883                 .setup          = pci_default_setup,
 884         },
 885         {
 886                 .vendor         = PCI_VENDOR_ID_SIIG,
 887                 .device         = PCI_DEVICE_ID_SIIG_4S_20x_850,
 888                 .subvendor      = PCI_ANY_ID,
 889                 .subdevice      = PCI_ANY_ID,
 890                 .init           = pci_siig20x_init,
 891                 .setup          = pci_default_setup,
 892         },
 893         /*
 894          * Titan cards
 895          */
 896         {
 897                 .vendor         = PCI_VENDOR_ID_TITAN,
 898                 .device         = PCI_DEVICE_ID_TITAN_400L,
 899                 .subvendor      = PCI_ANY_ID,
 900                 .subdevice      = PCI_ANY_ID,
 901                 .setup          = titan_400l_800l_setup,
 902         },
 903         {
 904                 .vendor         = PCI_VENDOR_ID_TITAN,
 905                 .device         = PCI_DEVICE_ID_TITAN_800L,
 906                 .subvendor      = PCI_ANY_ID,
 907                 .subdevice      = PCI_ANY_ID,
 908                 .setup          = titan_400l_800l_setup,
 909         },
 910         /*
 911          * Timedia cards
 912          */
 913         {
 914                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
 915                 .device         = PCI_DEVICE_ID_TIMEDIA_1889,
 916                 .subvendor      = PCI_VENDOR_ID_TIMEDIA,
 917                 .subdevice      = PCI_ANY_ID,
 918                 .init           = pci_timedia_init,
 919                 .setup          = pci_timedia_setup,
 920         },
 921         {
 922                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
 923                 .device         = PCI_ANY_ID,
 924                 .subvendor      = PCI_ANY_ID,
 925                 .subdevice      = PCI_ANY_ID,
 926                 .setup          = pci_timedia_setup,
 927         },
 928         /*
 929          * Xircom cards
 930          */
 931         {
 932                 .vendor         = PCI_VENDOR_ID_XIRCOM,
 933                 .device         = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
 934                 .subvendor      = PCI_ANY_ID,
 935                 .subdevice      = PCI_ANY_ID,
 936                 .init           = pci_xircom_init,
 937                 .setup          = pci_default_setup,
 938         },
 939         /*
 940          * Default "match everything" terminator entry
 941          */
 942         {
 943                 .vendor         = PCI_ANY_ID,
 944                 .device         = PCI_ANY_ID,
 945                 .subvendor      = PCI_ANY_ID,
 946                 .subdevice      = PCI_ANY_ID,
 947                 .setup          = pci_default_setup,
 948         }
 949 };
 950
 951 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
 952 {
 953         return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
 954 }
 955
 956 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
 957 {
 958         struct pci_serial_quirk *quirk;
 959
 960         for (quirk = pci_serial_quirks; ; quirk++)
 961                 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
 962                     quirk_id_matches(quirk->device, dev->device) &&
 963                     quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
 964                     quirk_id_matches(quirk->subdevice, dev->subsystem_device))
 965                         break;
 966         return quirk;
 967 }
 968
 969 static _INLINE_ int
 970 get_pci_irq(struct pci_dev *dev, struct pci_board *board, int idx)
 971 {
 972         if (board->flags & FL_NOIRQ)
 973                 return 0;
 974         else
 975                 return dev->irq;
 976 }
 977
 978 /*
 979  * This is the configuration table for all of the PCI serial boards
 980  * which we support.  It is directly indexed by the pci_board_num_t enum
 981  * value, which is encoded in the pci_device_id PCI probe table's
 982  * driver_data member.
 983  *
 984  * The makeup of these names are:
 985  *  pbn_bn{_bt}_n_baud
 986  *
 987  *  bn   = PCI BAR number
 988  *  bt   = Index using PCI BARs
 989  *  n    = number of serial ports
 990  *  baud = baud rate
 991  *
 992  * Please note: in theory if n = 1, _bt infix should make no difference.
 993  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
 994  */
 995 enum pci_board_num_t {
 996         pbn_default = 0,
 997
 998         pbn_b0_1_115200,
 999         pbn_b0_2_115200,
1000         pbn_b0_4_115200,
1001         pbn_b0_5_115200,
1002
1003         pbn_b0_1_921600,
1004         pbn_b0_2_921600,
1005         pbn_b0_4_921600,
1006
1007         pbn_b0_bt_1_115200,
1008         pbn_b0_bt_2_115200,
1009         pbn_b0_bt_8_115200,
1010
1011         pbn_b0_bt_1_460800,
1012         pbn_b0_bt_2_460800,
1013         pbn_b0_bt_4_460800,
1014
1015         pbn_b0_bt_1_921600,
1016         pbn_b0_bt_2_921600,
1017         pbn_b0_bt_4_921600,
1018         pbn_b0_bt_8_921600,
1019
1020         pbn_b1_1_115200,
1021         pbn_b1_2_115200,
1022         pbn_b1_4_115200,
1023         pbn_b1_8_115200,
1024
1025         pbn_b1_1_921600,
1026         pbn_b1_2_921600,
1027         pbn_b1_4_921600,
1028         pbn_b1_8_921600,
1029
1030         pbn_b1_bt_2_921600,
1031
1032         pbn_b1_2_1382400,
1033         pbn_b1_4_1382400,
1034         pbn_b1_8_1382400,
1035
1036         pbn_b2_1_115200,
1037         pbn_b2_8_115200,
1038
1039         pbn_b2_1_460800,
1040         pbn_b2_4_460800,
1041         pbn_b2_8_460800,
1042         pbn_b2_16_460800,
1043
1044         pbn_b2_1_921600,
1045         pbn_b2_4_921600,
1046         pbn_b2_8_921600,
1047
1048         pbn_b2_bt_1_115200,
1049         pbn_b2_bt_2_115200,
1050         pbn_b2_bt_4_115200,
1051
1052         pbn_b2_bt_2_921600,
1053         pbn_b2_bt_4_921600,
1054
1055         pbn_b3_4_115200,
1056         pbn_b3_8_115200,
1057
1058         /*
1059          * Board-specific versions.
1060          */
1061         pbn_panacom,
1062         pbn_panacom2,
1063         pbn_panacom4,
1064         pbn_plx_romulus,
1065         pbn_oxsemi,
1066         pbn_intel_i960,
1067         pbn_sgi_ioc3,
1068         pbn_nec_nile4,
1069         pbn_computone_4,
1070         pbn_computone_6,
1071         pbn_computone_8,
1072         pbn_sbsxrsio,
1073 };
1074
1075 /*
1076  * uart_offset - the space between channels
1077  * reg_shift   - describes how the UART registers are mapped
1078  *               to PCI memory by the card.
1079  * For example IER register on SBS, Inc. PMC-OctPro is located at
1080  * offset 0x10 from the UART base, while UART_IER is defined as 1
1081  * in include/linux/serial_reg.h,
1082  * see first lines of serial_in() and serial_out() in 8250.c
1083 */
1084
1085 static struct pci_board pci_boards[] __devinitdata = {
1086         [pbn_default] = {
1087                 .flags          = FL_BASE0,
1088                 .num_ports      = 1,
1089                 .base_baud      = 115200,
1090                 .uart_offset    = 8,
1091         },
1092         [pbn_b0_1_115200] = {
1093                 .flags          = FL_BASE0,
1094                 .num_ports      = 1,
1095                 .base_baud      = 115200,
1096                 .uart_offset    = 8,
1097         },
1098         [pbn_b0_2_115200] = {
1099                 .flags          = FL_BASE0,
1100                 .num_ports      = 2,
1101                 .base_baud      = 115200,
1102                 .uart_offset    = 8,
1103         },
1104         [pbn_b0_4_115200] = {
1105                 .flags          = FL_BASE0,
1106                 .num_ports      = 4,
1107                 .base_baud      = 115200,
1108                 .uart_offset    = 8,
1109         },
1110         [pbn_b0_5_115200] = {
1111                 .flags          = FL_BASE0,
1112                 .num_ports      = 5,
1113                 .base_baud      = 115200,
1114                 .uart_offset    = 8,
1115         },
1116
1117         [pbn_b0_1_921600] = {
1118                 .flags          = FL_BASE0,
1119                 .num_ports      = 1,
1120                 .base_baud      = 921600,
1121                 .uart_offset    = 8,
1122         },
1123         [pbn_b0_2_921600] = {
1124                 .flags          = FL_BASE0,
1125                 .num_ports      = 2,
1126                 .base_baud      = 921600,
1127                 .uart_offset    = 8,
1128         },
1129         [pbn_b0_4_921600] = {
1130                 .flags          = FL_BASE0,
1131                 .num_ports      = 4,
1132                 .base_baud      = 921600,
1133                 .uart_offset    = 8,
1134         },
1135
1136         [pbn_b0_bt_1_115200] = {
1137                 .flags          = FL_BASE0|FL_BASE_BARS,
1138                 .num_ports      = 1,
1139                 .base_baud      = 115200,
1140                 .uart_offset    = 8,
1141         },
1142         [pbn_b0_bt_2_115200] = {
1143                 .flags          = FL_BASE0|FL_BASE_BARS,
1144                 .num_ports      = 2,
1145                 .base_baud      = 115200,
1146                 .uart_offset    = 8,
1147         },
1148         [pbn_b0_bt_8_115200] = {
1149                 .flags          = FL_BASE0|FL_BASE_BARS,
1150                 .num_ports      = 8,
1151                 .base_baud      = 115200,
1152                 .uart_offset    = 8,
1153         },
1154
1155         [pbn_b0_bt_1_460800] = {
1156                 .flags          = FL_BASE0|FL_BASE_BARS,
1157                 .num_ports      = 1,
1158                 .base_baud      = 460800,
1159                 .uart_offset    = 8,
1160         },
1161         [pbn_b0_bt_2_460800] = {
1162                 .flags          = FL_BASE0|FL_BASE_BARS,
1163                 .num_ports      = 2,
1164                 .base_baud      = 460800,
1165                 .uart_offset    = 8,
1166         },
1167         [pbn_b0_bt_4_460800] = {
1168                 .flags          = FL_BASE0|FL_BASE_BARS,
1169                 .num_ports      = 4,
1170                 .base_baud      = 460800,
1171                 .uart_offset    = 8,
1172         },
1173
1174         [pbn_b0_bt_1_921600] = {
1175                 .flags          = FL_BASE0|FL_BASE_BARS,
1176                 .num_ports      = 1,
1177                 .base_baud      = 921600,
1178                 .uart_offset    = 8,
1179         },
1180         [pbn_b0_bt_2_921600] = {
1181                 .flags          = FL_BASE0|FL_BASE_BARS,
1182                 .num_ports      = 2,
1183                 .base_baud      = 921600,
1184                 .uart_offset    = 8,
1185         },
1186         [pbn_b0_bt_4_921600] = {
1187                 .flags          = FL_BASE0|FL_BASE_BARS,
1188                 .num_ports      = 4,
1189                 .base_baud      = 921600,
1190                 .uart_offset    = 8,
1191         },
1192         [pbn_b0_bt_8_921600] = {
1193                 .flags          = FL_BASE0|FL_BASE_BARS,
1194                 .num_ports      = 8,
1195                 .base_baud      = 921600,
1196                 .uart_offset    = 8,
1197         },
1198
1199         [pbn_b1_1_115200] = {
1200                 .flags          = FL_BASE1,
1201                 .num_ports      = 1,
1202                 .base_baud      = 115200,
1203                 .uart_offset    = 8,
1204         },
1205         [pbn_b1_2_115200] = {
1206                 .flags          = FL_BASE1,
1207                 .num_ports      = 2,
1208                 .base_baud      = 115200,
1209                 .uart_offset    = 8,
1210         },
1211         [pbn_b1_4_115200] = {
1212                 .flags          = FL_BASE1,
1213                 .num_ports      = 4,
1214                 .base_baud      = 115200,
1215                 .uart_offset    = 8,
1216         },
1217         [pbn_b1_8_115200] = {
1218                 .flags          = FL_BASE1,
1219                 .num_ports      = 8,
1220                 .base_baud      = 115200,
1221                 .uart_offset    = 8,
1222         },
1223
1224         [pbn_b1_1_921600] = {
1225                 .flags          = FL_BASE1,
1226                 .num_ports      = 1,
1227                 .base_baud      = 921600,
1228                 .uart_offset    = 8,
1229         },
1230         [pbn_b1_2_921600] = {
1231                 .flags          = FL_BASE1,
1232                 .num_ports      = 2,
1233                 .base_baud      = 921600,
1234                 .uart_offset    = 8,
1235         },
1236         [pbn_b1_4_921600] = {
1237                 .flags          = FL_BASE1,
1238                 .num_ports      = 4,
1239                 .base_baud      = 921600,
1240                 .uart_offset    = 8,
1241         },
1242         [pbn_b1_8_921600] = {
1243                 .flags          = FL_BASE1,
1244                 .num_ports      = 8,
1245                 .base_baud      = 921600,
1246                 .uart_offset    = 8,
1247         },
1248
1249         [pbn_b1_bt_2_921600] = {
1250                 .flags          = FL_BASE1|FL_BASE_BARS,
1251                 .num_ports      = 2,
1252                 .base_baud      = 921600,
1253                 .uart_offset    = 8,
1254         },
1255
1256         [pbn_b1_2_1382400] = {
1257                 .flags          = FL_BASE1,
1258                 .num_ports      = 2,
1259                 .base_baud      = 1382400,
1260                 .uart_offset    = 8,
1261         },
1262         [pbn_b1_4_1382400] = {
1263                 .flags          = FL_BASE1,
1264                 .num_ports      = 4,
1265                 .base_baud      = 1382400,
1266                 .uart_offset    = 8,
1267         },
1268         [pbn_b1_8_1382400] = {
1269                 .flags          = FL_BASE1,
1270                 .num_ports      = 8,
1271                 .base_baud      = 1382400,
1272                 .uart_offset    = 8,
1273         },
1274
1275         [pbn_b2_1_115200] = {
1276                 .flags          = FL_BASE2,
1277                 .num_ports      = 1,
1278                 .base_baud      = 115200,
1279                 .uart_offset    = 8,
1280         },
1281         [pbn_b2_8_115200] = {
1282                 .flags          = FL_BASE2,
1283                 .num_ports      = 8,
1284                 .base_baud      = 115200,
1285                 .uart_offset    = 8,
1286         },
1287
1288         [pbn_b2_1_460800] = {
1289                 .flags          = FL_BASE2,
1290                 .num_ports      = 1,
1291                 .base_baud      = 460800,
1292                 .uart_offset    = 8,
1293         },
1294         [pbn_b2_4_460800] = {
1295                 .flags          = FL_BASE2,
1296                 .num_ports      = 4,
1297                 .base_baud      = 460800,
1298                 .uart_offset    = 8,
1299         },
1300         [pbn_b2_8_460800] = {
1301                 .flags          = FL_BASE2,
1302                 .num_ports      = 8,
1303                 .base_baud      = 460800,
1304                 .uart_offset    = 8,
1305         },
1306         [pbn_b2_16_460800] = {
1307                 .flags          = FL_BASE2,
1308                 .num_ports      = 16,
1309                 .base_baud      = 460800,
1310                 .uart_offset    = 8,
1311          },
1312
1313         [pbn_b2_1_921600] = {
1314                 .flags          = FL_BASE2,
1315                 .num_ports      = 1,
1316                 .base_baud      = 921600,
1317                 .uart_offset    = 8,
1318         },
1319         [pbn_b2_4_921600] = {
1320                 .flags          = FL_BASE2,
1321                 .num_ports      = 4,
1322                 .base_baud      = 921600,
1323                 .uart_offset    = 8,
1324         },
1325         [pbn_b2_8_921600] = {
1326                 .flags          = FL_BASE2,
1327                 .num_ports      = 8,
1328                 .base_baud      = 921600,
1329                 .uart_offset    = 8,
1330         },
1331
1332         [pbn_b2_bt_1_115200] = {
1333                 .flags          = FL_BASE2|FL_BASE_BARS,
1334                 .num_ports      = 1,
1335                 .base_baud      = 115200,
1336                 .uart_offset    = 8,
1337         },
1338         [pbn_b2_bt_2_115200] = {
1339                 .flags          = FL_BASE2|FL_BASE_BARS,
1340                 .num_ports      = 2,
1341                 .base_baud      = 115200,
1342                 .uart_offset    = 8,
1343         },
1344         [pbn_b2_bt_4_115200] = {
1345                 .flags          = FL_BASE2|FL_BASE_BARS,
1346                 .num_ports      = 4,
1347                 .base_baud      = 115200,
1348                 .uart_offset    = 8,
1349         },
1350
1351         [pbn_b2_bt_2_921600] = {
1352                 .flags          = FL_BASE2|FL_BASE_BARS,
1353                 .num_ports      = 2,
1354                 .base_baud      = 921600,
1355                 .uart_offset    = 8,
1356         },
1357         [pbn_b2_bt_4_921600] = {
1358                 .flags          = FL_BASE2|FL_BASE_BARS,
1359                 .num_ports      = 4,
1360                 .base_baud      = 921600,
1361                 .uart_offset    = 8,
1362         },
1363
1364         [pbn_b3_4_115200] = {
1365                 .flags          = FL_BASE3,
1366                 .num_ports      = 4,
1367                 .base_baud      = 115200,
1368                 .uart_offset    = 8,
1369         },
1370         [pbn_b3_8_115200] = {
1371                 .flags          = FL_BASE3,
1372                 .num_ports      = 8,
1373                 .base_baud      = 115200,
1374                 .uart_offset    = 8,
1375         },
1376
1377         /*
1378          * Entries following this are board-specific.
1379          */
1380
1381         /*
1382          * Panacom - IOMEM
1383          */
1384         [pbn_panacom] = {
1385                 .flags          = FL_BASE2,
1386                 .num_ports      = 2,
1387                 .base_baud      = 921600,
1388                 .uart_offset    = 0x400,
1389                 .reg_shift      = 7,
1390         },
1391         [pbn_panacom2] = {
1392                 .flags          = FL_BASE2|FL_BASE_BARS,
1393                 .num_ports      = 2,
1394                 .base_baud      = 921600,
1395                 .uart_offset    = 0x400,
1396                 .reg_shift      = 7,
1397         },
1398         [pbn_panacom4] = {
1399                 .flags          = FL_BASE2|FL_BASE_BARS,
1400                 .num_ports      = 4,
1401                 .base_baud      = 921600,
1402                 .uart_offset    = 0x400,
1403                 .reg_shift      = 7,
1404         },
1405
1406         /* I think this entry is broken - the first_offset looks wrong --rmk */
1407         [pbn_plx_romulus] = {
1408                 .flags          = FL_BASE2,
1409                 .num_ports      = 4,
1410                 .base_baud      = 921600,
1411                 .uart_offset    = 8 << 2,
1412                 .reg_shift      = 2,
1413                 .first_offset   = 0x03,
1414         },
1415
1416         /*
1417          * This board uses the size of PCI Base region 0 to
1418          * signal now many ports are available
1419          */
1420         [pbn_oxsemi] = {
1421                 .flags          = FL_BASE0|FL_REGION_SZ_CAP,
1422                 .num_ports      = 32,
1423                 .base_baud      = 115200,
1424                 .uart_offset    = 8,
1425         },
1426
1427         /*
1428          * EKF addition for i960 Boards form EKF with serial port.
1429          * Max 256 ports.
1430          */
1431         [pbn_intel_i960] = {
1432                 .flags          = FL_BASE0,
1433                 .num_ports      = 32,
1434                 .base_baud      = 921600,
1435                 .uart_offset    = 8 << 2,
1436                 .reg_shift      = 2,
1437                 .first_offset   = 0x10000,
1438         },
1439         [pbn_sgi_ioc3] = {
1440                 .flags          = FL_BASE0|FL_NOIRQ,
1441                 .num_ports      = 1,
1442                 .base_baud      = 458333,
1443                 .uart_offset    = 8,
1444                 .reg_shift      = 0,
1445                 .first_offset   = 0x20178,
1446         },
1447
1448         /*
1449          * NEC Vrc-5074 (Nile 4) builtin UART.
1450          */
1451         [pbn_nec_nile4] = {
1452                 .flags          = FL_BASE0,
1453                 .num_ports      = 1,
1454                 .base_baud      = 520833,
1455                 .uart_offset    = 8 << 3,
1456                 .reg_shift      = 3,
1457                 .first_offset   = 0x300,
1458         },
1459
1460         /*
1461          * Computone - uses IOMEM.
1462          */
1463         [pbn_computone_4] = {
1464                 .flags          = FL_BASE0,
1465                 .num_ports      = 4,
1466                 .base_baud      = 921600,
1467                 .uart_offset    = 0x40,
1468                 .reg_shift      = 2,
1469                 .first_offset   = 0x200,
1470         },
1471         [pbn_computone_6] = {
1472                 .flags          = FL_BASE0,
1473                 .num_ports      = 6,
1474                 .base_baud      = 921600,
1475                 .uart_offset    = 0x40,
1476                 .reg_shift      = 2,
1477                 .first_offset   = 0x200,
1478         },
1479         [pbn_computone_8] = {
1480                 .flags          = FL_BASE0,
1481                 .num_ports      = 8,
1482                 .base_baud      = 921600,
1483                 .uart_offset    = 0x40,
1484                 .reg_shift      = 2,
1485                 .first_offset   = 0x200,
1486         },
1487         [pbn_sbsxrsio] = {
1488                 .flags          = FL_BASE0,
1489                 .num_ports      = 8,
1490                 .base_baud      = 460800,
1491                 .uart_offset    = 256,
1492                 .reg_shift      = 4,
1493         }
1494 };
1495
1496 /*
1497  * Given a complete unknown PCI device, try to use some heuristics to
1498  * guess what the configuration might be, based on the pitiful PCI
1499  * serial specs.  Returns 0 on success, 1 on failure.
1500  */
1501 static int __devinit
1502 serial_pci_guess_board(struct pci_dev *dev, struct pci_board *board)
1503 {
1504         int num_iomem, num_port, first_port = -1, i;
1505
1506         /*
1507          * If it is not a communications device or the programming
1508          * interface is greater than 6, give up.
1509          *
1510          * (Should we try to make guesses for multiport serial devices
1511          * later?)
1512          */
1513         if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
1514              ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
1515             (dev->class & 0xff) > 6)
1516                 return -ENODEV;
1517
1518         num_iomem = num_port = 0;
1519         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1520                 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
1521                         num_port++;
1522                         if (first_port == -1)
1523                                 first_port = i;
1524                 }
1525                 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
1526                         num_iomem++;
1527         }
1528
1529         /*
1530          * If there is 1 or 0 iomem regions, and exactly one port,
1531          * use it.  We guess the number of ports based on the IO
1532          * region size.
1533          */
1534         if (num_iomem <= 1 && num_port == 1) {
1535                 board->flags = first_port;
1536                 board->num_ports = pci_resource_len(dev, first_port) / 8;
1537                 return 0;
1538         }
1539
1540         /*
1541          * Now guess if we've got a board which indexes by BARs.
1542          * Each IO BAR should be 8 bytes, and they should follow
1543          * consecutively.
1544          */
1545         first_port = -1;
1546         num_port = 0;
1547         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1548                 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
1549                     pci_resource_len(dev, i) == 8 &&
1550                     (first_port == -1 || (first_port + num_port) == i)) {
1551                         num_port++;
1552                         if (first_port == -1)
1553                                 first_port = i;
1554                 }
1555         }
1556
1557         if (num_port > 1) {
1558                 board->flags = first_port | FL_BASE_BARS;
1559                 board->num_ports = num_port;
1560                 return 0;
1561         }
1562
1563         return -ENODEV;
1564 }
1565
1566 static inline int
1567 serial_pci_matches(struct pci_board *board, struct pci_board *guessed)
1568 {
1569         return
1570             board->num_ports == guessed->num_ports &&
1571             board->base_baud == guessed->base_baud &&
1572             board->uart_offset == guessed->uart_offset &&
1573             board->reg_shift == guessed->reg_shift &&
1574             board->first_offset == guessed->first_offset;
1575 }
1576
1577 /*
1578  * Probe one serial board.  Unfortunately, there is no rhyme nor reason
1579  * to the arrangement of serial ports on a PCI card.
1580  */
1581 static int __devinit
1582 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
1583 {
1584         struct serial_private *priv;
1585         struct pci_board *board, tmp;
1586         struct pci_serial_quirk *quirk;
1587         struct serial_struct serial_req;
1588         int base_baud, rc, nr_ports, i;
1589
1590         if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
1591                 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
1592                         ent->driver_data);
1593                 return -EINVAL;
1594         }
1595
1596         board = &pci_boards[ent->driver_data];
1597
1598         rc = pci_enable_device(dev);
1599         if (rc)
1600                 return rc;
1601
1602         if (ent->driver_data == pbn_default) {
1603                 /*
1604                  * Use a copy of the pci_board entry for this;
1605                  * avoid changing entries in the table.
1606                  */
1607                 memcpy(&tmp, board, sizeof(struct pci_board));
1608                 board = &tmp;
1609
1610                 /*
1611                  * We matched one of our class entries.  Try to
1612                  * determine the parameters of this board.
1613                  */
1614                 rc = serial_pci_guess_board(dev, board);
1615                 if (rc)
1616                         goto disable;
1617         } else {
1618                 /*
1619                  * We matched an explicit entry.  If we are able to
1620                  * detect this boards settings with our heuristic,
1621                  * then we no longer need this entry.
1622                  */
1623                 memcpy(&tmp, &pci_boards[pbn_default], sizeof(struct pci_board));
1624                 rc = serial_pci_guess_board(dev, &tmp);
1625                 if (rc == 0 && serial_pci_matches(board, &tmp))
1626                         moan_device("Redundant entry in serial pci_table.",
1627                                     dev);
1628         }
1629
1630         nr_ports = board->num_ports;
1631
1632         /*
1633          * Find an init and setup quirks.
1634          */
1635         quirk = find_quirk(dev);
1636
1637         /*
1638          * Run the new-style initialization function.
1639          * The initialization function returns:
1640          *  <0  - error
1641          *   0  - use board->num_ports
1642          *  >0  - number of ports
1643          */
1644         if (quirk->init) {
1645                 rc = quirk->init(dev);
1646                 if (rc < 0)
1647                         goto disable;
1648                 if (rc)
1649                         nr_ports = rc;
1650         }
1651
1652         priv = kmalloc(sizeof(struct serial_private) +
1653                        sizeof(unsigned int) * nr_ports,
1654                        GFP_KERNEL);
1655         if (!priv) {
1656                 rc = -ENOMEM;
1657                 goto deinit;
1658         }
1659
1660         memset(priv, 0, sizeof(struct serial_private) +
1661                         sizeof(unsigned int) * nr_ports);
1662
1663         priv->quirk = quirk;
1664         pci_set_drvdata(dev, priv);
1665
1666         base_baud = board->base_baud;
1667         if (!base_baud) {
1668                 moan_device("Board entry does not specify baud rate.", dev);
1669                 base_baud = BASE_BAUD;
1670         }
1671         for (i = 0; i < nr_ports; i++) {
1672                 memset(&serial_req, 0, sizeof(serial_req));
1673                 serial_req.flags = UPF_SKIP_TEST | UPF_AUTOPROBE |
1674                                    UPF_RESOURCES | UPF_SHARE_IRQ;
1675                 serial_req.baud_base = base_baud;
1676                 serial_req.irq = get_pci_irq(dev, board, i);
1677                 if (quirk->setup(dev, board, &serial_req, i))
1678                         break;
1679 #ifdef SERIAL_DEBUG_PCI
1680                 printk("Setup PCI port: port %x, irq %d, type %d\n",
1681                        serial_req.port, serial_req.irq, serial_req.io_type);
1682 #endif
1683
1684                 priv->line[i] = register_serial(&serial_req);
1685                 if (priv->line[i] < 0) {
1686                         printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
1687                         break;
1688                 }
1689         }
1690
1691         priv->nr = i;
1692
1693         return 0;
1694
1695  deinit:
1696         if (quirk->exit)
1697                 quirk->exit(dev);
1698  disable:
1699         pci_disable_device(dev);
1700         return rc;
1701 }
1702
1703 static void __devexit pciserial_remove_one(struct pci_dev *dev)
1704 {
1705         struct serial_private *priv = pci_get_drvdata(dev);
1706
1707         pci_set_drvdata(dev, NULL);
1708
1709         if (priv) {
1710                 struct pci_serial_quirk *quirk;
1711                 int i;
1712
1713                 for (i = 0; i < priv->nr; i++)
1714                         unregister_serial(priv->line[i]);
1715
1716                 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1717                         if (priv->remapped_bar[i])
1718                                 iounmap(priv->remapped_bar[i]);
1719                         priv->remapped_bar[i] = NULL;
1720                 }
1721
1722                 /*
1723                  * Find the exit quirks.
1724                  */
1725                 quirk = find_quirk(dev);
1726                 if (quirk->exit)
1727                         quirk->exit(dev);
1728
1729                 pci_disable_device(dev);
1730
1731                 kfree(priv);
1732         }
1733 }
1734
1735 static int pciserial_suspend_one(struct pci_dev *dev, u32 state)
1736 {
1737         struct serial_private *priv = pci_get_drvdata(dev);
1738
1739         if (priv) {
1740                 int i;
1741
1742                 for (i = 0; i < priv->nr; i++)
1743                         serial8250_suspend_port(priv->line[i]);
1744         }
1745         return 0;
1746 }
1747
1748 static int pciserial_resume_one(struct pci_dev *dev)
1749 {
1750         struct serial_private *priv = pci_get_drvdata(dev);
1751
1752         if (priv) {
1753                 int i;
1754
1755                 /*
1756                  * Ensure that the board is correctly configured.
1757                  */
1758                 if (priv->quirk->init)
1759                         priv->quirk->init(dev);
1760
1761                 for (i = 0; i < priv->nr; i++)
1762                         serial8250_resume_port(priv->line[i]);
1763         }
1764         return 0;
1765 }
1766
1767 static struct pci_device_id serial_pci_tbl[] = {
1768         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1769                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1770                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1771                 pbn_b1_8_1382400 },
1772         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1773                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1774                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1775                 pbn_b1_4_1382400 },
1776         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1777                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1778                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1779                 pbn_b1_2_1382400 },
1780         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1781                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1782                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1783                 pbn_b1_8_1382400 },
1784         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1785                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1786                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1787                 pbn_b1_4_1382400 },
1788         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1789                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1790                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1791                 pbn_b1_2_1382400 },
1792         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1793                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1794                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
1795                 pbn_b1_8_921600 },
1796         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1797                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1798                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
1799                 pbn_b1_8_921600 },
1800         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1801                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1802                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
1803                 pbn_b1_4_921600 },
1804         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1805                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1806                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
1807                 pbn_b1_4_921600 },
1808         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1809                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1810                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
1811                 pbn_b1_2_921600 },
1812         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1813                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1814                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
1815                 pbn_b1_8_921600 },
1816         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1817                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1818                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
1819                 pbn_b1_8_921600 },
1820         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1821                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1822                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
1823                 pbn_b1_4_921600 },
1824
1825         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
1826                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1827                 pbn_b2_bt_1_115200 },
1828         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
1829                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1830                 pbn_b2_bt_2_115200 },
1831         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
1832                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1833                 pbn_b2_bt_4_115200 },
1834         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
1835                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1836                 pbn_b2_bt_2_115200 },
1837         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
1838                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1839                 pbn_b2_bt_4_115200 },
1840         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
1841                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1842                 pbn_b2_8_115200 },
1843
1844         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
1845                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1846                 pbn_b2_bt_2_115200 },
1847         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
1848                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1849                 pbn_b2_bt_2_921600 },
1850         /*
1851          * VScom SPCOM800, from sl@s.pl
1852          */
1853         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
1854                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1855                 pbn_b2_8_921600 },
1856         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
1857                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1858                 pbn_b2_4_921600 },
1859         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1860                 PCI_SUBVENDOR_ID_KEYSPAN,
1861                 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
1862                 pbn_panacom },
1863         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
1864                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1865                 pbn_panacom4 },
1866         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
1867                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1868                 pbn_panacom2 },
1869         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1870                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1871                 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
1872                 pbn_b2_4_460800 },
1873         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1874                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1875                 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
1876                 pbn_b2_8_460800 },
1877         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1878                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1879                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
1880                 pbn_b2_16_460800 },
1881         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1882                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1883                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
1884                 pbn_b2_16_460800 },
1885         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1886                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
1887                 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
1888                 pbn_b2_4_460800 },
1889         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1890                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
1891                 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
1892                 pbn_b2_8_460800 },
1893         /*
1894          * Megawolf Romulus PCI Serial Card, from Mike Hudson
1895          * (Exoray@isys.ca)
1896          */
1897         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
1898                 0x10b5, 0x106a, 0, 0,
1899                 pbn_plx_romulus },
1900         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
1901                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1902                 pbn_b1_4_115200 },
1903         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
1904                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1905                 pbn_b1_2_115200 },
1906         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
1907                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1908                 pbn_b1_8_115200 },
1909         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
1910                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1911                 pbn_b1_8_115200 },
1912         {       PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
1913                 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 0, 0,
1914                 pbn_b0_4_921600 },
1915         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1916                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1917                 pbn_b0_4_115200 },
1918         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
1919                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1920                 pbn_b0_bt_2_921600 },
1921
1922         /*
1923          * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
1924          * from skokodyn@yahoo.com
1925          */
1926         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1927                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
1928                 pbn_sbsxrsio },
1929         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1930                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
1931                 pbn_sbsxrsio },
1932         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1933                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
1934                 pbn_sbsxrsio },
1935         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1936                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
1937                 pbn_sbsxrsio },
1938
1939         /*
1940          * Digitan DS560-558, from jimd@esoft.com
1941          */
1942         {       PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
1943                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1944                 pbn_b1_1_115200 },
1945
1946         /*
1947          * Titan Electronic cards
1948          *  The 400L and 800L have a custom setup quirk.
1949          */
1950         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
1951                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1952                 pbn_b0_1_921600 },
1953         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
1954                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1955                 pbn_b0_2_921600 },
1956         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
1957                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1958                 pbn_b0_4_921600 },
1959         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
1960                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1961                 pbn_b0_4_921600 },
1962         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
1963                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1964                 pbn_b1_1_921600 },
1965         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
1966                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1967                 pbn_b1_bt_2_921600 },
1968         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
1969                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1970                 pbn_b0_bt_4_921600 },
1971         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
1972                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1973                 pbn_b0_bt_8_921600 },
1974
1975         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
1976                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1977                 pbn_b2_1_460800 },
1978         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
1979                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1980                 pbn_b2_1_460800 },
1981         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
1982                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1983                 pbn_b2_1_460800 },
1984         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
1985                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1986                 pbn_b2_bt_2_921600 },
1987         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
1988                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1989                 pbn_b2_bt_2_921600 },
1990         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
1991                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1992                 pbn_b2_bt_2_921600 },
1993         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
1994                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1995                 pbn_b2_bt_4_921600 },
1996         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
1997                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1998                 pbn_b2_bt_4_921600 },
1999         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
2000                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2001                 pbn_b2_bt_4_921600 },
2002         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
2003                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2004                 pbn_b0_1_921600 },
2005         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
2006                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2007                 pbn_b0_1_921600 },
2008         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
2009                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2010                 pbn_b0_1_921600 },
2011         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
2012                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2013                 pbn_b0_bt_2_921600 },
2014         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
2015                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2016                 pbn_b0_bt_2_921600 },
2017         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
2018                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2019                 pbn_b0_bt_2_921600 },
2020         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
2021                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2022                 pbn_b0_bt_4_921600 },
2023         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
2024                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2025                 pbn_b0_bt_4_921600 },
2026         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
2027                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2028                 pbn_b0_bt_4_921600 },
2029
2030         /*
2031          * Computone devices submitted by Doug McNash dmcnash@computone.com
2032          */
2033         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2034                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
2035                 0, 0, pbn_computone_4 },
2036         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2037                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
2038                 0, 0, pbn_computone_8 },
2039         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2040                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
2041                 0, 0, pbn_computone_6 },
2042
2043         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
2044                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2045                 pbn_oxsemi },
2046         {       PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
2047                 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
2048                 pbn_b0_bt_1_921600 },
2049
2050         /*
2051          * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
2052          */
2053         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
2054                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2055                 pbn_b0_bt_8_115200 },
2056         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
2057                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2058                 pbn_b0_bt_8_115200 },
2059
2060         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
2061                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2062                 pbn_b0_bt_2_115200 },
2063         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
2064                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2065                 pbn_b0_bt_2_115200 },
2066         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
2067                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2068                 pbn_b0_bt_2_115200 },
2069         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
2070                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2071                 pbn_b0_bt_4_460800 },
2072         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
2073                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2074                 pbn_b0_bt_4_460800 },
2075         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
2076                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2077                 pbn_b0_bt_2_460800 },
2078         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
2079                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2080                 pbn_b0_bt_2_460800 },
2081         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
2082                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2083                 pbn_b0_bt_2_460800 },
2084         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
2085                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2086                 pbn_b0_bt_1_115200 },
2087         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
2088                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2089                 pbn_b0_bt_1_460800 },
2090
2091         /*
2092          * RAStel 2 port modem, gerg@moreton.com.au
2093          */
2094         {       PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
2095                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2096                 pbn_b2_bt_2_115200 },
2097
2098         /*
2099          * EKF addition for i960 Boards form EKF with serial port
2100          */
2101         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
2102                 0xE4BF, PCI_ANY_ID, 0, 0,
2103                 pbn_intel_i960 },
2104
2105         /*
2106          * Xircom Cardbus/Ethernet combos
2107          */
2108         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2109                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2110                 pbn_b0_1_115200 },
2111         /*
2112          * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
2113          */
2114         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
2115                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2116                 pbn_b0_1_115200 },
2117
2118         /*
2119          * Untested PCI modems, sent in from various folks...
2120          */
2121
2122         /*
2123          * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
2124          */
2125         {       PCI_VENDOR_ID_ROCKWELL, 0x1004,
2126                 0x1048, 0x1500, 0, 0,
2127                 pbn_b1_1_115200 },
2128
2129         {       PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
2130                 0xFF00, 0, 0, 0,
2131                 pbn_sgi_ioc3 },
2132
2133         /*
2134          * HP Diva card
2135          */
2136         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2137                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2138                 pbn_b0_5_115200 },
2139         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
2140                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2141                 pbn_b2_1_115200 },
2142
2143         /*
2144          * NEC Vrc-5074 (Nile 4) builtin UART.
2145          */
2146         {       PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_NILE4,
2147                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2148                 pbn_nec_nile4 },
2149
2150         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
2151                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2152                 pbn_b3_4_115200 },
2153         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
2154                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2155                 pbn_b3_8_115200 },
2156
2157         /*
2158          * These entries match devices with class COMMUNICATION_SERIAL,
2159          * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
2160          */
2161         {       PCI_ANY_ID, PCI_ANY_ID,
2162                 PCI_ANY_ID, PCI_ANY_ID,
2163                 PCI_CLASS_COMMUNICATION_SERIAL << 8,
2164                 0xffff00, pbn_default },
2165         {       PCI_ANY_ID, PCI_ANY_ID,
2166                 PCI_ANY_ID, PCI_ANY_ID,
2167                 PCI_CLASS_COMMUNICATION_MODEM << 8,
2168                 0xffff00, pbn_default },
2169         {       PCI_ANY_ID, PCI_ANY_ID,
2170                 PCI_ANY_ID, PCI_ANY_ID,
2171                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
2172                 0xffff00, pbn_default },
2173         { 0, }
2174 };
2175
2176 static struct pci_driver serial_pci_driver = {
2177         .name           = "serial",
2178         .probe          = pciserial_init_one,
2179         .remove         = __devexit_p(pciserial_remove_one),
2180         .suspend        = pciserial_suspend_one,
2181         .resume         = pciserial_resume_one,
2182         .id_table       = serial_pci_tbl,
2183 };
2184
2185 static int __init serial8250_pci_init(void)
2186 {
2187         return pci_module_init(&serial_pci_driver);
2188 }
2189
2190 static void __exit serial8250_pci_exit(void)
2191 {
2192         pci_unregister_driver(&serial_pci_driver);
2193 }
2194
2195 module_init(serial8250_pci_init);
2196 module_exit(serial8250_pci_exit);
2197
2198 MODULE_LICENSE("GPL");
2199 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
2200 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);