drivers/serial/8250_pci.c

   1 /*
   2  *  linux/drivers/char/8250_pci.c
   3  *
   4  *  Probe module for 8250/16550-type PCI serial ports.
   5  *
   6  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   7  *
   8  *  Copyright (C) 2001 Russell King, All Rights Reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License.
  13  *
  14  *  $Id: 8250_pci.c,v 1.28 2002/11/02 11:14:18 rmk Exp $
  15  */
  16 #include <linux/module.h>
  17 #include <linux/init.h>
  18 #include <linux/pci.h>
  19 #include <linux/sched.h>
  20 #include <linux/string.h>
  21 #include <linux/kernel.h>
  22 #include <linux/slab.h>
  23 #include <linux/delay.h>
  24 #include <linux/tty.h>
  25 #include <linux/serial_core.h>
  26 #include <linux/8250_pci.h>
  27 #include <linux/bitops.h>
  28
  29 #include <asm/byteorder.h>
  30 #include <asm/io.h>
  31
  32 #include "8250.h"
  33
  34 /*
  35  * Definitions for PCI support.
  36  */
  37 #define FL_BASE_MASK            0x0007
  38 #define FL_BASE0                0x0000
  39 #define FL_BASE1                0x0001
  40 #define FL_BASE2                0x0002
  41 #define FL_BASE3                0x0003
  42 #define FL_BASE4                0x0004
  43 #define FL_GET_BASE(x)          (x & FL_BASE_MASK)
  44
  45 /* Use successive BARs (PCI base address registers),
  46    else use offset into some specified BAR */
  47 #define FL_BASE_BARS            0x0008
  48
  49 /* do not assign an irq */
  50 #define FL_NOIRQ                0x0080
  51
  52 /* Use the Base address register size to cap number of ports */
  53 #define FL_REGION_SZ_CAP        0x0100
  54
  55 struct pci_board {
  56         unsigned int flags;
  57         unsigned int num_ports;
  58         unsigned int base_baud;
  59         unsigned int uart_offset;
  60         unsigned int reg_shift;
  61         unsigned int first_offset;
  62 };
  63
  64 /*
  65  * init function returns:
  66  *  > 0 - number of ports
  67  *  = 0 - use board->num_ports
  68  *  < 0 - error
  69  */
  70 struct pci_serial_quirk {
  71         u32     vendor;
  72         u32     device;
  73         u32     subvendor;
  74         u32     subdevice;
  75         int     (*init)(struct pci_dev *dev);
  76         int     (*setup)(struct pci_dev *dev, struct pci_board *board,
  77                          struct uart_port *port, int idx);
  78         void    (*exit)(struct pci_dev *dev);
  79 };
  80
  81 #define PCI_NUM_BAR_RESOURCES   6
  82
  83 struct serial_private {
  84         unsigned int            nr;
  85         void __iomem            *remapped_bar[PCI_NUM_BAR_RESOURCES];
  86         struct pci_serial_quirk *quirk;
  87         int                     line[0];
  88 };
  89
  90 static void moan_device(const char *str, struct pci_dev *dev)
  91 {
  92         printk(KERN_WARNING "%s: %s\n"
  93                KERN_WARNING "Please send the output of lspci -vv, this\n"
  94                KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
  95                KERN_WARNING "manufacturer and name of serial board or\n"
  96                KERN_WARNING "modem board to rmk+serial@arm.linux.org.uk.\n",
  97                pci_name(dev), str, dev->vendor, dev->device,
  98                dev->subsystem_vendor, dev->subsystem_device);
  99 }
 100
 101 static int
 102 setup_port(struct pci_dev *dev, struct uart_port *port,
 103            int bar, int offset, int regshift)
 104 {
 105         struct serial_private *priv = pci_get_drvdata(dev);
 106         unsigned long base, len;
 107
 108         if (bar >= PCI_NUM_BAR_RESOURCES)
 109                 return -EINVAL;
 110
 111         if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
 112                 base = pci_resource_start(dev, bar);
 113                 len =  pci_resource_len(dev, bar);
 114
 115                 if (!priv->remapped_bar[bar])
 116                         priv->remapped_bar[bar] = ioremap(base, len);
 117                 if (!priv->remapped_bar[bar])
 118                         return -ENOMEM;
 119
 120                 port->iotype = UPIO_MEM;
 121                 port->mapbase = base + offset;
 122                 port->membase = priv->remapped_bar[bar] + offset;
 123                 port->regshift = regshift;
 124         } else {
 125                 base = pci_resource_start(dev, bar) + offset;
 126                 port->iotype = UPIO_PORT;
 127                 port->iobase = base;
 128         }
 129         return 0;
 130 }
 131
 132 /*
 133  * AFAVLAB uses a different mixture of BARs and offsets
 134  * Not that ugly ;) -- HW
 135  */
 136 static int
 137 afavlab_setup(struct pci_dev *dev, struct pci_board *board,
 138               struct uart_port *port, int idx)
 139 {
 140         unsigned int bar, offset = board->first_offset;
 141
 142         bar = FL_GET_BASE(board->flags);
 143         if (idx < 4)
 144                 bar += idx;
 145         else {
 146                 bar = 4;
 147                 offset += (idx - 4) * board->uart_offset;
 148         }
 149
 150         return setup_port(dev, port, bar, offset, board->reg_shift);
 151 }
 152
 153 /*
 154  * HP's Remote Management Console.  The Diva chip came in several
 155  * different versions.  N-class, L2000 and A500 have two Diva chips, each
 156  * with 3 UARTs (the third UART on the second chip is unused).  Superdome
 157  * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
 158  * one Diva chip, but it has been expanded to 5 UARTs.
 159  */
 160 static int __devinit pci_hp_diva_init(struct pci_dev *dev)
 161 {
 162         int rc = 0;
 163
 164         switch (dev->subsystem_device) {
 165         case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
 166         case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
 167         case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
 168         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 169                 rc = 3;
 170                 break;
 171         case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
 172                 rc = 2;
 173                 break;
 174         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 175                 rc = 4;
 176                 break;
 177         case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
 178                 rc = 1;
 179                 break;
 180         }
 181
 182         return rc;
 183 }
 184
 185 /*
 186  * HP's Diva chip puts the 4th/5th serial port further out, and
 187  * some serial ports are supposed to be hidden on certain models.
 188  */
 189 static int
 190 pci_hp_diva_setup(struct pci_dev *dev, struct pci_board *board,
 191               struct uart_port *port, int idx)
 192 {
 193         unsigned int offset = board->first_offset;
 194         unsigned int bar = FL_GET_BASE(board->flags);
 195
 196         switch (dev->subsystem_device) {
 197         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 198                 if (idx == 3)
 199                         idx++;
 200                 break;
 201         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 202                 if (idx > 0)
 203                         idx++;
 204                 if (idx > 2)
 205                         idx++;
 206                 break;
 207         }
 208         if (idx > 2)
 209                 offset = 0x18;
 210
 211         offset += idx * board->uart_offset;
 212
 213         return setup_port(dev, port, bar, offset, board->reg_shift);
 214 }
 215
 216 /*
 217  * Added for EKF Intel i960 serial boards
 218  */
 219 static int __devinit pci_inteli960ni_init(struct pci_dev *dev)
 220 {
 221         unsigned long oldval;
 222
 223         if (!(dev->subsystem_device & 0x1000))
 224                 return -ENODEV;
 225
 226         /* is firmware started? */
 227         pci_read_config_dword(dev, 0x44, (void*) &oldval);
 228         if (oldval == 0x00001000L) { /* RESET value */
 229                 printk(KERN_DEBUG "Local i960 firmware missing");
 230                 return -ENODEV;
 231         }
 232         return 0;
 233 }
 234
 235 /*
 236  * Some PCI serial cards using the PLX 9050 PCI interface chip require
 237  * that the card interrupt be explicitly enabled or disabled.  This
 238  * seems to be mainly needed on card using the PLX which also use I/O
 239  * mapped memory.
 240  */
 241 static int __devinit pci_plx9050_init(struct pci_dev *dev)
 242 {
 243         u8 irq_config;
 244         void __iomem *p;
 245
 246         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
 247                 moan_device("no memory in bar 0", dev);
 248                 return 0;
 249         }
 250
 251         irq_config = 0x41;
 252         if (dev->vendor == PCI_VENDOR_ID_PANACOM)
 253                 irq_config = 0x43;
 254         if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
 255             (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) {
 256                 /*
 257                  * As the megawolf cards have the int pins active
 258                  * high, and have 2 UART chips, both ints must be
 259                  * enabled on the 9050. Also, the UARTS are set in
 260                  * 16450 mode by default, so we have to enable the
 261                  * 16C950 'enhanced' mode so that we can use the
 262                  * deep FIFOs
 263                  */
 264                 irq_config = 0x5b;
 265         }
 266
 267         /*
 268          * enable/disable interrupts
 269          */
 270         p = ioremap(pci_resource_start(dev, 0), 0x80);
 271         if (p == NULL)
 272                 return -ENOMEM;
 273         writel(irq_config, p + 0x4c);
 274
 275         /*
 276          * Read the register back to ensure that it took effect.
 277          */
 278         readl(p + 0x4c);
 279         iounmap(p);
 280
 281         return 0;
 282 }
 283
 284 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
 285 {
 286         u8 __iomem *p;
 287
 288         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
 289                 return;
 290
 291         /*
 292          * disable interrupts
 293          */
 294         p = ioremap(pci_resource_start(dev, 0), 0x80);
 295         if (p != NULL) {
 296                 writel(0, p + 0x4c);
 297
 298                 /*
 299                  * Read the register back to ensure that it took effect.
 300                  */
 301                 readl(p + 0x4c);
 302                 iounmap(p);
 303         }
 304 }
 305
 306 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
 307 static int
 308 sbs_setup(struct pci_dev *dev, struct pci_board *board,
 309                 struct uart_port *port, int idx)
 310 {
 311         unsigned int bar, offset = board->first_offset;
 312
 313         bar = 0;
 314
 315         if (idx < 4) {
 316                 /* first four channels map to 0, 0x100, 0x200, 0x300 */
 317                 offset += idx * board->uart_offset;
 318         } else if (idx < 8) {
 319                 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
 320                 offset += idx * board->uart_offset + 0xC00;
 321         } else /* we have only 8 ports on PMC-OCTALPRO */
 322                 return 1;
 323
 324         return setup_port(dev, port, bar, offset, board->reg_shift);
 325 }
 326
 327 /*
 328 * This does initialization for PMC OCTALPRO cards:
 329 * maps the device memory, resets the UARTs (needed, bc
 330 * if the module is removed and inserted again, the card
 331 * is in the sleep mode) and enables global interrupt.
 332 */
 333
 334 /* global control register offset for SBS PMC-OctalPro */
 335 #define OCT_REG_CR_OFF          0x500
 336
 337 static int __devinit sbs_init(struct pci_dev *dev)
 338 {
 339         u8 __iomem *p;
 340
 341         p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
 342
 343         if (p == NULL)
 344                 return -ENOMEM;
 345         /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
 346         writeb(0x10,p + OCT_REG_CR_OFF);
 347         udelay(50);
 348         writeb(0x0,p + OCT_REG_CR_OFF);
 349
 350         /* Set bit-2 (INTENABLE) of Control Register */
 351         writeb(0x4, p + OCT_REG_CR_OFF);
 352         iounmap(p);
 353
 354         return 0;
 355 }
 356
 357 /*
 358  * Disables the global interrupt of PMC-OctalPro
 359  */
 360
 361 static void __devexit sbs_exit(struct pci_dev *dev)
 362 {
 363         u8 __iomem *p;
 364
 365         p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
 366         if (p != NULL) {
 367                 writeb(0, p + OCT_REG_CR_OFF);
 368         }
 369         iounmap(p);
 370 }
 371
 372 /*
 373  * SIIG serial cards have an PCI interface chip which also controls
 374  * the UART clocking frequency. Each UART can be clocked independently
 375  * (except cards equiped with 4 UARTs) and initial clocking settings
 376  * are stored in the EEPROM chip. It can cause problems because this
 377  * version of serial driver doesn't support differently clocked UART's
 378  * on single PCI card. To prevent this, initialization functions set
 379  * high frequency clocking for all UART's on given card. It is safe (I
 380  * hope) because it doesn't touch EEPROM settings to prevent conflicts
 381  * with other OSes (like M$ DOS).
 382  *
 383  *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
 384  *
 385  * There is two family of SIIG serial cards with different PCI
 386  * interface chip and different configuration methods:
 387  *     - 10x cards have control registers in IO and/or memory space;
 388  *     - 20x cards have control registers in standard PCI configuration space.
 389  *
 390  * Note: some SIIG cards are probed by the parport_serial object.
 391  */
 392
 393 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
 394 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
 395
 396 static int pci_siig10x_init(struct pci_dev *dev)
 397 {
 398         u16 data;
 399         void __iomem *p;
 400
 401         switch (dev->device & 0xfff8) {
 402         case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
 403                 data = 0xffdf;
 404                 break;
 405         case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
 406                 data = 0xf7ff;
 407                 break;
 408         default:                        /* 1S1P, 4S */
 409                 data = 0xfffb;
 410                 break;
 411         }
 412
 413         p = ioremap(pci_resource_start(dev, 0), 0x80);
 414         if (p == NULL)
 415                 return -ENOMEM;
 416
 417         writew(readw(p + 0x28) & data, p + 0x28);
 418         readw(p + 0x28);
 419         iounmap(p);
 420         return 0;
 421 }
 422
 423 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
 424 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
 425
 426 static int pci_siig20x_init(struct pci_dev *dev)
 427 {
 428         u8 data;
 429
 430         /* Change clock frequency for the first UART. */
 431         pci_read_config_byte(dev, 0x6f, &data);
 432         pci_write_config_byte(dev, 0x6f, data & 0xef);
 433
 434         /* If this card has 2 UART, we have to do the same with second UART. */
 435         if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
 436             ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
 437                 pci_read_config_byte(dev, 0x73, &data);
 438                 pci_write_config_byte(dev, 0x73, data & 0xef);
 439         }
 440         return 0;
 441 }
 442
 443 int pci_siig10x_fn(struct pci_dev *dev, int enable)
 444 {
 445         int ret = 0;
 446         if (enable)
 447                 ret = pci_siig10x_init(dev);
 448         return ret;
 449 }
 450
 451 int pci_siig20x_fn(struct pci_dev *dev, int enable)
 452 {
 453         int ret = 0;
 454         if (enable)
 455                 ret = pci_siig20x_init(dev);
 456         return ret;
 457 }
 458
 459 EXPORT_SYMBOL(pci_siig10x_fn);
 460 EXPORT_SYMBOL(pci_siig20x_fn);
 461
 462 /*
 463  * Timedia has an explosion of boards, and to avoid the PCI table from
 464  * growing *huge*, we use this function to collapse some 70 entries
 465  * in the PCI table into one, for sanity's and compactness's sake.
 466  */
 467 static unsigned short timedia_single_port[] = {
 468         0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
 469 };
 470
 471 static unsigned short timedia_dual_port[] = {
 472         0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
 473         0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
 474         0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
 475         0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
 476         0xD079, 0
 477 };
 478
 479 static unsigned short timedia_quad_port[] = {
 480         0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
 481         0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
 482         0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
 483         0xB157, 0
 484 };
 485
 486 static unsigned short timedia_eight_port[] = {
 487         0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
 488         0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
 489 };
 490
 491 static struct timedia_struct {
 492         int num;
 493         unsigned short *ids;
 494 } timedia_data[] = {
 495         { 1, timedia_single_port },
 496         { 2, timedia_dual_port },
 497         { 4, timedia_quad_port },
 498         { 8, timedia_eight_port },
 499         { 0, NULL }
 500 };
 501
 502 static int __devinit pci_timedia_init(struct pci_dev *dev)
 503 {
 504         unsigned short *ids;
 505         int i, j;
 506
 507         for (i = 0; timedia_data[i].num; i++) {
 508                 ids = timedia_data[i].ids;
 509                 for (j = 0; ids[j]; j++)
 510                         if (dev->subsystem_device == ids[j])
 511                                 return timedia_data[i].num;
 512         }
 513         return 0;
 514 }
 515
 516 /*
 517  * Timedia/SUNIX uses a mixture of BARs and offsets
 518  * Ugh, this is ugly as all hell --- TYT
 519  */
 520 static int
 521 pci_timedia_setup(struct pci_dev *dev, struct pci_board *board,
 522                   struct uart_port *port, int idx)
 523 {
 524         unsigned int bar = 0, offset = board->first_offset;
 525
 526         switch (idx) {
 527         case 0:
 528                 bar = 0;
 529                 break;
 530         case 1:
 531                 offset = board->uart_offset;
 532                 bar = 0;
 533                 break;
 534         case 2:
 535                 bar = 1;
 536                 break;
 537         case 3:
 538                 offset = board->uart_offset;
 539                 bar = 1;
 540         case 4: /* BAR 2 */
 541         case 5: /* BAR 3 */
 542         case 6: /* BAR 4 */
 543         case 7: /* BAR 5 */
 544                 bar = idx - 2;
 545         }
 546
 547         return setup_port(dev, port, bar, offset, board->reg_shift);
 548 }
 549
 550 /*
 551  * Some Titan cards are also a little weird
 552  */
 553 static int
 554 titan_400l_800l_setup(struct pci_dev *dev, struct pci_board *board,
 555                       struct uart_port *port, int idx)
 556 {
 557         unsigned int bar, offset = board->first_offset;
 558
 559         switch (idx) {
 560         case 0:
 561                 bar = 1;
 562                 break;
 563         case 1:
 564                 bar = 2;
 565                 break;
 566         default:
 567                 bar = 4;
 568                 offset = (idx - 2) * board->uart_offset;
 569         }
 570
 571         return setup_port(dev, port, bar, offset, board->reg_shift);
 572 }
 573
 574 static int __devinit pci_xircom_init(struct pci_dev *dev)
 575 {
 576         msleep(100);
 577         return 0;
 578 }
 579
 580 static int
 581 pci_default_setup(struct pci_dev *dev, struct pci_board *board,
 582                   struct uart_port *port, int idx)
 583 {
 584         unsigned int bar, offset = board->first_offset, maxnr;
 585
 586         bar = FL_GET_BASE(board->flags);
 587         if (board->flags & FL_BASE_BARS)
 588                 bar += idx;
 589         else
 590                 offset += idx * board->uart_offset;
 591
 592         maxnr = (pci_resource_len(dev, bar) - board->first_offset) /
 593                 (8 << board->reg_shift);
 594
 595         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
 596                 return 1;
 597
 598         return setup_port(dev, port, bar, offset, board->reg_shift);
 599 }
 600
 601 /* This should be in linux/pci_ids.h */
 602 #define PCI_VENDOR_ID_SBSMODULARIO      0x124B
 603 #define PCI_SUBVENDOR_ID_SBSMODULARIO   0x124B
 604 #define PCI_DEVICE_ID_OCTPRO            0x0001
 605 #define PCI_SUBDEVICE_ID_OCTPRO232      0x0108
 606 #define PCI_SUBDEVICE_ID_OCTPRO422      0x0208
 607 #define PCI_SUBDEVICE_ID_POCTAL232      0x0308
 608 #define PCI_SUBDEVICE_ID_POCTAL422      0x0408
 609
 610 /*
 611  * Master list of serial port init/setup/exit quirks.
 612  * This does not describe the general nature of the port.
 613  * (ie, baud base, number and location of ports, etc)
 614  *
 615  * This list is ordered alphabetically by vendor then device.
 616  * Specific entries must come before more generic entries.
 617  */
 618 static struct pci_serial_quirk pci_serial_quirks[] = {
 619         /*
 620          * AFAVLAB cards.
 621          *  It is not clear whether this applies to all products.
 622          */
 623         {
 624                 .vendor         = PCI_VENDOR_ID_AFAVLAB,
 625                 .device         = PCI_ANY_ID,
 626                 .subvendor      = PCI_ANY_ID,
 627                 .subdevice      = PCI_ANY_ID,
 628                 .setup          = afavlab_setup,
 629         },
 630         /*
 631          * HP Diva
 632          */
 633         {
 634                 .vendor         = PCI_VENDOR_ID_HP,
 635                 .device         = PCI_DEVICE_ID_HP_DIVA,
 636                 .subvendor      = PCI_ANY_ID,
 637                 .subdevice      = PCI_ANY_ID,
 638                 .init           = pci_hp_diva_init,
 639                 .setup          = pci_hp_diva_setup,
 640         },
 641         /*
 642          * Intel
 643          */
 644         {
 645                 .vendor         = PCI_VENDOR_ID_INTEL,
 646                 .device         = PCI_DEVICE_ID_INTEL_80960_RP,
 647                 .subvendor      = 0xe4bf,
 648                 .subdevice      = PCI_ANY_ID,
 649                 .init           = pci_inteli960ni_init,
 650                 .setup          = pci_default_setup,
 651         },
 652         /*
 653          * Panacom
 654          */
 655         {
 656                 .vendor         = PCI_VENDOR_ID_PANACOM,
 657                 .device         = PCI_DEVICE_ID_PANACOM_QUADMODEM,
 658                 .subvendor      = PCI_ANY_ID,
 659                 .subdevice      = PCI_ANY_ID,
 660                 .init           = pci_plx9050_init,
 661                 .setup          = pci_default_setup,
 662                 .exit           = __devexit_p(pci_plx9050_exit),
 663         },
 664         {
 665                 .vendor         = PCI_VENDOR_ID_PANACOM,
 666                 .device         = PCI_DEVICE_ID_PANACOM_DUALMODEM,
 667                 .subvendor      = PCI_ANY_ID,
 668                 .subdevice      = PCI_ANY_ID,
 669                 .init           = pci_plx9050_init,
 670                 .setup          = pci_default_setup,
 671                 .exit           = __devexit_p(pci_plx9050_exit),
 672         },
 673         /*
 674          * PLX
 675          */
 676         {
 677                 .vendor         = PCI_VENDOR_ID_PLX,
 678                 .device         = PCI_DEVICE_ID_PLX_9050,
 679                 .subvendor      = PCI_SUBVENDOR_ID_KEYSPAN,
 680                 .subdevice      = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
 681                 .init           = pci_plx9050_init,
 682                 .setup          = pci_default_setup,
 683                 .exit           = __devexit_p(pci_plx9050_exit),
 684         },
 685         {
 686                 .vendor         = PCI_VENDOR_ID_PLX,
 687                 .device         = PCI_DEVICE_ID_PLX_ROMULUS,
 688                 .subvendor      = PCI_VENDOR_ID_PLX,
 689                 .subdevice      = PCI_DEVICE_ID_PLX_ROMULUS,
 690                 .init           = pci_plx9050_init,
 691                 .setup          = pci_default_setup,
 692                 .exit           = __devexit_p(pci_plx9050_exit),
 693         },
 694         /*
 695          * SBS Technologies, Inc., PMC-OCTALPRO 232
 696          */
 697         {
 698                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 699                 .device         = PCI_DEVICE_ID_OCTPRO,
 700                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 701                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO232,
 702                 .init           = sbs_init,
 703                 .setup          = sbs_setup,
 704                 .exit           = __devexit_p(sbs_exit),
 705         },
 706         /*
 707          * SBS Technologies, Inc., PMC-OCTALPRO 422
 708          */
 709         {
 710                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 711                 .device         = PCI_DEVICE_ID_OCTPRO,
 712                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 713                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO422,
 714                 .init           = sbs_init,
 715                 .setup          = sbs_setup,
 716                 .exit           = __devexit_p(sbs_exit),
 717         },
 718         /*
 719          * SBS Technologies, Inc., P-Octal 232
 720          */
 721         {
 722                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 723                 .device         = PCI_DEVICE_ID_OCTPRO,
 724                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 725                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL232,
 726                 .init           = sbs_init,
 727                 .setup          = sbs_setup,
 728                 .exit           = __devexit_p(sbs_exit),
 729         },
 730         /*
 731          * SBS Technologies, Inc., P-Octal 422
 732          */
 733         {
 734                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 735                 .device         = PCI_DEVICE_ID_OCTPRO,
 736                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 737                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL422,
 738                 .init           = sbs_init,
 739                 .setup          = sbs_setup,
 740                 .exit           = __devexit_p(sbs_exit),
 741         },
 742
 743         /*
 744          * SIIG cards.
 745          *  It is not clear whether these could be collapsed.
 746          */
 747         {
 748                 .vendor         = PCI_VENDOR_ID_SIIG,
 749                 .device         = PCI_DEVICE_ID_SIIG_1S_10x_550,
 750                 .subvendor      = PCI_ANY_ID,
 751                 .subdevice      = PCI_ANY_ID,
 752                 .init           = pci_siig10x_init,
 753                 .setup          = pci_default_setup,
 754         },
 755         {
 756                 .vendor         = PCI_VENDOR_ID_SIIG,
 757                 .device         = PCI_DEVICE_ID_SIIG_1S_10x_650,
 758                 .subvendor      = PCI_ANY_ID,
 759                 .subdevice      = PCI_ANY_ID,
 760                 .init           = pci_siig10x_init,
 761                 .setup          = pci_default_setup,
 762         },
 763         {
 764                 .vendor         = PCI_VENDOR_ID_SIIG,
 765                 .device         = PCI_DEVICE_ID_SIIG_1S_10x_850,
 766                 .subvendor      = PCI_ANY_ID,
 767                 .subdevice      = PCI_ANY_ID,
 768                 .init           = pci_siig10x_init,
 769                 .setup          = pci_default_setup,
 770         },
 771         {
 772                 .vendor         = PCI_VENDOR_ID_SIIG,
 773                 .device         = PCI_DEVICE_ID_SIIG_2S_10x_550,
 774                 .subvendor      = PCI_ANY_ID,
 775                 .subdevice      = PCI_ANY_ID,
 776                 .init           = pci_siig10x_init,
 777                 .setup          = pci_default_setup,
 778         },
 779         {
 780                 .vendor         = PCI_VENDOR_ID_SIIG,
 781                 .device         = PCI_DEVICE_ID_SIIG_2S_10x_650,
 782                 .subvendor      = PCI_ANY_ID,
 783                 .subdevice      = PCI_ANY_ID,
 784                 .init           = pci_siig10x_init,
 785                 .setup          = pci_default_setup,
 786         },
 787         {
 788                 .vendor         = PCI_VENDOR_ID_SIIG,
 789                 .device         = PCI_DEVICE_ID_SIIG_2S_10x_850,
 790                 .subvendor      = PCI_ANY_ID,
 791                 .subdevice      = PCI_ANY_ID,
 792                 .init           = pci_siig10x_init,
 793                 .setup          = pci_default_setup,
 794         },
 795         {
 796                 .vendor         = PCI_VENDOR_ID_SIIG,
 797                 .device         = PCI_DEVICE_ID_SIIG_4S_10x_550,
 798                 .subvendor      = PCI_ANY_ID,
 799                 .subdevice      = PCI_ANY_ID,
 800                 .init           = pci_siig10x_init,
 801                 .setup          = pci_default_setup,
 802         },
 803         {
 804                 .vendor         = PCI_VENDOR_ID_SIIG,
 805                 .device         = PCI_DEVICE_ID_SIIG_4S_10x_650,
 806                 .subvendor      = PCI_ANY_ID,
 807                 .subdevice      = PCI_ANY_ID,
 808                 .init           = pci_siig10x_init,
 809                 .setup          = pci_default_setup,
 810         },
 811         {
 812                 .vendor         = PCI_VENDOR_ID_SIIG,
 813                 .device         = PCI_DEVICE_ID_SIIG_4S_10x_850,
 814                 .subvendor      = PCI_ANY_ID,
 815                 .subdevice      = PCI_ANY_ID,
 816                 .init           = pci_siig10x_init,
 817                 .setup          = pci_default_setup,
 818         },
 819         {
 820                 .vendor         = PCI_VENDOR_ID_SIIG,
 821                 .device         = PCI_DEVICE_ID_SIIG_1S_20x_550,
 822                 .subvendor      = PCI_ANY_ID,
 823                 .subdevice      = PCI_ANY_ID,
 824                 .init           = pci_siig20x_init,
 825                 .setup          = pci_default_setup,
 826         },
 827         {
 828                 .vendor         = PCI_VENDOR_ID_SIIG,
 829                 .device         = PCI_DEVICE_ID_SIIG_1S_20x_650,
 830                 .subvendor      = PCI_ANY_ID,
 831                 .subdevice      = PCI_ANY_ID,
 832                 .init           = pci_siig20x_init,
 833                 .setup          = pci_default_setup,
 834         },
 835         {
 836                 .vendor         = PCI_VENDOR_ID_SIIG,
 837                 .device         = PCI_DEVICE_ID_SIIG_1S_20x_850,
 838                 .subvendor      = PCI_ANY_ID,
 839                 .subdevice      = PCI_ANY_ID,
 840                 .init           = pci_siig20x_init,
 841                 .setup          = pci_default_setup,
 842         },
 843         {
 844                 .vendor         = PCI_VENDOR_ID_SIIG,
 845                 .device         = PCI_DEVICE_ID_SIIG_2S_20x_550,
 846                 .subvendor      = PCI_ANY_ID,
 847                 .subdevice      = PCI_ANY_ID,
 848                 .init           = pci_siig20x_init,
 849                 .setup          = pci_default_setup,
 850         },
 851         {       .vendor         = PCI_VENDOR_ID_SIIG,
 852                 .device         = PCI_DEVICE_ID_SIIG_2S_20x_650,
 853                 .subvendor      = PCI_ANY_ID,
 854                 .subdevice      = PCI_ANY_ID,
 855                 .init           = pci_siig20x_init,
 856                 .setup          = pci_default_setup,
 857         },
 858         {
 859                 .vendor         = PCI_VENDOR_ID_SIIG,
 860                 .device         = PCI_DEVICE_ID_SIIG_2S_20x_850,
 861                 .subvendor      = PCI_ANY_ID,
 862                 .subdevice      = PCI_ANY_ID,
 863                 .init           = pci_siig20x_init,
 864                 .setup          = pci_default_setup,
 865         },
 866         {
 867                 .vendor         = PCI_VENDOR_ID_SIIG,
 868                 .device         = PCI_DEVICE_ID_SIIG_4S_20x_550,
 869                 .subvendor      = PCI_ANY_ID,
 870                 .subdevice      = PCI_ANY_ID,
 871                 .init           = pci_siig20x_init,
 872                 .setup          = pci_default_setup,
 873         },
 874         {
 875                 .vendor         = PCI_VENDOR_ID_SIIG,
 876                 .device         = PCI_DEVICE_ID_SIIG_4S_20x_650,
 877                 .subvendor      = PCI_ANY_ID,
 878                 .subdevice      = PCI_ANY_ID,
 879                 .init           = pci_siig20x_init,
 880                 .setup          = pci_default_setup,
 881         },
 882         {
 883                 .vendor         = PCI_VENDOR_ID_SIIG,
 884                 .device         = PCI_DEVICE_ID_SIIG_4S_20x_850,
 885                 .subvendor      = PCI_ANY_ID,
 886                 .subdevice      = PCI_ANY_ID,
 887                 .init           = pci_siig20x_init,
 888                 .setup          = pci_default_setup,
 889         },
 890         /*
 891          * Titan cards
 892          */
 893         {
 894                 .vendor         = PCI_VENDOR_ID_TITAN,
 895                 .device         = PCI_DEVICE_ID_TITAN_400L,
 896                 .subvendor      = PCI_ANY_ID,
 897                 .subdevice      = PCI_ANY_ID,
 898                 .setup          = titan_400l_800l_setup,
 899         },
 900         {
 901                 .vendor         = PCI_VENDOR_ID_TITAN,
 902                 .device         = PCI_DEVICE_ID_TITAN_800L,
 903                 .subvendor      = PCI_ANY_ID,
 904                 .subdevice      = PCI_ANY_ID,
 905                 .setup          = titan_400l_800l_setup,
 906         },
 907         /*
 908          * Timedia cards
 909          */
 910         {
 911                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
 912                 .device         = PCI_DEVICE_ID_TIMEDIA_1889,
 913                 .subvendor      = PCI_VENDOR_ID_TIMEDIA,
 914                 .subdevice      = PCI_ANY_ID,
 915                 .init           = pci_timedia_init,
 916                 .setup          = pci_timedia_setup,
 917         },
 918         {
 919                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
 920                 .device         = PCI_ANY_ID,
 921                 .subvendor      = PCI_ANY_ID,
 922                 .subdevice      = PCI_ANY_ID,
 923                 .setup          = pci_timedia_setup,
 924         },
 925         /*
 926          * Xircom cards
 927          */
 928         {
 929                 .vendor         = PCI_VENDOR_ID_XIRCOM,
 930                 .device         = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
 931                 .subvendor      = PCI_ANY_ID,
 932                 .subdevice      = PCI_ANY_ID,
 933                 .init           = pci_xircom_init,
 934                 .setup          = pci_default_setup,
 935         },
 936         /*
 937          * Default "match everything" terminator entry
 938          */
 939         {
 940                 .vendor         = PCI_ANY_ID,
 941                 .device         = PCI_ANY_ID,
 942                 .subvendor      = PCI_ANY_ID,
 943                 .subdevice      = PCI_ANY_ID,
 944                 .setup          = pci_default_setup,
 945         }
 946 };
 947
 948 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
 949 {
 950         return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
 951 }
 952
 953 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
 954 {
 955         struct pci_serial_quirk *quirk;
 956
 957         for (quirk = pci_serial_quirks; ; quirk++)
 958                 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
 959                     quirk_id_matches(quirk->device, dev->device) &&
 960                     quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
 961                     quirk_id_matches(quirk->subdevice, dev->subsystem_device))
 962                         break;
 963         return quirk;
 964 }
 965
 966 static _INLINE_ int
 967 get_pci_irq(struct pci_dev *dev, struct pci_board *board, int idx)
 968 {
 969         if (board->flags & FL_NOIRQ)
 970                 return 0;
 971         else
 972                 return dev->irq;
 973 }
 974
 975 /*
 976  * This is the configuration table for all of the PCI serial boards
 977  * which we support.  It is directly indexed by the pci_board_num_t enum
 978  * value, which is encoded in the pci_device_id PCI probe table's
 979  * driver_data member.
 980  *
 981  * The makeup of these names are:
 982  *  pbn_bn{_bt}_n_baud
 983  *
 984  *  bn   = PCI BAR number
 985  *  bt   = Index using PCI BARs
 986  *  n    = number of serial ports
 987  *  baud = baud rate
 988  *
 989  * Please note: in theory if n = 1, _bt infix should make no difference.
 990  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
 991  */
 992 enum pci_board_num_t {
 993         pbn_default = 0,
 994
 995         pbn_b0_1_115200,
 996         pbn_b0_2_115200,
 997         pbn_b0_4_115200,
 998         pbn_b0_5_115200,
 999
1000         pbn_b0_1_921600,
1001         pbn_b0_2_921600,
1002         pbn_b0_4_921600,
1003
1004         pbn_b0_bt_1_115200,
1005         pbn_b0_bt_2_115200,
1006         pbn_b0_bt_8_115200,
1007
1008         pbn_b0_bt_1_460800,
1009         pbn_b0_bt_2_460800,
1010         pbn_b0_bt_4_460800,
1011
1012         pbn_b0_bt_1_921600,
1013         pbn_b0_bt_2_921600,
1014         pbn_b0_bt_4_921600,
1015         pbn_b0_bt_8_921600,
1016
1017         pbn_b1_1_115200,
1018         pbn_b1_2_115200,
1019         pbn_b1_4_115200,
1020         pbn_b1_8_115200,
1021
1022         pbn_b1_1_921600,
1023         pbn_b1_2_921600,
1024         pbn_b1_4_921600,
1025         pbn_b1_8_921600,
1026
1027         pbn_b1_bt_2_921600,
1028
1029         pbn_b1_1_1382400,
1030         pbn_b1_2_1382400,
1031         pbn_b1_4_1382400,
1032         pbn_b1_8_1382400,
1033
1034         pbn_b2_1_115200,
1035         pbn_b2_8_115200,
1036
1037         pbn_b2_1_460800,
1038         pbn_b2_4_460800,
1039         pbn_b2_8_460800,
1040         pbn_b2_16_460800,
1041
1042         pbn_b2_1_921600,
1043         pbn_b2_4_921600,
1044         pbn_b2_8_921600,
1045
1046         pbn_b2_bt_1_115200,
1047         pbn_b2_bt_2_115200,
1048         pbn_b2_bt_4_115200,
1049
1050         pbn_b2_bt_2_921600,
1051         pbn_b2_bt_4_921600,
1052
1053         pbn_b3_4_115200,
1054         pbn_b3_8_115200,
1055
1056         /*
1057          * Board-specific versions.
1058          */
1059         pbn_panacom,
1060         pbn_panacom2,
1061         pbn_panacom4,
1062         pbn_plx_romulus,
1063         pbn_oxsemi,
1064         pbn_intel_i960,
1065         pbn_sgi_ioc3,
1066         pbn_nec_nile4,
1067         pbn_computone_4,
1068         pbn_computone_6,
1069         pbn_computone_8,
1070         pbn_sbsxrsio,
1071         pbn_exar_XR17C152,
1072         pbn_exar_XR17C154,
1073         pbn_exar_XR17C158,
1074 };
1075
1076 /*
1077  * uart_offset - the space between channels
1078  * reg_shift   - describes how the UART registers are mapped
1079  *               to PCI memory by the card.
1080  * For example IER register on SBS, Inc. PMC-OctPro is located at
1081  * offset 0x10 from the UART base, while UART_IER is defined as 1
1082  * in include/linux/serial_reg.h,
1083  * see first lines of serial_in() and serial_out() in 8250.c
1084 */
1085
1086 static struct pci_board pci_boards[] __devinitdata = {
1087         [pbn_default] = {
1088                 .flags          = FL_BASE0,
1089                 .num_ports      = 1,
1090                 .base_baud      = 115200,
1091                 .uart_offset    = 8,
1092         },
1093         [pbn_b0_1_115200] = {
1094                 .flags          = FL_BASE0,
1095                 .num_ports      = 1,
1096                 .base_baud      = 115200,
1097                 .uart_offset    = 8,
1098         },
1099         [pbn_b0_2_115200] = {
1100                 .flags          = FL_BASE0,
1101                 .num_ports      = 2,
1102                 .base_baud      = 115200,
1103                 .uart_offset    = 8,
1104         },
1105         [pbn_b0_4_115200] = {
1106                 .flags          = FL_BASE0,
1107                 .num_ports      = 4,
1108                 .base_baud      = 115200,
1109                 .uart_offset    = 8,
1110         },
1111         [pbn_b0_5_115200] = {
1112                 .flags          = FL_BASE0,
1113                 .num_ports      = 5,
1114                 .base_baud      = 115200,
1115                 .uart_offset    = 8,
1116         },
1117
1118         [pbn_b0_1_921600] = {
1119                 .flags          = FL_BASE0,
1120                 .num_ports      = 1,
1121                 .base_baud      = 921600,
1122                 .uart_offset    = 8,
1123         },
1124         [pbn_b0_2_921600] = {
1125                 .flags          = FL_BASE0,
1126                 .num_ports      = 2,
1127                 .base_baud      = 921600,
1128                 .uart_offset    = 8,
1129         },
1130         [pbn_b0_4_921600] = {
1131                 .flags          = FL_BASE0,
1132                 .num_ports      = 4,
1133                 .base_baud      = 921600,
1134                 .uart_offset    = 8,
1135         },
1136
1137         [pbn_b0_bt_1_115200] = {
1138                 .flags          = FL_BASE0|FL_BASE_BARS,
1139                 .num_ports      = 1,
1140                 .base_baud      = 115200,
1141                 .uart_offset    = 8,
1142         },
1143         [pbn_b0_bt_2_115200] = {
1144                 .flags          = FL_BASE0|FL_BASE_BARS,
1145                 .num_ports      = 2,
1146                 .base_baud      = 115200,
1147                 .uart_offset    = 8,
1148         },
1149         [pbn_b0_bt_8_115200] = {
1150                 .flags          = FL_BASE0|FL_BASE_BARS,
1151                 .num_ports      = 8,
1152                 .base_baud      = 115200,
1153                 .uart_offset    = 8,
1154         },
1155
1156         [pbn_b0_bt_1_460800] = {
1157                 .flags          = FL_BASE0|FL_BASE_BARS,
1158                 .num_ports      = 1,
1159                 .base_baud      = 460800,
1160                 .uart_offset    = 8,
1161         },
1162         [pbn_b0_bt_2_460800] = {
1163                 .flags          = FL_BASE0|FL_BASE_BARS,
1164                 .num_ports      = 2,
1165                 .base_baud      = 460800,
1166                 .uart_offset    = 8,
1167         },
1168         [pbn_b0_bt_4_460800] = {
1169                 .flags          = FL_BASE0|FL_BASE_BARS,
1170                 .num_ports      = 4,
1171                 .base_baud      = 460800,
1172                 .uart_offset    = 8,
1173         },
1174
1175         [pbn_b0_bt_1_921600] = {
1176                 .flags          = FL_BASE0|FL_BASE_BARS,
1177                 .num_ports      = 1,
1178                 .base_baud      = 921600,
1179                 .uart_offset    = 8,
1180         },
1181         [pbn_b0_bt_2_921600] = {
1182                 .flags          = FL_BASE0|FL_BASE_BARS,
1183                 .num_ports      = 2,
1184                 .base_baud      = 921600,
1185                 .uart_offset    = 8,
1186         },
1187         [pbn_b0_bt_4_921600] = {
1188                 .flags          = FL_BASE0|FL_BASE_BARS,
1189                 .num_ports      = 4,
1190                 .base_baud      = 921600,
1191                 .uart_offset    = 8,
1192         },
1193         [pbn_b0_bt_8_921600] = {
1194                 .flags          = FL_BASE0|FL_BASE_BARS,
1195                 .num_ports      = 8,
1196                 .base_baud      = 921600,
1197                 .uart_offset    = 8,
1198         },
1199
1200         [pbn_b1_1_115200] = {
1201                 .flags          = FL_BASE1,
1202                 .num_ports      = 1,
1203                 .base_baud      = 115200,
1204                 .uart_offset    = 8,
1205         },
1206         [pbn_b1_2_115200] = {
1207                 .flags          = FL_BASE1,
1208                 .num_ports      = 2,
1209                 .base_baud      = 115200,
1210                 .uart_offset    = 8,
1211         },
1212         [pbn_b1_4_115200] = {
1213                 .flags          = FL_BASE1,
1214                 .num_ports      = 4,
1215                 .base_baud      = 115200,
1216                 .uart_offset    = 8,
1217         },
1218         [pbn_b1_8_115200] = {
1219                 .flags          = FL_BASE1,
1220                 .num_ports      = 8,
1221                 .base_baud      = 115200,
1222                 .uart_offset    = 8,
1223         },
1224
1225         [pbn_b1_1_921600] = {
1226                 .flags          = FL_BASE1,
1227                 .num_ports      = 1,
1228                 .base_baud      = 921600,
1229                 .uart_offset    = 8,
1230         },
1231         [pbn_b1_2_921600] = {
1232                 .flags          = FL_BASE1,
1233                 .num_ports      = 2,
1234                 .base_baud      = 921600,
1235                 .uart_offset    = 8,
1236         },
1237         [pbn_b1_4_921600] = {
1238                 .flags          = FL_BASE1,
1239                 .num_ports      = 4,
1240                 .base_baud      = 921600,
1241                 .uart_offset    = 8,
1242         },
1243         [pbn_b1_8_921600] = {
1244                 .flags          = FL_BASE1,
1245                 .num_ports      = 8,
1246                 .base_baud      = 921600,
1247                 .uart_offset    = 8,
1248         },
1249
1250         [pbn_b1_bt_2_921600] = {
1251                 .flags          = FL_BASE1|FL_BASE_BARS,
1252                 .num_ports      = 2,
1253                 .base_baud      = 921600,
1254                 .uart_offset    = 8,
1255         },
1256
1257         [pbn_b1_1_1382400] = {
1258                 .flags          = FL_BASE1,
1259                 .num_ports      = 1,
1260                 .base_baud      = 1382400,
1261                 .uart_offset    = 8,
1262         },
1263         [pbn_b1_2_1382400] = {
1264                 .flags          = FL_BASE1,
1265                 .num_ports      = 2,
1266                 .base_baud      = 1382400,
1267                 .uart_offset    = 8,
1268         },
1269         [pbn_b1_4_1382400] = {
1270                 .flags          = FL_BASE1,
1271                 .num_ports      = 4,
1272                 .base_baud      = 1382400,
1273                 .uart_offset    = 8,
1274         },
1275         [pbn_b1_8_1382400] = {
1276                 .flags          = FL_BASE1,
1277                 .num_ports      = 8,
1278                 .base_baud      = 1382400,
1279                 .uart_offset    = 8,
1280         },
1281
1282         [pbn_b2_1_115200] = {
1283                 .flags          = FL_BASE2,
1284                 .num_ports      = 1,
1285                 .base_baud      = 115200,
1286                 .uart_offset    = 8,
1287         },
1288         [pbn_b2_8_115200] = {
1289                 .flags          = FL_BASE2,
1290                 .num_ports      = 8,
1291                 .base_baud      = 115200,
1292                 .uart_offset    = 8,
1293         },
1294
1295         [pbn_b2_1_460800] = {
1296                 .flags          = FL_BASE2,
1297                 .num_ports      = 1,
1298                 .base_baud      = 460800,
1299                 .uart_offset    = 8,
1300         },
1301         [pbn_b2_4_460800] = {
1302                 .flags          = FL_BASE2,
1303                 .num_ports      = 4,
1304                 .base_baud      = 460800,
1305                 .uart_offset    = 8,
1306         },
1307         [pbn_b2_8_460800] = {
1308                 .flags          = FL_BASE2,
1309                 .num_ports      = 8,
1310                 .base_baud      = 460800,
1311                 .uart_offset    = 8,
1312         },
1313         [pbn_b2_16_460800] = {
1314                 .flags          = FL_BASE2,
1315                 .num_ports      = 16,
1316                 .base_baud      = 460800,
1317                 .uart_offset    = 8,
1318          },
1319
1320         [pbn_b2_1_921600] = {
1321                 .flags          = FL_BASE2,
1322                 .num_ports      = 1,
1323                 .base_baud      = 921600,
1324                 .uart_offset    = 8,
1325         },
1326         [pbn_b2_4_921600] = {
1327                 .flags          = FL_BASE2,
1328                 .num_ports      = 4,
1329                 .base_baud      = 921600,
1330                 .uart_offset    = 8,
1331         },
1332         [pbn_b2_8_921600] = {
1333                 .flags          = FL_BASE2,
1334                 .num_ports      = 8,
1335                 .base_baud      = 921600,
1336                 .uart_offset    = 8,
1337         },
1338
1339         [pbn_b2_bt_1_115200] = {
1340                 .flags          = FL_BASE2|FL_BASE_BARS,
1341                 .num_ports      = 1,
1342                 .base_baud      = 115200,
1343                 .uart_offset    = 8,
1344         },
1345         [pbn_b2_bt_2_115200] = {
1346                 .flags          = FL_BASE2|FL_BASE_BARS,
1347                 .num_ports      = 2,
1348                 .base_baud      = 115200,
1349                 .uart_offset    = 8,
1350         },
1351         [pbn_b2_bt_4_115200] = {
1352                 .flags          = FL_BASE2|FL_BASE_BARS,
1353                 .num_ports      = 4,
1354                 .base_baud      = 115200,
1355                 .uart_offset    = 8,
1356         },
1357
1358         [pbn_b2_bt_2_921600] = {
1359                 .flags          = FL_BASE2|FL_BASE_BARS,
1360                 .num_ports      = 2,
1361                 .base_baud      = 921600,
1362                 .uart_offset    = 8,
1363         },
1364         [pbn_b2_bt_4_921600] = {
1365                 .flags          = FL_BASE2|FL_BASE_BARS,
1366                 .num_ports      = 4,
1367                 .base_baud      = 921600,
1368                 .uart_offset    = 8,
1369         },
1370
1371         [pbn_b3_4_115200] = {
1372                 .flags          = FL_BASE3,
1373                 .num_ports      = 4,
1374                 .base_baud      = 115200,
1375                 .uart_offset    = 8,
1376         },
1377         [pbn_b3_8_115200] = {
1378                 .flags          = FL_BASE3,
1379                 .num_ports      = 8,
1380                 .base_baud      = 115200,
1381                 .uart_offset    = 8,
1382         },
1383
1384         /*
1385          * Entries following this are board-specific.
1386          */
1387
1388         /*
1389          * Panacom - IOMEM
1390          */
1391         [pbn_panacom] = {
1392                 .flags          = FL_BASE2,
1393                 .num_ports      = 2,
1394                 .base_baud      = 921600,
1395                 .uart_offset    = 0x400,
1396                 .reg_shift      = 7,
1397         },
1398         [pbn_panacom2] = {
1399                 .flags          = FL_BASE2|FL_BASE_BARS,
1400                 .num_ports      = 2,
1401                 .base_baud      = 921600,
1402                 .uart_offset    = 0x400,
1403                 .reg_shift      = 7,
1404         },
1405         [pbn_panacom4] = {
1406                 .flags          = FL_BASE2|FL_BASE_BARS,
1407                 .num_ports      = 4,
1408                 .base_baud      = 921600,
1409                 .uart_offset    = 0x400,
1410                 .reg_shift      = 7,
1411         },
1412
1413         /* I think this entry is broken - the first_offset looks wrong --rmk */
1414         [pbn_plx_romulus] = {
1415                 .flags          = FL_BASE2,
1416                 .num_ports      = 4,
1417                 .base_baud      = 921600,
1418                 .uart_offset    = 8 << 2,
1419                 .reg_shift      = 2,
1420                 .first_offset   = 0x03,
1421         },
1422
1423         /*
1424          * This board uses the size of PCI Base region 0 to
1425          * signal now many ports are available
1426          */
1427         [pbn_oxsemi] = {
1428                 .flags          = FL_BASE0|FL_REGION_SZ_CAP,
1429                 .num_ports      = 32,
1430                 .base_baud      = 115200,
1431                 .uart_offset    = 8,
1432         },
1433
1434         /*
1435          * EKF addition for i960 Boards form EKF with serial port.
1436          * Max 256 ports.
1437          */
1438         [pbn_intel_i960] = {
1439                 .flags          = FL_BASE0,
1440                 .num_ports      = 32,
1441                 .base_baud      = 921600,
1442                 .uart_offset    = 8 << 2,
1443                 .reg_shift      = 2,
1444                 .first_offset   = 0x10000,
1445         },
1446         [pbn_sgi_ioc3] = {
1447                 .flags          = FL_BASE0|FL_NOIRQ,
1448                 .num_ports      = 1,
1449                 .base_baud      = 458333,
1450                 .uart_offset    = 8,
1451                 .reg_shift      = 0,
1452                 .first_offset   = 0x20178,
1453         },
1454
1455         /*
1456          * NEC Vrc-5074 (Nile 4) builtin UART.
1457          */
1458         [pbn_nec_nile4] = {
1459                 .flags          = FL_BASE0,
1460                 .num_ports      = 1,
1461                 .base_baud      = 520833,
1462                 .uart_offset    = 8 << 3,
1463                 .reg_shift      = 3,
1464                 .first_offset   = 0x300,
1465         },
1466
1467         /*
1468          * Computone - uses IOMEM.
1469          */
1470         [pbn_computone_4] = {
1471                 .flags          = FL_BASE0,
1472                 .num_ports      = 4,
1473                 .base_baud      = 921600,
1474                 .uart_offset    = 0x40,
1475                 .reg_shift      = 2,
1476                 .first_offset   = 0x200,
1477         },
1478         [pbn_computone_6] = {
1479                 .flags          = FL_BASE0,
1480                 .num_ports      = 6,
1481                 .base_baud      = 921600,
1482                 .uart_offset    = 0x40,
1483                 .reg_shift      = 2,
1484                 .first_offset   = 0x200,
1485         },
1486         [pbn_computone_8] = {
1487                 .flags          = FL_BASE0,
1488                 .num_ports      = 8,
1489                 .base_baud      = 921600,
1490                 .uart_offset    = 0x40,
1491                 .reg_shift      = 2,
1492                 .first_offset   = 0x200,
1493         },
1494         [pbn_sbsxrsio] = {
1495                 .flags          = FL_BASE0,
1496                 .num_ports      = 8,
1497                 .base_baud      = 460800,
1498                 .uart_offset    = 256,
1499                 .reg_shift      = 4,
1500         },
1501         /*
1502          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
1503          *  Only basic 16550A support.
1504          *  XR17C15[24] are not tested, but they should work.
1505          */
1506         [pbn_exar_XR17C152] = {
1507                 .flags          = FL_BASE0,
1508                 .num_ports      = 2,
1509                 .base_baud      = 921600,
1510                 .uart_offset    = 0x200,
1511         },
1512         [pbn_exar_XR17C154] = {
1513                 .flags          = FL_BASE0,
1514                 .num_ports      = 4,
1515                 .base_baud      = 921600,
1516                 .uart_offset    = 0x200,
1517         },
1518         [pbn_exar_XR17C158] = {
1519                 .flags          = FL_BASE0,
1520                 .num_ports      = 8,
1521                 .base_baud      = 921600,
1522                 .uart_offset    = 0x200,
1523         },
1524 };
1525
1526 /*
1527  * Given a complete unknown PCI device, try to use some heuristics to
1528  * guess what the configuration might be, based on the pitiful PCI
1529  * serial specs.  Returns 0 on success, 1 on failure.
1530  */
1531 static int __devinit
1532 serial_pci_guess_board(struct pci_dev *dev, struct pci_board *board)
1533 {
1534         int num_iomem, num_port, first_port = -1, i;
1535
1536         /*
1537          * If it is not a communications device or the programming
1538          * interface is greater than 6, give up.
1539          *
1540          * (Should we try to make guesses for multiport serial devices
1541          * later?)
1542          */
1543         if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
1544              ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
1545             (dev->class & 0xff) > 6)
1546                 return -ENODEV;
1547
1548         num_iomem = num_port = 0;
1549         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1550                 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
1551                         num_port++;
1552                         if (first_port == -1)
1553                                 first_port = i;
1554                 }
1555                 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
1556                         num_iomem++;
1557         }
1558
1559         /*
1560          * If there is 1 or 0 iomem regions, and exactly one port,
1561          * use it.  We guess the number of ports based on the IO
1562          * region size.
1563          */
1564         if (num_iomem <= 1 && num_port == 1) {
1565                 board->flags = first_port;
1566                 board->num_ports = pci_resource_len(dev, first_port) / 8;
1567                 return 0;
1568         }
1569
1570         /*
1571          * Now guess if we've got a board which indexes by BARs.
1572          * Each IO BAR should be 8 bytes, and they should follow
1573          * consecutively.
1574          */
1575         first_port = -1;
1576         num_port = 0;
1577         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1578                 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
1579                     pci_resource_len(dev, i) == 8 &&
1580                     (first_port == -1 || (first_port + num_port) == i)) {
1581                         num_port++;
1582                         if (first_port == -1)
1583                                 first_port = i;
1584                 }
1585         }
1586
1587         if (num_port > 1) {
1588                 board->flags = first_port | FL_BASE_BARS;
1589                 board->num_ports = num_port;
1590                 return 0;
1591         }
1592
1593         return -ENODEV;
1594 }
1595
1596 static inline int
1597 serial_pci_matches(struct pci_board *board, struct pci_board *guessed)
1598 {
1599         return
1600             board->num_ports == guessed->num_ports &&
1601             board->base_baud == guessed->base_baud &&
1602             board->uart_offset == guessed->uart_offset &&
1603             board->reg_shift == guessed->reg_shift &&
1604             board->first_offset == guessed->first_offset;
1605 }
1606
1607 /*
1608  * Probe one serial board.  Unfortunately, there is no rhyme nor reason
1609  * to the arrangement of serial ports on a PCI card.
1610  */
1611 static int __devinit
1612 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
1613 {
1614         struct serial_private *priv;
1615         struct pci_board *board, tmp;
1616         struct pci_serial_quirk *quirk;
1617         int rc, nr_ports, i;
1618
1619         if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
1620                 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
1621                         ent->driver_data);
1622                 return -EINVAL;
1623         }
1624
1625         board = &pci_boards[ent->driver_data];
1626
1627         rc = pci_enable_device(dev);
1628         if (rc)
1629                 return rc;
1630
1631         if (ent->driver_data == pbn_default) {
1632                 /*
1633                  * Use a copy of the pci_board entry for this;
1634                  * avoid changing entries in the table.
1635                  */
1636                 memcpy(&tmp, board, sizeof(struct pci_board));
1637                 board = &tmp;
1638
1639                 /*
1640                  * We matched one of our class entries.  Try to
1641                  * determine the parameters of this board.
1642                  */
1643                 rc = serial_pci_guess_board(dev, board);
1644                 if (rc)
1645                         goto disable;
1646         } else {
1647                 /*
1648                  * We matched an explicit entry.  If we are able to
1649                  * detect this boards settings with our heuristic,
1650                  * then we no longer need this entry.
1651                  */
1652                 memcpy(&tmp, &pci_boards[pbn_default], sizeof(struct pci_board));
1653                 rc = serial_pci_guess_board(dev, &tmp);
1654                 if (rc == 0 && serial_pci_matches(board, &tmp))
1655                         moan_device("Redundant entry in serial pci_table.",
1656                                     dev);
1657         }
1658
1659         nr_ports = board->num_ports;
1660
1661         /*
1662          * Find an init and setup quirks.
1663          */
1664         quirk = find_quirk(dev);
1665
1666         /*
1667          * Run the new-style initialization function.
1668          * The initialization function returns:
1669          *  <0  - error
1670          *   0  - use board->num_ports
1671          *  >0  - number of ports
1672          */
1673         if (quirk->init) {
1674                 rc = quirk->init(dev);
1675                 if (rc < 0)
1676                         goto disable;
1677                 if (rc)
1678                         nr_ports = rc;
1679         }
1680
1681         priv = kmalloc(sizeof(struct serial_private) +
1682                        sizeof(unsigned int) * nr_ports,
1683                        GFP_KERNEL);
1684         if (!priv) {
1685                 rc = -ENOMEM;
1686                 goto deinit;
1687         }
1688
1689         memset(priv, 0, sizeof(struct serial_private) +
1690                         sizeof(unsigned int) * nr_ports);
1691
1692         priv->quirk = quirk;
1693         pci_set_drvdata(dev, priv);
1694
1695         for (i = 0; i < nr_ports; i++) {
1696                 struct uart_port serial_port;
1697                 memset(&serial_port, 0, sizeof(struct uart_port));
1698
1699                 serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF |
1700                                     UPF_SHARE_IRQ;
1701                 serial_port.uartclk = board->base_baud * 16;
1702                 serial_port.irq = get_pci_irq(dev, board, i);
1703                 serial_port.dev = &dev->dev;
1704                 if (quirk->setup(dev, board, &serial_port, i))
1705                         break;
1706 #ifdef SERIAL_DEBUG_PCI
1707                 printk("Setup PCI port: port %x, irq %d, type %d\n",
1708                        serial_port.iobase, serial_port.irq, serial_port.iotype);
1709 #endif
1710
1711                 priv->line[i] = serial8250_register_port(&serial_port);
1712                 if (priv->line[i] < 0) {
1713                         printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
1714                         break;
1715                 }
1716         }
1717
1718         priv->nr = i;
1719
1720         return 0;
1721
1722  deinit:
1723         if (quirk->exit)
1724                 quirk->exit(dev);
1725  disable:
1726         pci_disable_device(dev);
1727         return rc;
1728 }
1729
1730 static void __devexit pciserial_remove_one(struct pci_dev *dev)
1731 {
1732         struct serial_private *priv = pci_get_drvdata(dev);
1733
1734         pci_set_drvdata(dev, NULL);
1735
1736         if (priv) {
1737                 struct pci_serial_quirk *quirk;
1738                 int i;
1739
1740                 for (i = 0; i < priv->nr; i++)
1741                         serial8250_unregister_port(priv->line[i]);
1742
1743                 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1744                         if (priv->remapped_bar[i])
1745                                 iounmap(priv->remapped_bar[i]);
1746                         priv->remapped_bar[i] = NULL;
1747                 }
1748
1749                 /*
1750                  * Find the exit quirks.
1751                  */
1752                 quirk = find_quirk(dev);
1753                 if (quirk->exit)
1754                         quirk->exit(dev);
1755
1756                 pci_disable_device(dev);
1757
1758                 kfree(priv);
1759         }
1760 }
1761
1762 static int pciserial_suspend_one(struct pci_dev *dev, u32 state)
1763 {
1764         struct serial_private *priv = pci_get_drvdata(dev);
1765
1766         if (priv) {
1767                 int i;
1768
1769                 for (i = 0; i < priv->nr; i++)
1770                         serial8250_suspend_port(priv->line[i]);
1771         }
1772         return 0;
1773 }
1774
1775 static int pciserial_resume_one(struct pci_dev *dev)
1776 {
1777         struct serial_private *priv = pci_get_drvdata(dev);
1778
1779         if (priv) {
1780                 int i;
1781
1782                 /*
1783                  * Ensure that the board is correctly configured.
1784                  */
1785                 if (priv->quirk->init)
1786                         priv->quirk->init(dev);
1787
1788                 for (i = 0; i < priv->nr; i++)
1789                         serial8250_resume_port(priv->line[i]);
1790         }
1791         return 0;
1792 }
1793
1794 static struct pci_device_id serial_pci_tbl[] = {
1795         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1796                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1797                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1798                 pbn_b1_8_1382400 },
1799         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1800                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1801                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1802                 pbn_b1_4_1382400 },
1803         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1804                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1805                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1806                 pbn_b1_2_1382400 },
1807         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1808                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1809                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1810                 pbn_b1_8_1382400 },
1811         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1812                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1813                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1814                 pbn_b1_4_1382400 },
1815         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1816                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1817                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1818                 pbn_b1_2_1382400 },
1819         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1820                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1821                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
1822                 pbn_b1_8_921600 },
1823         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1824                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1825                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
1826                 pbn_b1_8_921600 },
1827         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1828                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1829                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
1830                 pbn_b1_4_921600 },
1831         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1832                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1833                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
1834                 pbn_b1_4_921600 },
1835         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1836                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1837                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
1838                 pbn_b1_2_921600 },
1839         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1840                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1841                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
1842                 pbn_b1_8_921600 },
1843         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1844                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1845                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
1846                 pbn_b1_8_921600 },
1847         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1848                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1849                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
1850                 pbn_b1_4_921600 },
1851
1852         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
1853                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1854                 pbn_b2_bt_1_115200 },
1855         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
1856                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1857                 pbn_b2_bt_2_115200 },
1858         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
1859                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1860                 pbn_b2_bt_4_115200 },
1861         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
1862                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1863                 pbn_b2_bt_2_115200 },
1864         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
1865                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1866                 pbn_b2_bt_4_115200 },
1867         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
1868                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1869                 pbn_b2_8_115200 },
1870
1871         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
1872                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1873                 pbn_b2_bt_2_115200 },
1874         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
1875                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1876                 pbn_b2_bt_2_921600 },
1877         /*
1878          * VScom SPCOM800, from sl@s.pl
1879          */
1880         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
1881                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1882                 pbn_b2_8_921600 },
1883         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
1884                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1885                 pbn_b2_4_921600 },
1886         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1887                 PCI_SUBVENDOR_ID_KEYSPAN,
1888                 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
1889                 pbn_panacom },
1890         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
1891                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1892                 pbn_panacom4 },
1893         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
1894                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1895                 pbn_panacom2 },
1896         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1897                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1898                 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
1899                 pbn_b2_4_460800 },
1900         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1901                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1902                 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
1903                 pbn_b2_8_460800 },
1904         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1905                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1906                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
1907                 pbn_b2_16_460800 },
1908         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1909                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1910                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
1911                 pbn_b2_16_460800 },
1912         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1913                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
1914                 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
1915                 pbn_b2_4_460800 },
1916         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1917                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
1918                 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
1919                 pbn_b2_8_460800 },
1920         /*
1921          * Megawolf Romulus PCI Serial Card, from Mike Hudson
1922          * (Exoray@isys.ca)
1923          */
1924         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
1925                 0x10b5, 0x106a, 0, 0,
1926                 pbn_plx_romulus },
1927         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
1928                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1929                 pbn_b1_4_115200 },
1930         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
1931                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1932                 pbn_b1_2_115200 },
1933         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
1934                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1935                 pbn_b1_8_115200 },
1936         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
1937                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1938                 pbn_b1_8_115200 },
1939         {       PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
1940                 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 0, 0,
1941                 pbn_b0_4_921600 },
1942         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1943                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1944                 pbn_b0_4_115200 },
1945         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
1946                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1947                 pbn_b0_bt_2_921600 },
1948
1949         /*
1950          * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
1951          * from skokodyn@yahoo.com
1952          */
1953         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1954                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
1955                 pbn_sbsxrsio },
1956         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1957                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
1958                 pbn_sbsxrsio },
1959         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1960                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
1961                 pbn_sbsxrsio },
1962         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1963                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
1964                 pbn_sbsxrsio },
1965
1966         /*
1967          * Digitan DS560-558, from jimd@esoft.com
1968          */
1969         {       PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
1970                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1971                 pbn_b1_1_115200 },
1972
1973         /*
1974          * Titan Electronic cards
1975          *  The 400L and 800L have a custom setup quirk.
1976          */
1977         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
1978                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1979                 pbn_b0_1_921600 },
1980         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
1981                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1982                 pbn_b0_2_921600 },
1983         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
1984                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1985                 pbn_b0_4_921600 },
1986         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
1987                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1988                 pbn_b0_4_921600 },
1989         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
1990                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1991                 pbn_b1_1_921600 },
1992         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
1993                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1994                 pbn_b1_bt_2_921600 },
1995         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
1996                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1997                 pbn_b0_bt_4_921600 },
1998         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
1999                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2000                 pbn_b0_bt_8_921600 },
2001
2002         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
2003                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2004                 pbn_b2_1_460800 },
2005         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
2006                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2007                 pbn_b2_1_460800 },
2008         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
2009                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2010                 pbn_b2_1_460800 },
2011         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
2012                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2013                 pbn_b2_bt_2_921600 },
2014         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
2015                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2016                 pbn_b2_bt_2_921600 },
2017         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
2018                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2019                 pbn_b2_bt_2_921600 },
2020         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
2021                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2022                 pbn_b2_bt_4_921600 },
2023         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
2024                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2025                 pbn_b2_bt_4_921600 },
2026         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
2027                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2028                 pbn_b2_bt_4_921600 },
2029         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
2030                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2031                 pbn_b0_1_921600 },
2032         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
2033                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2034                 pbn_b0_1_921600 },
2035         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
2036                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2037                 pbn_b0_1_921600 },
2038         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
2039                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2040                 pbn_b0_bt_2_921600 },
2041         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
2042                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2043                 pbn_b0_bt_2_921600 },
2044         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
2045                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2046                 pbn_b0_bt_2_921600 },
2047         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
2048                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2049                 pbn_b0_bt_4_921600 },
2050         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
2051                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2052                 pbn_b0_bt_4_921600 },
2053         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
2054                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2055                 pbn_b0_bt_4_921600 },
2056
2057         /*
2058          * Computone devices submitted by Doug McNash dmcnash@computone.com
2059          */
2060         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2061                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
2062                 0, 0, pbn_computone_4 },
2063         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2064                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
2065                 0, 0, pbn_computone_8 },
2066         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2067                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
2068                 0, 0, pbn_computone_6 },
2069
2070         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
2071                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2072                 pbn_oxsemi },
2073         {       PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
2074                 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
2075                 pbn_b0_bt_1_921600 },
2076
2077         /*
2078          * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
2079          */
2080         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
2081                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2082                 pbn_b0_bt_8_115200 },
2083         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
2084                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2085                 pbn_b0_bt_8_115200 },
2086
2087         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
2088                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2089                 pbn_b0_bt_2_115200 },
2090         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
2091                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2092                 pbn_b0_bt_2_115200 },
2093         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
2094                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2095                 pbn_b0_bt_2_115200 },
2096         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
2097                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2098                 pbn_b0_bt_4_460800 },
2099         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
2100                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2101                 pbn_b0_bt_4_460800 },
2102         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
2103                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2104                 pbn_b0_bt_2_460800 },
2105         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
2106                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2107                 pbn_b0_bt_2_460800 },
2108         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
2109                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2110                 pbn_b0_bt_2_460800 },
2111         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
2112                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2113                 pbn_b0_bt_1_115200 },
2114         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
2115                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2116                 pbn_b0_bt_1_460800 },
2117
2118         /*
2119          * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
2120          */
2121         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
2122                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2123                 pbn_b1_1_1382400 },
2124
2125         /*
2126          * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
2127          */
2128         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
2129                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2130                 pbn_b1_1_1382400 },
2131
2132         /*
2133          * RAStel 2 port modem, gerg@moreton.com.au
2134          */
2135         {       PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
2136                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2137                 pbn_b2_bt_2_115200 },
2138
2139         /*
2140          * EKF addition for i960 Boards form EKF with serial port
2141          */
2142         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
2143                 0xE4BF, PCI_ANY_ID, 0, 0,
2144                 pbn_intel_i960 },
2145
2146         /*
2147          * Xircom Cardbus/Ethernet combos
2148          */
2149         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2150                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2151                 pbn_b0_1_115200 },
2152         /*
2153          * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
2154          */
2155         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
2156                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2157                 pbn_b0_1_115200 },
2158
2159         /*
2160          * Untested PCI modems, sent in from various folks...
2161          */
2162
2163         /*
2164          * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
2165          */
2166         {       PCI_VENDOR_ID_ROCKWELL, 0x1004,
2167                 0x1048, 0x1500, 0, 0,
2168                 pbn_b1_1_115200 },
2169
2170         {       PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
2171                 0xFF00, 0, 0, 0,
2172                 pbn_sgi_ioc3 },
2173
2174         /*
2175          * HP Diva card
2176          */
2177         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2178                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2179                 pbn_b0_5_115200 },
2180         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
2181                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2182                 pbn_b2_1_115200 },
2183
2184         /*
2185          * NEC Vrc-5074 (Nile 4) builtin UART.
2186          */
2187         {       PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_NILE4,
2188                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2189                 pbn_nec_nile4 },
2190
2191         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
2192                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2193                 pbn_b3_4_115200 },
2194         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
2195                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2196                 pbn_b3_8_115200 },
2197
2198         /*
2199          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2200          */
2201         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2202                 PCI_ANY_ID, PCI_ANY_ID,
2203                 0,
2204                 0, pbn_exar_XR17C152 },
2205         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2206                 PCI_ANY_ID, PCI_ANY_ID,
2207                 0,
2208                 0, pbn_exar_XR17C154 },
2209         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2210                 PCI_ANY_ID, PCI_ANY_ID,
2211                 0,
2212                 0, pbn_exar_XR17C158 },
2213
2214         /*
2215          * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
2216          */
2217         {       PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
2218                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2219                 pbn_b0_1_115200 },
2220
2221         /*
2222          * These entries match devices with class COMMUNICATION_SERIAL,
2223          * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
2224          */
2225         {       PCI_ANY_ID, PCI_ANY_ID,
2226                 PCI_ANY_ID, PCI_ANY_ID,
2227                 PCI_CLASS_COMMUNICATION_SERIAL << 8,
2228                 0xffff00, pbn_default },
2229         {       PCI_ANY_ID, PCI_ANY_ID,
2230                 PCI_ANY_ID, PCI_ANY_ID,
2231                 PCI_CLASS_COMMUNICATION_MODEM << 8,
2232                 0xffff00, pbn_default },
2233         {       PCI_ANY_ID, PCI_ANY_ID,
2234                 PCI_ANY_ID, PCI_ANY_ID,
2235                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
2236                 0xffff00, pbn_default },
2237         { 0, }
2238 };
2239
2240 static struct pci_driver serial_pci_driver = {
2241         .name           = "serial",
2242         .probe          = pciserial_init_one,
2243         .remove         = __devexit_p(pciserial_remove_one),
2244         .suspend        = pciserial_suspend_one,
2245         .resume         = pciserial_resume_one,
2246         .id_table       = serial_pci_tbl,
2247 };
2248
2249 static int __init serial8250_pci_init(void)
2250 {
2251         return pci_register_driver(&serial_pci_driver);
2252 }
2253
2254 static void __exit serial8250_pci_exit(void)
2255 {
2256         pci_unregister_driver(&serial_pci_driver);
2257 }
2258
2259 module_init(serial8250_pci_init);
2260 module_exit(serial8250_pci_exit);
2261
2262 MODULE_LICENSE("GPL");
2263 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
2264 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);