drivers/serial/cpm_uart/cpm_uart_cpm2.c

   1 /*
   2  *  linux/drivers/serial/cpm_uart_cpm2.c
   3  *
   4  *  Driver for CPM (SCC/SMC) serial ports; CPM2 definitions
   5  *
   6  *  Maintainer: Kumar Gala (galak@kernel.crashing.org) (CPM2)
   7  *              Pantelis Antoniou (panto@intracom.gr) (CPM1)
   8  *
   9  *  Copyright (C) 2004 Freescale Semiconductor, Inc.
  10  *            (C) 2004 Intracom, S.A.
  11  *            (C) 2006 MontaVista Software, Inc.
  12  *              Vitaly Bordug <vbordug@ru.mvista.com>
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License as published by
  16  * the Free Software Foundation; either version 2 of the License, or
  17  * (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  27  *
  28  */
  29
  30 #include <linux/config.h>
  31 #include <linux/module.h>
  32 #include <linux/tty.h>
  33 #include <linux/ioport.h>
  34 #include <linux/init.h>
  35 #include <linux/serial.h>
  36 #include <linux/console.h>
  37 #include <linux/sysrq.h>
  38 #include <linux/device.h>
  39 #include <linux/bootmem.h>
  40 #include <linux/dma-mapping.h>
  41
  42 #include <asm/io.h>
  43 #include <asm/irq.h>
  44
  45 #include <linux/serial_core.h>
  46 #include <linux/kernel.h>
  47
  48 #include "cpm_uart.h"
  49
  50 /**************************************************************/
  51
  52 void cpm_line_cr_cmd(int line, int cmd)
  53 {
  54         volatile cpm_cpm2_t *cp = cpmp;
  55         ulong val;
  56
  57         switch (line) {
  58         case UART_SMC1:
  59                 val = mk_cr_cmd(CPM_CR_SMC1_PAGE, CPM_CR_SMC1_SBLOCK, 0,
  60                                 cmd) | CPM_CR_FLG;
  61                 break;
  62         case UART_SMC2:
  63                 val = mk_cr_cmd(CPM_CR_SMC2_PAGE, CPM_CR_SMC2_SBLOCK, 0,
  64                                 cmd) | CPM_CR_FLG;
  65                 break;
  66         case UART_SCC1:
  67                 val = mk_cr_cmd(CPM_CR_SCC1_PAGE, CPM_CR_SCC1_SBLOCK, 0,
  68                                 cmd) | CPM_CR_FLG;
  69                 break;
  70         case UART_SCC2:
  71                 val = mk_cr_cmd(CPM_CR_SCC2_PAGE, CPM_CR_SCC2_SBLOCK, 0,
  72                                 cmd) | CPM_CR_FLG;
  73                 break;
  74         case UART_SCC3:
  75                 val = mk_cr_cmd(CPM_CR_SCC3_PAGE, CPM_CR_SCC3_SBLOCK, 0,
  76                                 cmd) | CPM_CR_FLG;
  77                 break;
  78         case UART_SCC4:
  79                 val = mk_cr_cmd(CPM_CR_SCC4_PAGE, CPM_CR_SCC4_SBLOCK, 0,
  80                                 cmd) | CPM_CR_FLG;
  81                 break;
  82         default:
  83                 return;
  84
  85         }
  86         cp->cp_cpcr = val;
  87         while (cp->cp_cpcr & CPM_CR_FLG) ;
  88 }
  89
  90 void smc1_lineif(struct uart_cpm_port *pinfo)
  91 {
  92         volatile iop_cpm2_t *io = &cpm2_immr->im_ioport;
  93
  94         /* SMC1 is only on port D */
  95         io->iop_ppard |= 0x00c00000;
  96         io->iop_pdird |= 0x00400000;
  97         io->iop_pdird &= ~0x00800000;
  98         io->iop_psord &= ~0x00c00000;
  99
 100         /* Wire BRG1 to SMC1 */
 101         cpm2_immr->im_cpmux.cmx_smr &= 0x0f;
 102         pinfo->brg = 1;
 103 }
 104
 105 void smc2_lineif(struct uart_cpm_port *pinfo)
 106 {
 107         volatile iop_cpm2_t *io = &cpm2_immr->im_ioport;
 108
 109         /* SMC2 is only on port A */
 110         io->iop_ppara |= 0x00c00000;
 111         io->iop_pdira |= 0x00400000;
 112         io->iop_pdira &= ~0x00800000;
 113         io->iop_psora &= ~0x00c00000;
 114
 115         /* Wire BRG2 to SMC2 */
 116         cpm2_immr->im_cpmux.cmx_smr &= 0xf0;
 117         pinfo->brg = 2;
 118 }
 119
 120 void scc1_lineif(struct uart_cpm_port *pinfo)
 121 {
 122         volatile iop_cpm2_t *io = &cpm2_immr->im_ioport;
 123
 124         /* Use Port D for SCC1 instead of other functions.  */
 125         io->iop_ppard |= 0x00000003;
 126         io->iop_psord &= ~0x00000001;   /* Rx */
 127         io->iop_psord |= 0x00000002;    /* Tx */
 128         io->iop_pdird &= ~0x00000001;   /* Rx */
 129         io->iop_pdird |= 0x00000002;    /* Tx */
 130
 131         /* Wire BRG1 to SCC1 */
 132         cpm2_immr->im_cpmux.cmx_scr &= 0x00ffffff;
 133         cpm2_immr->im_cpmux.cmx_scr |= 0x00000000;
 134         pinfo->brg = 1;
 135 }
 136
 137 void scc2_lineif(struct uart_cpm_port *pinfo)
 138 {
 139         /*
 140          * STx GP3 uses the SCC2 secondary option pin assignment
 141          * which this driver doesn't account for in the static
 142          * pin assignments. This kind of board specific info
 143          * really has to get out of the driver so boards can
 144          * be supported in a sane fashion.
 145          */
 146 #ifndef CONFIG_STX_GP3
 147         volatile iop_cpm2_t *io = &cpm2_immr->im_ioport;
 148         io->iop_pparb |= 0x008b0000;
 149         io->iop_pdirb |= 0x00880000;
 150         io->iop_psorb |= 0x00880000;
 151         io->iop_pdirb &= ~0x00030000;
 152         io->iop_psorb &= ~0x00030000;
 153 #endif
 154         cpm2_immr->im_cpmux.cmx_scr &= 0xff00ffff;
 155         cpm2_immr->im_cpmux.cmx_scr |= 0x00090000;
 156         pinfo->brg = 2;
 157 }
 158
 159 void scc3_lineif(struct uart_cpm_port *pinfo)
 160 {
 161         volatile iop_cpm2_t *io = &cpm2_immr->im_ioport;
 162         io->iop_pparb |= 0x008b0000;
 163         io->iop_pdirb |= 0x00880000;
 164         io->iop_psorb |= 0x00880000;
 165         io->iop_pdirb &= ~0x00030000;
 166         io->iop_psorb &= ~0x00030000;
 167         cpm2_immr->im_cpmux.cmx_scr &= 0xffff00ff;
 168         cpm2_immr->im_cpmux.cmx_scr |= 0x00001200;
 169         pinfo->brg = 3;
 170 }
 171
 172 void scc4_lineif(struct uart_cpm_port *pinfo)
 173 {
 174         volatile iop_cpm2_t *io = &cpm2_immr->im_ioport;
 175
 176         io->iop_ppard |= 0x00000600;
 177         io->iop_psord &= ~0x00000600;   /* Tx/Rx */
 178         io->iop_pdird &= ~0x00000200;   /* Rx */
 179         io->iop_pdird |= 0x00000400;    /* Tx */
 180
 181         cpm2_immr->im_cpmux.cmx_scr &= 0xffffff00;
 182         cpm2_immr->im_cpmux.cmx_scr |= 0x0000001b;
 183         pinfo->brg = 4;
 184 }
 185
 186 /*
 187  * Allocate DP-Ram and memory buffers. We need to allocate a transmit and
 188  * receive buffer descriptors from dual port ram, and a character
 189  * buffer area from host mem. If we are allocating for the console we need
 190  * to do it from bootmem
 191  */
 192 int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned int is_con)
 193 {
 194         int dpmemsz, memsz;
 195         u8 *dp_mem;
 196         uint dp_offset;
 197         u8 *mem_addr;
 198         dma_addr_t dma_addr = 0;
 199
 200         pr_debug("CPM uart[%d]:allocbuf\n", pinfo->port.line);
 201
 202         dpmemsz = sizeof(cbd_t) * (pinfo->rx_nrfifos + pinfo->tx_nrfifos);
 203         dp_offset = cpm_dpalloc(dpmemsz, 8);
 204         if (IS_DPERR(dp_offset)) {
 205                 printk(KERN_ERR
 206                        "cpm_uart_cpm.c: could not allocate buffer descriptors\n");
 207                 return -ENOMEM;
 208         }
 209
 210         dp_mem = cpm_dpram_addr(dp_offset);
 211
 212         memsz = L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize) +
 213             L1_CACHE_ALIGN(pinfo->tx_nrfifos * pinfo->tx_fifosize);
 214         if (is_con) {
 215                 mem_addr = alloc_bootmem(memsz);
 216                 dma_addr = virt_to_bus(mem_addr);
 217         }
 218         else
 219                 mem_addr = dma_alloc_coherent(NULL, memsz, &dma_addr,
 220                                               GFP_KERNEL);
 221
 222         if (mem_addr == NULL) {
 223                 cpm_dpfree(dp_offset);
 224                 printk(KERN_ERR
 225                        "cpm_uart_cpm.c: could not allocate coherent memory\n");
 226                 return -ENOMEM;
 227         }
 228
 229         pinfo->dp_addr = dp_offset;
 230         pinfo->mem_addr = mem_addr;
 231         pinfo->dma_addr = dma_addr;
 232         pinfo->mem_size = memsz;
 233
 234         pinfo->rx_buf = mem_addr;
 235         pinfo->tx_buf = pinfo->rx_buf + L1_CACHE_ALIGN(pinfo->rx_nrfifos
 236                                                        * pinfo->rx_fifosize);
 237
 238         pinfo->rx_bd_base = (volatile cbd_t *)dp_mem;
 239         pinfo->tx_bd_base = pinfo->rx_bd_base + pinfo->rx_nrfifos;
 240
 241         return 0;
 242 }
 243
 244 void cpm_uart_freebuf(struct uart_cpm_port *pinfo)
 245 {
 246         dma_free_coherent(NULL, L1_CACHE_ALIGN(pinfo->rx_nrfifos *
 247                                                pinfo->rx_fifosize) +
 248                           L1_CACHE_ALIGN(pinfo->tx_nrfifos *
 249                                          pinfo->tx_fifosize), pinfo->mem_addr,
 250                           pinfo->dma_addr);
 251
 252         cpm_dpfree(pinfo->dp_addr);
 253 }
 254
 255 /* Setup any dynamic params in the uart desc */
 256 int cpm_uart_init_portdesc(void)
 257 {
 258         pr_debug("CPM uart[-]:init portdesc\n");
 259
 260         cpm_uart_nr = 0;
 261 #ifdef CONFIG_SERIAL_CPM_SMC1
 262         cpm_uart_ports[UART_SMC1].smcp = (smc_t *) & cpm2_immr->im_smc[0];
 263         cpm_uart_ports[UART_SMC1].smcup =
 264             (smc_uart_t *) & cpm2_immr->im_dprambase[PROFF_SMC1];
 265         *(u16 *)(&cpm2_immr->im_dprambase[PROFF_SMC1_BASE]) = PROFF_SMC1;
 266         cpm_uart_ports[UART_SMC1].port.mapbase =
 267             (unsigned long)&cpm2_immr->im_smc[0];
 268         cpm_uart_ports[UART_SMC1].smcp->smc_smcm |= (SMCM_RX | SMCM_TX);
 269         cpm_uart_ports[UART_SMC1].smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
 270         cpm_uart_ports[UART_SMC1].port.uartclk = (((bd_t *) __res)->bi_intfreq);
 271         cpm_uart_port_map[cpm_uart_nr++] = UART_SMC1;
 272 #endif
 273
 274 #ifdef CONFIG_SERIAL_CPM_SMC2
 275         cpm_uart_ports[UART_SMC2].smcp = (smc_t *) & cpm2_immr->im_smc[1];
 276         cpm_uart_ports[UART_SMC2].smcup =
 277             (smc_uart_t *) & cpm2_immr->im_dprambase[PROFF_SMC2];
 278         *(u16 *)(&cpm2_immr->im_dprambase[PROFF_SMC2_BASE]) = PROFF_SMC2;
 279         cpm_uart_ports[UART_SMC2].port.mapbase =
 280             (unsigned long)&cpm2_immr->im_smc[1];
 281         cpm_uart_ports[UART_SMC2].smcp->smc_smcm |= (SMCM_RX | SMCM_TX);
 282         cpm_uart_ports[UART_SMC2].smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
 283         cpm_uart_ports[UART_SMC2].port.uartclk = (((bd_t *) __res)->bi_intfreq);
 284         cpm_uart_port_map[cpm_uart_nr++] = UART_SMC2;
 285 #endif
 286
 287 #ifdef CONFIG_SERIAL_CPM_SCC1
 288         cpm_uart_ports[UART_SCC1].sccp = (scc_t *) & cpm2_immr->im_scc[0];
 289         cpm_uart_ports[UART_SCC1].sccup =
 290             (scc_uart_t *) & cpm2_immr->im_dprambase[PROFF_SCC1];
 291         cpm_uart_ports[UART_SCC1].port.mapbase =
 292             (unsigned long)&cpm2_immr->im_scc[0];
 293         cpm_uart_ports[UART_SCC1].sccp->scc_sccm &=
 294             ~(UART_SCCM_TX | UART_SCCM_RX);
 295         cpm_uart_ports[UART_SCC1].sccp->scc_gsmrl &=
 296             ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
 297         cpm_uart_ports[UART_SCC1].port.uartclk = (((bd_t *) __res)->bi_intfreq);
 298         cpm_uart_port_map[cpm_uart_nr++] = UART_SCC1;
 299 #endif
 300
 301 #ifdef CONFIG_SERIAL_CPM_SCC2
 302         cpm_uart_ports[UART_SCC2].sccp = (scc_t *) & cpm2_immr->im_scc[1];
 303         cpm_uart_ports[UART_SCC2].sccup =
 304             (scc_uart_t *) & cpm2_immr->im_dprambase[PROFF_SCC2];
 305         cpm_uart_ports[UART_SCC2].port.mapbase =
 306             (unsigned long)&cpm2_immr->im_scc[1];
 307         cpm_uart_ports[UART_SCC2].sccp->scc_sccm &=
 308             ~(UART_SCCM_TX | UART_SCCM_RX);
 309         cpm_uart_ports[UART_SCC2].sccp->scc_gsmrl &=
 310             ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
 311         cpm_uart_ports[UART_SCC2].port.uartclk = (((bd_t *) __res)->bi_intfreq);
 312         cpm_uart_port_map[cpm_uart_nr++] = UART_SCC2;
 313 #endif
 314
 315 #ifdef CONFIG_SERIAL_CPM_SCC3
 316         cpm_uart_ports[UART_SCC3].sccp = (scc_t *) & cpm2_immr->im_scc[2];
 317         cpm_uart_ports[UART_SCC3].sccup =
 318             (scc_uart_t *) & cpm2_immr->im_dprambase[PROFF_SCC3];
 319         cpm_uart_ports[UART_SCC3].port.mapbase =
 320             (unsigned long)&cpm2_immr->im_scc[2];
 321         cpm_uart_ports[UART_SCC3].sccp->scc_sccm &=
 322             ~(UART_SCCM_TX | UART_SCCM_RX);
 323         cpm_uart_ports[UART_SCC3].sccp->scc_gsmrl &=
 324             ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
 325         cpm_uart_ports[UART_SCC3].port.uartclk = (((bd_t *) __res)->bi_intfreq);
 326         cpm_uart_port_map[cpm_uart_nr++] = UART_SCC3;
 327 #endif
 328
 329 #ifdef CONFIG_SERIAL_CPM_SCC4
 330         cpm_uart_ports[UART_SCC4].sccp = (scc_t *) & cpm2_immr->im_scc[3];
 331         cpm_uart_ports[UART_SCC4].sccup =
 332             (scc_uart_t *) & cpm2_immr->im_dprambase[PROFF_SCC4];
 333         cpm_uart_ports[UART_SCC4].port.mapbase =
 334             (unsigned long)&cpm2_immr->im_scc[3];
 335         cpm_uart_ports[UART_SCC4].sccp->scc_sccm &=
 336             ~(UART_SCCM_TX | UART_SCCM_RX);
 337         cpm_uart_ports[UART_SCC4].sccp->scc_gsmrl &=
 338             ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
 339         cpm_uart_ports[UART_SCC4].port.uartclk = (((bd_t *) __res)->bi_intfreq);
 340         cpm_uart_port_map[cpm_uart_nr++] = UART_SCC4;
 341 #endif
 342
 343         return 0;
 344 }