drivers/serial/sh-sci.c

   1 /*
   2  * drivers/serial/sh-sci.c
   3  *
   4  * SuperH on-chip serial module support.  (SCI with no FIFO / with FIFO)
   5  *
   6  *  Copyright (C) 2002, 2003  Paul Mundt
   7  *
   8  * based off of the old drivers/char/sh-sci.c by:
   9  *
  10  *   Copyright (C) 1999, 2000  Niibe Yutaka
  11  *   Copyright (C) 2000  Sugioka Toshinobu
  12  *   Modified to support multiple serial ports. Stuart Menefy (May 2000).
  13  *   Modified to support SecureEdge. David McCullough (2002)
  14  *   Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
  15  *
  16  * This file is subject to the terms and conditions of the GNU General Public
  17  * License.  See the file "COPYING" in the main directory of this archive
  18  * for more details.
  19  */
  20
  21 #define DEBUG
  22 #include <linux/config.h>
  23 #include <linux/module.h>
  24 #include <linux/errno.h>
  25 #include <linux/signal.h>
  26 #include <linux/sched.h>
  27 #include <linux/timer.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/tty.h>
  30 #include <linux/tty_flip.h>
  31 #include <linux/serial.h>
  32 #include <linux/major.h>
  33 #include <linux/string.h>
  34 #include <linux/sysrq.h>
  35 #include <linux/fcntl.h>
  36 #include <linux/ptrace.h>
  37 #include <linux/ioport.h>
  38 #include <linux/mm.h>
  39 #include <linux/slab.h>
  40 #include <linux/init.h>
  41 #include <linux/delay.h>
  42 #include <linux/console.h>
  43
  44 #ifdef CONFIG_CPU_FREQ
  45 #include <linux/notifier.h>
  46 #include <linux/cpufreq.h>
  47 #endif
  48
  49 #include <asm/system.h>
  50 #include <asm/io.h>
  51 #include <asm/irq.h>
  52 #include <asm/uaccess.h>
  53 #include <asm/bitops.h>
  54
  55 #include <linux/generic_serial.h>
  56
  57 #ifdef CONFIG_SH_STANDARD_BIOS
  58 #include <asm/sh_bios.h>
  59 #endif
  60
  61 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  62 #define SUPPORT_SYSRQ
  63 #endif
  64
  65 #include "sh-sci.h"
  66
  67 #ifdef CONFIG_SH_KGDB
  68 #include <asm/kgdb.h>
  69
  70 static int kgdb_get_char(struct sci_port *port);
  71 static void kgdb_put_char(struct sci_port *port, char c);
  72 static void kgdb_handle_error(struct sci_port *port);
  73 static struct sci_port *kgdb_sci_port;
  74 #endif /* CONFIG_SH_KGDB */
  75
  76 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
  77 static struct sci_port *serial_console_port = 0;
  78 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
  79
  80 /* Function prototypes */
  81 static void sci_stop_tx(struct uart_port *port, unsigned int tty_stop);
  82 static void sci_start_tx(struct uart_port *port, unsigned int tty_start);
  83 static void sci_start_rx(struct uart_port *port, unsigned int tty_start);
  84 static void sci_stop_rx(struct uart_port *port);
  85 static int sci_request_irq(struct sci_port *port);
  86 static void sci_free_irq(struct sci_port *port);
  87
  88 static struct sci_port sci_ports[SCI_NPORTS];
  89 static struct uart_driver sci_uart_driver;
  90
  91 #if defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB)
  92
  93 static void handle_error(struct uart_port *port)
  94 {                               /* Clear error flags */
  95         sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
  96 }
  97
  98 static int get_char(struct uart_port *port)
  99 {
 100         unsigned long flags;
 101         unsigned short status;
 102         int c;
 103
 104         local_irq_save(flags);
 105         do {
 106                 status = sci_in(port, SCxSR);
 107                 if (status & SCxSR_ERRORS(port)) {
 108                         handle_error(port);
 109                         continue;
 110                 }
 111         } while (!(status & SCxSR_RDxF(port)));
 112         c = sci_in(port, SCxRDR);
 113         sci_in(port, SCxSR);            /* Dummy read */
 114         sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
 115         local_irq_restore(flags);
 116
 117         return c;
 118 }
 119
 120 /* Taken from sh-stub.c of GDB 4.18 */
 121 static const char hexchars[] = "0123456789abcdef";
 122
 123 static __inline__ char highhex(int  x)
 124 {
 125         return hexchars[(x >> 4) & 0xf];
 126 }
 127
 128 static __inline__ char lowhex(int  x)
 129 {
 130         return hexchars[x & 0xf];
 131 }
 132
 133 #endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */
 134
 135 /*
 136  * Send the packet in buffer.  The host gets one chance to read it.
 137  * This routine does not wait for a positive acknowledge.
 138  */
 139
 140 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
 141 static void put_char(struct uart_port *port, char c)
 142 {
 143         unsigned long flags;
 144         unsigned short status;
 145
 146         local_irq_save(flags);
 147
 148         do {
 149                 status = sci_in(port, SCxSR);
 150         } while (!(status & SCxSR_TDxE(port)));
 151
 152         sci_out(port, SCxTDR, c);
 153         sci_in(port, SCxSR);            /* Dummy read */
 154         sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
 155
 156         local_irq_restore(flags);
 157 }
 158
 159 static void put_string(struct sci_port *sci_port, const char *buffer, int count)
 160 {
 161         struct uart_port *port = &sci_port->port;
 162         const unsigned char *p = buffer;
 163         int i;
 164
 165 #if defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB)
 166         int checksum;
 167         int usegdb=0;
 168
 169 #ifdef CONFIG_SH_STANDARD_BIOS
 170         /* This call only does a trap the first time it is
 171          * called, and so is safe to do here unconditionally
 172          */
 173         usegdb |= sh_bios_in_gdb_mode();
 174 #endif
 175 #ifdef CONFIG_SH_KGDB
 176         usegdb |= (kgdb_in_gdb_mode && (port == kgdb_sci_port));
 177 #endif
 178
 179         if (usegdb) {
 180             /*  $<packet info>#<checksum>. */
 181             do {
 182                 unsigned char c;
 183                 put_char(port, '$');
 184                 put_char(port, 'O'); /* 'O'utput to console */
 185                 checksum = 'O';
 186
 187                 for (i=0; i<count; i++) { /* Don't use run length encoding */
 188                         int h, l;
 189
 190                         c = *p++;
 191                         h = highhex(c);
 192                         l = lowhex(c);
 193                         put_char(port, h);
 194                         put_char(port, l);
 195                         checksum += h + l;
 196                 }
 197                 put_char(port, '#');
 198                 put_char(port, highhex(checksum));
 199                 put_char(port, lowhex(checksum));
 200             } while  (get_char(port) != '+');
 201         } else
 202 #endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */
 203         for (i=0; i<count; i++) {
 204                 if (*p == 10)
 205                         put_char(port, '\r');
 206                 put_char(port, *p++);
 207         }
 208 }
 209 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
 210
 211
 212 #ifdef CONFIG_SH_KGDB
 213
 214 /* Is the SCI ready, ie is there a char waiting? */
 215 static int kgdb_is_char_ready(struct sci_port *port)
 216 {
 217         unsigned short status = sci_in(port, SCxSR);
 218
 219         if (status & (SCxSR_ERRORS(port) | SCxSR_BRK(port)))
 220                 kgdb_handle_error(port);
 221
 222         return (status & SCxSR_RDxF(port));
 223 }
 224
 225 /* Write a char */
 226 static void kgdb_put_char(struct sci_port *port, char c)
 227 {
 228         unsigned short status;
 229
 230         do
 231                 status = sci_in(port, SCxSR);
 232         while (!(status & SCxSR_TDxE(port)));
 233
 234         sci_out(port, SCxTDR, c);
 235         sci_in(port, SCxSR);    /* Dummy read */
 236         sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
 237 }
 238
 239 /* Get a char if there is one, else ret -1 */
 240 static int kgdb_get_char(struct sci_port *port)
 241 {
 242         int c;
 243
 244         if (kgdb_is_char_ready(port) == 0)
 245                 c = -1;
 246         else {
 247                 c = sci_in(port, SCxRDR);
 248                 sci_in(port, SCxSR);    /* Dummy read */
 249                 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
 250         }
 251
 252         return c;
 253 }
 254
 255 /* Called from kgdbstub.c to get a character, i.e. is blocking */
 256 static int kgdb_sci_getchar(void)
 257 {
 258         volatile int c;
 259
 260         /* Keep trying to read a character, this could be neater */
 261         while ((c = kgdb_get_char(kgdb_sci_port)) < 0);
 262
 263         return c;
 264 }
 265
 266 /* Called from kgdbstub.c to put a character, just a wrapper */
 267 static void kgdb_sci_putchar(int c)
 268 {
 269
 270         kgdb_put_char(kgdb_sci_port, c);
 271 }
 272
 273 /* Clear any errors on the SCI */
 274 static void kgdb_handle_error(struct sci_port *port)
 275 {
 276         sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));  /* Clear error flags */
 277 }
 278
 279 /* Breakpoint if there's a break sent on the serial port */
 280 static void kgdb_break_interrupt(int irq, void *ptr, struct pt_regs *regs)
 281 {
 282         struct sci_port *port = ptr;
 283         unsigned short status = sci_in(port, SCxSR);
 284
 285         if (status & SCxSR_BRK(port)) {
 286
 287                 /* Break into the debugger if a break is detected */
 288                 BREAKPOINT();
 289
 290                 /* Clear */
 291                 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
 292         }
 293 }
 294
 295 #endif /* CONFIG_SH_KGDB */
 296
 297 #if defined(__H8300S__)
 298 enum { sci_disable, sci_enable };
 299
 300 static void h8300_sci_enable(struct uart_port* port, unsigned int ctrl)
 301 {
 302         volatile unsigned char *mstpcrl=(volatile unsigned char *)MSTPCRL;
 303         int ch = (port->mapbase  - SMR0) >> 3;
 304         unsigned char mask = 1 << (ch+1);
 305
 306         if (ctrl == sci_disable) {
 307                 *mstpcrl |= mask;
 308         } else {
 309                 *mstpcrl &= ~mask;
 310         }
 311 }
 312 #endif
 313
 314 #if defined(SCI_ONLY) || defined(SCI_AND_SCIF)
 315 #if defined(__H8300H__) || defined(__H8300S__)
 316 static void sci_init_pins_sci(struct uart_port* port, unsigned int cflag)
 317 {
 318         int ch = (port->mapbase - SMR0) >> 3;
 319
 320         /* set DDR regs */
 321         H8300_GPIO_DDR(h8300_sci_pins[ch].port,h8300_sci_pins[ch].rx,H8300_GPIO_INPUT);
 322         H8300_GPIO_DDR(h8300_sci_pins[ch].port,h8300_sci_pins[ch].tx,H8300_GPIO_OUTPUT);
 323         /* tx mark output*/
 324         H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
 325 }
 326 #else
 327 static void sci_init_pins_sci(struct uart_port *port, unsigned int cflag)
 328 {
 329 }
 330 #endif
 331 #endif
 332
 333 #if defined(SCIF_ONLY) || defined(SCI_AND_SCIF)
 334 #if defined(CONFIG_CPU_SH3)
 335 /* For SH7707, SH7709, SH7709A, SH7729, SH7300*/
 336 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
 337 {
 338         unsigned int fcr_val = 0;
 339 #if !defined(CONFIG_CPU_SUBTYPE_SH7300) /* SH7300 doesn't use RTS/CTS */
 340         {
 341                 unsigned short data;
 342
 343                 /* We need to set SCPCR to enable RTS/CTS */
 344                 data = ctrl_inw(SCPCR);
 345                 /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
 346                 ctrl_outw(data&0x0fcf, SCPCR);
 347         }
 348         if (cflag & CRTSCTS)
 349                 fcr_val |= SCFCR_MCE;
 350         else {
 351                 unsigned short data;
 352
 353                 /* We need to set SCPCR to enable RTS/CTS */
 354                 data = ctrl_inw(SCPCR);
 355                 /* Clear out SCP7MD1,0, SCP4MD1,0,
 356                    Set SCP6MD1,0 = {01} (output)  */
 357                 ctrl_outw((data&0x0fcf)|0x1000, SCPCR);
 358
 359                 data = ctrl_inb(SCPDR);
 360                 /* Set /RTS2 (bit6) = 0 */
 361                 ctrl_outb(data&0xbf, SCPDR);
 362         }
 363 #endif
 364         sci_out(port, SCFCR, fcr_val);
 365 }
 366
 367 static void sci_init_pins_irda(struct uart_port *port, unsigned int cflag)
 368 {
 369         unsigned int fcr_val = 0;
 370
 371         if (cflag & CRTSCTS)
 372                 fcr_val |= SCFCR_MCE;
 373
 374         sci_out(port, SCFCR, fcr_val);
 375 }
 376
 377 #else
 378
 379 /* For SH7750 */
 380 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
 381 {
 382         unsigned int fcr_val = 0;
 383
 384         if (cflag & CRTSCTS) {
 385                 fcr_val |= SCFCR_MCE;
 386         } else {
 387                 ctrl_outw(0x0080, SCSPTR2); /* Set RTS = 1 */
 388         }
 389         sci_out(port, SCFCR, fcr_val);
 390 }
 391
 392 #endif
 393 #endif /* SCIF_ONLY || SCI_AND_SCIF */
 394
 395 /* ********************************************************************** *
 396  *                   the interrupt related routines                       *
 397  * ********************************************************************** */
 398
 399 static void sci_transmit_chars(struct uart_port *port)
 400 {
 401         struct circ_buf *xmit = &port->info->xmit;
 402         unsigned int stopped = uart_tx_stopped(port);
 403         unsigned long flags;
 404         unsigned short status;
 405         unsigned short ctrl;
 406         int count, txroom;
 407
 408         status = sci_in(port, SCxSR);
 409         if (!(status & SCxSR_TDxE(port))) {
 410                 local_irq_save(flags);
 411                 ctrl = sci_in(port, SCSCR);
 412                 if (uart_circ_empty(xmit)) {
 413                         ctrl &= ~SCI_CTRL_FLAGS_TIE;
 414                 } else {
 415                         ctrl |= SCI_CTRL_FLAGS_TIE;
 416                 }
 417                 sci_out(port, SCSCR, ctrl);
 418                 local_irq_restore(flags);
 419                 return;
 420         }
 421
 422 #if !defined(SCI_ONLY)
 423         if (port->type == PORT_SCIF) {
 424                 txroom = SCIF_TXROOM_MAX - (sci_in(port, SCFDR)>>8);
 425         } else {
 426                 txroom = (sci_in(port, SCxSR) & SCI_TDRE)?1:0;
 427         }
 428 #else
 429         txroom = (sci_in(port, SCxSR) & SCI_TDRE)?1:0;
 430 #endif
 431
 432         count = txroom;
 433
 434         do {
 435                 unsigned char c;
 436
 437                 if (port->x_char) {
 438                         c = port->x_char;
 439                         port->x_char = 0;
 440                 } else if (!uart_circ_empty(xmit) && !stopped) {
 441                         c = xmit->buf[xmit->tail];
 442                         xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 443                 } else {
 444                         break;
 445                 }
 446
 447                 sci_out(port, SCxTDR, c);
 448
 449                 port->icount.tx++;
 450         } while (--count > 0);
 451
 452         sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
 453
 454         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 455                 uart_write_wakeup(port);
 456         if (uart_circ_empty(xmit)) {
 457                 sci_stop_tx(port, 0);
 458         } else {
 459                 local_irq_save(flags);
 460                 ctrl = sci_in(port, SCSCR);
 461
 462 #if !defined(SCI_ONLY)
 463                 if (port->type == PORT_SCIF) {
 464                         sci_in(port, SCxSR); /* Dummy read */
 465                         sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
 466                 }
 467 #endif
 468
 469                 ctrl |= SCI_CTRL_FLAGS_TIE;
 470                 sci_out(port, SCSCR, ctrl);
 471                 local_irq_restore(flags);
 472         }
 473 }
 474
 475 /* On SH3, SCIF may read end-of-break as a space->mark char */
 476 #define STEPFN(c)  ({int __c=(c); (((__c-1)|(__c)) == -1); })
 477
 478 static inline void sci_receive_chars(struct uart_port *port,
 479                                      struct pt_regs *regs)
 480 {
 481         struct tty_struct *tty = port->info->tty;
 482         int i, count, copied = 0;
 483         unsigned short status;
 484
 485         status = sci_in(port, SCxSR);
 486         if (!(status & SCxSR_RDxF(port)))
 487                 return;
 488
 489         while (1) {
 490 #if !defined(SCI_ONLY)
 491                 if (port->type == PORT_SCIF) {
 492                         count = sci_in(port, SCFDR)&SCIF_RFDC_MASK ;
 493                 } else {
 494                         count = (sci_in(port, SCxSR)&SCxSR_RDxF(port))?1:0;
 495                 }
 496 #else
 497                 count = (sci_in(port, SCxSR)&SCxSR_RDxF(port))?1:0;
 498 #endif
 499
 500                 /* Don't copy more bytes than there is room for in the buffer */
 501                 if (tty->flip.count + count > TTY_FLIPBUF_SIZE)
 502                         count = TTY_FLIPBUF_SIZE - tty->flip.count;
 503
 504                 /* If for any reason we can't copy more data, we're done! */
 505                 if (count == 0)
 506                         break;
 507
 508                 if (port->type == PORT_SCI) {
 509                         char c = sci_in(port, SCxRDR);
 510                        if(((struct sci_port *)port)->break_flag
 511                             || uart_handle_sysrq_char(port, c, regs)) {
 512                                 count = 0;
 513                         } else {
 514                             tty->flip.char_buf_ptr[0] = c;
 515                             tty->flip.flag_buf_ptr[0] = TTY_NORMAL;
 516                         }
 517                 } else {
 518                         for (i=0; i<count; i++) {
 519                                 char c = sci_in(port, SCxRDR);
 520                                 status = sci_in(port, SCxSR);
 521 #if defined(CONFIG_CPU_SH3)
 522                                 /* Skip "chars" during break */
 523                                 if (((struct sci_port *)port)->break_flag) {
 524                                         if ((c == 0) &&
 525                                             (status & SCxSR_FER(port))) {
 526                                                 count--; i--;
 527                                                 continue;
 528                                         }
 529                                         /* Nonzero => end-of-break */
 530                                         pr_debug("scif: debounce<%02x>\n", c);
 531                                         ((struct sci_port *)port)->break_flag = 0;
 532                                         if (STEPFN(c)) {
 533                                                 count--; i--;
 534                                                 continue;
 535                                         }
 536                                 }
 537 #endif /* CONFIG_CPU_SH3 */
 538                                 if (uart_handle_sysrq_char(port, c, regs)) {
 539                                         count--; i--;
 540                                         continue;
 541                                 }
 542
 543                                 /* Store data and status */
 544                                 tty->flip.char_buf_ptr[i] = c;
 545                                 if (status&SCxSR_FER(port)) {
 546                                         tty->flip.flag_buf_ptr[i] = TTY_FRAME;
 547                                         pr_debug("sci: frame error\n");
 548                                 } else if (status&SCxSR_PER(port)) {
 549                                         tty->flip.flag_buf_ptr[i] = TTY_PARITY;
 550                                         pr_debug("sci: parity error\n");
 551                                 } else {
 552                                         tty->flip.flag_buf_ptr[i] = TTY_NORMAL;
 553                                 }
 554                         }
 555                 }
 556
 557                 sci_in(port, SCxSR); /* dummy read */
 558                 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
 559
 560                 /* Update the kernel buffer end */
 561                 tty->flip.count += count;
 562                 tty->flip.char_buf_ptr += count;
 563                 tty->flip.flag_buf_ptr += count;
 564                 copied += count;
 565                 port->icount.rx += count;
 566         }
 567
 568         if (copied) {
 569                 /* Tell the rest of the system the news. New characters! */
 570                 tty_flip_buffer_push(tty);
 571         } else {
 572                 sci_in(port, SCxSR); /* dummy read */
 573                 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
 574         }
 575 }
 576
 577 #define SCI_BREAK_JIFFIES (HZ/20)
 578 /* The sci generates interrupts during the break,
 579  * 1 per millisecond or so during the break period, for 9600 baud.
 580  * So dont bother disabling interrupts.
 581  * But dont want more than 1 break event.
 582  * Use a kernel timer to periodically poll the rx line until
 583  * the break is finished.
 584  */
 585 static void sci_schedule_break_timer(struct sci_port *port)
 586 {
 587         port->break_timer.expires = jiffies + SCI_BREAK_JIFFIES;
 588         add_timer(&port->break_timer);
 589 }
 590 /* Ensure that two consecutive samples find the break over. */
 591 static void sci_break_timer(unsigned long data)
 592 {
 593     struct sci_port * port = (struct sci_port *)data;
 594         if(sci_rxd_in(&port->port) == 0) {
 595                 port->break_flag = 1;
 596             sci_schedule_break_timer(port);
 597         } else if(port->break_flag == 1){
 598                 /* break is over. */
 599                 port->break_flag = 2;
 600             sci_schedule_break_timer(port);
 601         } else port->break_flag = 0;
 602 }
 603
 604 static inline int sci_handle_errors(struct uart_port *port)
 605 {
 606         int copied = 0;
 607         unsigned short status = sci_in(port, SCxSR);
 608         struct tty_struct *tty = port->info->tty;
 609
 610         if (status&SCxSR_ORER(port) && tty->flip.count<TTY_FLIPBUF_SIZE) {
 611                 /* overrun error */
 612                 copied++;
 613                 *tty->flip.flag_buf_ptr++ = TTY_OVERRUN;
 614                 pr_debug("sci: overrun error\n");
 615         }
 616
 617         if (status&SCxSR_FER(port) && tty->flip.count<TTY_FLIPBUF_SIZE) {
 618                 if (sci_rxd_in(port) == 0) {
 619                         /* Notify of BREAK */
 620                         struct sci_port * sci_port = (struct sci_port *)port;
 621                        if(!sci_port->break_flag) {
 622                                 sci_port->break_flag = 1;
 623                                sci_schedule_break_timer((struct sci_port *)port);
 624                                 /* Do sysrq handling. */
 625                                 if(uart_handle_break(port)) {
 626                                         return 0;
 627                                 }
 628                                 pr_debug("sci: BREAK detected\n");
 629                                 copied++;
 630                                 *tty->flip.flag_buf_ptr++ = TTY_BREAK;
 631                        }
 632                 }
 633                 else {
 634                         /* frame error */
 635                         copied++;
 636                         *tty->flip.flag_buf_ptr++ = TTY_FRAME;
 637                         pr_debug("sci: frame error\n");
 638                 }
 639         }
 640
 641         if (status&SCxSR_PER(port) && tty->flip.count<TTY_FLIPBUF_SIZE) {
 642                 /* parity error */
 643                 copied++;
 644                 *tty->flip.flag_buf_ptr++ = TTY_PARITY;
 645                 pr_debug("sci: parity error\n");
 646         }
 647
 648         if (copied) {
 649                 tty->flip.count += copied;
 650                 tty_flip_buffer_push(tty);
 651         }
 652
 653         return copied;
 654 }
 655
 656 static inline int sci_handle_breaks(struct uart_port *port)
 657 {
 658         int copied = 0;
 659         unsigned short status = sci_in(port, SCxSR);
 660         struct tty_struct *tty = port->info->tty;
 661         struct sci_port *s = &sci_ports[port->line];
 662
 663         if (!s->break_flag && status & SCxSR_BRK(port) &&
 664             tty->flip.count < TTY_FLIPBUF_SIZE) {
 665 #if defined(CONFIG_CPU_SH3)
 666                 /* Debounce break */
 667                 s->break_flag = 1;
 668 #endif
 669                 /* Notify of BREAK */
 670                 copied++;
 671                 *tty->flip.flag_buf_ptr++ = TTY_BREAK;
 672                 pr_debug("sci: BREAK detected\n");
 673         }
 674
 675 #if defined(SCIF_ORER)
 676         /* XXX: Handle SCIF overrun error */
 677         if (port->type == PORT_SCIF && (sci_in(port, SCLSR) & SCIF_ORER) != 0) {
 678                 sci_out(port, SCLSR, 0);
 679                 if(tty->flip.count<TTY_FLIPBUF_SIZE) {
 680                         copied++;
 681                         *tty->flip.flag_buf_ptr++ = TTY_OVERRUN;
 682                         pr_debug("sci: overrun error\n");
 683                 }
 684         }
 685 #endif
 686
 687         if (copied) {
 688                 tty->flip.count += copied;
 689                 tty_flip_buffer_push(tty);
 690         }
 691
 692         return copied;
 693 }
 694
 695 static irqreturn_t sci_rx_interrupt(int irq, void *ptr, struct pt_regs *regs)
 696 {
 697         struct uart_port *port = ptr;
 698
 699         /* I think sci_receive_chars has to be called irrespective
 700          * of whether the I_IXOFF is set, otherwise, how is the interrupt
 701          * to be disabled?
 702          */
 703         sci_receive_chars(port, regs);
 704
 705         return IRQ_HANDLED;
 706 }
 707
 708 static irqreturn_t sci_tx_interrupt(int irq, void *ptr, struct pt_regs *regs)
 709 {
 710         struct uart_port *port = ptr;
 711
 712         sci_transmit_chars(port);
 713
 714         return IRQ_HANDLED;
 715 }
 716
 717 static irqreturn_t sci_er_interrupt(int irq, void *ptr, struct pt_regs *regs)
 718 {
 719         struct uart_port *port = ptr;
 720
 721         /* Handle errors */
 722         if (port->type == PORT_SCI) {
 723                 if (sci_handle_errors(port)) {
 724                         /* discard character in rx buffer */
 725                         sci_in(port, SCxSR);
 726                         sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
 727                 }
 728         } else {
 729 #if defined(SCIF_ORER)
 730                 if((sci_in(port, SCLSR) & SCIF_ORER) != 0) {
 731                         struct tty_struct *tty = port->info->tty;
 732
 733                         sci_out(port, SCLSR, 0);
 734                         if(tty->flip.count<TTY_FLIPBUF_SIZE) {
 735                                 *tty->flip.flag_buf_ptr++ = TTY_OVERRUN;
 736                                 tty->flip.count++;
 737                                 tty_flip_buffer_push(tty);
 738                                 pr_debug("scif: overrun error\n");
 739                         }
 740                 }
 741 #endif
 742                 sci_rx_interrupt(irq, ptr, regs);
 743         }
 744
 745         sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
 746
 747         /* Kick the transmission */
 748         sci_tx_interrupt(irq, ptr, regs);
 749
 750         return IRQ_HANDLED;
 751 }
 752
 753 static irqreturn_t sci_br_interrupt(int irq, void *ptr, struct pt_regs *regs)
 754 {
 755         struct uart_port *port = ptr;
 756
 757         /* Handle BREAKs */
 758         sci_handle_breaks(port);
 759         sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
 760
 761         return IRQ_HANDLED;
 762 }
 763
 764 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr, struct pt_regs *regs)
 765 {
 766         unsigned short ssr_status, scr_status;
 767         struct uart_port *port = ptr;
 768
 769         ssr_status = sci_in(port,SCxSR);
 770         scr_status = sci_in(port,SCSCR);
 771
 772         /* Tx Interrupt */
 773         if ((ssr_status&0x0020) && (scr_status&0x0080))
 774                 sci_tx_interrupt(irq, ptr, regs);
 775         /* Rx Interrupt */
 776         if ((ssr_status&0x0002) && (scr_status&0x0040))
 777                 sci_rx_interrupt(irq, ptr, regs);
 778         /* Error Interrupt */
 779         if ((ssr_status&0x0080) && (scr_status&0x0400))
 780                 sci_er_interrupt(irq, ptr, regs);
 781         /* Break Interrupt */
 782         if ((ssr_status&0x0010) && (scr_status&0x0200))
 783                 sci_br_interrupt(irq, ptr, regs);
 784
 785         return IRQ_HANDLED;
 786 }
 787
 788 #ifdef CONFIG_CPU_FREQ
 789 /*
 790  * Here we define a transistion notifier so that we can update all of our
 791  * ports' baud rate when the peripheral clock changes.
 792  */
 793 static int sci_notifier(struct notifier_block *self, unsigned long phase, void *p)
 794 {
 795         struct cpufreq_freqs *freqs = p;
 796         int i;
 797
 798         if ((phase == CPUFREQ_POSTCHANGE) ||
 799             (phase == CPUFREQ_RESUMECHANGE)){
 800                 for (i = 0; i < SCI_NPORTS; i++) {
 801                         struct uart_port *port = &sci_ports[i];
 802
 803                         /*
 804                          * Update the uartclk per-port if frequency has
 805                          * changed, since it will no longer necessarily be
 806                          * consistent with the old frequency.
 807                          *
 808                          * Really we want to be able to do something like
 809                          * uart_change_speed() or something along those lines
 810                          * here to implicitly reset the per-port baud rate..
 811                          *
 812                          * Clean this up later..
 813                          */
 814                         port->uartclk = current_cpu_data.module_clock * 16;
 815                 }
 816
 817                 printk("%s: got a postchange notification for cpu %d (old %d, new %d)\n",
 818                                 __FUNCTION__, freqs->cpu, freqs->old, freqs->new);
 819         }
 820
 821         return NOTIFY_OK;
 822 }
 823
 824 static struct notifier_block sci_nb = { &sci_notifier, NULL, 0 };
 825 #endif /* CONFIG_CPU_FREQ */
 826
 827 static int sci_request_irq(struct sci_port *port)
 828 {
 829         int i;
 830         irqreturn_t (*handlers[4])(int irq, void *ptr, struct pt_regs *regs) = {
 831                 sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt,
 832                 sci_br_interrupt,
 833         };
 834         const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full",
 835                                "SCI Transmit Data Empty", "SCI Break" };
 836
 837         if (port->irqs[0] == port->irqs[1]) {
 838                 if (!port->irqs[0]) {
 839                         printk(KERN_ERR "sci: Cannot allocate irq.(IRQ=0)\n");
 840                         return -ENODEV;
 841                 }
 842                 if (request_irq(port->irqs[0], sci_mpxed_interrupt, SA_INTERRUPT,
 843                                 "sci", port)) {
 844                         printk(KERN_ERR "sci: Cannot allocate irq.\n");
 845                         return -ENODEV;
 846                 }
 847         } else {
 848                 for (i = 0; i < ARRAY_SIZE(handlers); i++) {
 849                         if (!port->irqs[i])
 850                                 continue;
 851                         if (request_irq(port->irqs[i], handlers[i], SA_INTERRUPT,
 852                                         desc[i], port)) {
 853                                 printk(KERN_ERR "sci: Cannot allocate irq.\n");
 854                                 return -ENODEV;
 855                         }
 856                 }
 857         }
 858
 859         return 0;
 860 }
 861
 862 static void sci_free_irq(struct sci_port *port)
 863 {
 864         int i;
 865
 866         if (port->irqs[0] == port->irqs[1]) {
 867                 if (!port->irqs[0])
 868                         printk("sci: sci_free_irq error\n");
 869                 else
 870                         free_irq(port->irqs[0], port);
 871         } else {
 872                 for (i = 0; i < ARRAY_SIZE(port->irqs); i++) {
 873                         if (!port->irqs[i])
 874                                 continue;
 875
 876                         free_irq(port->irqs[i], port);
 877                 }
 878         }
 879 }
 880
 881 static unsigned int sci_tx_empty(struct uart_port *port)
 882 {
 883         /* Can't detect */
 884         return TIOCSER_TEMT;
 885 }
 886
 887 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
 888 {
 889         /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */
 890         /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */
 891         /* If you have signals for DTR and DCD, please implement here. */
 892 }
 893
 894 static unsigned int sci_get_mctrl(struct uart_port *port)
 895 {
 896         /* This routine is used for geting signals of: DTR, DCD, DSR, RI,
 897            and CTS/RTS */
 898
 899         return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR;
 900 }
 901
 902 static void sci_start_tx(struct uart_port *port, unsigned int tty_start)
 903 {
 904         struct sci_port *s = &sci_ports[port->line];
 905
 906         disable_irq(s->irqs[SCIx_TXI_IRQ]);
 907         sci_transmit_chars(port);
 908         enable_irq(s->irqs[SCIx_TXI_IRQ]);
 909 }
 910
 911 static void sci_stop_tx(struct uart_port *port, unsigned int tty_stop)
 912 {
 913         unsigned long flags;
 914         unsigned short ctrl;
 915
 916         /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
 917         local_irq_save(flags);
 918         ctrl = sci_in(port, SCSCR);
 919         ctrl &= ~SCI_CTRL_FLAGS_TIE;
 920         sci_out(port, SCSCR, ctrl);
 921         local_irq_restore(flags);
 922 }
 923
 924 static void sci_start_rx(struct uart_port *port, unsigned int tty_start)
 925 {
 926         unsigned long flags;
 927         unsigned short ctrl;
 928
 929         /* Set RIE (Receive Interrupt Enable) bit in SCSCR */
 930         local_irq_save(flags);
 931         ctrl = sci_in(port, SCSCR);
 932         ctrl |= SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE;
 933         sci_out(port, SCSCR, ctrl);
 934         local_irq_restore(flags);
 935 }
 936
 937 static void sci_stop_rx(struct uart_port *port)
 938 {
 939         unsigned long flags;
 940         unsigned short ctrl;
 941
 942         /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */
 943         local_irq_save(flags);
 944         ctrl = sci_in(port, SCSCR);
 945         ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE);
 946         sci_out(port, SCSCR, ctrl);
 947         local_irq_restore(flags);
 948 }
 949
 950 static void sci_enable_ms(struct uart_port *port)
 951 {
 952         /* Nothing here yet .. */
 953 }
 954
 955 static void sci_break_ctl(struct uart_port *port, int break_state)
 956 {
 957         /* Nothing here yet .. */
 958 }
 959
 960 static int sci_startup(struct uart_port *port)
 961 {
 962         struct sci_port *s = &sci_ports[port->line];
 963
 964 #if defined(__H8300S__)
 965         h8300_sci_enable(port, sci_enable);
 966 #endif
 967
 968         sci_request_irq(s);
 969         sci_start_tx(port, 1);
 970         sci_start_rx(port, 1);
 971
 972         return 0;
 973 }
 974
 975 static void sci_shutdown(struct uart_port *port)
 976 {
 977         struct sci_port *s = &sci_ports[port->line];
 978
 979         sci_stop_rx(port);
 980         sci_stop_tx(port, 1);
 981         sci_free_irq(s);
 982
 983 #if defined(__H8300S__)
 984         h8300_sci_enable(port, sci_disable);
 985 #endif
 986 }
 987
 988 static void sci_set_termios(struct uart_port *port, struct termios *termios,
 989                             struct termios *old)
 990 {
 991         struct sci_port *s = &sci_ports[port->line];
 992         unsigned int status, baud, smr_val;
 993         unsigned long flags;
 994         int t;
 995
 996         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
 997
 998         spin_lock_irqsave(&port->lock, flags);
 999
1000         do {
1001                 status = sci_in(port, SCxSR);
1002         } while (!(status & SCxSR_TEND(port)));
1003
1004         sci_out(port, SCSCR, 0x00);     /* TE=0, RE=0, CKE1=0 */
1005
1006 #if !defined(SCI_ONLY)
1007         if (port->type == PORT_SCIF) {
1008                 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1009         }
1010 #endif
1011
1012         smr_val = sci_in(port, SCSMR) & 3;
1013         if ((termios->c_cflag & CSIZE) == CS7)
1014                 smr_val |= 0x40;
1015         if (termios->c_cflag & PARENB)
1016                 smr_val |= 0x20;
1017         if (termios->c_cflag & PARODD)
1018                 smr_val |= 0x30;
1019         if (termios->c_cflag & CSTOPB)
1020                 smr_val |= 0x08;
1021
1022         uart_update_timeout(port, termios->c_cflag, baud);
1023
1024         sci_out(port, SCSMR, smr_val);
1025
1026         switch (baud) {
1027                 case 0:         t = -1;         break;
1028                 case 2400:      t = BPS_2400;   break;
1029                 case 4800:      t = BPS_4800;   break;
1030                 case 9600:      t = BPS_9600;   break;
1031                 case 19200:     t = BPS_19200;  break;
1032                 case 38400:     t = BPS_38400;  break;
1033                 case 57600:     t = BPS_57600;  break;
1034                 case 115200:    t = BPS_115200; break;
1035                 default:        t = SCBRR_VALUE(baud); break;
1036         }
1037
1038         if (t > 0) {
1039                 if(t >= 256) {
1040                         sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
1041                         t >>= 2;
1042                 } else {
1043                         sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3);
1044                 }
1045                 sci_out(port, SCBRR, t);
1046                 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1047         }
1048
1049         s->init_pins(port, termios->c_cflag);
1050         sci_out(port, SCSCR, SCSCR_INIT(port));
1051
1052         if ((termios->c_cflag & CREAD) != 0)
1053               sci_start_rx(port,0);
1054
1055         spin_unlock_irqrestore(&port->lock, flags);
1056 }
1057
1058 static const char *sci_type(struct uart_port *port)
1059 {
1060         switch (port->type) {
1061                 case PORT_SCI:  return "sci";
1062                 case PORT_SCIF: return "scif";
1063                 case PORT_IRDA: return "irda";
1064         }
1065
1066         return 0;
1067 }
1068
1069 static void sci_release_port(struct uart_port *port)
1070 {
1071         /* Nothing here yet .. */
1072 }
1073
1074 static int sci_request_port(struct uart_port *port)
1075 {
1076         /* Nothing here yet .. */
1077         return 0;
1078 }
1079
1080 static void sci_config_port(struct uart_port *port, int flags)
1081 {
1082         struct sci_port *s = &sci_ports[port->line];
1083
1084         port->type = s->type;
1085
1086 #if defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
1087         if (port->mapbase == 0)
1088                 port->mapbase = onchip_remap(SCIF_ADDR_SH5, 1024, "SCIF");
1089
1090         port->membase = (void *)port->mapbase;
1091 #endif
1092 }
1093
1094 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
1095 {
1096         struct sci_port *s = &sci_ports[port->line];
1097
1098         if (ser->irq != s->irqs[SCIx_TXI_IRQ] || ser->irq > NR_IRQS)
1099                 return -EINVAL;
1100         if (ser->baud_base < 2400)
1101                 /* No paper tape reader for Mitch.. */
1102                 return -EINVAL;
1103
1104         return 0;
1105 }
1106
1107 static struct uart_ops sci_uart_ops = {
1108         .tx_empty       = sci_tx_empty,
1109         .set_mctrl      = sci_set_mctrl,
1110         .get_mctrl      = sci_get_mctrl,
1111         .start_tx       = sci_start_tx,
1112         .stop_tx        = sci_stop_tx,
1113         .stop_rx        = sci_stop_rx,
1114         .enable_ms      = sci_enable_ms,
1115         .break_ctl      = sci_break_ctl,
1116         .startup        = sci_startup,
1117         .shutdown       = sci_shutdown,
1118         .set_termios    = sci_set_termios,
1119         .type           = sci_type,
1120         .release_port   = sci_release_port,
1121         .request_port   = sci_request_port,
1122         .config_port    = sci_config_port,
1123         .verify_port    = sci_verify_port,
1124 };
1125
1126 static struct sci_port sci_ports[SCI_NPORTS] = {
1127 #if defined(CONFIG_CPU_SUBTYPE_SH7708)
1128         {
1129                 .port   = {
1130                         .membase        = (void *)0xfffffe80,
1131                         .mapbase        = 0xfffffe80,
1132                         .iotype         = SERIAL_IO_MEM,
1133                         .irq            = 25,
1134                         .ops            = &sci_uart_ops,
1135                         .flags          = ASYNC_BOOT_AUTOCONF,
1136                         .line           = 0,
1137                 },
1138                 .type           = PORT_SCI,
1139                 .irqs           = SCI_IRQS,
1140                 .init_pins      = sci_init_pins_sci,
1141         },
1142 #elif defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
1143         {
1144                 .port   = {
1145                         .membase        = (void *)0xfffffe80,
1146                         .mapbase        = 0xfffffe80,
1147                         .iotype         = SERIAL_IO_MEM,
1148                         .irq            = 25,
1149                         .ops            = &sci_uart_ops,
1150                         .flags          = ASYNC_BOOT_AUTOCONF,
1151                         .line           = 0,
1152                 },
1153                 .type           = PORT_SCI,
1154                 .irqs           = SCI_IRQS,
1155                 .init_pins      = sci_init_pins_sci,
1156         },
1157         {
1158                 .port   = {
1159                         .membase        = (void *)0xa4000150,
1160                         .mapbase        = 0xa4000150,
1161                         .iotype         = SERIAL_IO_MEM,
1162                         .irq            = 59,
1163                         .ops            = &sci_uart_ops,
1164                         .flags          = ASYNC_BOOT_AUTOCONF,
1165                         .line           = 1,
1166                 },
1167                 .type           = PORT_SCIF,
1168                 .irqs           = SH3_SCIF_IRQS,
1169                 .init_pins      = sci_init_pins_scif,
1170         },
1171         {
1172                 .port   = {
1173                         .membase        = (void *)0xa4000140,
1174                         .mapbase        = 0xa4000140,
1175                         .iotype         = SERIAL_IO_MEM,
1176                         .irq            = 55,
1177                         .ops            = &sci_uart_ops,
1178                         .flags          = ASYNC_BOOT_AUTOCONF,
1179                         .line           = 2,
1180                 },
1181                 .type           = PORT_IRDA,
1182                 .irqs           = SH3_IRDA_IRQS,
1183                 .init_pins      = sci_init_pins_irda,
1184         }
1185 #elif defined(CONFIG_CPU_SUBTYPE_SH7300)
1186         {
1187                 .port   = {
1188                         .membase        = (void *)0xA4430000,
1189                         .mapbase        = 0xA4430000,
1190                         .iotype         = SERIAL_IO_MEM,
1191                         .irq            = 25,
1192                         .ops            = &sci_uart_ops,
1193                         .flags          = ASYNC_BOOT_AUTOCONF,
1194                         .line           = 0,
1195                 },
1196                 .type           = PORT_SCIF,
1197                 .irqs           = SH7300_SCIF0_IRQS,
1198                 .init_pins      = sci_init_pins_scif,
1199         },
1200 #elif defined(CONFIG_SH_RTS7751R2D)
1201         {
1202                 .port   = {
1203                         .membase        = (void *)0xffe80000,
1204                         .mapbase        = 0xffe80000,
1205                         .iotype         = SERIAL_IO_MEM,
1206                         .irq            = 43,
1207                         .ops            = &sci_uart_ops,
1208                         .flags          = ASYNC_BOOT_AUTOCONF,
1209                         .line           = 0,
1210                 },
1211                 .type           = PORT_SCIF,
1212                 .irqs           = SH4_SCIF_IRQS,
1213                 .init_pins      = sci_init_pins_scif,
1214         },
1215 #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751)
1216         {
1217                 .port   = {
1218                         .membase        = (void *)0xffe00000,
1219                         .mapbase        = 0xffe00000,
1220                         .iotype         = SERIAL_IO_MEM,
1221                         .irq            = 25,
1222                         .ops            = &sci_uart_ops,
1223                         .flags          = ASYNC_BOOT_AUTOCONF,
1224                         .line           = 0,
1225                 },
1226                 .type           = PORT_SCI,
1227                 .irqs           = SCI_IRQS,
1228                 .init_pins      = sci_init_pins_sci,
1229         },
1230         {
1231                 .port   = {
1232                         .membase        = (void *)0xffe80000,
1233                         .mapbase        = 0xffe80000,
1234                         .iotype         = SERIAL_IO_MEM,
1235                         .irq            = 43,
1236                         .ops            = &sci_uart_ops,
1237                         .flags          = ASYNC_BOOT_AUTOCONF,
1238                         .line           = 1,
1239                 },
1240                 .type           = PORT_SCIF,
1241                 .irqs           = SH4_SCIF_IRQS,
1242                 .init_pins      = sci_init_pins_scif,
1243         },
1244 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
1245         {
1246                 .port   = {
1247                         .membase        = (void *)0xfe600000,
1248                         .mapbase        = 0xfe600000,
1249                         .iotype         = SERIAL_IO_MEM,
1250                         .irq            = 55,
1251                         .ops            = &sci_uart_ops,
1252                         .flags          = ASYNC_BOOT_AUTOCONF,
1253                         .line           = 0,
1254                 },
1255                 .type           = PORT_SCIF,
1256                 .irqs           = SH7760_SCIF0_IRQS,
1257                 .init_pins      = sci_init_pins_scif,
1258         },
1259         {
1260                 .port   = {
1261                         .membase        = (void *)0xfe610000,
1262                         .mapbase        = 0xfe610000,
1263                         .iotype         = SERIAL_IO_MEM,
1264                         .irq            = 75,
1265                         .ops            = &sci_uart_ops,
1266                         .flags          = ASYNC_BOOT_AUTOCONF,
1267                         .line           = 1,
1268                 },
1269                 .type           = PORT_SCIF,
1270                 .irqs           = SH7760_SCIF1_IRQS,
1271                 .init_pins      = sci_init_pins_scif,
1272         },
1273         {
1274                 .port   = {
1275                         .membase        = (void *)0xfe620000,
1276                         .mapbase        = 0xfe620000,
1277                         .iotype         = SERIAL_IO_MEM,
1278                         .irq            = 79,
1279                         .ops            = &sci_uart_ops,
1280                         .flags          = ASYNC_BOOT_AUTOCONF,
1281                         .line           = 2,
1282                 },
1283                 .type           = PORT_SCIF,
1284                 .irqs           = SH7760_SCIF2_IRQS,
1285                 .init_pins      = sci_init_pins_scif,
1286         },
1287 #elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
1288         {
1289                 .port   = {
1290                         .membase        = (void *)0xffe00000,
1291                         .mapbase        = 0xffe00000,
1292                         .iotype         = SERIAL_IO_MEM,
1293                         .irq            = 26,
1294                         .ops            = &sci_uart_ops,
1295                         .flags          = ASYNC_BOOT_AUTOCONF,
1296                         .line           = 0,
1297                 },
1298                 .type           = PORT_SCIF,
1299                 .irqs           = STB1_SCIF1_IRQS,
1300                 .init_pins      = sci_init_pins_scif,
1301         },
1302         {
1303                 .port   = {
1304                         .membase        = (void *)0xffe80000,
1305                         .mapbase        = 0xffe80000,
1306                         .iotype         = SERIAL_IO_MEM,
1307                         .irq            = 43,
1308                         .ops            = &sci_uart_ops,
1309                         .flags          = ASYNC_BOOT_AUTOCONF,
1310                         .line           = 1,
1311                 },
1312                 .type           = PORT_SCIF,
1313                 .irqs           = SH4_SCIF_IRQS,
1314                 .init_pins      = sci_init_pins_scif,
1315         },
1316 #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
1317         {
1318                 .port   = {
1319                         .iotype         = SERIAL_IO_MEM,
1320                         .irq            = 42,
1321                         .ops            = &sci_uart_ops,
1322                         .flags          = ASYNC_BOOT_AUTOCONF,
1323                         .line           = 0,
1324                 },
1325                 .type           = PORT_SCIF,
1326                 .irqs           = SH5_SCIF_IRQS,
1327                 .init_pins      = sci_init_pins_scif,
1328         },
1329 #elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
1330         {
1331                 .port   = {
1332                         .membase        = (void *)0x00ffffb0,
1333                         .mapbase        = 0x00ffffb0,
1334                         .iotype         = SERIAL_IO_MEM,
1335                         .irq            = 54,
1336                         .ops            = &sci_uart_ops,
1337                         .flags          = ASYNC_BOOT_AUTOCONF,
1338                         .line           = 0,
1339                 },
1340                 .type           = PORT_SCI,
1341                 .irqs           = H8300H_SCI_IRQS0,
1342                 .init_pins      = sci_init_pins_sci,
1343         },
1344         {
1345                 .port   = {
1346                         .membase        = (void *)0x00ffffb8,
1347                         .mapbase        = 0x00ffffb8,
1348                         .iotype         = SERIAL_IO_MEM,
1349                         .irq            = 58,
1350                         .ops            = &sci_uart_ops,
1351                         .flags          = ASYNC_BOOT_AUTOCONF,
1352                         .line           = 1,
1353                 },
1354                 .type           = PORT_SCI,
1355                 .irqs           = H8300H_SCI_IRQS1,
1356                 .init_pins      = sci_init_pins_sci,
1357         },
1358         {
1359                 .port   = {
1360                         .membase        = (void *)0x00ffffc0,
1361                         .mapbase        = 0x00ffffc0,
1362                         .iotype         = SERIAL_IO_MEM,
1363                         .irq            = 62,
1364                         .ops            = &sci_uart_ops,
1365                         .flags          = ASYNC_BOOT_AUTOCONF,
1366                         .line           = 2,
1367                 },
1368                 .type           = PORT_SCI,
1369                 .irqs           = H8300H_SCI_IRQS2,
1370                 .init_pins      = sci_init_pins_sci,
1371         },
1372 #elif defined(CONFIG_H8S2678)
1373         {
1374                 .port   = {
1375                         .membase        = (void *)0x00ffff78,
1376                         .mapbase        = 0x00ffff78,
1377                         .iotype         = SERIAL_IO_MEM,
1378                         .irq            = 90,
1379                         .ops            = &sci_uart_ops,
1380                         .flags          = ASYNC_BOOT_AUTOCONF,
1381                         .line           = 0,
1382                 },
1383                 .type           = PORT_SCI,
1384                 .irqs           = H8S_SCI_IRQS0,
1385                 .init_pins      = sci_init_pins_sci,
1386         },
1387         {
1388                 .port   = {
1389                         .membase        = (void *)0x00ffff80,
1390                         .mapbase        = 0x00ffff80,
1391                         .iotype         = SERIAL_IO_MEM,
1392                         .irq            = 94,
1393                         .ops            = &sci_uart_ops,
1394                         .flags          = ASYNC_BOOT_AUTOCONF,
1395                         .line           = 1,
1396                 },
1397                 .type           = PORT_SCI,
1398                 .irqs           = H8S_SCI_IRQS1,
1399                 .init_pins      = sci_init_pins_sci,
1400         },
1401         {
1402                 .port   = {
1403                         .membase        = (void *)0x00ffff88,
1404                         .mapbase        = 0x00ffff88,
1405                         .iotype         = SERIAL_IO_MEM,
1406                         .irq            = 98,
1407                         .ops            = &sci_uart_ops,
1408                         .flags          = ASYNC_BOOT_AUTOCONF,
1409                         .line           = 2,
1410                 },
1411                 .type           = PORT_SCI,
1412                 .irqs           = H8S_SCI_IRQS2,
1413                 .init_pins      = sci_init_pins_sci,
1414         },
1415 #else
1416 #error "CPU subtype not defined"
1417 #endif
1418 };
1419
1420 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1421 /*
1422  *      Print a string to the serial port trying not to disturb
1423  *      any possible real use of the port...
1424  */
1425 static void serial_console_write(struct console *co, const char *s,
1426                                  unsigned count)
1427 {
1428         put_string(serial_console_port, s, count);
1429 }
1430
1431 static int __init serial_console_setup(struct console *co, char *options)
1432 {
1433         struct uart_port *port;
1434         int baud = 115200;
1435         int bits = 8;
1436         int parity = 'n';
1437         int flow = 'n';
1438         int ret;
1439
1440         if (co->index >= SCI_NPORTS)
1441                 co->index = 0;
1442
1443         serial_console_port = &sci_ports[co->index];
1444         port = &serial_console_port->port;
1445         port->type = serial_console_port->type;
1446
1447 #ifdef CONFIG_SUPERH64
1448         /* This is especially needed on sh64 to remap the SCIF */
1449         sci_config_port(port, 0);
1450 #endif
1451
1452         /*
1453          * We need to set the initial uartclk here, since otherwise it will
1454          * only ever be setup at sci_init() time.
1455          */
1456 #if !defined(__H8300H__) && !defined(__H8300S__)
1457         port->uartclk = current_cpu_data.module_clock * 16;
1458 #else
1459         port->uartclk = CONFIG_CPU_CLOCK;
1460 #endif
1461 #if defined(__H8300S__)
1462         h8300_sci_enable(port, sci_enable);
1463 #endif
1464         if (options)
1465                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1466
1467         ret = uart_set_options(port, co, baud, parity, bits, flow);
1468 #if defined(__H8300H__) || defined(__H8300S__)
1469         /* disable rx interrupt */
1470         if (ret == 0)
1471                 sci_stop_rx(port);
1472 #endif
1473         return ret;
1474 }
1475
1476 static struct console serial_console = {
1477         .name           = "ttySC",
1478         .device         = uart_console_device,
1479         .write          = serial_console_write,
1480         .setup          = serial_console_setup,
1481         .flags          = CON_PRINTBUFFER,
1482         .index          = -1,
1483         .data           = &sci_uart_driver,
1484 };
1485
1486 static int __init sci_console_init(void)
1487 {
1488         register_console(&serial_console);
1489         return 0;
1490 }
1491
1492 console_initcall(sci_console_init);
1493 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1494
1495 #ifdef CONFIG_SH_KGDB
1496 /*
1497  * FIXME: Most of this can go away.. at the moment, we rely on
1498  * arch/sh/kernel/setup.c to do the command line parsing for kgdb, though
1499  * most of that can easily be done here instead.
1500  *
1501  * For the time being, just accept the values that were parsed earlier..
1502  */
1503 static void __init kgdb_console_get_options(struct uart_port *port, int *baud,
1504                                             int *parity, int *bits)
1505 {
1506         *baud = kgdb_baud;
1507         *parity = tolower(kgdb_parity);
1508         *bits = kgdb_bits - '0';
1509 }
1510
1511 /*
1512  * The naming here is somewhat misleading, since kgdb_console_setup() takes
1513  * care of the early-on initialization for kgdb, regardless of whether we
1514  * actually use kgdb as a console or not.
1515  *
1516  * On the plus side, this lets us kill off the old kgdb_sci_setup() nonsense.
1517  */
1518 int __init kgdb_console_setup(struct console *co, char *options)
1519 {
1520         struct uart_port *port = &sci_ports[kgdb_portnum].port;
1521         int baud = 38400;
1522         int bits = 8;
1523         int parity = 'n';
1524         int flow = 'n';
1525
1526         if (co->index >= SCI_NPORTS || co->index != kgdb_portnum)
1527                 co->index = kgdb_portnum;
1528
1529         if (options)
1530                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1531         else
1532                 kgdb_console_get_options(port, &baud, &parity, &bits);
1533
1534         kgdb_getchar = kgdb_sci_getchar;
1535         kgdb_putchar = kgdb_sci_putchar;
1536
1537         return uart_set_options(port, co, baud, parity, bits, flow);
1538 }
1539 #endif /* CONFIG_SH_KGDB */
1540
1541 #ifdef CONFIG_SH_KGDB_CONSOLE
1542 static struct console kgdb_console = {
1543         .name           = "ttySC",
1544         .write          = kgdb_console_write,
1545         .setup          = kgdb_console_setup,
1546         .flags          = CON_PRINTBUFFER | CON_ENABLED,
1547         .index          = -1,
1548         .data           = &sci_uart_driver,
1549 };
1550
1551 /* Register the KGDB console so we get messages (d'oh!) */
1552 static int __init kgdb_console_init(void)
1553 {
1554         register_console(&kgdb_console);
1555         return 0;
1556 }
1557
1558 console_initcall(kgdb_console_init);
1559 #endif /* CONFIG_SH_KGDB_CONSOLE */
1560
1561 #if defined(CONFIG_SH_KGDB_CONSOLE)
1562 #define SCI_CONSOLE     &kgdb_console
1563 #elif defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1564 #define SCI_CONSOLE     &serial_console
1565 #else
1566 #define SCI_CONSOLE     0
1567 #endif
1568
1569 static char banner[] __initdata =
1570         KERN_INFO "SuperH SCI(F) driver initialized\n";
1571
1572 static struct uart_driver sci_uart_driver = {
1573         .owner          = THIS_MODULE,
1574         .driver_name    = "sci",
1575 #ifdef CONFIG_DEVFS_FS
1576         .devfs_name     = "ttsc/",
1577 #endif
1578         .dev_name       = "ttySC",
1579         .major          = SCI_MAJOR,
1580         .minor          = SCI_MINOR_START,
1581         .nr             = SCI_NPORTS,
1582         .cons           = SCI_CONSOLE,
1583 };
1584
1585 static int __init sci_init(void)
1586 {
1587         int chan, ret;
1588
1589         printk("%s", banner);
1590
1591         ret = uart_register_driver(&sci_uart_driver);
1592         if (ret == 0) {
1593                 for (chan = 0; chan < SCI_NPORTS; chan++) {
1594                         struct sci_port *sciport = &sci_ports[chan];
1595
1596 #if !defined(__H8300H__) && !defined(__H8300S__)
1597                         sciport->port.uartclk = (current_cpu_data.module_clock * 16);
1598 #else
1599                         sciport->port.uartclk = CONFIG_CPU_CLOCK;
1600 #endif
1601                         uart_add_one_port(&sci_uart_driver, &sciport->port);
1602                         sciport->break_timer.data = (unsigned long)sciport;
1603                         sciport->break_timer.function = sci_break_timer;
1604                         init_timer(&sciport->break_timer);
1605                 }
1606         }
1607
1608 #ifdef CONFIG_CPU_FREQ
1609         cpufreq_register_notifier(&sci_nb, CPUFREQ_TRANSITION_NOTIFIER);
1610         printk("sci: CPU frequency notifier registered\n");
1611 #endif
1612
1613 #ifdef CONFIG_SH_STANDARD_BIOS
1614         sh_bios_gdb_detach();
1615 #endif
1616
1617         return ret;
1618 }
1619
1620 static void __exit sci_exit(void)
1621 {
1622         int chan;
1623
1624         for (chan = 0; chan < SCI_NPORTS; chan++)
1625                 uart_remove_one_port(&sci_uart_driver, &sci_ports[chan].port);
1626
1627         uart_unregister_driver(&sci_uart_driver);
1628 }
1629
1630 module_init(sci_init);
1631 module_exit(sci_exit);
1632