drivers/serial/sh-sci.c

   1 /*
   2  * drivers/serial/sh-sci.c
   3  *
   4  * SuperH on-chip serial module support.  (SCI with no FIFO / with FIFO)
   5  *
   6  *  Copyright (C) 2002, 2003  Paul Mundt
   7  *
   8  * based off of the old drivers/char/sh-sci.c by:
   9  *
  10  *   Copyright (C) 1999, 2000  Niibe Yutaka
  11  *   Copyright (C) 2000  Sugioka Toshinobu
  12  *   Modified to support multiple serial ports. Stuart Menefy (May 2000).
  13  *   Modified to support SecureEdge. David McCullough (2002)
  14  *   Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
  15  *
  16  * This file is subject to the terms and conditions of the GNU General Public
  17  * License.  See the file "COPYING" in the main directory of this archive
  18  * for more details.
  19  */
  20
  21 #define DEBUG
  22 #include <linux/config.h>
  23 #include <linux/module.h>
  24 #include <linux/errno.h>
  25 #include <linux/signal.h>
  26 #include <linux/sched.h>
  27 #include <linux/timer.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/tty.h>
  30 #include <linux/tty_flip.h>
  31 #include <linux/serial.h>
  32 #include <linux/major.h>
  33 #include <linux/string.h>
  34 #include <linux/sysrq.h>
  35 #include <linux/fcntl.h>
  36 #include <linux/ptrace.h>
  37 #include <linux/ioport.h>
  38 #include <linux/mm.h>
  39 #include <linux/slab.h>
  40 #include <linux/init.h>
  41 #include <linux/delay.h>
  42 #include <linux/console.h>
  43
  44 #ifdef CONFIG_CPU_FREQ
  45 #include <linux/notifier.h>
  46 #include <linux/cpufreq.h>
  47 #endif
  48
  49 #include <asm/system.h>
  50 #include <asm/io.h>
  51 #include <asm/irq.h>
  52 #include <asm/uaccess.h>
  53 #include <asm/bitops.h>
  54
  55 #include <linux/generic_serial.h>
  56
  57 #ifdef CONFIG_SH_STANDARD_BIOS
  58 #include <asm/sh_bios.h>
  59 #endif
  60
  61 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  62 #define SUPPORT_SYSRQ
  63 #endif
  64
  65 #include "sh-sci.h"
  66
  67 #ifdef CONFIG_SH_KGDB
  68 #include <asm/kgdb.h>
  69
  70 static int kgdb_get_char(struct sci_port *port);
  71 static void kgdb_put_char(struct sci_port *port, char c);
  72 static void kgdb_handle_error(struct sci_port *port);
  73 static struct sci_port *kgdb_sci_port;
  74 #endif /* CONFIG_SH_KGDB */
  75
  76 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
  77 static struct sci_port *serial_console_port = 0;
  78 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
  79
  80 /* Function prototypes */
  81 static void sci_stop_tx(struct uart_port *port, unsigned int tty_stop);
  82 static void sci_start_tx(struct uart_port *port, unsigned int tty_start);
  83 static void sci_start_rx(struct uart_port *port, unsigned int tty_start);
  84 static void sci_stop_rx(struct uart_port *port);
  85 static int sci_request_irq(struct sci_port *port);
  86 static void sci_free_irq(struct sci_port *port);
  87
  88 static struct sci_port sci_ports[SCI_NPORTS];
  89 static struct uart_driver sci_uart_driver;
  90
  91 #if defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB)
  92
  93 static void handle_error(struct sci_port *port)
  94 {                               /* Clear error flags */
  95         sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
  96 }
  97
  98 static int get_char(struct sci_port *port)
  99 {
 100         unsigned long flags;
 101         unsigned short status;
 102         int c;
 103
 104         local_irq_save(flags);
 105         do {
 106                 status = sci_in(port, SCxSR);
 107                 if (status & SCxSR_ERRORS(port)) {
 108                         handle_error(port);
 109                         continue;
 110                 }
 111         } while (!(status & SCxSR_RDxF(port)));
 112         c = sci_in(port, SCxRDR);
 113         sci_in(port, SCxSR);            /* Dummy read */
 114         sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
 115         local_irq_restore(flags);
 116
 117         return c;
 118 }
 119
 120 /* Taken from sh-stub.c of GDB 4.18 */
 121 static const char hexchars[] = "0123456789abcdef";
 122
 123 static __inline__ char highhex(int  x)
 124 {
 125         return hexchars[(x >> 4) & 0xf];
 126 }
 127
 128 static __inline__ char lowhex(int  x)
 129 {
 130         return hexchars[x & 0xf];
 131 }
 132
 133 #endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */
 134
 135 /*
 136  * Send the packet in buffer.  The host gets one chance to read it.
 137  * This routine does not wait for a positive acknowledge.
 138  */
 139
 140 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
 141 static void put_char(struct uart_port *port, char c)
 142 {
 143         unsigned long flags;
 144         unsigned short status;
 145
 146         local_irq_save(flags);
 147
 148         do {
 149                 status = sci_in(port, SCxSR);
 150         } while (!(status & SCxSR_TDxE(port)));
 151
 152         sci_out(port, SCxTDR, c);
 153         sci_in(port, SCxSR);            /* Dummy read */
 154         sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
 155
 156         local_irq_restore(flags);
 157 }
 158
 159 static void put_string(struct sci_port *sci_port, const char *buffer, int count)
 160 {
 161         struct uart_port *port = &sci_port->port;
 162         const unsigned char *p = buffer;
 163         int i;
 164
 165 #if defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB)
 166         int checksum;
 167         int usegdb=0;
 168
 169 #ifdef CONFIG_SH_STANDARD_BIOS
 170         /* This call only does a trap the first time it is
 171          * called, and so is safe to do here unconditionally
 172          */
 173         usegdb |= sh_bios_in_gdb_mode();
 174 #endif
 175 #ifdef CONFIG_SH_KGDB
 176         usegdb |= (kgdb_in_gdb_mode && (port == kgdb_sci_port));
 177 #endif
 178
 179         if (usegdb) {
 180             /*  $<packet info>#<checksum>. */
 181             do {
 182                 unsigned char c;
 183                 put_char(port, '$');
 184                 put_char(port, 'O'); /* 'O'utput to console */
 185                 checksum = 'O';
 186
 187                 for (i=0; i<count; i++) { /* Don't use run length encoding */
 188                         int h, l;
 189
 190                         c = *p++;
 191                         h = highhex(c);
 192                         l = lowhex(c);
 193                         put_char(port, h);
 194                         put_char(port, l);
 195                         checksum += h + l;
 196                 }
 197                 put_char(port, '#');
 198                 put_char(port, highhex(checksum));
 199                 put_char(port, lowhex(checksum));
 200             } while  (get_char(port) != '+');
 201         } else
 202 #endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */
 203         for (i=0; i<count; i++) {
 204                 if (*p == 10)
 205                         put_char(port, '\r');
 206                 put_char(port, *p++);
 207         }
 208 }
 209 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
 210
 211
 212 #ifdef CONFIG_SH_KGDB
 213
 214 /* Is the SCI ready, ie is there a char waiting? */
 215 static int kgdb_is_char_ready(struct sci_port *port)
 216 {
 217         unsigned short status = sci_in(port, SCxSR);
 218
 219         if (status & (SCxSR_ERRORS(port) | SCxSR_BRK(port)))
 220                 kgdb_handle_error(port);
 221
 222         return (status & SCxSR_RDxF(port));
 223 }
 224
 225 /* Write a char */
 226 static void kgdb_put_char(struct sci_port *port, char c)
 227 {
 228         unsigned short status;
 229
 230         do
 231                 status = sci_in(port, SCxSR);
 232         while (!(status & SCxSR_TDxE(port)));
 233
 234         sci_out(port, SCxTDR, c);
 235         sci_in(port, SCxSR);    /* Dummy read */
 236         sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
 237 }
 238
 239 /* Get a char if there is one, else ret -1 */
 240 static int kgdb_get_char(struct sci_port *port)
 241 {
 242         int c;
 243
 244         if (kgdb_is_char_ready(port) == 0)
 245                 c = -1;
 246         else {
 247                 c = sci_in(port, SCxRDR);
 248                 sci_in(port, SCxSR);    /* Dummy read */
 249                 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
 250         }
 251
 252         return c;
 253 }
 254
 255 /* Called from kgdbstub.c to get a character, i.e. is blocking */
 256 static int kgdb_sci_getchar(void)
 257 {
 258         volatile int c;
 259
 260         /* Keep trying to read a character, this could be neater */
 261         while ((c = kgdb_get_char(kgdb_sci_port)) < 0);
 262
 263         return c;
 264 }
 265
 266 /* Called from kgdbstub.c to put a character, just a wrapper */
 267 static void kgdb_sci_putchar(int c)
 268 {
 269
 270         kgdb_put_char(kgdb_sci_port, c);
 271 }
 272
 273 /* Clear any errors on the SCI */
 274 static void kgdb_handle_error(struct sci_port *port)
 275 {
 276         sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));  /* Clear error flags */
 277 }
 278
 279 /* Breakpoint if there's a break sent on the serial port */
 280 static void kgdb_break_interrupt(int irq, void *ptr, struct pt_regs *regs)
 281 {
 282         struct sci_port *port = ptr;
 283         unsigned short status = sci_in(port, SCxSR);
 284
 285         if (status & SCxSR_BRK(port)) {
 286
 287                 /* Break into the debugger if a break is detected */
 288                 BREAKPOINT();
 289
 290                 /* Clear */
 291                 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
 292         }
 293 }
 294
 295 #endif /* CONFIG_SH_KGDB */
 296
 297 #if defined(__H8300S__)
 298 enum { sci_disable, sci_enable };
 299
 300 static void h8300_sci_enable(struct uart_port* port, unsigned int ctrl)
 301 {
 302         volatile unsigned char *mstpcrl=(volatile unsigned char *)MSTPCRL;
 303         int ch = (port->mapbase  - SMR0) >> 3;
 304         unsigned char mask = 1 << (ch+1);
 305
 306         if (ctrl == sci_disable) {
 307                 *mstpcrl |= mask;
 308         } else {
 309                 *mstpcrl &= ~mask;
 310         }
 311 }
 312 #endif
 313
 314 #if defined(SCI_ONLY) || defined(SCI_AND_SCIF)
 315 #if defined(__H8300H__) || defined(__H8300S__)
 316 static void sci_init_pins_sci(struct uart_port* port, unsigned int cflag)
 317 {
 318         int ch = (port->mapbase - SMR0) >> 3;
 319
 320         /* set DDR regs */
 321         H8300_GPIO_DDR(h8300_sci_pins[ch].port,h8300_sci_pins[ch].rx,H8300_GPIO_INPUT);
 322         H8300_GPIO_DDR(h8300_sci_pins[ch].port,h8300_sci_pins[ch].tx,H8300_GPIO_OUTPUT);
 323         /* tx mark output*/
 324         H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
 325 }
 326 #else
 327 static void sci_init_pins_sci(struct uart_port *port, unsigned int cflag)
 328 {
 329 }
 330 #endif
 331 #endif
 332
 333 #if defined(SCIF_ONLY) || defined(SCI_AND_SCIF)
 334 #if defined(CONFIG_CPU_SH3)
 335 /* For SH7707, SH7709, SH7709A, SH7729 */
 336 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
 337 {
 338         unsigned int fcr_val = 0;
 339
 340         {
 341                 unsigned short data;
 342
 343                 /* We need to set SCPCR to enable RTS/CTS */
 344                 data = ctrl_inw(SCPCR);
 345                 /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
 346                 ctrl_outw(data&0x0fcf, SCPCR);
 347         }
 348         if (cflag & CRTSCTS)
 349                 fcr_val |= SCFCR_MCE;
 350         else {
 351                 unsigned short data;
 352
 353                 /* We need to set SCPCR to enable RTS/CTS */
 354                 data = ctrl_inw(SCPCR);
 355                 /* Clear out SCP7MD1,0, SCP4MD1,0,
 356                    Set SCP6MD1,0 = {01} (output)  */
 357                 ctrl_outw((data&0x0fcf)|0x1000, SCPCR);
 358
 359                 data = ctrl_inb(SCPDR);
 360                 /* Set /RTS2 (bit6) = 0 */
 361                 ctrl_outb(data&0xbf, SCPDR);
 362         }
 363         sci_out(port, SCFCR, fcr_val);
 364 }
 365
 366 static void sci_init_pins_irda(struct uart_port *port, unsigned int cflag)
 367 {
 368         unsigned int fcr_val = 0;
 369
 370         if (cflag & CRTSCTS)
 371                 fcr_val |= SCFCR_MCE;
 372
 373         sci_out(port, SCFCR, fcr_val);
 374 }
 375
 376 #else
 377
 378 /* For SH7750 */
 379 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
 380 {
 381         unsigned int fcr_val = 0;
 382
 383         if (cflag & CRTSCTS) {
 384                 fcr_val |= SCFCR_MCE;
 385         } else {
 386                 ctrl_outw(0x0080, SCSPTR2); /* Set RTS = 1 */
 387         }
 388         sci_out(port, SCFCR, fcr_val);
 389 }
 390
 391 #endif
 392 #endif /* SCIF_ONLY || SCI_AND_SCIF */
 393
 394 /* ********************************************************************** *
 395  *                   the interrupt related routines                       *
 396  * ********************************************************************** */
 397
 398 static void sci_transmit_chars(struct uart_port *port)
 399 {
 400         struct circ_buf *xmit = &port->info->xmit;
 401         unsigned int stopped = uart_tx_stopped(port);
 402         unsigned long flags;
 403         unsigned short status;
 404         unsigned short ctrl;
 405         int count, txroom;
 406
 407         status = sci_in(port, SCxSR);
 408         if (!(status & SCxSR_TDxE(port))) {
 409                 local_irq_save(flags);
 410                 ctrl = sci_in(port, SCSCR);
 411                 if (uart_circ_empty(xmit)) {
 412                         ctrl &= ~SCI_CTRL_FLAGS_TIE;
 413                 } else {
 414                         ctrl |= SCI_CTRL_FLAGS_TIE;
 415                 }
 416                 sci_out(port, SCSCR, ctrl);
 417                 local_irq_restore(flags);
 418                 return;
 419         }
 420
 421 #if !defined(SCI_ONLY)
 422         if (port->type == PORT_SCIF) {
 423                 txroom = 16 - (sci_in(port, SCFDR)>>8);
 424         } else {
 425                 txroom = (sci_in(port, SCxSR) & SCI_TDRE)?1:0;
 426         }
 427 #else
 428         txroom = (sci_in(port, SCxSR) & SCI_TDRE)?1:0;
 429 #endif
 430
 431         count = txroom;
 432
 433         do {
 434                 unsigned char c;
 435
 436                 if (port->x_char) {
 437                         c = port->x_char;
 438                         port->x_char = 0;
 439                 } else if (!uart_circ_empty(xmit) && !stopped) {
 440                         c = xmit->buf[xmit->tail];
 441                         xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 442                 } else {
 443                         break;
 444                 }
 445
 446                 sci_out(port, SCxTDR, c);
 447
 448                 port->icount.tx++;
 449         } while (--count > 0);
 450
 451         sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
 452
 453         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 454                 uart_write_wakeup(port);
 455         if (uart_circ_empty(xmit)) {
 456                 sci_stop_tx(port, 0);
 457         } else {
 458                 local_irq_save(flags);
 459                 ctrl = sci_in(port, SCSCR);
 460
 461 #if !defined(SCI_ONLY)
 462                 if (port->type == PORT_SCIF) {
 463                         sci_in(port, SCxSR); /* Dummy read */
 464                         sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
 465                 }
 466 #endif
 467
 468                 ctrl |= SCI_CTRL_FLAGS_TIE;
 469                 sci_out(port, SCSCR, ctrl);
 470                 local_irq_restore(flags);
 471         }
 472 }
 473
 474 /* On SH3, SCIF may read end-of-break as a space->mark char */
 475 #define STEPFN(c)  ({int __c=(c); (((__c-1)|(__c)) == -1); })
 476
 477 static inline void sci_receive_chars(struct uart_port *port,
 478                                      struct pt_regs *regs)
 479 {
 480         struct tty_struct *tty = port->info->tty;
 481         int i, count, copied = 0;
 482         unsigned short status;
 483
 484         status = sci_in(port, SCxSR);
 485         if (!(status & SCxSR_RDxF(port)))
 486                 return;
 487
 488         while (1) {
 489 #if !defined(SCI_ONLY)
 490                 if (port->type == PORT_SCIF) {
 491                         count = sci_in(port, SCFDR)&0x001f;
 492                 } else {
 493                         count = (sci_in(port, SCxSR)&SCxSR_RDxF(port))?1:0;
 494                 }
 495 #else
 496                 count = (sci_in(port, SCxSR)&SCxSR_RDxF(port))?1:0;
 497 #endif
 498
 499                 /* Don't copy more bytes than there is room for in the buffer */
 500                 if (tty->flip.count + count > TTY_FLIPBUF_SIZE)
 501                         count = TTY_FLIPBUF_SIZE - tty->flip.count;
 502
 503                 /* If for any reason we can't copy more data, we're done! */
 504                 if (count == 0)
 505                         break;
 506
 507                 if (port->type == PORT_SCI) {
 508                         char c = sci_in(port, SCxRDR);
 509                        if(((struct sci_port *)port)->break_flag
 510                             || uart_handle_sysrq_char(port, c, regs)) {
 511                                 count = 0;
 512                         } else {
 513                             tty->flip.char_buf_ptr[0] = c;
 514                             tty->flip.flag_buf_ptr[0] = TTY_NORMAL;
 515                         }
 516                 } else {
 517                         for (i=0; i<count; i++) {
 518                                 char c = sci_in(port, SCxRDR);
 519                                 status = sci_in(port, SCxSR);
 520 #if defined(CONFIG_CPU_SH3)
 521                                 /* Skip "chars" during break */
 522                                 if (((struct sci_port *)port)->break_flag) {
 523                                         if ((c == 0) &&
 524                                             (status & SCxSR_FER(port))) {
 525                                                 count--; i--;
 526                                                 continue;
 527                                         }
 528                                         /* Nonzero => end-of-break */
 529                                         pr_debug("scif: debounce<%02x>\n", c);
 530                                         ((struct sci_port *)port)->break_flag = 0;
 531                                         if (STEPFN(c)) {
 532                                                 count--; i--;
 533                                                 continue;
 534                                         }
 535                                 }
 536 #endif /* CONFIG_CPU_SH3 */
 537                                 if (uart_handle_sysrq_char(port, c, regs)) {
 538                                         count--; i--;
 539                                         continue;
 540                                 }
 541
 542                                 /* Store data and status */
 543                                 tty->flip.char_buf_ptr[i] = c;
 544                                 if (status&SCxSR_FER(port)) {
 545                                         tty->flip.flag_buf_ptr[i] = TTY_FRAME;
 546                                         pr_debug("sci: frame error\n");
 547                                 } else if (status&SCxSR_PER(port)) {
 548                                         tty->flip.flag_buf_ptr[i] = TTY_PARITY;
 549                                         pr_debug("sci: parity error\n");
 550                                 } else {
 551                                         tty->flip.flag_buf_ptr[i] = TTY_NORMAL;
 552                                 }
 553                         }
 554                 }
 555
 556                 sci_in(port, SCxSR); /* dummy read */
 557                 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
 558
 559                 /* Update the kernel buffer end */
 560                 tty->flip.count += count;
 561                 tty->flip.char_buf_ptr += count;
 562                 tty->flip.flag_buf_ptr += count;
 563                 copied += count;
 564                 port->icount.rx += count;
 565         }
 566
 567         if (copied) {
 568                 /* Tell the rest of the system the news. New characters! */
 569                 tty_flip_buffer_push(tty);
 570         } else {
 571                 sci_in(port, SCxSR); /* dummy read */
 572                 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
 573         }
 574 }
 575
 576 #define SCI_BREAK_JIFFIES (HZ/20)
 577 /* The sci generates interrupts during the break,
 578  * 1 per millisecond or so during the break period, for 9600 baud.
 579  * So dont bother disabling interrupts.
 580  * But dont want more than 1 break event.
 581  * Use a kernel timer to periodically poll the rx line until
 582  * the break is finished.
 583  */
 584 static void sci_schedule_break_timer(struct sci_port *port)
 585 {
 586         port->break_timer.expires = jiffies + SCI_BREAK_JIFFIES;
 587         add_timer(&port->break_timer);
 588 }
 589 /* Ensure that two consecutive samples find the break over. */
 590 static void sci_break_timer(unsigned long data)
 591 {
 592     struct sci_port * port = (struct sci_port *)data;
 593         if(sci_rxd_in(&port->port) == 0) {
 594                 port->break_flag = 1;
 595             sci_schedule_break_timer(port);
 596         } else if(port->break_flag == 1){
 597                 /* break is over. */
 598                 port->break_flag = 2;
 599             sci_schedule_break_timer(port);
 600         } else port->break_flag = 0;
 601 }
 602
 603 static inline int sci_handle_errors(struct uart_port *port)
 604 {
 605         int copied = 0;
 606         unsigned short status = sci_in(port, SCxSR);
 607         struct tty_struct *tty = port->info->tty;
 608
 609         if (status&SCxSR_ORER(port) && tty->flip.count<TTY_FLIPBUF_SIZE) {
 610                 /* overrun error */
 611                 copied++;
 612                 *tty->flip.flag_buf_ptr++ = TTY_OVERRUN;
 613                 pr_debug("sci: overrun error\n");
 614         }
 615
 616         if (status&SCxSR_FER(port) && tty->flip.count<TTY_FLIPBUF_SIZE) {
 617                 if (sci_rxd_in(port) == 0) {
 618                         /* Notify of BREAK */
 619                         struct sci_port * sci_port = (struct sci_port *)port;
 620                        if(!sci_port->break_flag) {
 621                                 sci_port->break_flag = 1;
 622                                sci_schedule_break_timer((struct sci_port *)port);
 623                                 /* Do sysrq handling. */
 624                                 if(uart_handle_break(port)) {
 625                                         return 0;
 626                                 }
 627                                 pr_debug("sci: BREAK detected\n");
 628                                 copied++;
 629                                 *tty->flip.flag_buf_ptr++ = TTY_BREAK;
 630                        }
 631                 }
 632                 else {
 633                         /* frame error */
 634                         copied++;
 635                         *tty->flip.flag_buf_ptr++ = TTY_FRAME;
 636                         pr_debug("sci: frame error\n");
 637                 }
 638         }
 639
 640         if (status&SCxSR_PER(port) && tty->flip.count<TTY_FLIPBUF_SIZE) {
 641                 /* parity error */
 642                 copied++;
 643                 *tty->flip.flag_buf_ptr++ = TTY_PARITY;
 644                 pr_debug("sci: parity error\n");
 645         }
 646
 647         if (copied) {
 648                 tty->flip.count += copied;
 649                 tty_flip_buffer_push(tty);
 650         }
 651
 652         return copied;
 653 }
 654
 655 static inline int sci_handle_breaks(struct uart_port *port)
 656 {
 657         int copied = 0;
 658         unsigned short status = sci_in(port, SCxSR);
 659         struct tty_struct *tty = port->info->tty;
 660         struct sci_port *s = &sci_ports[port->line];
 661
 662         if (!s->break_flag && status & SCxSR_BRK(port) &&
 663             tty->flip.count < TTY_FLIPBUF_SIZE) {
 664 #if defined(CONFIG_CPU_SH3)
 665                 /* Debounce break */
 666                 s->break_flag = 1;
 667 #endif
 668                 /* Notify of BREAK */
 669                 copied++;
 670                 *tty->flip.flag_buf_ptr++ = TTY_BREAK;
 671                 pr_debug("sci: BREAK detected\n");
 672         }
 673
 674 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_ST40STB1) || \
 675     defined(CONFIG_CPU_SUBTYPE_SH7760)
 676         /* XXX: Handle SCIF overrun error */
 677         if (port->type == PORT_SCIF && (sci_in(port, SCLSR) & SCIF_ORER) != 0) {
 678                 sci_out(port, SCLSR, 0);
 679                 if(tty->flip.count<TTY_FLIPBUF_SIZE) {
 680                         copied++;
 681                         *tty->flip.flag_buf_ptr++ = TTY_OVERRUN;
 682                         pr_debug("sci: overrun error\n");
 683                 }
 684         }
 685 #endif
 686
 687         if (copied) {
 688                 tty->flip.count += copied;
 689                 tty_flip_buffer_push(tty);
 690         }
 691
 692         return copied;
 693 }
 694
 695 static irqreturn_t sci_rx_interrupt(int irq, void *ptr, struct pt_regs *regs)
 696 {
 697         struct uart_port *port = ptr;
 698
 699         /* I think sci_receive_chars has to be called irrespective
 700          * of whether the I_IXOFF is set, otherwise, how is the interrupt
 701          * to be disabled?
 702          */
 703         sci_receive_chars(port, regs);
 704
 705         return IRQ_HANDLED;
 706 }
 707
 708 static irqreturn_t sci_tx_interrupt(int irq, void *ptr, struct pt_regs *regs)
 709 {
 710         struct uart_port *port = ptr;
 711
 712         sci_transmit_chars(port);
 713
 714         return IRQ_HANDLED;
 715 }
 716
 717 static irqreturn_t sci_er_interrupt(int irq, void *ptr, struct pt_regs *regs)
 718 {
 719         struct uart_port *port = ptr;
 720
 721         /* Handle errors */
 722         if (port->type == PORT_SCI) {
 723                 if (sci_handle_errors(port)) {
 724                         /* discard character in rx buffer */
 725                         sci_in(port, SCxSR);
 726                         sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
 727                 }
 728         } else {
 729                 sci_rx_interrupt(irq, ptr, regs);
 730         }
 731
 732         sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
 733
 734         /* Kick the transmission */
 735         sci_tx_interrupt(irq, ptr, regs);
 736
 737         return IRQ_HANDLED;
 738 }
 739
 740 static irqreturn_t sci_br_interrupt(int irq, void *ptr, struct pt_regs *regs)
 741 {
 742         struct uart_port *port = ptr;
 743
 744         /* Handle BREAKs */
 745         sci_handle_breaks(port);
 746         sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
 747
 748         return IRQ_HANDLED;
 749 }
 750
 751 #ifdef CONFIG_CPU_FREQ
 752 /*
 753  * Here we define a transistion notifier so that we can update all of our
 754  * ports' baud rate when the peripheral clock changes.
 755  */
 756 static int sci_notifier(struct notifier_block *self, unsigned long phase, void *p)
 757 {
 758         struct cpufreq_freqs *freqs = p;
 759         int i;
 760
 761         if ((phase == CPUFREQ_POSTCHANGE) ||
 762             (phase == CPUFREQ_RESUMECHANGE)){
 763                 for (i = 0; i < SCI_NPORTS; i++) {
 764                         struct uart_port *port = &sci_ports[i];
 765
 766                         /*
 767                          * Update the uartclk per-port if frequency has
 768                          * changed, since it will no longer necessarily be
 769                          * consistent with the old frequency.
 770                          *
 771                          * Really we want to be able to do something like
 772                          * uart_change_speed() or something along those lines
 773                          * here to implicitly reset the per-port baud rate..
 774                          *
 775                          * Clean this up later..
 776                          */
 777                         port->uartclk = current_cpu_data.module_clock * 16;
 778                 }
 779
 780                 printk("%s: got a postchange notification for cpu %d (old %d, new %d)\n",
 781                                 __FUNCTION__, freqs->cpu, freqs->old, freqs->new);
 782         }
 783
 784         return NOTIFY_OK;
 785 }
 786
 787 static struct notifier_block sci_nb = { &sci_notifier, NULL, 0 };
 788 #endif /* CONFIG_CPU_FREQ */
 789
 790 static int sci_request_irq(struct sci_port *port)
 791 {
 792         int i;
 793         irqreturn_t (*handlers[4])(int irq, void *ptr, struct pt_regs *regs) = {
 794                 sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt,
 795                 sci_br_interrupt,
 796         };
 797         const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full",
 798                                "SCI Transmit Data Empty", "SCI Break" };
 799
 800         for (i = 0; i < ARRAY_SIZE(handlers); i++) {
 801                 if (!port->irqs[i])
 802                         continue;
 803                 if (request_irq(port->irqs[i], handlers[i], SA_INTERRUPT,
 804                                 desc[i], port)) {
 805                         printk(KERN_ERR "sci: Cannot allocate irq.\n");
 806                         return -ENODEV;
 807                 }
 808         }
 809
 810         return 0;
 811 }
 812
 813 static void sci_free_irq(struct sci_port *port)
 814 {
 815         int i;
 816
 817         for (i = 0; i < ARRAY_SIZE(port->irqs); i++) {
 818                 if (!port->irqs[i])
 819                         continue;
 820
 821                 free_irq(port->irqs[i], port);
 822         }
 823 }
 824
 825 static unsigned int sci_tx_empty(struct uart_port *port)
 826 {
 827         /* Can't detect */
 828         return TIOCSER_TEMT;
 829 }
 830
 831 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
 832 {
 833         /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */
 834         /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */
 835         /* If you have signals for DTR and DCD, please implement here. */
 836 }
 837
 838 static unsigned int sci_get_mctrl(struct uart_port *port)
 839 {
 840         /* This routine is used for geting signals of: DTR, DCD, DSR, RI,
 841            and CTS/RTS */
 842
 843         return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR;
 844 }
 845
 846 static void sci_start_tx(struct uart_port *port, unsigned int tty_start)
 847 {
 848         struct sci_port *s = &sci_ports[port->line];
 849
 850         disable_irq(s->irqs[SCIx_TXI_IRQ]);
 851         sci_transmit_chars(port);
 852         enable_irq(s->irqs[SCIx_TXI_IRQ]);
 853 }
 854
 855 static void sci_stop_tx(struct uart_port *port, unsigned int tty_stop)
 856 {
 857         unsigned long flags;
 858         unsigned short ctrl;
 859
 860         /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
 861         local_irq_save(flags);
 862         ctrl = sci_in(port, SCSCR);
 863         ctrl &= ~SCI_CTRL_FLAGS_TIE;
 864         sci_out(port, SCSCR, ctrl);
 865         local_irq_restore(flags);
 866 }
 867
 868 static void sci_start_rx(struct uart_port *port, unsigned int tty_start)
 869 {
 870         unsigned long flags;
 871         unsigned short ctrl;
 872
 873         /* Set RIE (Receive Interrupt Enable) bit in SCSCR */
 874         local_irq_save(flags);
 875         ctrl = sci_in(port, SCSCR);
 876         ctrl |= SCI_CTRL_FLAGS_RIE;
 877         sci_out(port, SCSCR, ctrl);
 878         local_irq_restore(flags);
 879 }
 880
 881 static void sci_stop_rx(struct uart_port *port)
 882 {
 883         unsigned long flags;
 884         unsigned short ctrl;
 885
 886         /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */
 887         local_irq_save(flags);
 888         ctrl = sci_in(port, SCSCR);
 889         ctrl &= ~SCI_CTRL_FLAGS_RIE;
 890         sci_out(port, SCSCR, ctrl);
 891         local_irq_restore(flags);
 892 }
 893
 894 static void sci_enable_ms(struct uart_port *port)
 895 {
 896         /* Nothing here yet .. */
 897 }
 898
 899 static void sci_break_ctl(struct uart_port *port, int break_state)
 900 {
 901         /* Nothing here yet .. */
 902 }
 903
 904 static int sci_startup(struct uart_port *port)
 905 {
 906         struct sci_port *s = &sci_ports[port->line];
 907
 908 #if defined(__H8300S__)
 909         h8300_sci_enable(port, sci_enable);
 910 #endif
 911
 912         sci_request_irq(s);
 913         sci_start_tx(port, 1);
 914         sci_start_rx(port, 1);
 915
 916         return 0;
 917 }
 918
 919 static void sci_shutdown(struct uart_port *port)
 920 {
 921         struct sci_port *s = &sci_ports[port->line];
 922
 923         sci_stop_rx(port);
 924         sci_stop_tx(port, 1);
 925         sci_free_irq(s);
 926
 927 #if defined(__H8300S__)
 928         h8300_sci_enable(port, sci_disable);
 929 #endif
 930 }
 931
 932 static void sci_set_termios(struct uart_port *port, struct termios *termios,
 933                             struct termios *old)
 934 {
 935         struct sci_port *s = &sci_ports[port->line];
 936         unsigned int status, baud, smr_val;
 937         unsigned long flags;
 938         int t;
 939
 940         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
 941
 942         spin_lock_irqsave(&port->lock, flags);
 943
 944         do {
 945                 status = sci_in(port, SCxSR);
 946         } while (!(status & SCxSR_TEND(port)));
 947
 948         sci_out(port, SCSCR, 0x00);     /* TE=0, RE=0, CKE1=0 */
 949
 950 #if !defined(SCI_ONLY)
 951         if (port->type == PORT_SCIF) {
 952                 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
 953         }
 954 #endif
 955
 956         smr_val = sci_in(port, SCSMR) & 3;
 957         if ((termios->c_cflag & CSIZE) == CS7)
 958                 smr_val |= 0x40;
 959         if (termios->c_cflag & PARENB)
 960                 smr_val |= 0x20;
 961         if (termios->c_cflag & PARODD)
 962                 smr_val |= 0x30;
 963         if (termios->c_cflag & CSTOPB)
 964                 smr_val |= 0x08;
 965
 966         uart_update_timeout(port, termios->c_cflag, baud);
 967
 968         sci_out(port, SCSMR, smr_val);
 969
 970         switch (baud) {
 971                 case 0:         t = -1;         break;
 972                 case 2400:      t = BPS_2400;   break;
 973                 case 4800:      t = BPS_4800;   break;
 974                 case 9600:      t = BPS_9600;   break;
 975                 case 19200:     t = BPS_19200;  break;
 976                 case 38400:     t = BPS_38400;  break;
 977                 case 57600:     t = BPS_57600;  break;
 978                 case 115200:    t = BPS_115200; break;
 979                 default:        t = BPS_115200; break;
 980         }
 981
 982         if (t > 0) {
 983                 if(t >= 256) {
 984                         sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
 985                         t >>= 2;
 986                 } else {
 987                         sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3);
 988                 }
 989                 sci_out(port, SCBRR, t);
 990                 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
 991         }
 992
 993         s->init_pins(port, termios->c_cflag);
 994         sci_out(port, SCSCR, SCSCR_INIT(port));
 995
 996         if ((termios->c_cflag & CREAD) != 0)
 997               sci_start_rx(port,0);
 998
 999         spin_unlock_irqrestore(&port->lock, flags);
1000 }
1001
1002 static const char *sci_type(struct uart_port *port)
1003 {
1004         switch (port->type) {
1005                 case PORT_SCI:  return "sci";
1006                 case PORT_SCIF: return "scif";
1007                 case PORT_IRDA: return "irda";
1008         }
1009
1010         return 0;
1011 }
1012
1013 static void sci_release_port(struct uart_port *port)
1014 {
1015         /* Nothing here yet .. */
1016 }
1017
1018 static int sci_request_port(struct uart_port *port)
1019 {
1020         /* Nothing here yet .. */
1021         return 0;
1022 }
1023
1024 static void sci_config_port(struct uart_port *port, int flags)
1025 {
1026         struct sci_port *s = &sci_ports[port->line];
1027
1028         port->type = s->type;
1029 }
1030
1031 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
1032 {
1033         struct sci_port *s = &sci_ports[port->line];
1034
1035         if (ser->irq != s->irqs[SCIx_TXI_IRQ] || ser->irq > NR_IRQS)
1036                 return -EINVAL;
1037         if (ser->baud_base < 2400)
1038                 /* No paper tape reader for Mitch.. */
1039                 return -EINVAL;
1040
1041         return 0;
1042 }
1043
1044 static struct uart_ops sci_uart_ops = {
1045         .tx_empty       = sci_tx_empty,
1046         .set_mctrl      = sci_set_mctrl,
1047         .get_mctrl      = sci_get_mctrl,
1048         .start_tx       = sci_start_tx,
1049         .stop_tx        = sci_stop_tx,
1050         .stop_rx        = sci_stop_rx,
1051         .enable_ms      = sci_enable_ms,
1052         .break_ctl      = sci_break_ctl,
1053         .startup        = sci_startup,
1054         .shutdown       = sci_shutdown,
1055         .set_termios    = sci_set_termios,
1056         .type           = sci_type,
1057         .release_port   = sci_release_port,
1058         .request_port   = sci_request_port,
1059         .config_port    = sci_config_port,
1060         .verify_port    = sci_verify_port,
1061 };
1062
1063 static struct sci_port sci_ports[SCI_NPORTS] = {
1064 #if defined(CONFIG_CPU_SUBTYPE_SH7708)
1065         {
1066                 .port   = {
1067                         .membase        = (void *)0xfffffe80,
1068                         .mapbase        = 0xfffffe80,
1069                         .iotype         = SERIAL_IO_MEM,
1070                         .irq            = 25,
1071                         .ops            = &sci_uart_ops,
1072                         .flags          = ASYNC_BOOT_AUTOCONF,
1073                         .line           = 0,
1074                 },
1075                 .type           = PORT_SCI,
1076                 .irqs           = SCI_IRQS,
1077                 .init_pins      = sci_init_pins_sci,
1078         },
1079 #elif defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
1080         {
1081                 .port   = {
1082                         .membase        = (void *)0xfffffe80,
1083                         .mapbase        = 0xfffffe80,
1084                         .iotype         = SERIAL_IO_MEM,
1085                         .irq            = 25,
1086                         .ops            = &sci_uart_ops,
1087                         .flags          = ASYNC_BOOT_AUTOCONF,
1088                         .line           = 0,
1089                 },
1090                 .type           = PORT_SCI,
1091                 .irqs           = SCI_IRQS,
1092                 .init_pins      = sci_init_pins_sci,
1093         },
1094         {
1095                 .port   = {
1096                         .membase        = (void *)0xa4000150,
1097                         .mapbase        = 0xa4000150,
1098                         .iotype         = SERIAL_IO_MEM,
1099                         .irq            = 59,
1100                         .ops            = &sci_uart_ops,
1101                         .flags          = ASYNC_BOOT_AUTOCONF,
1102                         .line           = 1,
1103                 },
1104                 .type           = PORT_SCIF,
1105                 .irqs           = SH3_SCIF_IRQS,
1106                 .init_pins      = sci_init_pins_scif,
1107         },
1108         {
1109                 .port   = {
1110                         .membase        = (void *)0xa4000140,
1111                         .mapbase        = 0xa4000140,
1112                         .iotype         = SERIAL_IO_MEM,
1113                         .irq            = 55,
1114                         .ops            = &sci_uart_ops,
1115                         .flags          = ASYNC_BOOT_AUTOCONF,
1116                         .line           = 2,
1117                 },
1118                 .type           = PORT_IRDA,
1119                 .irqs           = SH3_IRDA_IRQS,
1120                 .init_pins      = sci_init_pins_irda,
1121         }
1122 #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751)
1123         {
1124                 .port   = {
1125                         .membase        = (void *)0xffe00000,
1126                         .mapbase        = 0xffe00000,
1127                         .iotype         = SERIAL_IO_MEM,
1128                         .irq            = 25,
1129                         .ops            = &sci_uart_ops,
1130                         .flags          = ASYNC_BOOT_AUTOCONF,
1131                         .line           = 0,
1132                 },
1133                 .type           = PORT_SCI,
1134                 .irqs           = SCI_IRQS,
1135                 .init_pins      = sci_init_pins_sci,
1136         },
1137         {
1138                 .port   = {
1139                         .membase        = (void *)0xffe80000,
1140                         .mapbase        = 0xffe80000,
1141                         .iotype         = SERIAL_IO_MEM,
1142                         .irq            = 43,
1143                         .ops            = &sci_uart_ops,
1144                         .flags          = ASYNC_BOOT_AUTOCONF,
1145                         .line           = 1,
1146                 },
1147                 .type           = PORT_SCIF,
1148                 .irqs           = SH4_SCIF_IRQS,
1149                 .init_pins      = sci_init_pins_scif,
1150         },
1151 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
1152         {
1153                 .port   = {
1154                         .membase        = (void *)0xfe600000,
1155                         .mapbase        = 0xfe600000,
1156                         .iotype         = SERIAL_IO_MEM,
1157                         .irq            = 55,
1158                         .ops            = &sci_uart_ops,
1159                         .flags          = ASYNC_BOOT_AUTOCONF,
1160                         .line           = 0,
1161                 },
1162                 .type           = PORT_SCIF,
1163                 .irqs           = SH7760_SCIF0_IRQS,
1164                 .init_pins      = sci_init_pins_scif,
1165         },
1166         {
1167                 .port   = {
1168                         .membase        = (void *)0xfe610000,
1169                         .mapbase        = 0xfe610000,
1170                         .iotype         = SERIAL_IO_MEM,
1171                         .irq            = 75,
1172                         .ops            = &sci_uart_ops,
1173                         .flags          = ASYNC_BOOT_AUTOCONF,
1174                         .line           = 1,
1175                 },
1176                 .type           = PORT_SCIF,
1177                 .irqs           = SH7760_SCIF1_IRQS,
1178                 .init_pins      = sci_init_pins_scif,
1179         },
1180         {
1181                 .port   = {
1182                         .membase        = (void *)0xfe620000,
1183                         .mapbase        = 0xfe620000,
1184                         .iotype         = SERIAL_IO_MEM,
1185                         .irq            = 79,
1186                         .ops            = &sci_uart_ops,
1187                         .flags          = ASYNC_BOOT_AUTOCONF,
1188                         .line           = 2,
1189                 },
1190                 .type           = PORT_SCIF,
1191                 .irqs           = SH7760_SCIF2_IRQS,
1192                 .init_pins      = sci_init_pins_scif,
1193         },
1194 #elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
1195         {
1196                 .port   = {
1197                         .membase        = (void *)0xffe00000,
1198                         .mapbase        = 0xffe00000,
1199                         .iotype         = SERIAL_IO_MEM,
1200                         .irq            = 26,
1201                         .ops            = &sci_uart_ops,
1202                         .flags          = ASYNC_BOOT_AUTOCONF,
1203                         .line           = 0,
1204                 },
1205                 .type           = PORT_SCIF,
1206                 .irqs           = STB1_SCIF1_IRQS,
1207                 .init_pins      = sci_init_pins_scif,
1208         },
1209         {
1210                 .port   = {
1211                         .membase        = (void *)0xffe80000,
1212                         .mapbase        = 0xffe80000,
1213                         .iotype         = SERIAL_IO_MEM,
1214                         .irq            = 43,
1215                         .ops            = &sci_uart_ops,
1216                         .flags          = ASYNC_BOOT_AUTOCONF,
1217                         .line           = 1,
1218                 },
1219                 .type           = PORT_SCIF,
1220                 .irqs           = SH4_SCIF_IRQS,
1221                 .init_pins      = sci_init_pins_scif,
1222         },
1223 #elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
1224         {
1225                 .port   = {
1226                         .membase        = (void *)0x00ffffb0,
1227                         .mapbase        = 0x00ffffb0,
1228                         .iotype         = SERIAL_IO_MEM,
1229                         .irq            = 54,
1230                         .ops            = &sci_uart_ops,
1231                         .flags          = ASYNC_BOOT_AUTOCONF,
1232                         .line           = 0,
1233                 },
1234                 .type           = PORT_SCI,
1235                 .irqs           = H8300H_SCI_IRQS0,
1236                 .init_pins      = sci_init_pins_sci,
1237         },
1238         {
1239                 .port   = {
1240                         .membase        = (void *)0x00ffffb8,
1241                         .mapbase        = 0x00ffffb8,
1242                         .iotype         = SERIAL_IO_MEM,
1243                         .irq            = 58,
1244                         .ops            = &sci_uart_ops,
1245                         .flags          = ASYNC_BOOT_AUTOCONF,
1246                         .line           = 1,
1247                 },
1248                 .type           = PORT_SCI,
1249                 .irqs           = H8300H_SCI_IRQS1,
1250                 .init_pins      = sci_init_pins_sci,
1251         },
1252         {
1253                 .port   = {
1254                         .membase        = (void *)0x00ffffc0,
1255                         .mapbase        = 0x00ffffc0,
1256                         .iotype         = SERIAL_IO_MEM,
1257                         .irq            = 62,
1258                         .ops            = &sci_uart_ops,
1259                         .flags          = ASYNC_BOOT_AUTOCONF,
1260                         .line           = 2,
1261                 },
1262                 .type           = PORT_SCI,
1263                 .irqs           = H8300H_SCI_IRQS2,
1264                 .init_pins      = sci_init_pins_sci,
1265         },
1266 #elif defined(CONFIG_H8S2678)
1267         {
1268                 .port   = {
1269                         .membase        = (void *)0x00ffff78,
1270                         .mapbase        = 0x00ffff78,
1271                         .iotype         = SERIAL_IO_MEM,
1272                         .irq            = 90,
1273                         .ops            = &sci_uart_ops,
1274                         .flags          = ASYNC_BOOT_AUTOCONF,
1275                         .line           = 0,
1276                 },
1277                 .type           = PORT_SCI,
1278                 .irqs           = H8S_SCI_IRQS0,
1279                 .init_pins      = sci_init_pins_sci,
1280         },
1281         {
1282                 .port   = {
1283                         .membase        = (void *)0x00ffff80,
1284                         .mapbase        = 0x00ffff80,
1285                         .iotype         = SERIAL_IO_MEM,
1286                         .irq            = 94,
1287                         .ops            = &sci_uart_ops,
1288                         .flags          = ASYNC_BOOT_AUTOCONF,
1289                         .line           = 1,
1290                 },
1291                 .type           = PORT_SCI,
1292                 .irqs           = H8S_SCI_IRQS1,
1293                 .init_pins      = sci_init_pins_sci,
1294         },
1295         {
1296                 .port   = {
1297                         .membase        = (void *)0x00ffff88,
1298                         .mapbase        = 0x00ffff88,
1299                         .iotype         = SERIAL_IO_MEM,
1300                         .irq            = 98,
1301                         .ops            = &sci_uart_ops,
1302                         .flags          = ASYNC_BOOT_AUTOCONF,
1303                         .line           = 2,
1304                 },
1305                 .type           = PORT_SCI,
1306                 .irqs           = H8S_SCI_IRQS2,
1307                 .init_pins      = sci_init_pins_sci,
1308         },
1309 #else
1310 #error "CPU subtype not defined"
1311 #endif
1312 };
1313
1314 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1315 /*
1316  *      Print a string to the serial port trying not to disturb
1317  *      any possible real use of the port...
1318  */
1319 static void serial_console_write(struct console *co, const char *s,
1320                                  unsigned count)
1321 {
1322         put_string(serial_console_port, s, count);
1323 }
1324
1325 static int __init serial_console_setup(struct console *co, char *options)
1326 {
1327         struct uart_port *port;
1328         int baud = 115200;
1329         int bits = 8;
1330         int parity = 'n';
1331         int flow = 'n';
1332         int ret;
1333
1334         if (co->index >= SCI_NPORTS)
1335                 co->index = 0;
1336
1337         serial_console_port = &sci_ports[co->index];
1338         port = &serial_console_port->port;
1339         port->type = serial_console_port->type;
1340
1341         /*
1342          * We need to set the initial uartclk here, since otherwise it will
1343          * only ever be setup at sci_init() time.
1344          */
1345 #if !defined(__H8300H__) && !defined(__H8300S__)
1346         port->uartclk = current_cpu_data.module_clock * 16;
1347 #else
1348         port->uartclk = CONFIG_CPU_CLOCK;
1349 #endif
1350 #if defined(__H8300S__)
1351         h8300_sci_enable(port, sci_enable);
1352 #endif
1353         if (options)
1354                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1355
1356         ret = uart_set_options(port, co, baud, parity, bits, flow);
1357 #if defined(__H8300H__) || defined(__H8300S__)
1358         /* disable rx interrupt */
1359         if (ret == 0)
1360                 sci_stop_rx(port);
1361 #endif
1362         return ret;
1363 }
1364
1365 static struct console serial_console = {
1366         .name           = "ttySC",
1367         .device         = uart_console_device,
1368         .write          = serial_console_write,
1369         .setup          = serial_console_setup,
1370         .flags          = CON_PRINTBUFFER,
1371         .index          = -1,
1372         .data           = &sci_uart_driver,
1373 };
1374
1375 static int __init sci_console_init(void)
1376 {
1377 #ifdef CONFIG_SH_EARLY_PRINTK
1378         extern void sh_console_unregister(void);
1379
1380         /*
1381          * Now that the real console is available, unregister the one we
1382          * used while first booting.
1383          */
1384         sh_console_unregister();
1385 #endif
1386
1387         register_console(&serial_console);
1388
1389         return 0;
1390 }
1391
1392 console_initcall(sci_console_init);
1393 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1394
1395 #ifdef CONFIG_SH_KGDB
1396 /*
1397  * FIXME: Most of this can go away.. at the moment, we rely on
1398  * arch/sh/kernel/setup.c to do the command line parsing for kgdb, though
1399  * most of that can easily be done here instead.
1400  *
1401  * For the time being, just accept the values that were parsed earlier..
1402  */
1403 static void __init kgdb_console_get_options(struct uart_port *port, int *baud,
1404                                             int *parity, int *bits)
1405 {
1406         *baud = kgdb_baud;
1407         *parity = tolower(kgdb_parity);
1408         *bits = kgdb_bits - '0';
1409 }
1410
1411 /*
1412  * The naming here is somewhat misleading, since kgdb_console_setup() takes
1413  * care of the early-on initialization for kgdb, regardless of whether we
1414  * actually use kgdb as a console or not.
1415  *
1416  * On the plus side, this lets us kill off the old kgdb_sci_setup() nonsense.
1417  */
1418 int __init kgdb_console_setup(struct console *co, char *options)
1419 {
1420         struct uart_port *port = &sci_ports[kgdb_portnum].port;
1421         int baud = 38400;
1422         int bits = 8;
1423         int parity = 'n';
1424         int flow = 'n';
1425
1426         if (co->index >= SCI_NPORTS || co->index != kgdb_portnum)
1427                 co->index = kgdb_portnum;
1428
1429         if (options)
1430                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1431         else
1432                 kgdb_console_get_options(port, &baud, &parity, &bits);
1433
1434         kgdb_getchar = kgdb_sci_getchar;
1435         kgdb_putchar = kgdb_sci_putchar;
1436
1437         return uart_set_options(port, co, baud, parity, bits, flow);
1438 }
1439 #endif /* CONFIG_SH_KGDB */
1440
1441 #ifdef CONFIG_SH_KGDB_CONSOLE
1442 static struct console kgdb_console = {
1443         .name           = "ttySC",
1444         .write          = kgdb_console_write,
1445         .setup          = kgdb_console_setup,
1446         .flags          = CON_PRINTBUFFER | CON_ENABLED,
1447         .index          = -1,
1448         .data           = &sci_uart_driver,
1449 };
1450
1451 /* Register the KGDB console so we get messages (d'oh!) */
1452 static int __init kgdb_console_init(void)
1453 {
1454         register_console(&kgdb_console);
1455
1456         return 0;
1457 }
1458
1459 console_initcall(kgdb_console_init);
1460 #endif /* CONFIG_SH_KGDB_CONSOLE */
1461
1462 #if defined(CONFIG_SH_KGDB_CONSOLE)
1463 #define SCI_CONSOLE     &kgdb_console
1464 #elif defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1465 #define SCI_CONSOLE     &serial_console
1466 #else
1467 #define SCI_CONSOLE     0
1468 #endif
1469
1470 static char banner[] __initdata =
1471         KERN_INFO "SuperH SCI(F) driver initialized\n";
1472
1473 static struct uart_driver sci_uart_driver = {
1474         .owner          = THIS_MODULE,
1475         .driver_name    = "sci",
1476 #ifdef CONFIG_DEVFS_FS
1477         .devfs_name     = "ttsc/",
1478 #endif
1479         .dev_name       = "ttySC",
1480         .major          = SCI_MAJOR,
1481         .minor          = SCI_MINOR_START,
1482         .nr             = SCI_NPORTS,
1483         .cons           = SCI_CONSOLE,
1484 };
1485
1486 static int __init sci_init(void)
1487 {
1488         int chan, ret;
1489
1490         printk("%s", banner);
1491
1492         ret = uart_register_driver(&sci_uart_driver);
1493         if (ret == 0) {
1494                 for (chan = 0; chan < SCI_NPORTS; chan++) {
1495                         struct sci_port *sciport = &sci_ports[chan];
1496
1497 #if !defined(__H8300H__) && !defined(__H8300S__)
1498                         sciport->port.uartclk = (current_cpu_data.module_clock * 16);
1499 #else
1500                         sciport->port.uartclk = CONFIG_CPU_CLOCK;
1501 #endif
1502                         uart_add_one_port(&sci_uart_driver, &sciport->port);
1503                         sciport->break_timer.data = (unsigned long)sciport;
1504                         sciport->break_timer.function = sci_break_timer;
1505                         init_timer(&sciport->break_timer);
1506                 }
1507         }
1508
1509 #ifdef CONFIG_CPU_FREQ
1510         cpufreq_register_notifier(&sci_nb, CPUFREQ_TRANSITION_NOTIFIER);
1511         printk("sci: CPU frequency notifier registered\n");
1512 #endif
1513
1514 #ifdef CONFIG_SH_STANDARD_BIOS
1515         sh_bios_gdb_detach();
1516 #endif
1517
1518         return ret;
1519 }
1520
1521 static void __exit sci_exit(void)
1522 {
1523         int chan;
1524
1525         for (chan = 0; chan < SCI_NPORTS; chan++)
1526                 uart_remove_one_port(&sci_uart_driver, &sci_ports[chan].port);
1527
1528         uart_unregister_driver(&sci_uart_driver);
1529 }
1530
1531 module_init(sci_init);
1532 module_exit(sci_exit);
1533