drivers/serial/sunzilog.c

   1 /*
   2  * sunzilog.c
   3  *
   4  * Driver for Zilog serial chips found on Sun workstations and
   5  * servers.  This driver could actually be made more generic.
   6  *
   7  * This is based on the old drivers/sbus/char/zs.c code.  A lot
   8  * of code has been simply moved over directly from there but
   9  * much has been rewritten.  Credits therefore go out to Eddie
  10  * C. Dost, Pete Zaitcev, Ted Ts'o and Alex Buell for their
  11  * work there.
  12  *
  13  *  Copyright (C) 2002 David S. Miller (davem@redhat.com)
  14  */
  15
  16 #include <linux/config.h>
  17 #include <linux/module.h>
  18 #include <linux/kernel.h>
  19 #include <linux/sched.h>
  20 #include <linux/errno.h>
  21 #include <linux/delay.h>
  22 #include <linux/tty.h>
  23 #include <linux/tty_flip.h>
  24 #include <linux/major.h>
  25 #include <linux/string.h>
  26 #include <linux/ptrace.h>
  27 #include <linux/ioport.h>
  28 #include <linux/slab.h>
  29 #include <linux/circ_buf.h>
  30 #include <linux/serial.h>
  31 #include <linux/sysrq.h>
  32 #include <linux/console.h>
  33 #include <linux/spinlock.h>
  34 #ifdef CONFIG_SERIO
  35 #include <linux/serio.h>
  36 #endif
  37 #include <linux/init.h>
  38
  39 #include <asm/io.h>
  40 #include <asm/irq.h>
  41 #ifdef CONFIG_SPARC64
  42 #include <asm/fhc.h>
  43 #endif
  44 #include <asm/sbus.h>
  45
  46 #if defined(CONFIG_SERIAL_SUNZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  47 #define SUPPORT_SYSRQ
  48 #endif
  49
  50 #include <linux/serial_core.h>
  51
  52 #include "suncore.h"
  53 #include "sunzilog.h"
  54
  55 /* On 32-bit sparcs we need to delay after register accesses
  56  * to accommodate sun4 systems, but we do not need to flush writes.
  57  * On 64-bit sparc we only need to flush single writes to ensure
  58  * completion.
  59  */
  60 #ifndef CONFIG_SPARC64
  61 #define ZSDELAY()               udelay(5)
  62 #define ZSDELAY_LONG()          udelay(20)
  63 #define ZS_WSYNC(channel)       do { } while (0)
  64 #else
  65 #define ZSDELAY()
  66 #define ZSDELAY_LONG()
  67 #define ZS_WSYNC(__channel) \
  68         sbus_readb(&((__channel)->control))
  69 #endif
  70
  71 static int num_sunzilog;
  72 #define NUM_SUNZILOG    num_sunzilog
  73 #define NUM_CHANNELS    (NUM_SUNZILOG * 2)
  74
  75 #define KEYBOARD_LINE 0x2
  76 #define MOUSE_LINE    0x3
  77
  78 #define ZS_CLOCK                4915200 /* Zilog input clock rate. */
  79 #define ZS_CLOCK_DIVISOR        16      /* Divisor this driver uses. */
  80
  81 /*
  82  * We wrap our port structure around the generic uart_port.
  83  */
  84 struct uart_sunzilog_port {
  85         struct uart_port                port;
  86
  87         /* IRQ servicing chain.  */
  88         struct uart_sunzilog_port       *next;
  89
  90         /* Current values of Zilog write registers.  */
  91         unsigned char                   curregs[NUM_ZSREGS];
  92
  93         unsigned int                    flags;
  94 #define SUNZILOG_FLAG_CONS_KEYB         0x00000001
  95 #define SUNZILOG_FLAG_CONS_MOUSE        0x00000002
  96 #define SUNZILOG_FLAG_IS_CONS           0x00000004
  97 #define SUNZILOG_FLAG_IS_KGDB           0x00000008
  98 #define SUNZILOG_FLAG_MODEM_STATUS      0x00000010
  99 #define SUNZILOG_FLAG_IS_CHANNEL_A      0x00000020
 100 #define SUNZILOG_FLAG_REGS_HELD         0x00000040
 101 #define SUNZILOG_FLAG_TX_STOPPED        0x00000080
 102 #define SUNZILOG_FLAG_TX_ACTIVE         0x00000100
 103
 104         unsigned int cflag;
 105
 106         unsigned char                   parity_mask;
 107         unsigned char                   prev_status;
 108
 109 #ifdef CONFIG_SERIO
 110         struct serio                    serio;
 111         int                             serio_open;
 112 #endif
 113 };
 114
 115 #define ZILOG_CHANNEL_FROM_PORT(PORT)   ((struct zilog_channel *)((PORT)->membase))
 116 #define UART_ZILOG(PORT)                ((struct uart_sunzilog_port *)(PORT))
 117
 118 #define ZS_IS_KEYB(UP)  ((UP)->flags & SUNZILOG_FLAG_CONS_KEYB)
 119 #define ZS_IS_MOUSE(UP) ((UP)->flags & SUNZILOG_FLAG_CONS_MOUSE)
 120 #define ZS_IS_CONS(UP)  ((UP)->flags & SUNZILOG_FLAG_IS_CONS)
 121 #define ZS_IS_KGDB(UP)  ((UP)->flags & SUNZILOG_FLAG_IS_KGDB)
 122 #define ZS_WANTS_MODEM_STATUS(UP)       ((UP)->flags & SUNZILOG_FLAG_MODEM_STATUS)
 123 #define ZS_IS_CHANNEL_A(UP)     ((UP)->flags & SUNZILOG_FLAG_IS_CHANNEL_A)
 124 #define ZS_REGS_HELD(UP)        ((UP)->flags & SUNZILOG_FLAG_REGS_HELD)
 125 #define ZS_TX_STOPPED(UP)       ((UP)->flags & SUNZILOG_FLAG_TX_STOPPED)
 126 #define ZS_TX_ACTIVE(UP)        ((UP)->flags & SUNZILOG_FLAG_TX_ACTIVE)
 127
 128 /* Reading and writing Zilog8530 registers.  The delays are to make this
 129  * driver work on the Sun4 which needs a settling delay after each chip
 130  * register access, other machines handle this in hardware via auxiliary
 131  * flip-flops which implement the settle time we do in software.
 132  *
 133  * The port lock must be held and local IRQs must be disabled
 134  * when {read,write}_zsreg is invoked.
 135  */
 136 static unsigned char read_zsreg(struct zilog_channel *channel,
 137                                 unsigned char reg)
 138 {
 139         unsigned char retval;
 140
 141         sbus_writeb(reg, &channel->control);
 142         ZSDELAY();
 143         retval = sbus_readb(&channel->control);
 144         ZSDELAY();
 145
 146         return retval;
 147 }
 148
 149 static void write_zsreg(struct zilog_channel *channel,
 150                         unsigned char reg, unsigned char value)
 151 {
 152         sbus_writeb(reg, &channel->control);
 153         ZSDELAY();
 154         sbus_writeb(value, &channel->control);
 155         ZSDELAY();
 156 }
 157
 158 static void sunzilog_clear_fifo(struct zilog_channel *channel)
 159 {
 160         int i;
 161
 162         for (i = 0; i < 32; i++) {
 163                 unsigned char regval;
 164
 165                 regval = sbus_readb(&channel->control);
 166                 ZSDELAY();
 167                 if (regval & Rx_CH_AV)
 168                         break;
 169
 170                 regval = read_zsreg(channel, R1);
 171                 sbus_readb(&channel->data);
 172                 ZSDELAY();
 173
 174                 if (regval & (PAR_ERR | Rx_OVR | CRC_ERR)) {
 175                         sbus_writeb(ERR_RES, &channel->control);
 176                         ZSDELAY();
 177                         ZS_WSYNC(channel);
 178                 }
 179         }
 180 }
 181
 182 /* This function must only be called when the TX is not busy.  The UART
 183  * port lock must be held and local interrupts disabled.
 184  */
 185 static void __load_zsregs(struct zilog_channel *channel, unsigned char *regs)
 186 {
 187         int i;
 188
 189         /* Let pending transmits finish.  */
 190         for (i = 0; i < 1000; i++) {
 191                 unsigned char stat = read_zsreg(channel, R1);
 192                 if (stat & ALL_SNT)
 193                         break;
 194                 udelay(100);
 195         }
 196
 197         sbus_writeb(ERR_RES, &channel->control);
 198         ZSDELAY();
 199         ZS_WSYNC(channel);
 200
 201         sunzilog_clear_fifo(channel);
 202
 203         /* Disable all interrupts.  */
 204         write_zsreg(channel, R1,
 205                     regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
 206
 207         /* Set parity, sync config, stop bits, and clock divisor.  */
 208         write_zsreg(channel, R4, regs[R4]);
 209
 210         /* Set misc. TX/RX control bits.  */
 211         write_zsreg(channel, R10, regs[R10]);
 212
 213         /* Set TX/RX controls sans the enable bits.  */
 214         write_zsreg(channel, R3, regs[R3] & ~RxENAB);
 215         write_zsreg(channel, R5, regs[R5] & ~TxENAB);
 216
 217         /* Synchronous mode config.  */
 218         write_zsreg(channel, R6, regs[R6]);
 219         write_zsreg(channel, R7, regs[R7]);
 220
 221         /* Don't mess with the interrupt vector (R2, unused by us) and
 222          * master interrupt control (R9).  We make sure this is setup
 223          * properly at probe time then never touch it again.
 224          */
 225
 226         /* Disable baud generator.  */
 227         write_zsreg(channel, R14, regs[R14] & ~BRENAB);
 228
 229         /* Clock mode control.  */
 230         write_zsreg(channel, R11, regs[R11]);
 231
 232         /* Lower and upper byte of baud rate generator divisor.  */
 233         write_zsreg(channel, R12, regs[R12]);
 234         write_zsreg(channel, R13, regs[R13]);
 235
 236         /* Now rewrite R14, with BRENAB (if set).  */
 237         write_zsreg(channel, R14, regs[R14]);
 238
 239         /* External status interrupt control.  */
 240         write_zsreg(channel, R15, regs[R15]);
 241
 242         /* Reset external status interrupts.  */
 243         write_zsreg(channel, R0, RES_EXT_INT);
 244         write_zsreg(channel, R0, RES_EXT_INT);
 245
 246         /* Rewrite R3/R5, this time without enables masked.  */
 247         write_zsreg(channel, R3, regs[R3]);
 248         write_zsreg(channel, R5, regs[R5]);
 249
 250         /* Rewrite R1, this time without IRQ enabled masked.  */
 251         write_zsreg(channel, R1, regs[R1]);
 252 }
 253
 254 /* Reprogram the Zilog channel HW registers with the copies found in the
 255  * software state struct.  If the transmitter is busy, we defer this update
 256  * until the next TX complete interrupt.  Else, we do it right now.
 257  *
 258  * The UART port lock must be held and local interrupts disabled.
 259  */
 260 static void sunzilog_maybe_update_regs(struct uart_sunzilog_port *up,
 261                                        struct zilog_channel *channel)
 262 {
 263         if (!ZS_REGS_HELD(up)) {
 264                 if (ZS_TX_ACTIVE(up)) {
 265                         up->flags |= SUNZILOG_FLAG_REGS_HELD;
 266                 } else {
 267                         __load_zsregs(channel, up->curregs);
 268                 }
 269         }
 270 }
 271
 272 static void sunzilog_change_mouse_baud(struct uart_sunzilog_port *up)
 273 {
 274         unsigned int cur_cflag = up->cflag;
 275         int brg, new_baud;
 276
 277         up->cflag &= ~CBAUD;
 278         up->cflag |= suncore_mouse_baud_cflag_next(cur_cflag, &new_baud);
 279
 280         brg = BPS_TO_BRG(new_baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
 281         up->curregs[R12] = (brg & 0xff);
 282         up->curregs[R13] = (brg >> 8) & 0xff;
 283         sunzilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(&up->port));
 284 }
 285
 286 static void sunzilog_kbdms_receive_chars(struct uart_sunzilog_port *up,
 287                                          unsigned char ch, int is_break,
 288                                          struct pt_regs *regs)
 289 {
 290         if (ZS_IS_KEYB(up)) {
 291                 /* Stop-A is handled by drivers/char/keyboard.c now. */
 292 #ifdef CONFIG_SERIO
 293                 if (up->serio_open)
 294                         serio_interrupt(&up->serio, ch, 0, regs);
 295 #endif
 296         } else if (ZS_IS_MOUSE(up)) {
 297                 int ret = suncore_mouse_baud_detection(ch, is_break);
 298
 299                 switch (ret) {
 300                 case 2:
 301                         sunzilog_change_mouse_baud(up);
 302                         /* fallthru */
 303                 case 1:
 304                         break;
 305
 306                 case 0:
 307 #ifdef CONFIG_SERIO
 308                         if (up->serio_open)
 309                                 serio_interrupt(&up->serio, ch, 0, regs);
 310 #endif
 311                         break;
 312                 };
 313         }
 314 }
 315
 316 static void sunzilog_receive_chars(struct uart_sunzilog_port *up,
 317                                    struct zilog_channel *channel,
 318                                    struct pt_regs *regs)
 319 {
 320         struct tty_struct *tty;
 321         unsigned char ch, r1;
 322
 323         tty = NULL;
 324         if (up->port.info != NULL &&            /* Unopened serial console */
 325             up->port.info->tty != NULL)         /* Keyboard || mouse */
 326                 tty = up->port.info->tty;
 327
 328         for (;;) {
 329
 330                 r1 = read_zsreg(channel, R1);
 331                 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
 332                         sbus_writeb(ERR_RES, &channel->control);
 333                         ZSDELAY();
 334                         ZS_WSYNC(channel);
 335                 }
 336
 337                 ch = sbus_readb(&channel->control);
 338                 ZSDELAY();
 339
 340                 /* This funny hack depends upon BRK_ABRT not interfering
 341                  * with the other bits we care about in R1.
 342                  */
 343                 if (ch & BRK_ABRT)
 344                         r1 |= BRK_ABRT;
 345
 346                 if (!(ch & Rx_CH_AV))
 347                         break;
 348
 349                 ch = sbus_readb(&channel->data);
 350                 ZSDELAY();
 351
 352                 ch &= up->parity_mask;
 353
 354                 if (unlikely(ZS_IS_KEYB(up)) || unlikely(ZS_IS_MOUSE(up))) {
 355                         sunzilog_kbdms_receive_chars(up, ch, 0, regs);
 356                         continue;
 357                 }
 358
 359                 if (tty == NULL) {
 360                         uart_handle_sysrq_char(&up->port, ch, regs);
 361                         continue;
 362                 }
 363
 364                 if (unlikely(tty->flip.count >= TTY_FLIPBUF_SIZE)) {
 365                         tty->flip.work.func((void *)tty);
 366                         /*
 367                          * The 8250 bails out of the loop here,
 368                          * but we need to read everything, or die.
 369                          */
 370                         if (tty->flip.count >= TTY_FLIPBUF_SIZE)
 371                                 continue;
 372                 }
 373
 374                 /* A real serial line, record the character and status.  */
 375                 *tty->flip.char_buf_ptr = ch;
 376                 *tty->flip.flag_buf_ptr = TTY_NORMAL;
 377                 up->port.icount.rx++;
 378                 if (r1 & (BRK_ABRT | PAR_ERR | Rx_OVR | CRC_ERR)) {
 379                         if (r1 & BRK_ABRT) {
 380                                 r1 &= ~(PAR_ERR | CRC_ERR);
 381                                 up->port.icount.brk++;
 382                                 if (uart_handle_break(&up->port))
 383                                         continue;
 384                         }
 385                         else if (r1 & PAR_ERR)
 386                                 up->port.icount.parity++;
 387                         else if (r1 & CRC_ERR)
 388                                 up->port.icount.frame++;
 389                         if (r1 & Rx_OVR)
 390                                 up->port.icount.overrun++;
 391                         r1 &= up->port.read_status_mask;
 392                         if (r1 & BRK_ABRT)
 393                                 *tty->flip.flag_buf_ptr = TTY_BREAK;
 394                         else if (r1 & PAR_ERR)
 395                                 *tty->flip.flag_buf_ptr = TTY_PARITY;
 396                         else if (r1 & CRC_ERR)
 397                                 *tty->flip.flag_buf_ptr = TTY_FRAME;
 398                 }
 399                 if (uart_handle_sysrq_char(&up->port, ch, regs))
 400                         continue;
 401
 402                 if (up->port.ignore_status_mask == 0xff ||
 403                     (r1 & up->port.ignore_status_mask) == 0) {
 404                         tty->flip.flag_buf_ptr++;
 405                         tty->flip.char_buf_ptr++;
 406                         tty->flip.count++;
 407                 }
 408                 if ((r1 & Rx_OVR) &&
 409                     tty->flip.count < TTY_FLIPBUF_SIZE) {
 410                         *tty->flip.flag_buf_ptr = TTY_OVERRUN;
 411                         tty->flip.flag_buf_ptr++;
 412                         tty->flip.char_buf_ptr++;
 413                         tty->flip.count++;
 414                 }
 415         }
 416
 417         if (tty)
 418                 tty_flip_buffer_push(tty);
 419 }
 420
 421 static void sunzilog_status_handle(struct uart_sunzilog_port *up,
 422                                    struct zilog_channel *channel,
 423                                    struct pt_regs *regs)
 424 {
 425         unsigned char status;
 426
 427         status = sbus_readb(&channel->control);
 428         ZSDELAY();
 429
 430         sbus_writeb(RES_EXT_INT, &channel->control);
 431         ZSDELAY();
 432         ZS_WSYNC(channel);
 433
 434         if (status & BRK_ABRT) {
 435                 if (ZS_IS_MOUSE(up))
 436                         sunzilog_kbdms_receive_chars(up, 0, 1, regs);
 437                 if (ZS_IS_CONS(up)) {
 438                         /* Wait for BREAK to deassert to avoid potentially
 439                          * confusing the PROM.
 440                          */
 441                         while (1) {
 442                                 status = sbus_readb(&channel->control);
 443                                 ZSDELAY();
 444                                 if (!(status & BRK_ABRT))
 445                                         break;
 446                         }
 447                         sun_do_break();
 448                         return;
 449                 }
 450         }
 451
 452         if (ZS_WANTS_MODEM_STATUS(up)) {
 453                 if (status & SYNC)
 454                         up->port.icount.dsr++;
 455
 456                 /* The Zilog just gives us an interrupt when DCD/CTS/etc. change.
 457                  * But it does not tell us which bit has changed, we have to keep
 458                  * track of this ourselves.
 459                  */
 460                 if ((status ^ up->prev_status) ^ DCD)
 461                         uart_handle_dcd_change(&up->port,
 462                                                (status & DCD));
 463                 if ((status ^ up->prev_status) ^ CTS)
 464                         uart_handle_cts_change(&up->port,
 465                                                (status & CTS));
 466
 467                 wake_up_interruptible(&up->port.info->delta_msr_wait);
 468         }
 469
 470         up->prev_status = status;
 471 }
 472
 473 static void sunzilog_transmit_chars(struct uart_sunzilog_port *up,
 474                                     struct zilog_channel *channel)
 475 {
 476         struct circ_buf *xmit;
 477
 478         if (ZS_IS_CONS(up)) {
 479                 unsigned char status = sbus_readb(&channel->control);
 480                 ZSDELAY();
 481
 482                 /* TX still busy?  Just wait for the next TX done interrupt.
 483                  *
 484                  * It can occur because of how we do serial console writes.  It would
 485                  * be nice to transmit console writes just like we normally would for
 486                  * a TTY line. (ie. buffered and TX interrupt driven).  That is not
 487                  * easy because console writes cannot sleep.  One solution might be
 488                  * to poll on enough port->xmit space becomming free.  -DaveM
 489                  */
 490                 if (!(status & Tx_BUF_EMP))
 491                         return;
 492         }
 493
 494         up->flags &= ~SUNZILOG_FLAG_TX_ACTIVE;
 495
 496         if (ZS_REGS_HELD(up)) {
 497                 __load_zsregs(channel, up->curregs);
 498                 up->flags &= ~SUNZILOG_FLAG_REGS_HELD;
 499         }
 500
 501         if (ZS_TX_STOPPED(up)) {
 502                 up->flags &= ~SUNZILOG_FLAG_TX_STOPPED;
 503                 goto ack_tx_int;
 504         }
 505
 506         if (up->port.x_char) {
 507                 up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
 508                 sbus_writeb(up->port.x_char, &channel->data);
 509                 ZSDELAY();
 510                 ZS_WSYNC(channel);
 511
 512                 up->port.icount.tx++;
 513                 up->port.x_char = 0;
 514                 return;
 515         }
 516
 517         if (up->port.info == NULL)
 518                 goto ack_tx_int;
 519         xmit = &up->port.info->xmit;
 520         if (uart_circ_empty(xmit)) {
 521                 uart_write_wakeup(&up->port);
 522                 goto ack_tx_int;
 523         }
 524         if (uart_tx_stopped(&up->port))
 525                 goto ack_tx_int;
 526
 527         up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
 528         sbus_writeb(xmit->buf[xmit->tail], &channel->data);
 529         ZSDELAY();
 530         ZS_WSYNC(channel);
 531
 532         xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 533         up->port.icount.tx++;
 534
 535         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 536                 uart_write_wakeup(&up->port);
 537
 538         return;
 539
 540 ack_tx_int:
 541         sbus_writeb(RES_Tx_P, &channel->control);
 542         ZSDELAY();
 543         ZS_WSYNC(channel);
 544 }
 545
 546 static irqreturn_t sunzilog_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 547 {
 548         struct uart_sunzilog_port *up = dev_id;
 549
 550         while (up) {
 551                 struct zilog_channel *channel
 552                         = ZILOG_CHANNEL_FROM_PORT(&up->port);
 553                 unsigned char r3;
 554
 555                 spin_lock(&up->port.lock);
 556                 r3 = read_zsreg(channel, R3);
 557
 558                 /* Channel A */
 559                 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
 560                         sbus_writeb(RES_H_IUS, &channel->control);
 561                         ZSDELAY();
 562                         ZS_WSYNC(channel);
 563
 564                         if (r3 & CHARxIP)
 565                                 sunzilog_receive_chars(up, channel, regs);
 566                         if (r3 & CHAEXT)
 567                                 sunzilog_status_handle(up, channel, regs);
 568                         if (r3 & CHATxIP)
 569                                 sunzilog_transmit_chars(up, channel);
 570                 }
 571                 spin_unlock(&up->port.lock);
 572
 573                 /* Channel B */
 574                 up = up->next;
 575                 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
 576
 577                 spin_lock(&up->port.lock);
 578                 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
 579                         sbus_writeb(RES_H_IUS, &channel->control);
 580                         ZSDELAY();
 581                         ZS_WSYNC(channel);
 582
 583                         if (r3 & CHBRxIP)
 584                                 sunzilog_receive_chars(up, channel, regs);
 585                         if (r3 & CHBEXT)
 586                                 sunzilog_status_handle(up, channel, regs);
 587                         if (r3 & CHBTxIP)
 588                                 sunzilog_transmit_chars(up, channel);
 589                 }
 590                 spin_unlock(&up->port.lock);
 591
 592                 up = up->next;
 593         }
 594
 595         return IRQ_HANDLED;
 596 }
 597
 598 /* A convenient way to quickly get R0 status.  The caller must _not_ hold the
 599  * port lock, it is acquired here.
 600  */
 601 static __inline__ unsigned char sunzilog_read_channel_status(struct uart_port *port)
 602 {
 603         struct zilog_channel *channel;
 604         unsigned long flags;
 605         unsigned char status;
 606
 607         spin_lock_irqsave(&port->lock, flags);
 608
 609         channel = ZILOG_CHANNEL_FROM_PORT(port);
 610         status = sbus_readb(&channel->control);
 611         ZSDELAY();
 612
 613         spin_unlock_irqrestore(&port->lock, flags);
 614
 615         return status;
 616 }
 617
 618 /* The port lock is not held.  */
 619 static unsigned int sunzilog_tx_empty(struct uart_port *port)
 620 {
 621         unsigned char status;
 622         unsigned int ret;
 623
 624         status = sunzilog_read_channel_status(port);
 625         if (status & Tx_BUF_EMP)
 626                 ret = TIOCSER_TEMT;
 627         else
 628                 ret = 0;
 629
 630         return ret;
 631 }
 632
 633 /* The port lock is not held.  */
 634 static unsigned int sunzilog_get_mctrl(struct uart_port *port)
 635 {
 636         unsigned char status;
 637         unsigned int ret;
 638
 639         status = sunzilog_read_channel_status(port);
 640
 641         ret = 0;
 642         if (status & DCD)
 643                 ret |= TIOCM_CAR;
 644         if (status & SYNC)
 645                 ret |= TIOCM_DSR;
 646         if (status & CTS)
 647                 ret |= TIOCM_CTS;
 648
 649         return ret;
 650 }
 651
 652 /* The port lock is held and interrupts are disabled.  */
 653 static void sunzilog_set_mctrl(struct uart_port *port, unsigned int mctrl)
 654 {
 655         struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
 656         struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
 657         unsigned char set_bits, clear_bits;
 658
 659         set_bits = clear_bits = 0;
 660
 661         if (mctrl & TIOCM_RTS)
 662                 set_bits |= RTS;
 663         else
 664                 clear_bits |= RTS;
 665         if (mctrl & TIOCM_DTR)
 666                 set_bits |= DTR;
 667         else
 668                 clear_bits |= DTR;
 669
 670         /* NOTE: Not subject to 'transmitter active' rule.  */
 671         up->curregs[R5] |= set_bits;
 672         up->curregs[R5] &= ~clear_bits;
 673         write_zsreg(channel, R5, up->curregs[R5]);
 674 }
 675
 676 /* The port lock is held and interrupts are disabled.  */
 677 static void sunzilog_stop_tx(struct uart_port *port, unsigned int tty_stop)
 678 {
 679         struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
 680
 681         up->flags |= SUNZILOG_FLAG_TX_STOPPED;
 682 }
 683
 684 /* The port lock is held and interrupts are disabled.  */
 685 static void sunzilog_start_tx(struct uart_port *port, unsigned int tty_start)
 686 {
 687         struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
 688         struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
 689         unsigned char status;
 690
 691         up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
 692         up->flags &= ~SUNZILOG_FLAG_TX_STOPPED;
 693
 694         status = sbus_readb(&channel->control);
 695         ZSDELAY();
 696
 697         /* TX busy?  Just wait for the TX done interrupt.  */
 698         if (!(status & Tx_BUF_EMP))
 699                 return;
 700
 701         /* Send the first character to jump-start the TX done
 702          * IRQ sending engine.
 703          */
 704         if (port->x_char) {
 705                 sbus_writeb(port->x_char, &channel->data);
 706                 ZSDELAY();
 707                 ZS_WSYNC(channel);
 708
 709                 port->icount.tx++;
 710                 port->x_char = 0;
 711         } else {
 712                 struct circ_buf *xmit = &port->info->xmit;
 713
 714                 sbus_writeb(xmit->buf[xmit->tail], &channel->data);
 715                 ZSDELAY();
 716                 ZS_WSYNC(channel);
 717
 718                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 719                 port->icount.tx++;
 720
 721                 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 722                         uart_write_wakeup(&up->port);
 723         }
 724 }
 725
 726 /* The port lock is held.  */
 727 static void sunzilog_stop_rx(struct uart_port *port)
 728 {
 729         struct uart_sunzilog_port *up = UART_ZILOG(port);
 730         struct zilog_channel *channel;
 731
 732         if (ZS_IS_CONS(up))
 733                 return;
 734
 735         channel = ZILOG_CHANNEL_FROM_PORT(port);
 736
 737         /* Disable all RX interrupts.  */
 738         up->curregs[R1] &= ~RxINT_MASK;
 739         sunzilog_maybe_update_regs(up, channel);
 740 }
 741
 742 /* The port lock is held.  */
 743 static void sunzilog_enable_ms(struct uart_port *port)
 744 {
 745         struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
 746         struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
 747         unsigned char new_reg;
 748
 749         new_reg = up->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
 750         if (new_reg != up->curregs[R15]) {
 751                 up->curregs[R15] = new_reg;
 752
 753                 /* NOTE: Not subject to 'transmitter active' rule.  */
 754                 write_zsreg(channel, R15, up->curregs[R15]);
 755         }
 756 }
 757
 758 /* The port lock is not held.  */
 759 static void sunzilog_break_ctl(struct uart_port *port, int break_state)
 760 {
 761         struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
 762         struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
 763         unsigned char set_bits, clear_bits, new_reg;
 764         unsigned long flags;
 765
 766         set_bits = clear_bits = 0;
 767
 768         if (break_state)
 769                 set_bits |= SND_BRK;
 770         else
 771                 clear_bits |= SND_BRK;
 772
 773         spin_lock_irqsave(&port->lock, flags);
 774
 775         new_reg = (up->curregs[R5] | set_bits) & ~clear_bits;
 776         if (new_reg != up->curregs[R5]) {
 777                 up->curregs[R5] = new_reg;
 778
 779                 /* NOTE: Not subject to 'transmitter active' rule.  */
 780                 write_zsreg(channel, R5, up->curregs[R5]);
 781         }
 782
 783         spin_unlock_irqrestore(&port->lock, flags);
 784 }
 785
 786 static void __sunzilog_startup(struct uart_sunzilog_port *up)
 787 {
 788         struct zilog_channel *channel;
 789
 790         channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
 791         up->prev_status = sbus_readb(&channel->control);
 792
 793         /* Enable receiver and transmitter.  */
 794         up->curregs[R3] |= RxENAB;
 795         up->curregs[R5] |= TxENAB;
 796
 797         up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
 798         sunzilog_maybe_update_regs(up, channel);
 799 }
 800
 801 static int sunzilog_startup(struct uart_port *port)
 802 {
 803         struct uart_sunzilog_port *up = UART_ZILOG(port);
 804         unsigned long flags;
 805
 806         if (ZS_IS_CONS(up))
 807                 return 0;
 808
 809         spin_lock_irqsave(&port->lock, flags);
 810         __sunzilog_startup(up);
 811         spin_unlock_irqrestore(&port->lock, flags);
 812         return 0;
 813 }
 814
 815 /*
 816  * The test for ZS_IS_CONS is explained by the following e-mail:
 817  *****
 818  * From: Russell King <rmk@arm.linux.org.uk>
 819  * Date: Sun, 8 Dec 2002 10:18:38 +0000
 820  *
 821  * On Sun, Dec 08, 2002 at 02:43:36AM -0500, Pete Zaitcev wrote:
 822  * > I boot my 2.5 boxes using "console=ttyS0,9600" argument,
 823  * > and I noticed that something is not right with reference
 824  * > counting in this case. It seems that when the console
 825  * > is open by kernel initially, this is not accounted
 826  * > as an open, and uart_startup is not called.
 827  *
 828  * That is correct.  We are unable to call uart_startup when the serial
 829  * console is initialised because it may need to allocate memory (as
 830  * request_irq does) and the memory allocators may not have been
 831  * initialised.
 832  *
 833  * 1. initialise the port into a state where it can send characters in the
 834  *    console write method.
 835  *
 836  * 2. don't do the actual hardware shutdown in your shutdown() method (but
 837  *    do the normal software shutdown - ie, free irqs etc)
 838  *****
 839  */
 840 static void sunzilog_shutdown(struct uart_port *port)
 841 {
 842         struct uart_sunzilog_port *up = UART_ZILOG(port);
 843         struct zilog_channel *channel;
 844         unsigned long flags;
 845
 846         if (ZS_IS_CONS(up))
 847                 return;
 848
 849         spin_lock_irqsave(&port->lock, flags);
 850
 851         channel = ZILOG_CHANNEL_FROM_PORT(port);
 852
 853         /* Disable receiver and transmitter.  */
 854         up->curregs[R3] &= ~RxENAB;
 855         up->curregs[R5] &= ~TxENAB;
 856
 857         /* Disable all interrupts and BRK assertion.  */
 858         up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
 859         up->curregs[R5] &= ~SND_BRK;
 860         sunzilog_maybe_update_regs(up, channel);
 861
 862         spin_unlock_irqrestore(&port->lock, flags);
 863 }
 864
 865 /* Shared by TTY driver and serial console setup.  The port lock is held
 866  * and local interrupts are disabled.
 867  */
 868 static void
 869 sunzilog_convert_to_zs(struct uart_sunzilog_port *up, unsigned int cflag,
 870                        unsigned int iflag, int brg)
 871 {
 872
 873         up->curregs[R10] = NRZ;
 874         up->curregs[R11] = TCBR | RCBR;
 875
 876         /* Program BAUD and clock source. */
 877         up->curregs[R4] &= ~XCLK_MASK;
 878         up->curregs[R4] |= X16CLK;
 879         up->curregs[R12] = brg & 0xff;
 880         up->curregs[R13] = (brg >> 8) & 0xff;
 881         up->curregs[R14] = BRSRC | BRENAB;
 882
 883         /* Character size, stop bits, and parity. */
 884         up->curregs[3] &= ~RxN_MASK;
 885         up->curregs[5] &= ~TxN_MASK;
 886         switch (cflag & CSIZE) {
 887         case CS5:
 888                 up->curregs[3] |= Rx5;
 889                 up->curregs[5] |= Tx5;
 890                 up->parity_mask = 0x1f;
 891                 break;
 892         case CS6:
 893                 up->curregs[3] |= Rx6;
 894                 up->curregs[5] |= Tx6;
 895                 up->parity_mask = 0x3f;
 896                 break;
 897         case CS7:
 898                 up->curregs[3] |= Rx7;
 899                 up->curregs[5] |= Tx7;
 900                 up->parity_mask = 0x7f;
 901                 break;
 902         case CS8:
 903         default:
 904                 up->curregs[3] |= Rx8;
 905                 up->curregs[5] |= Tx8;
 906                 up->parity_mask = 0xff;
 907                 break;
 908         };
 909         up->curregs[4] &= ~0x0c;
 910         if (cflag & CSTOPB)
 911                 up->curregs[4] |= SB2;
 912         else
 913                 up->curregs[4] |= SB1;
 914         if (cflag & PARENB)
 915                 up->curregs[4] |= PAR_ENAB;
 916         else
 917                 up->curregs[4] &= ~PAR_ENAB;
 918         if (!(cflag & PARODD))
 919                 up->curregs[4] |= PAR_EVEN;
 920         else
 921                 up->curregs[4] &= ~PAR_EVEN;
 922
 923         up->port.read_status_mask = Rx_OVR;
 924         if (iflag & INPCK)
 925                 up->port.read_status_mask |= CRC_ERR | PAR_ERR;
 926         if (iflag & (BRKINT | PARMRK))
 927                 up->port.read_status_mask |= BRK_ABRT;
 928
 929         up->port.ignore_status_mask = 0;
 930         if (iflag & IGNPAR)
 931                 up->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
 932         if (iflag & IGNBRK) {
 933                 up->port.ignore_status_mask |= BRK_ABRT;
 934                 if (iflag & IGNPAR)
 935                         up->port.ignore_status_mask |= Rx_OVR;
 936         }
 937
 938         if ((cflag & CREAD) == 0)
 939                 up->port.ignore_status_mask = 0xff;
 940 }
 941
 942 /* The port lock is not held.  */
 943 static void
 944 sunzilog_set_termios(struct uart_port *port, struct termios *termios,
 945                      struct termios *old)
 946 {
 947         struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
 948         unsigned long flags;
 949         int baud, brg;
 950
 951         baud = uart_get_baud_rate(port, termios, old, 1200, 76800);
 952
 953         spin_lock_irqsave(&up->port.lock, flags);
 954
 955         brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
 956
 957         sunzilog_convert_to_zs(up, termios->c_cflag, termios->c_iflag, brg);
 958
 959         if (UART_ENABLE_MS(&up->port, termios->c_cflag))
 960                 up->flags |= SUNZILOG_FLAG_MODEM_STATUS;
 961         else
 962                 up->flags &= ~SUNZILOG_FLAG_MODEM_STATUS;
 963
 964         up->cflag = termios->c_cflag;
 965
 966         sunzilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port));
 967
 968         spin_unlock_irqrestore(&up->port.lock, flags);
 969 }
 970
 971 static const char *sunzilog_type(struct uart_port *port)
 972 {
 973         return "SunZilog";
 974 }
 975
 976 /* We do not request/release mappings of the registers here, this
 977  * happens at early serial probe time.
 978  */
 979 static void sunzilog_release_port(struct uart_port *port)
 980 {
 981 }
 982
 983 static int sunzilog_request_port(struct uart_port *port)
 984 {
 985         return 0;
 986 }
 987
 988 /* These do not need to do anything interesting either.  */
 989 static void sunzilog_config_port(struct uart_port *port, int flags)
 990 {
 991 }
 992
 993 /* We do not support letting the user mess with the divisor, IRQ, etc. */
 994 static int sunzilog_verify_port(struct uart_port *port, struct serial_struct *ser)
 995 {
 996         return -EINVAL;
 997 }
 998
 999 static struct uart_ops sunzilog_pops = {
1000         .tx_empty       =       sunzilog_tx_empty,
1001         .set_mctrl      =       sunzilog_set_mctrl,
1002         .get_mctrl      =       sunzilog_get_mctrl,
1003         .stop_tx        =       sunzilog_stop_tx,
1004         .start_tx       =       sunzilog_start_tx,
1005         .stop_rx        =       sunzilog_stop_rx,
1006         .enable_ms      =       sunzilog_enable_ms,
1007         .break_ctl      =       sunzilog_break_ctl,
1008         .startup        =       sunzilog_startup,
1009         .shutdown       =       sunzilog_shutdown,
1010         .set_termios    =       sunzilog_set_termios,
1011         .type           =       sunzilog_type,
1012         .release_port   =       sunzilog_release_port,
1013         .request_port   =       sunzilog_request_port,
1014         .config_port    =       sunzilog_config_port,
1015         .verify_port    =       sunzilog_verify_port,
1016 };
1017
1018 static struct uart_sunzilog_port *sunzilog_port_table;
1019 static struct zilog_layout **sunzilog_chip_regs;
1020
1021 static struct uart_sunzilog_port *sunzilog_irq_chain;
1022 static int zilog_irq = -1;
1023
1024 static struct uart_driver sunzilog_reg = {
1025         .owner          =       THIS_MODULE,
1026         .driver_name    =       "ttyS",
1027         .devfs_name     =       "tts/",
1028         .dev_name       =       "ttyS",
1029         .major          =       TTY_MAJOR,
1030 };
1031
1032 static void * __init alloc_one_table(unsigned long size)
1033 {
1034         void *ret;
1035
1036         ret = kmalloc(size, GFP_KERNEL);
1037         if (ret != NULL)
1038                 memset(ret, 0, size);
1039
1040         return ret;
1041 }
1042
1043 static void __init sunzilog_alloc_tables(void)
1044 {
1045         sunzilog_port_table = (struct uart_sunzilog_port *)
1046                 alloc_one_table(NUM_CHANNELS * sizeof(struct uart_sunzilog_port));
1047         sunzilog_chip_regs = (struct zilog_layout **)
1048                 alloc_one_table(NUM_SUNZILOG * sizeof(struct zilog_layout *));
1049
1050         if (sunzilog_port_table == NULL || sunzilog_chip_regs == NULL) {
1051                 prom_printf("SunZilog: Cannot allocate tables.\n");
1052                 prom_halt();
1053         }
1054 }
1055
1056 #ifdef CONFIG_SPARC64
1057
1058 /* We used to attempt to use the address property of the Zilog device node
1059  * but that totally is not necessary on sparc64.
1060  */
1061 static struct zilog_layout * __init get_zs_sun4u(int chip, int zsnode)
1062 {
1063         unsigned long mapped_addr;
1064         unsigned int sun4u_ino;
1065         struct sbus_bus *sbus = NULL;
1066         struct sbus_dev *sdev = NULL;
1067         int err;
1068
1069         if (central_bus == NULL) {
1070                 for_each_sbus(sbus) {
1071                         for_each_sbusdev(sdev, sbus) {
1072                                 if (sdev->prom_node == zsnode)
1073                                         goto found;
1074                         }
1075                 }
1076         }
1077  found:
1078         if (sdev == NULL && central_bus == NULL) {
1079                 prom_printf("SunZilog: sdev&&central == NULL for "
1080                             "Zilog %d in get_zs_sun4u.\n", chip);
1081                 prom_halt();
1082         }
1083         if (central_bus == NULL) {
1084                 mapped_addr =
1085                         sbus_ioremap(&sdev->resource[0], 0,
1086                                      PAGE_SIZE,
1087                                      "Zilog Registers");
1088         } else {
1089                 struct linux_prom_registers zsregs[1];
1090
1091                 err = prom_getproperty(zsnode, "reg",
1092                                        (char *) &zsregs[0],
1093                                        sizeof(zsregs));
1094                 if (err == -1) {
1095                         prom_printf("SunZilog: Cannot map "
1096                                     "Zilog %d regs on "
1097                                     "central bus.\n", chip);
1098                         prom_halt();
1099                 }
1100                 apply_fhc_ranges(central_bus->child,
1101                                  &zsregs[0], 1);
1102                 apply_central_ranges(central_bus, &zsregs[0], 1);
1103                 mapped_addr =
1104                         (((u64)zsregs[0].which_io)<<32UL) |
1105                         ((u64)zsregs[0].phys_addr);
1106         }
1107
1108         if (zilog_irq == -1) {
1109                 if (central_bus) {
1110                         unsigned long iclr, imap;
1111
1112                         iclr = central_bus->child->fhc_regs.uregs
1113                                 + FHC_UREGS_ICLR;
1114                         imap = central_bus->child->fhc_regs.uregs
1115                                 + FHC_UREGS_IMAP;
1116                         zilog_irq = build_irq(12, 0, iclr, imap);
1117                 } else {
1118                         err = prom_getproperty(zsnode, "interrupts",
1119                                                (char *) &sun4u_ino,
1120                                                sizeof(sun4u_ino));
1121                         zilog_irq = sbus_build_irq(sbus_root, sun4u_ino);
1122                 }
1123         }
1124
1125         return (struct zilog_layout *) mapped_addr;
1126 }
1127 #else /* CONFIG_SPARC64 */
1128
1129 /*
1130  * XXX The sun4d case is utterly screwed: it tries to re-walk the tree
1131  * (for the 3rd time) in order to find bootbus and cpu. Streamline it.
1132  */
1133 static struct zilog_layout * __init get_zs_sun4cmd(int chip, int node)
1134 {
1135         struct linux_prom_irqs irq_info[2];
1136         unsigned long mapped_addr = 0;
1137         int zsnode, cpunode, bbnode;
1138         struct linux_prom_registers zsreg[4];
1139         struct resource res;
1140
1141         if (sparc_cpu_model == sun4d) {
1142                 int walk;
1143
1144                 zsnode = 0;
1145                 bbnode = 0;
1146                 cpunode = 0;
1147                 for (walk = prom_getchild(prom_root_node);
1148                      (walk = prom_searchsiblings(walk, "cpu-unit")) != 0;
1149                      walk = prom_getsibling(walk)) {
1150                         bbnode = prom_getchild(walk);
1151                         if (bbnode &&
1152                             (bbnode = prom_searchsiblings(bbnode, "bootbus"))) {
1153                                 if ((zsnode = prom_getchild(bbnode)) == node) {
1154                                         cpunode = walk;
1155                                         break;
1156                                 }
1157                         }
1158                 }
1159                 if (!walk) {
1160                         prom_printf("SunZilog: Cannot find the %d'th bootbus on sun4d.\n",
1161                                     (chip / 2));
1162                         prom_halt();
1163                 }
1164
1165                 if (prom_getproperty(zsnode, "reg",
1166                                      (char *) zsreg, sizeof(zsreg)) == -1) {
1167                         prom_printf("SunZilog: Cannot map Zilog %d\n", chip);
1168                         prom_halt();
1169                 }
1170                 /* XXX Looks like an off by one? */
1171                 prom_apply_generic_ranges(bbnode, cpunode, zsreg, 1);
1172                 res.start = zsreg[0].phys_addr;
1173                 res.end = res.start + (8 - 1);
1174                 res.flags = zsreg[0].which_io | IORESOURCE_IO;
1175                 mapped_addr = sbus_ioremap(&res, 0, 8, "Zilog Serial");
1176
1177         } else {
1178                 zsnode = node;
1179
1180 #if 0 /* XXX When was this used? */
1181                 if (prom_getintdefault(zsnode, "slave", -1) != chipid) {
1182                         zsnode = prom_getsibling(zsnode);
1183                         continue;
1184                 }
1185 #endif
1186
1187                 /*
1188                  * "address" is only present on ports that OBP opened
1189                  * (from Mitch Bradley's "Hitchhiker's Guide to OBP").
1190                  * We do not use it.
1191                  */
1192
1193                 if (prom_getproperty(zsnode, "reg",
1194                                      (char *) zsreg, sizeof(zsreg)) == -1) {
1195                         prom_printf("SunZilog: Cannot map Zilog %d\n", chip);
1196                         prom_halt();
1197                 }
1198                 if (sparc_cpu_model == sun4m)   /* Crude. Pass parent. XXX */
1199                         prom_apply_obio_ranges(zsreg, 1);
1200                 res.start = zsreg[0].phys_addr;
1201                 res.end = res.start + (8 - 1);
1202                 res.flags = zsreg[0].which_io | IORESOURCE_IO;
1203                 mapped_addr = sbus_ioremap(&res, 0, 8, "Zilog Serial");
1204         }
1205
1206         if (prom_getproperty(zsnode, "intr",
1207                              (char *) irq_info, sizeof(irq_info))
1208                     % sizeof(struct linux_prom_irqs)) {
1209                 prom_printf("SunZilog: Cannot get IRQ property for Zilog %d.\n",
1210                             chip);
1211                 prom_halt();
1212         }
1213         if (zilog_irq == -1) {
1214                 zilog_irq = irq_info[0].pri;
1215         } else if (zilog_irq != irq_info[0].pri) {
1216                 /* XXX. Dumb. Should handle per-chip IRQ, for add-ons. */
1217                 prom_printf("SunZilog: Inconsistent IRQ layout for Zilog %d.\n",
1218                             chip);
1219                 prom_halt();
1220         }
1221
1222         return (struct zilog_layout *) mapped_addr;
1223 }
1224 #endif /* !(CONFIG_SPARC64) */
1225
1226 /* Get the address of the registers for SunZilog instance CHIP.  */
1227 static struct zilog_layout * __init get_zs(int chip, int node)
1228 {
1229         if (chip < 0 || chip >= NUM_SUNZILOG) {
1230                 prom_printf("SunZilog: Illegal chip number %d in get_zs.\n", chip);
1231                 prom_halt();
1232         }
1233
1234 #ifdef CONFIG_SPARC64
1235         return get_zs_sun4u(chip, node);
1236 #else
1237
1238         if (sparc_cpu_model == sun4) {
1239                 struct resource res;
1240
1241                 /* Not probe-able, hard code it. */
1242                 switch (chip) {
1243                 case 0:
1244                         res.start = 0xf1000000;
1245                         break;
1246                 case 1:
1247                         res.start = 0xf0000000;
1248                         break;
1249                 };
1250                 zilog_irq = 12;
1251                 res.end = (res.start + (8 - 1));
1252                 res.flags = IORESOURCE_IO;
1253                 return (struct zilog_layout *) sbus_ioremap(&res, 0, 8, "SunZilog");
1254         }
1255
1256         return get_zs_sun4cmd(chip, node);
1257 #endif
1258 }
1259
1260 #define ZS_PUT_CHAR_MAX_DELAY   2000    /* 10 ms */
1261
1262 static void sunzilog_put_char(struct zilog_channel *channel, unsigned char ch)
1263 {
1264         int loops = ZS_PUT_CHAR_MAX_DELAY;
1265
1266         /* This is a timed polling loop so do not switch the explicit
1267          * udelay with ZSDELAY as that is a NOP on some platforms.  -DaveM
1268          */
1269         do {
1270                 unsigned char val = sbus_readb(&channel->control);
1271                 if (val & Tx_BUF_EMP) {
1272                         ZSDELAY();
1273                         break;
1274                 }
1275                 udelay(5);
1276         } while (--loops);
1277
1278         sbus_writeb(ch, &channel->data);
1279         ZSDELAY();
1280         ZS_WSYNC(channel);
1281 }
1282
1283 #ifdef CONFIG_SERIO
1284
1285 static spinlock_t sunzilog_serio_lock = SPIN_LOCK_UNLOCKED;
1286
1287 static int sunzilog_serio_write(struct serio *serio, unsigned char ch)
1288 {
1289         struct uart_sunzilog_port *up = serio->driver;
1290         unsigned long flags;
1291
1292         spin_lock_irqsave(&sunzilog_serio_lock, flags);
1293
1294         sunzilog_put_char(ZILOG_CHANNEL_FROM_PORT(&up->port), ch);
1295
1296         spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1297
1298         return 0;
1299 }
1300
1301 static int sunzilog_serio_open(struct serio *serio)
1302 {
1303         struct uart_sunzilog_port *up = serio->driver;
1304         unsigned long flags;
1305         int ret;
1306
1307         spin_lock_irqsave(&sunzilog_serio_lock, flags);
1308         if (!up->serio_open) {
1309                 up->serio_open = 1;
1310                 ret = 0;
1311         } else
1312                 ret = -EBUSY;
1313         spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1314
1315         return ret;
1316 }
1317
1318 static void sunzilog_serio_close(struct serio *serio)
1319 {
1320         struct uart_sunzilog_port *up = serio->driver;
1321         unsigned long flags;
1322
1323         spin_lock_irqsave(&sunzilog_serio_lock, flags);
1324         up->serio_open = 0;
1325         spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1326 }
1327
1328 #endif /* CONFIG_SERIO */
1329
1330 #ifdef CONFIG_SERIAL_SUNZILOG_CONSOLE
1331 static void
1332 sunzilog_console_write(struct console *con, const char *s, unsigned int count)
1333 {
1334         struct uart_sunzilog_port *up = &sunzilog_port_table[con->index];
1335         struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
1336         unsigned long flags;
1337         int i;
1338
1339         spin_lock_irqsave(&up->port.lock, flags);
1340         for (i = 0; i < count; i++, s++) {
1341                 sunzilog_put_char(channel, *s);
1342                 if (*s == 10)
1343                         sunzilog_put_char(channel, 13);
1344         }
1345         udelay(2);
1346         spin_unlock_irqrestore(&up->port.lock, flags);
1347 }
1348
1349 static int __init sunzilog_console_setup(struct console *con, char *options)
1350 {
1351         struct uart_sunzilog_port *up = &sunzilog_port_table[con->index];
1352         unsigned long flags;
1353         int baud, brg;
1354
1355         printk(KERN_INFO "Console: ttyS%d (SunZilog zs%d)\n",
1356                (sunzilog_reg.minor - 64) + con->index, con->index);
1357
1358         /* Get firmware console settings.  */
1359         sunserial_console_termios(con);
1360
1361         /* Firmware console speed is limited to 150-->38400 baud so
1362          * this hackish cflag thing is OK.
1363          */
1364         switch (con->cflag & CBAUD) {
1365         case B150: baud = 150; break;
1366         case B300: baud = 300; break;
1367         case B600: baud = 600; break;
1368         case B1200: baud = 1200; break;
1369         case B2400: baud = 2400; break;
1370         case B4800: baud = 4800; break;
1371         default: case B9600: baud = 9600; break;
1372         case B19200: baud = 19200; break;
1373         case B38400: baud = 38400; break;
1374         };
1375
1376         brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1377
1378         spin_lock_irqsave(&up->port.lock, flags);
1379
1380         up->curregs[R15] = BRKIE;
1381         sunzilog_convert_to_zs(up, con->cflag, 0, brg);
1382
1383         sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
1384         __sunzilog_startup(up);
1385
1386         spin_unlock_irqrestore(&up->port.lock, flags);
1387
1388         return 0;
1389 }
1390
1391 static struct console sunzilog_console = {
1392         .name   =       "ttyS",
1393         .write  =       sunzilog_console_write,
1394         .device =       uart_console_device,
1395         .setup  =       sunzilog_console_setup,
1396         .flags  =       CON_PRINTBUFFER,
1397         .index  =       -1,
1398         .data   =       &sunzilog_reg,
1399 };
1400 #define SUNZILOG_CONSOLE        (&sunzilog_console)
1401
1402 static int __init sunzilog_console_init(void)
1403 {
1404         int i;
1405
1406         if (con_is_present())
1407                 return 0;
1408
1409         for (i = 0; i < NUM_CHANNELS; i++) {
1410                 int this_minor = sunzilog_reg.minor + i;
1411
1412                 if ((this_minor - 64) == (serial_console - 1))
1413                         break;
1414         }
1415         if (i == NUM_CHANNELS)
1416                 return 0;
1417
1418         sunzilog_console.index = i;
1419         sunzilog_port_table[i].flags |= SUNZILOG_FLAG_IS_CONS;
1420         register_console(&sunzilog_console);
1421         return 0;
1422 }
1423 #else
1424 #define SUNZILOG_CONSOLE        (NULL)
1425 #define sunzilog_console_init() do { } while (0)
1426 #endif
1427
1428 /*
1429  * We scan the PROM tree recursively. This is the most reliable way
1430  * to find Zilog nodes on various platforms. However, we face an extreme
1431  * shortage of kernel stack, so we must be very careful. To that end,
1432  * we scan only to a certain depth, and we use a common property buffer
1433  * in the scan structure.
1434  */
1435 #define ZS_PROPSIZE  128
1436 #define ZS_SCAN_DEPTH   5
1437
1438 struct zs_probe_scan {
1439         int depth;
1440         void (*scanner)(struct zs_probe_scan *t, int node);
1441
1442         int devices;
1443         char prop[ZS_PROPSIZE];
1444 };
1445
1446 static int __inline__ sunzilog_node_ok(int node, const char *name, int len)
1447 {
1448         if (strncmp(name, "zs", len) == 0)
1449                 return 1;
1450         /* Don't fold this procedure just yet. Compare to su_node_ok(). */
1451         return 0;
1452 }
1453
1454 static void __init sunzilog_scan(struct zs_probe_scan *t, int node)
1455 {
1456         int len;
1457
1458         for (; node != 0; node = prom_getsibling(node)) {
1459                 len = prom_getproperty(node, "name", t->prop, ZS_PROPSIZE);
1460                 if (len <= 1)
1461                         continue;               /* Broken PROM node */
1462                 if (sunzilog_node_ok(node, t->prop, len)) {
1463                         (*t->scanner)(t, node);
1464                 } else {
1465                         if (t->depth < ZS_SCAN_DEPTH) {
1466                                 t->depth++;
1467                                 sunzilog_scan(t, prom_getchild(node));
1468                                 --t->depth;
1469                         }
1470                 }
1471         }
1472 }
1473
1474 static void __init sunzilog_prepare(void)
1475 {
1476         struct uart_sunzilog_port *up;
1477         struct zilog_layout *rp;
1478         int channel, chip;
1479
1480         /*
1481          * Temporary fix.
1482          */
1483         for (channel = 0; channel < NUM_CHANNELS; channel++)
1484                 spin_lock_init(&sunzilog_port_table[channel].port.lock);
1485
1486         sunzilog_irq_chain = up = &sunzilog_port_table[0];
1487         for (channel = 0; channel < NUM_CHANNELS - 1; channel++)
1488                 up[channel].next = &up[channel + 1];
1489         up[channel].next = NULL;
1490
1491         for (chip = 0; chip < NUM_SUNZILOG; chip++) {
1492                 rp = sunzilog_chip_regs[chip];
1493                 up[(chip * 2) + 0].port.membase = (char *) &rp->channelA;
1494                 up[(chip * 2) + 1].port.membase = (char *) &rp->channelB;
1495
1496                 /* Channel A */
1497                 up[(chip * 2) + 0].port.iotype = SERIAL_IO_MEM;
1498                 up[(chip * 2) + 0].port.irq = zilog_irq;
1499                 up[(chip * 2) + 0].port.uartclk = ZS_CLOCK;
1500                 up[(chip * 2) + 0].port.fifosize = 1;
1501                 up[(chip * 2) + 0].port.ops = &sunzilog_pops;
1502                 up[(chip * 2) + 0].port.type = PORT_SUNZILOG;
1503                 up[(chip * 2) + 0].port.flags = 0;
1504                 up[(chip * 2) + 0].port.line = (chip * 2) + 0;
1505                 up[(chip * 2) + 0].flags |= SUNZILOG_FLAG_IS_CHANNEL_A;
1506
1507                 /* Channel B */
1508                 up[(chip * 2) + 1].port.iotype = SERIAL_IO_MEM;
1509                 up[(chip * 2) + 1].port.irq = zilog_irq;
1510                 up[(chip * 2) + 1].port.uartclk = ZS_CLOCK;
1511                 up[(chip * 2) + 1].port.fifosize = 1;
1512                 up[(chip * 2) + 1].port.ops = &sunzilog_pops;
1513                 up[(chip * 2) + 1].port.type = PORT_SUNZILOG;
1514                 up[(chip * 2) + 1].port.flags = 0;
1515                 up[(chip * 2) + 1].port.line = (chip * 2) + 1;
1516                 up[(chip * 2) + 1].flags |= 0;
1517         }
1518 }
1519
1520 static void __init sunzilog_init_kbdms(struct uart_sunzilog_port *up, int channel)
1521 {
1522         int baud, brg;
1523
1524         if (channel == KEYBOARD_LINE) {
1525                 up->flags |= SUNZILOG_FLAG_CONS_KEYB;
1526                 up->cflag = B1200 | CS8 | CLOCAL | CREAD;
1527                 baud = 1200;
1528         } else {
1529                 up->flags |= SUNZILOG_FLAG_CONS_MOUSE;
1530                 up->cflag = B4800 | CS8 | CLOCAL | CREAD;
1531                 baud = 4800;
1532         }
1533         printk(KERN_INFO "zs%d at 0x%p (irq = %s) is a SunZilog\n",
1534                channel, up->port.membase, __irq_itoa(zilog_irq));
1535
1536         up->curregs[R15] = BRKIE;
1537         brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1538         sunzilog_convert_to_zs(up, up->cflag, 0, brg);
1539
1540 #ifdef CONFIG_SERIO
1541         memset(&up->serio, 0, sizeof(up->serio));
1542
1543         up->serio.driver = up;
1544
1545         up->serio.type = SERIO_RS232;
1546         if (channel == KEYBOARD_LINE) {
1547                 up->serio.type |= SERIO_SUNKBD;
1548                 up->serio.name = "zskbd";
1549         } else {
1550                 up->serio.type |= (SERIO_SUN | (1 << 16));
1551                 up->serio.name = "zsms";
1552         }
1553         up->serio.phys = (channel == KEYBOARD_LINE ?
1554                           "zs/serio0" : "zs/serio1");
1555
1556         up->serio.write = sunzilog_serio_write;
1557         up->serio.open = sunzilog_serio_open;
1558         up->serio.close = sunzilog_serio_close;
1559
1560         serio_register_port(&up->serio);
1561 #endif
1562
1563         sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
1564         __sunzilog_startup(up);
1565 }
1566
1567 static void __init sunzilog_init_hw(void)
1568 {
1569         int i;
1570
1571         for (i = 0; i < NUM_CHANNELS; i++) {
1572                 struct uart_sunzilog_port *up = &sunzilog_port_table[i];
1573                 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
1574                 unsigned long flags;
1575                 int baud, brg;
1576
1577                 spin_lock_irqsave(&up->port.lock, flags);
1578
1579                 if (ZS_IS_CHANNEL_A(up)) {
1580                         write_zsreg(channel, R9, FHWRES);
1581                         ZSDELAY_LONG();
1582                         (void) read_zsreg(channel, R0);
1583                 }
1584
1585                 if (i == KEYBOARD_LINE || i == MOUSE_LINE) {
1586                         sunzilog_init_kbdms(up, i);
1587                         up->curregs[R9] |= (NV | MIE);
1588                         write_zsreg(channel, R9, up->curregs[R9]);
1589                 } else {
1590                         /* Normal serial TTY. */
1591                         up->parity_mask = 0xff;
1592                         up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1593                         up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1594                         up->curregs[R3] = RxENAB | Rx8;
1595                         up->curregs[R5] = TxENAB | Tx8;
1596                         up->curregs[R9] = NV | MIE;
1597                         up->curregs[R10] = NRZ;
1598                         up->curregs[R11] = TCBR | RCBR;
1599                         baud = 9600;
1600                         brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1601                         up->curregs[R12] = (brg & 0xff);
1602                         up->curregs[R13] = (brg >> 8) & 0xff;
1603                         up->curregs[R14] = BRSRC | BRENAB;
1604                         __load_zsregs(channel, up->curregs);
1605                         write_zsreg(channel, R9, up->curregs[R9]);
1606                 }
1607
1608                 spin_unlock_irqrestore(&up->port.lock, flags);
1609         }
1610 }
1611
1612 static struct zilog_layout * __init get_zs(int chip, int node);
1613
1614 static void __init sunzilog_scan_probe(struct zs_probe_scan *t, int node)
1615 {
1616         sunzilog_chip_regs[t->devices] = get_zs(t->devices, node);
1617         t->devices++;
1618 }
1619
1620 static int __init sunzilog_ports_init(void)
1621 {
1622         struct zs_probe_scan scan;
1623         int ret;
1624         int uart_count;
1625         int i;
1626
1627         printk(KERN_DEBUG "SunZilog: %d chips.\n", NUM_SUNZILOG);
1628
1629         scan.scanner = sunzilog_scan_probe;
1630         scan.depth = 0;
1631         scan.devices = 0;
1632         sunzilog_scan(&scan, prom_getchild(prom_root_node));
1633
1634         sunzilog_prepare();
1635
1636         if (request_irq(zilog_irq, sunzilog_interrupt, SA_SHIRQ,
1637                         "SunZilog", sunzilog_irq_chain)) {
1638                 prom_printf("SunZilog: Unable to register zs interrupt handler.\n");
1639                 prom_halt();
1640         }
1641
1642         sunzilog_init_hw();
1643
1644         /* We can only init this once we have probed the Zilogs
1645          * in the system. Do not count channels assigned to keyboards
1646          * or mice when we are deciding how many ports to register.
1647          */
1648         uart_count = 0;
1649         for (i = 0; i < NUM_CHANNELS; i++) {
1650                 struct uart_sunzilog_port *up = &sunzilog_port_table[i];
1651
1652                 if (ZS_IS_KEYB(up) || ZS_IS_MOUSE(up))
1653                         continue;
1654
1655                 uart_count++;
1656         }
1657
1658         sunzilog_reg.nr = uart_count;
1659         sunzilog_reg.cons = SUNZILOG_CONSOLE;
1660
1661         sunzilog_reg.minor = sunserial_current_minor;
1662         sunserial_current_minor += uart_count;
1663
1664         ret = uart_register_driver(&sunzilog_reg);
1665         if (ret == 0) {
1666                 for (i = 0; i < NUM_CHANNELS; i++) {
1667                         struct uart_sunzilog_port *up = &sunzilog_port_table[i];
1668
1669                         if (ZS_IS_KEYB(up) || ZS_IS_MOUSE(up))
1670                                 continue;
1671
1672                         if (uart_add_one_port(&sunzilog_reg, &up->port)) {
1673                                 printk(KERN_ERR
1674                                     "SunZilog: failed to add port zs%d\n", i);
1675                         }
1676                 }
1677         }
1678
1679         return ret;
1680 }
1681
1682 static void __init sunzilog_scan_count(struct zs_probe_scan *t, int node)
1683 {
1684         t->devices++;
1685 }
1686
1687 static int __init sunzilog_ports_count(void)
1688 {
1689         struct zs_probe_scan scan;
1690
1691         /* Sun4 Zilog setup is hard coded, no probing to do.  */
1692         if (sparc_cpu_model == sun4)
1693                 return 2;
1694
1695         scan.scanner = sunzilog_scan_count;
1696         scan.depth = 0;
1697         scan.devices = 0;
1698
1699         sunzilog_scan(&scan, prom_getchild(prom_root_node));
1700
1701         return scan.devices;
1702 }
1703
1704 static int __init sunzilog_init(void)
1705 {
1706
1707         NUM_SUNZILOG = sunzilog_ports_count();
1708         if (NUM_SUNZILOG == 0)
1709                 return -ENODEV;
1710
1711         sunzilog_alloc_tables();
1712
1713         sunzilog_ports_init();
1714         sunzilog_console_init();
1715
1716         return 0;
1717 }
1718
1719 static void __exit sunzilog_exit(void)
1720 {
1721         int i;
1722
1723         for (i = 0; i < NUM_CHANNELS; i++) {
1724                 struct uart_sunzilog_port *up = &sunzilog_port_table[i];
1725
1726                 if (ZS_IS_KEYB(up) || ZS_IS_MOUSE(up))
1727                         continue;
1728
1729                 uart_remove_one_port(&sunzilog_reg, &up->port);
1730         }
1731
1732         uart_unregister_driver(&sunzilog_reg);
1733 }
1734
1735 module_init(sunzilog_init);
1736 module_exit(sunzilog_exit);
1737
1738 MODULE_AUTHOR("David S. Miller");
1739 MODULE_DESCRIPTION("Sun Zilog serial port driver");
1740 MODULE_LICENSE("GPL");