drivers/usb/gadget/pxa2xx_udc.c

   1 /*
   2  * linux/drivers/usb/gadget/pxa2xx_udc.c
   3  * Intel PXA2xx and IXP4xx on-chip full speed USB device controllers
   4  *
   5  * Copyright (C) 2002 Intrinsyc, Inc. (Frank Becker)
   6  * Copyright (C) 2003 Robert Schwebel, Pengutronix
   7  * Copyright (C) 2003 Benedikt Spranger, Pengutronix
   8  * Copyright (C) 2003 David Brownell
   9  * Copyright (C) 2003 Joshua Wise
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  24  *
  25  */
  26
  27 #undef  DEBUG
  28 // #define      VERBOSE DBG_VERBOSE
  29
  30 #include <linux/config.h>
  31 #include <linux/module.h>
  32 #include <linux/kernel.h>
  33 #include <linux/ioport.h>
  34 #include <linux/types.h>
  35 #include <linux/version.h>
  36 #include <linux/errno.h>
  37 #include <linux/delay.h>
  38 #include <linux/sched.h>
  39 #include <linux/slab.h>
  40 #include <linux/init.h>
  41 #include <linux/timer.h>
  42 #include <linux/list.h>
  43 #include <linux/interrupt.h>
  44 #include <linux/proc_fs.h>
  45 #include <linux/mm.h>
  46 #include <linux/device.h>
  47 #include <linux/dma-mapping.h>
  48
  49 #include <asm/byteorder.h>
  50 #include <asm/dma.h>
  51 #include <asm/io.h>
  52 #include <asm/irq.h>
  53 #include <asm/system.h>
  54 #include <asm/mach-types.h>
  55 #include <asm/unaligned.h>
  56 #include <asm/hardware.h>
  57
  58 #include <linux/usb_ch9.h>
  59 #include <linux/usb_gadget.h>
  60
  61 #include <asm/arch/udc.h>
  62
  63
  64 /*
  65  * This driver handles the USB Device Controller (UDC) in Intel's PXA 2xx
  66  * series processors.  The UDC for the IXP 4xx series is very similar.
  67  * There are fifteen endpoints, in addition to ep0.
  68  *
  69  * Such controller drivers work with a gadget driver.  The gadget driver
  70  * returns descriptors, implements configuration and data protocols used
  71  * by the host to interact with this device, and allocates endpoints to
  72  * the different protocol interfaces.  The controller driver virtualizes
  73  * usb hardware so that the gadget drivers will be more portable.
  74  *
  75  * This UDC hardware wants to implement a bit too much USB protocol, so
  76  * it constrains the sorts of USB configuration change events that work.
  77  * The errata for these chips are misleading; some "fixed" bugs from
  78  * pxa250 a0/a1 b0/b1/b2 sure act like they're still there.
  79  */
  80
  81 #define DRIVER_VERSION  "14-Dec-2003"
  82 #define DRIVER_DESC     "PXA 2xx USB Device Controller driver"
  83
  84
  85 static const char driver_name [] = "pxa2xx_udc";
  86
  87 static const char ep0name [] = "ep0";
  88
  89
  90 // #define      USE_DMA
  91 // #define      USE_OUT_DMA
  92 // #define      DISABLE_TEST_MODE
  93
  94 #ifdef CONFIG_PROC_FS
  95 #define UDC_PROC_FILE
  96 #endif
  97
  98 #ifdef CONFIG_ARCH_IXP4XX
  99 #undef USE_DMA
 100
 101 /* cpu-specific register addresses are compiled in to this code */
 102 #ifdef CONFIG_ARCH_PXA
 103 #error "Can't configure both IXP and PXA"
 104 #endif
 105
 106 #endif
 107
 108 #include "pxa2xx_udc.h"
 109
 110
 111 #ifdef CONFIG_EMBEDDED
 112 /* few strings, and little code to use them */
 113 #undef  DEBUG
 114 #undef  UDC_PROC_FILE
 115 #endif
 116
 117 #ifdef  USE_DMA
 118 static int use_dma = 1;
 119 MODULE_PARM (use_dma, "i");
 120 MODULE_PARM_DESC (use_dma, "true to use dma");
 121
 122 static void dma_nodesc_handler (int dmach, void *_ep, struct pt_regs *r);
 123 static void kick_dma(struct pxa2xx_ep *ep, struct pxa2xx_request *req);
 124
 125 #ifdef USE_OUT_DMA
 126 #define DMASTR " (dma support)"
 127 #else
 128 #define DMASTR " (dma in)"
 129 #endif
 130
 131 #else   /* !USE_DMA */
 132 #define DMASTR " (pio only)"
 133 #undef  USE_OUT_DMA
 134 #endif
 135
 136 #ifdef  CONFIG_USB_PXA2XX_SMALL
 137 #define SIZE_STR        " (small)"
 138 #else
 139 #define SIZE_STR        ""
 140 #endif
 141
 142 #ifdef DISABLE_TEST_MODE
 143 /* (mode == 0) == no undocumented chip tweaks
 144  * (mode & 1)  == double buffer bulk IN
 145  * (mode & 2)  == double buffer bulk OUT
 146  * ... so mode = 3 (or 7, 15, etc) does it for both
 147  */
 148 static ushort fifo_mode = 0;
 149 MODULE_PARM (fifo_mode, "h");
 150 MODULE_PARM_DESC (fifo_mode, "pxa2xx udc fifo mode");
 151 #endif
 152
 153 /* ---------------------------------------------------------------------------
 154  *      endpoint related parts of the api to the usb controller hardware,
 155  *      used by gadget driver; and the inner talker-to-hardware core.
 156  * ---------------------------------------------------------------------------
 157  */
 158
 159 static void pxa2xx_ep_fifo_flush (struct usb_ep *ep);
 160 static void nuke (struct pxa2xx_ep *, int status);
 161
 162 static void pio_irq_enable(int bEndpointAddress)
 163 {
 164         bEndpointAddress &= 0xf;
 165         if (bEndpointAddress < 8)
 166                 UICR0 &= ~(1 << bEndpointAddress);
 167         else {
 168                 bEndpointAddress -= 8;
 169                 UICR1 &= ~(1 << bEndpointAddress);
 170         }
 171 }
 172
 173 static void pio_irq_disable(int bEndpointAddress)
 174 {
 175         bEndpointAddress &= 0xf;
 176         if (bEndpointAddress < 8)
 177                 UICR0 |= 1 << bEndpointAddress;
 178         else {
 179                 bEndpointAddress -= 8;
 180                 UICR1 |= 1 << bEndpointAddress;
 181         }
 182 }
 183
 184 /* The UDCCR reg contains mask and interrupt status bits,
 185  * so using '|=' isn't safe as it may ack an interrupt.
 186  */
 187 #define UDCCR_MASK_BITS         (UDCCR_REM | UDCCR_SRM | UDCCR_UDE)
 188
 189 static inline void udc_set_mask_UDCCR(int mask)
 190 {
 191         UDCCR = (UDCCR & UDCCR_MASK_BITS) | (mask & UDCCR_MASK_BITS);
 192 }
 193
 194 static inline void udc_clear_mask_UDCCR(int mask)
 195 {
 196         UDCCR = (UDCCR & UDCCR_MASK_BITS) & ~(mask & UDCCR_MASK_BITS);
 197 }
 198
 199 static inline void udc_ack_int_UDCCR(int mask)
 200 {
 201         /* udccr contains the bits we dont want to change */
 202         __u32 udccr = UDCCR & UDCCR_MASK_BITS;
 203
 204         UDCCR = udccr | (mask & ~UDCCR_MASK_BITS);
 205 }
 206
 207 /*
 208  * endpoint enable/disable
 209  *
 210  * we need to verify the descriptors used to enable endpoints.  since pxa2xx
 211  * endpoint configurations are fixed, and are pretty much always enabled,
 212  * there's not a lot to manage here.
 213  *
 214  * because pxa2xx can't selectively initialize bulk (or interrupt) endpoints,
 215  * (resetting endpoint halt and toggle), SET_INTERFACE is unusable except
 216  * for a single interface (with only the default altsetting) and for gadget
 217  * drivers that don't halt endpoints (not reset by set_interface).  that also
 218  * means that if you use ISO, you must violate the USB spec rule that all
 219  * iso endpoints must be in non-default altsettings.
 220  */
 221 static int pxa2xx_ep_enable (struct usb_ep *_ep,
 222                 const struct usb_endpoint_descriptor *desc)
 223 {
 224         struct pxa2xx_ep        *ep;
 225         struct pxa2xx_udc       *dev;
 226
 227         ep = container_of (_ep, struct pxa2xx_ep, ep);
 228         if (!_ep || !desc || ep->desc || _ep->name == ep0name
 229                         || desc->bDescriptorType != USB_DT_ENDPOINT
 230                         || ep->bEndpointAddress != desc->bEndpointAddress
 231                         || ep->fifo_size < le16_to_cpu
 232                                                 (desc->wMaxPacketSize)) {
 233                 DMSG("%s, bad ep or descriptor\n", __FUNCTION__);
 234                 return -EINVAL;
 235         }
 236
 237         /* xfer types must match, except that interrupt ~= bulk */
 238         if (ep->bmAttributes != desc->bmAttributes
 239                         && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
 240                         && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
 241                 DMSG("%s, %s type mismatch\n", __FUNCTION__, _ep->name);
 242                 return -EINVAL;
 243         }
 244
 245         /* hardware _could_ do smaller, but driver doesn't */
 246         if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
 247                                 && le16_to_cpu (desc->wMaxPacketSize)
 248                                                 != BULK_FIFO_SIZE)
 249                         || !desc->wMaxPacketSize) {
 250                 DMSG("%s, bad %s maxpacket\n", __FUNCTION__, _ep->name);
 251                 return -ERANGE;
 252         }
 253
 254         dev = ep->dev;
 255         if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
 256                 DMSG("%s, bogus device state\n", __FUNCTION__);
 257                 return -ESHUTDOWN;
 258         }
 259
 260         ep->desc = desc;
 261         ep->dma = -1;
 262         ep->stopped = 0;
 263         ep->pio_irqs = ep->dma_irqs = 0;
 264         ep->ep.maxpacket = le16_to_cpu (desc->wMaxPacketSize);
 265
 266         /* flush fifo (mostly for OUT buffers) */
 267         pxa2xx_ep_fifo_flush (_ep);
 268
 269         /* ... reset halt state too, if we could ... */
 270
 271 #ifdef  USE_DMA
 272         /* for (some) bulk and ISO endpoints, try to get a DMA channel and
 273          * bind it to the endpoint.  otherwise use PIO.
 274          */
 275         switch (ep->bmAttributes) {
 276         case USB_ENDPOINT_XFER_ISOC:
 277                 if (le16_to_cpu(desc->wMaxPacketSize) % 32)
 278                         break;
 279                 // fall through
 280         case USB_ENDPOINT_XFER_BULK:
 281                 if (!use_dma || !ep->reg_drcmr)
 282                         break;
 283                 ep->dma = pxa_request_dma ((char *)_ep->name,
 284                                 (le16_to_cpu (desc->wMaxPacketSize) > 64)
 285                                         ? DMA_PRIO_MEDIUM /* some iso */
 286                                         : DMA_PRIO_LOW,
 287                                 dma_nodesc_handler, ep);
 288                 if (ep->dma >= 0) {
 289                         *ep->reg_drcmr = DRCMR_MAPVLD | ep->dma;
 290                         DMSG("%s using dma%d\n", _ep->name, ep->dma);
 291                 }
 292         }
 293 #endif
 294
 295         DBG(DBG_VERBOSE, "enabled %s\n", _ep->name);
 296         return 0;
 297 }
 298
 299 static int pxa2xx_ep_disable (struct usb_ep *_ep)
 300 {
 301         struct pxa2xx_ep        *ep;
 302
 303         ep = container_of (_ep, struct pxa2xx_ep, ep);
 304         if (!_ep || !ep->desc) {
 305                 DMSG("%s, %s not enabled\n", __FUNCTION__,
 306                         _ep ? ep->ep.name : NULL);
 307                 return -EINVAL;
 308         }
 309         nuke (ep, -ESHUTDOWN);
 310
 311 #ifdef  USE_DMA
 312         if (ep->dma >= 0) {
 313                 *ep->reg_drcmr = 0;
 314                 pxa_free_dma (ep->dma);
 315                 ep->dma = -1;
 316         }
 317 #endif
 318
 319         /* flush fifo (mostly for IN buffers) */
 320         pxa2xx_ep_fifo_flush (_ep);
 321
 322         ep->desc = 0;
 323         ep->stopped = 1;
 324
 325         DBG(DBG_VERBOSE, "%s disabled\n", _ep->name);
 326         return 0;
 327 }
 328
 329 /*-------------------------------------------------------------------------*/
 330
 331 /* for the pxa2xx, these can just wrap kmalloc/kfree.  gadget drivers
 332  * must still pass correctly initialized endpoints, since other controller
 333  * drivers may care about how it's currently set up (dma issues etc).
 334  */
 335
 336 /*
 337  *      pxa2xx_ep_alloc_request - allocate a request data structure
 338  */
 339 static struct usb_request *
 340 pxa2xx_ep_alloc_request (struct usb_ep *_ep, int gfp_flags)
 341 {
 342         struct pxa2xx_request *req;
 343
 344         req = kmalloc (sizeof *req, gfp_flags);
 345         if (!req)
 346                 return 0;
 347
 348         memset (req, 0, sizeof *req);
 349         INIT_LIST_HEAD (&req->queue);
 350         return &req->req;
 351 }
 352
 353
 354 /*
 355  *      pxa2xx_ep_free_request - deallocate a request data structure
 356  */
 357 static void
 358 pxa2xx_ep_free_request (struct usb_ep *_ep, struct usb_request *_req)
 359 {
 360         struct pxa2xx_request   *req;
 361
 362         req = container_of (_req, struct pxa2xx_request, req);
 363         WARN_ON (!list_empty (&req->queue));
 364         kfree(req);
 365 }
 366
 367
 368 /* PXA cache needs flushing with DMA I/O (it's dma-incoherent), but there's
 369  * no device-affinity and the heap works perfectly well for i/o buffers.
 370  * It wastes much less memory than dma_alloc_coherent() would, and even
 371  * prevents cacheline (32 bytes wide) sharing problems.
 372  */
 373 static void *
 374 pxa2xx_ep_alloc_buffer(struct usb_ep *_ep, unsigned bytes,
 375         dma_addr_t *dma, int gfp_flags)
 376 {
 377         char                    *retval;
 378
 379         retval = kmalloc (bytes, gfp_flags & ~(__GFP_DMA|__GFP_HIGHMEM));
 380         if (retval)
 381                 *dma = virt_to_bus (retval);
 382         return retval;
 383 }
 384
 385 static void
 386 pxa2xx_ep_free_buffer(struct usb_ep *_ep, void *buf, dma_addr_t dma,
 387                 unsigned bytes)
 388 {
 389         kfree (buf);
 390 }
 391
 392 /*-------------------------------------------------------------------------*/
 393
 394 /*
 395  *      done - retire a request; caller blocked irqs
 396  */
 397 static void done(struct pxa2xx_ep *ep, struct pxa2xx_request *req, int status)
 398 {
 399         unsigned                stopped = ep->stopped;
 400
 401         list_del_init(&req->queue);
 402
 403         if (likely (req->req.status == -EINPROGRESS))
 404                 req->req.status = status;
 405         else
 406                 status = req->req.status;
 407
 408         if (status && status != -ESHUTDOWN)
 409                 DBG(DBG_VERBOSE, "complete %s req %p stat %d len %u/%u\n",
 410                         ep->ep.name, &req->req, status,
 411                         req->req.actual, req->req.length);
 412
 413         /* don't modify queue heads during completion callback */
 414         ep->stopped = 1;
 415         req->req.complete(&ep->ep, &req->req);
 416         ep->stopped = stopped;
 417 }
 418
 419
 420 static inline void ep0_idle (struct pxa2xx_udc *dev)
 421 {
 422         dev->ep0state = EP0_IDLE;
 423         LED_EP0_OFF;
 424 }
 425
 426 static int
 427 write_packet(volatile u32 *uddr, struct pxa2xx_request *req, unsigned max)
 428 {
 429         u8              *buf;
 430         unsigned        length, count;
 431
 432         buf = req->req.buf + req->req.actual;
 433         prefetch(buf);
 434
 435         /* how big will this packet be? */
 436         length = min(req->req.length - req->req.actual, max);
 437         req->req.actual += length;
 438
 439         count = length;
 440         while (likely(count--))
 441                 *uddr = *buf++;
 442
 443         return length;
 444 }
 445
 446 /*
 447  * write to an IN endpoint fifo, as many packets as possible.
 448  * irqs will use this to write the rest later.
 449  * caller guarantees at least one packet buffer is ready (or a zlp).
 450  */
 451 static int
 452 write_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req)
 453 {
 454         unsigned                max;
 455
 456         max = le16_to_cpu(ep->desc->wMaxPacketSize);
 457         do {
 458                 unsigned        count;
 459                 int             is_last, is_short;
 460
 461                 count = write_packet(ep->reg_uddr, req, max);
 462
 463                 /* last packet is usually short (or a zlp) */
 464                 if (unlikely (count != max))
 465                         is_last = is_short = 1;
 466                 else {
 467                         if (likely(req->req.length != req->req.actual)
 468                                         || req->req.zero)
 469                                 is_last = 0;
 470                         else
 471                                 is_last = 1;
 472                         /* interrupt/iso maxpacket may not fill the fifo */
 473                         is_short = unlikely (max < ep->fifo_size);
 474                 }
 475
 476                 DBG(DBG_VERY_NOISY, "wrote %s %d bytes%s%s %d left %p\n",
 477                         ep->ep.name, count,
 478                         is_last ? "/L" : "", is_short ? "/S" : "",
 479                         req->req.length - req->req.actual, req);
 480
 481                 /* let loose that packet. maybe try writing another one,
 482                  * double buffering might work.  TSP, TPC, and TFS
 483                  * bit values are the same for all normal IN endpoints.
 484                  */
 485                 *ep->reg_udccs = UDCCS_BI_TPC;
 486                 if (is_short)
 487                         *ep->reg_udccs = UDCCS_BI_TSP;
 488
 489                 /* requests complete when all IN data is in the FIFO */
 490                 if (is_last) {
 491                         done (ep, req, 0);
 492                         if (list_empty(&ep->queue) || unlikely(ep->dma >= 0)) {
 493                                 pio_irq_disable (ep->bEndpointAddress);
 494 #ifdef USE_DMA
 495                                 /* unaligned data and zlps couldn't use dma */
 496                                 if (unlikely(!list_empty(&ep->queue))) {
 497                                         req = list_entry(ep->queue.next,
 498                                                 struct pxa2xx_request, queue);
 499                                         kick_dma(ep,req);
 500                                         return 0;
 501                                 }
 502 #endif
 503                         }
 504                         return 1;
 505                 }
 506
 507                 // TODO experiment: how robust can fifo mode tweaking be?
 508                 // double buffering is off in the default fifo mode, which
 509                 // prevents TFS from being set here.
 510
 511         } while (*ep->reg_udccs & UDCCS_BI_TFS);
 512         return 0;
 513 }
 514
 515 /* caller asserts req->pending (ep0 irq status nyet cleared); starts
 516  * ep0 data stage.  these chips want very simple state transitions.
 517  */
 518 static inline
 519 void ep0start(struct pxa2xx_udc *dev, u32 flags, const char *tag)
 520 {
 521         UDCCS0 = flags|UDCCS0_SA|UDCCS0_OPR;
 522         USIR0 = USIR0_IR0;
 523         dev->req_pending = 0;
 524         DBG(DBG_VERY_NOISY, "%s %s, %02x/%02x\n",
 525                 __FUNCTION__, tag, UDCCS0, flags);
 526 }
 527
 528 static int
 529 write_ep0_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req)
 530 {
 531         unsigned        count;
 532         int             is_short;
 533
 534         count = write_packet(&UDDR0, req, EP0_FIFO_SIZE);
 535         ep->dev->stats.write.bytes += count;
 536
 537         /* last packet "must be" short (or a zlp) */
 538         is_short = (count != EP0_FIFO_SIZE);
 539
 540         DBG(DBG_VERY_NOISY, "ep0in %d bytes %d left %p\n", count,
 541                 req->req.length - req->req.actual, req);
 542
 543         if (unlikely (is_short)) {
 544                 if (ep->dev->req_pending)
 545                         ep0start(ep->dev, UDCCS0_IPR, "short IN");
 546                 else
 547                         UDCCS0 = UDCCS0_IPR;
 548
 549                 count = req->req.length;
 550                 done (ep, req, 0);
 551                 ep0_idle(ep->dev);
 552 #if 1
 553                 /* This seems to get rid of lost status irqs in some cases:
 554                  * host responds quickly, or next request involves config
 555                  * change automagic, or should have been hidden, or ...
 556                  *
 557                  * FIXME get rid of all udelays possible...
 558                  */
 559                 if (count >= EP0_FIFO_SIZE) {
 560                         count = 100;
 561                         do {
 562                                 if ((UDCCS0 & UDCCS0_OPR) != 0) {
 563                                         /* clear OPR, generate ack */
 564                                         UDCCS0 = UDCCS0_OPR;
 565                                         break;
 566                                 }
 567                                 count--;
 568                                 udelay(1);
 569                         } while (count);
 570                 }
 571 #endif
 572         } else if (ep->dev->req_pending)
 573                 ep0start(ep->dev, 0, "IN");
 574         return is_short;
 575 }
 576
 577
 578 /*
 579  * read_fifo -  unload packet(s) from the fifo we use for usb OUT
 580  * transfers and put them into the request.  caller should have made
 581  * sure there's at least one packet ready.
 582  *
 583  * returns true if the request completed because of short packet or the
 584  * request buffer having filled (and maybe overran till end-of-packet).
 585  */
 586 static int
 587 read_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req)
 588 {
 589         for (;;) {
 590                 u32             udccs;
 591                 u8              *buf;
 592                 unsigned        bufferspace, count, is_short;
 593
 594                 /* make sure there's a packet in the FIFO.
 595                  * UDCCS_{BO,IO}_RPC are all the same bit value.
 596                  * UDCCS_{BO,IO}_RNE are all the same bit value.
 597                  */
 598                 udccs = *ep->reg_udccs;
 599                 if (unlikely ((udccs & UDCCS_BO_RPC) == 0))
 600                         break;
 601                 buf = req->req.buf + req->req.actual;
 602                 prefetchw(buf);
 603                 bufferspace = req->req.length - req->req.actual;
 604
 605                 /* read all bytes from this packet */
 606                 if (likely (udccs & UDCCS_BO_RNE)) {
 607                         count = 1 + (0x0ff & *ep->reg_ubcr);
 608                         req->req.actual += min (count, bufferspace);
 609                 } else /* zlp */
 610                         count = 0;
 611                 is_short = (count < ep->ep.maxpacket);
 612                 DBG(DBG_VERY_NOISY, "read %s %02x, %d bytes%s req %p %d/%d\n",
 613                         ep->ep.name, udccs, count,
 614                         is_short ? "/S" : "",
 615                         req, req->req.actual, req->req.length);
 616                 while (likely (count-- != 0)) {
 617                         u8      byte = (u8) *ep->reg_uddr;
 618
 619                         if (unlikely (bufferspace == 0)) {
 620                                 /* this happens when the driver's buffer
 621                                  * is smaller than what the host sent.
 622                                  * discard the extra data.
 623                                  */
 624                                 if (req->req.status != -EOVERFLOW)
 625                                         DMSG("%s overflow %d\n",
 626                                                 ep->ep.name, count);
 627                                 req->req.status = -EOVERFLOW;
 628                         } else {
 629                                 *buf++ = byte;
 630                                 bufferspace--;
 631                         }
 632                 }
 633                 *ep->reg_udccs =  UDCCS_BO_RPC;
 634                 /* RPC/RSP/RNE could now reflect the other packet buffer */
 635
 636                 /* iso is one request per packet */
 637                 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 638                         if (udccs & UDCCS_IO_ROF)
 639                                 req->req.status = -EHOSTUNREACH;
 640                         /* more like "is_done" */
 641                         is_short = 1;
 642                 }
 643
 644                 /* completion */
 645                 if (is_short || req->req.actual == req->req.length) {
 646                         done (ep, req, 0);
 647                         if (list_empty(&ep->queue))
 648                                 pio_irq_disable (ep->bEndpointAddress);
 649                         return 1;
 650                 }
 651
 652                 /* finished that packet.  the next one may be waiting... */
 653         }
 654         return 0;
 655 }
 656
 657 /*
 658  * special ep0 version of the above.  no UBCR0 or double buffering; status
 659  * handshaking is magic.  most device protocols don't need control-OUT.
 660  * CDC vendor commands (and RNDIS), mass storage CB/CBI, and some other
 661  * protocols do use them.
 662  */
 663 static int
 664 read_ep0_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req)
 665 {
 666         u8              *buf, byte;
 667         unsigned        bufferspace;
 668
 669         buf = req->req.buf + req->req.actual;
 670         bufferspace = req->req.length - req->req.actual;
 671
 672         while (UDCCS0 & UDCCS0_RNE) {
 673                 byte = (u8) UDDR0;
 674
 675                 if (unlikely (bufferspace == 0)) {
 676                         /* this happens when the driver's buffer
 677                          * is smaller than what the host sent.
 678                          * discard the extra data.
 679                          */
 680                         if (req->req.status != -EOVERFLOW)
 681                                 DMSG("%s overflow\n", ep->ep.name);
 682                         req->req.status = -EOVERFLOW;
 683                 } else {
 684                         *buf++ = byte;
 685                         req->req.actual++;
 686                         bufferspace--;
 687                 }
 688         }
 689
 690         UDCCS0 = UDCCS0_OPR | UDCCS0_IPR;
 691
 692         /* completion */
 693         if (req->req.actual >= req->req.length)
 694                 return 1;
 695
 696         /* finished that packet.  the next one may be waiting... */
 697         return 0;
 698 }
 699
 700 #ifdef  USE_DMA
 701
 702 #define MAX_IN_DMA      ((DCMD_LENGTH + 1) - BULK_FIFO_SIZE)
 703
 704 static void
 705 start_dma_nodesc(struct pxa2xx_ep *ep, struct pxa2xx_request *req, int is_in)
 706 {
 707         u32     dcmd = req->req.length;
 708         u32     buf = req->req.dma;
 709         u32     fifo = io_v2p ((u32)ep->reg_uddr);
 710
 711         /* caller guarantees there's a packet or more remaining
 712          *  - IN may end with a short packet (TSP set separately),
 713          *  - OUT is always full length
 714          */
 715         buf += req->req.actual;
 716         dcmd -= req->req.actual;
 717         ep->dma_fixup = 0;
 718
 719         /* no-descriptor mode can be simple for bulk-in, iso-in, iso-out */
 720         DCSR(ep->dma) = DCSR_NODESC;
 721         if (is_in) {
 722                 DSADR(ep->dma) = buf;
 723                 DTADR(ep->dma) = fifo;
 724                 if (dcmd > MAX_IN_DMA)
 725                         dcmd = MAX_IN_DMA;
 726                 else
 727                         ep->dma_fixup = (dcmd % ep->ep.maxpacket) != 0;
 728                 dcmd |= DCMD_BURST32 | DCMD_WIDTH1
 729                         | DCMD_FLOWTRG | DCMD_INCSRCADDR;
 730         } else {
 731 #ifdef USE_OUT_DMA
 732                 DSADR(ep->dma) = fifo;
 733                 DTADR(ep->dma) = buf;
 734                 if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
 735                         dcmd = ep->ep.maxpacket;
 736                 dcmd |= DCMD_BURST32 | DCMD_WIDTH1
 737                         | DCMD_FLOWSRC | DCMD_INCTRGADDR;
 738 #endif
 739         }
 740         DCMD(ep->dma) = dcmd;
 741         DCSR(ep->dma) = DCSR_RUN | DCSR_NODESC
 742                 | (unlikely(is_in)
 743                         ? DCSR_STOPIRQEN        /* use dma_nodesc_handler() */
 744                         : 0);                   /* use handle_ep() */
 745 }
 746
 747 static void kick_dma(struct pxa2xx_ep *ep, struct pxa2xx_request *req)
 748 {
 749         int     is_in = ep->bEndpointAddress & USB_DIR_IN;
 750
 751         if (is_in) {
 752                 /* unaligned tx buffers and zlps only work with PIO */
 753                 if ((req->req.dma & 0x0f) != 0
 754                                 || unlikely((req->req.length - req->req.actual)
 755                                                 == 0)) {
 756                         pio_irq_enable(ep->bEndpointAddress);
 757                         if ((*ep->reg_udccs & UDCCS_BI_TFS) != 0)
 758                                 (void) write_fifo(ep, req);
 759                 } else {
 760                         start_dma_nodesc(ep, req, USB_DIR_IN);
 761                 }
 762         } else {
 763                 if ((req->req.length - req->req.actual) < ep->ep.maxpacket) {
 764                         DMSG("%s short dma read...\n", ep->ep.name);
 765                         /* we're always set up for pio out */
 766                         read_fifo (ep, req);
 767                 } else {
 768                         *ep->reg_udccs = UDCCS_BO_DME
 769                                 | (*ep->reg_udccs & UDCCS_BO_FST);
 770                         start_dma_nodesc(ep, req, USB_DIR_OUT);
 771                 }
 772         }
 773 }
 774
 775 static void cancel_dma(struct pxa2xx_ep *ep)
 776 {
 777         struct pxa2xx_request   *req;
 778         u32                     tmp;
 779
 780         if (DCSR(ep->dma) == 0 || list_empty(&ep->queue))
 781                 return;
 782
 783         DCSR(ep->dma) = 0;
 784         while ((DCSR(ep->dma) & DCSR_STOPSTATE) == 0)
 785                 cpu_relax();
 786
 787         req = list_entry(ep->queue.next, struct pxa2xx_request, queue);
 788         tmp = DCMD(ep->dma) & DCMD_LENGTH;
 789         req->req.actual = req->req.length - (tmp & DCMD_LENGTH);
 790
 791         /* the last tx packet may be incomplete, so flush the fifo.
 792          * FIXME correct req.actual if we can
 793          */
 794         if (ep->bEndpointAddress & USB_DIR_IN)
 795                 *ep->reg_udccs = UDCCS_BI_FTF;
 796 }
 797
 798 /* dma channel stopped ... normal tx end (IN), or on error (IN/OUT) */
 799 static void dma_nodesc_handler(int dmach, void *_ep, struct pt_regs *r)
 800 {
 801         struct pxa2xx_ep        *ep = _ep;
 802         struct pxa2xx_request   *req;
 803         u32                     tmp, completed;
 804
 805         local_irq_disable();
 806
 807         req = list_entry(ep->queue.next, struct pxa2xx_request, queue);
 808
 809         ep->dma_irqs++;
 810         ep->dev->stats.irqs++;
 811         HEX_DISPLAY(ep->dev->stats.irqs);
 812
 813         /* ack/clear */
 814         tmp = DCSR(ep->dma);
 815         DCSR(ep->dma) = tmp;
 816         if ((tmp & DCSR_STOPSTATE) == 0
 817                         || (DDADR(ep->dma) & DDADR_STOP) != 0) {
 818                 DBG(DBG_VERBOSE, "%s, dcsr %08x ddadr %08x\n",
 819                         ep->ep.name, DCSR(ep->dma), DDADR(ep->dma));
 820                 goto done;
 821         }
 822         DCSR(ep->dma) = 0;      /* clear DCSR_STOPSTATE */
 823
 824         /* update transfer status */
 825         completed = tmp & DCSR_BUSERR;
 826         if (ep->bEndpointAddress & USB_DIR_IN)
 827                 tmp = DSADR(ep->dma);
 828         else
 829                 tmp = DTADR(ep->dma);
 830         req->req.actual = tmp - req->req.dma;
 831
 832         /* FIXME seems we sometimes see partial transfers... */
 833
 834         if (unlikely(completed != 0))
 835                 req->req.status = -EIO;
 836         else if (req->req.actual) {
 837                 /* these registers have zeroes in low bits; they miscount
 838                  * some (end-of-transfer) short packets:  tx 14 as tx 12
 839                  */
 840                 if (ep->dma_fixup)
 841                         req->req.actual = min(req->req.actual + 3,
 842                                                 req->req.length);
 843
 844                 tmp = (req->req.length - req->req.actual);
 845                 completed = (tmp == 0);
 846                 if (completed && (ep->bEndpointAddress & USB_DIR_IN)) {
 847
 848                         /* maybe validate final short packet ... */
 849                         if ((req->req.actual % ep->ep.maxpacket) != 0)
 850                                 *ep->reg_udccs = UDCCS_BI_TSP/*|UDCCS_BI_TPC*/;
 851
 852                         /* ... or zlp, using pio fallback */
 853                         else if (ep->bmAttributes == USB_ENDPOINT_XFER_BULK
 854                                         && req->req.zero) {
 855                                 DMSG("%s zlp terminate ...\n", ep->ep.name);
 856                                 completed = 0;
 857                         }
 858                 }
 859         }
 860
 861         if (likely(completed)) {
 862                 done(ep, req, 0);
 863
 864                 /* maybe re-activate after completion */
 865                 if (ep->stopped || list_empty(&ep->queue))
 866                         goto done;
 867                 req = list_entry(ep->queue.next, struct pxa2xx_request, queue);
 868         }
 869         kick_dma(ep, req);
 870 done:
 871         local_irq_enable();
 872 }
 873
 874 #endif
 875
 876 /*-------------------------------------------------------------------------*/
 877
 878 static int
 879 pxa2xx_ep_queue(struct usb_ep *_ep, struct usb_request *_req, int gfp_flags)
 880 {
 881         struct pxa2xx_request   *req;
 882         struct pxa2xx_ep        *ep;
 883         struct pxa2xx_udc       *dev;
 884         unsigned long           flags;
 885
 886         req = container_of(_req, struct pxa2xx_request, req);
 887         if (unlikely (!_req || !_req->complete || !_req->buf
 888                         || !list_empty(&req->queue))) {
 889                 DMSG("%s, bad params\n", __FUNCTION__);
 890                 return -EINVAL;
 891         }
 892
 893         ep = container_of(_ep, struct pxa2xx_ep, ep);
 894         if (unlikely (!_ep || (!ep->desc && ep->ep.name != ep0name))) {
 895                 DMSG("%s, bad ep\n", __FUNCTION__);
 896                 return -EINVAL;
 897         }
 898
 899         dev = ep->dev;
 900         if (unlikely (!dev->driver
 901                         || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
 902                 DMSG("%s, bogus device state\n", __FUNCTION__);
 903                 return -ESHUTDOWN;
 904         }
 905
 906         /* iso is always one packet per request, that's the only way
 907          * we can report per-packet status.  that also helps with dma.
 908          */
 909         if (unlikely (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
 910                         && req->req.length > le16_to_cpu
 911                                                 (ep->desc->wMaxPacketSize)))
 912                 return -EMSGSIZE;
 913
 914 #ifdef  USE_DMA
 915         // FIXME caller may already have done the dma mapping
 916         if (ep->dma >= 0) {
 917                 _req->dma = dma_map_single(dev->dev,
 918                         _req->buf, _req->length,
 919                         ((ep->bEndpointAddress & USB_DIR_IN) != 0)
 920                                 ? DMA_TO_DEVICE
 921                                 : DMA_FROM_DEVICE);
 922         }
 923 #endif
 924
 925         DBG(DBG_NOISY, "%s queue req %p, len %d buf %p\n",
 926              _ep->name, _req, _req->length, _req->buf);
 927
 928         local_irq_save(flags);
 929
 930         _req->status = -EINPROGRESS;
 931         _req->actual = 0;
 932
 933         /* kickstart this i/o queue? */
 934         if (list_empty(&ep->queue) && !ep->stopped) {
 935                 if (ep->desc == 0 /* ep0 */) {
 936                         unsigned        length = _req->length;
 937
 938                         switch (dev->ep0state) {
 939                         case EP0_IN_DATA_PHASE:
 940                                 dev->stats.write.ops++;
 941                                 if (write_ep0_fifo(ep, req))
 942                                         req = 0;
 943                                 break;
 944
 945                         case EP0_OUT_DATA_PHASE:
 946                                 dev->stats.read.ops++;
 947                                 /* messy ... */
 948                                 if (dev->req_config) {
 949                                         DBG(DBG_VERBOSE, "ep0 config ack%s\n",
 950                                                 dev->has_cfr ?  "" : " raced");
 951                                         if (dev->has_cfr)
 952                                                 UDCCFR = UDCCFR_AREN|UDCCFR_ACM;
 953                                         done(ep, req, 0);
 954                                         dev->ep0state = EP0_END_XFER;
 955                                         return 0;
 956                                 }
 957                                 if (dev->req_pending)
 958                                         ep0start(dev, UDCCS0_IPR, "OUT");
 959                                 if (length == 0 || ((UDCCS0 & UDCCS0_RNE) != 0
 960                                                 && read_ep0_fifo(ep, req))) {
 961                                         ep0_idle(dev);
 962                                         done(ep, req, 0);
 963                                         req = 0;
 964                                 }
 965                                 break;
 966
 967                         default:
 968                                 DMSG("ep0 i/o, odd state %d\n", dev->ep0state);
 969                                 local_irq_restore (flags);
 970                                 return -EL2HLT;
 971                         }
 972 #ifdef  USE_DMA
 973                 /* either start dma or prime pio pump */
 974                 } else if (ep->dma >= 0) {
 975                         kick_dma(ep, req);
 976 #endif
 977                 /* can the FIFO can satisfy the request immediately? */
 978                 } else if ((ep->bEndpointAddress & USB_DIR_IN) != 0
 979                                 && (*ep->reg_udccs & UDCCS_BI_TFS) != 0
 980                                 && write_fifo(ep, req)) {
 981                         req = 0;
 982                 } else if ((*ep->reg_udccs & UDCCS_BO_RFS) != 0
 983                                 && read_fifo(ep, req)) {
 984                         req = 0;
 985                 }
 986
 987                 if (likely (req && ep->desc) && ep->dma < 0)
 988                         pio_irq_enable(ep->bEndpointAddress);
 989         }
 990
 991         /* pio or dma irq handler advances the queue. */
 992         if (likely (req != 0))
 993                 list_add_tail(&req->queue, &ep->queue);
 994         local_irq_restore(flags);
 995
 996         return 0;
 997 }
 998
 999
1000 /*
1001  *      nuke - dequeue ALL requests
1002  */
1003 static void nuke(struct pxa2xx_ep *ep, int status)
1004 {
1005         struct pxa2xx_request *req;
1006
1007         /* called with irqs blocked */
1008 #ifdef  USE_DMA
1009         if (ep->dma >= 0 && !ep->stopped)
1010                 cancel_dma(ep);
1011 #endif
1012         while (!list_empty(&ep->queue)) {
1013                 req = list_entry(ep->queue.next,
1014                                 struct pxa2xx_request,
1015                                 queue);
1016                 done(ep, req, status);
1017         }
1018         if (ep->desc)
1019                 pio_irq_disable (ep->bEndpointAddress);
1020 }
1021
1022
1023 /* dequeue JUST ONE request */
1024 static int pxa2xx_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1025 {
1026         struct pxa2xx_ep        *ep;
1027         struct pxa2xx_request   *req;
1028         unsigned long           flags;
1029
1030         ep = container_of(_ep, struct pxa2xx_ep, ep);
1031         if (!_ep || ep->ep.name == ep0name)
1032                 return -EINVAL;
1033
1034         local_irq_save(flags);
1035
1036         /* make sure it's actually queued on this endpoint */
1037         list_for_each_entry (req, &ep->queue, queue) {
1038                 if (&req->req == _req)
1039                         break;
1040         }
1041         if (&req->req != _req) {
1042                 local_irq_restore(flags);
1043                 return -EINVAL;
1044         }
1045
1046 #ifdef  USE_DMA
1047         if (ep->dma >= 0 && ep->queue.next == &req->queue && !ep->stopped) {
1048                 cancel_dma(ep);
1049                 done(ep, req, -ECONNRESET);
1050                 /* restart i/o */
1051                 if (!list_empty(&ep->queue)) {
1052                         req = list_entry(ep->queue.next,
1053                                         struct pxa2xx_request, queue);
1054                         kick_dma(ep, req);
1055                 }
1056         } else
1057 #endif
1058                 done(ep, req, -ECONNRESET);
1059
1060         local_irq_restore(flags);
1061         return 0;
1062 }
1063
1064 /*-------------------------------------------------------------------------*/
1065
1066 static int pxa2xx_ep_set_halt(struct usb_ep *_ep, int value)
1067 {
1068         struct pxa2xx_ep        *ep;
1069         unsigned long           flags;
1070
1071         ep = container_of(_ep, struct pxa2xx_ep, ep);
1072         if (unlikely (!_ep
1073                         || (!ep->desc && ep->ep.name != ep0name))
1074                         || ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
1075                 DMSG("%s, bad ep\n", __FUNCTION__);
1076                 return -EINVAL;
1077         }
1078         if (value == 0) {
1079                 /* this path (reset toggle+halt) is needed to implement
1080                  * SET_INTERFACE on normal hardware.  but it can't be
1081                  * done from software on the PXA UDC, and the hardware
1082                  * forgets to do it as part of SET_INTERFACE automagic.
1083                  */
1084                 DMSG("only host can clear %s halt\n", _ep->name);
1085                 return -EROFS;
1086         }
1087
1088         local_irq_save(flags);
1089
1090         if ((ep->bEndpointAddress & USB_DIR_IN) != 0
1091                         && ((*ep->reg_udccs & UDCCS_BI_TFS) == 0
1092                            || !list_empty(&ep->queue))) {
1093                 local_irq_restore(flags);
1094                 return -EAGAIN;
1095         }
1096
1097         /* FST bit is the same for control, bulk in, bulk out, interrupt in */
1098         *ep->reg_udccs = UDCCS_BI_FST|UDCCS_BI_FTF;
1099
1100         /* ep0 needs special care */
1101         if (!ep->desc) {
1102                 start_watchdog(ep->dev);
1103                 ep->dev->req_pending = 0;
1104                 ep->dev->ep0state = EP0_STALL;
1105                 LED_EP0_OFF;
1106
1107         /* and bulk/intr endpoints like dropping stalls too */
1108         } else {
1109                 unsigned i;
1110                 for (i = 0; i < 1000; i += 20) {
1111                         if (*ep->reg_udccs & UDCCS_BI_SST)
1112                                 break;
1113                         udelay(20);
1114                 }
1115         }
1116         local_irq_restore(flags);
1117
1118         DBG(DBG_VERBOSE, "%s halt\n", _ep->name);
1119         return 0;
1120 }
1121
1122 static int pxa2xx_ep_fifo_status(struct usb_ep *_ep)
1123 {
1124         struct pxa2xx_ep        *ep;
1125
1126         ep = container_of(_ep, struct pxa2xx_ep, ep);
1127         if (!_ep) {
1128                 DMSG("%s, bad ep\n", __FUNCTION__);
1129                 return -ENODEV;
1130         }
1131         /* pxa can't report unclaimed bytes from IN fifos */
1132         if ((ep->bEndpointAddress & USB_DIR_IN) != 0)
1133                 return -EOPNOTSUPP;
1134         if (ep->dev->gadget.speed == USB_SPEED_UNKNOWN
1135                         || (*ep->reg_udccs & UDCCS_BO_RFS) == 0)
1136                 return 0;
1137         else
1138                 return (*ep->reg_ubcr & 0xfff) + 1;
1139 }
1140
1141 static void pxa2xx_ep_fifo_flush(struct usb_ep *_ep)
1142 {
1143         struct pxa2xx_ep        *ep;
1144
1145         ep = container_of(_ep, struct pxa2xx_ep, ep);
1146         if (!_ep || ep->ep.name == ep0name || !list_empty(&ep->queue)) {
1147                 DMSG("%s, bad ep\n", __FUNCTION__);
1148                 return;
1149         }
1150
1151         /* toggle and halt bits stay unchanged */
1152
1153         /* for OUT, just read and discard the FIFO contents. */
1154         if ((ep->bEndpointAddress & USB_DIR_IN) == 0) {
1155                 while (((*ep->reg_udccs) & UDCCS_BO_RNE) != 0)
1156                         (void) *ep->reg_uddr;
1157                 return;
1158         }
1159
1160         /* most IN status is the same, but ISO can't stall */
1161         *ep->reg_udccs = UDCCS_BI_TPC|UDCCS_BI_FTF|UDCCS_BI_TUR
1162                 | (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
1163                         ? 0 : UDCCS_BI_SST;
1164 }
1165
1166
1167 static struct usb_ep_ops pxa2xx_ep_ops = {
1168         .enable         = pxa2xx_ep_enable,
1169         .disable        = pxa2xx_ep_disable,
1170
1171         .alloc_request  = pxa2xx_ep_alloc_request,
1172         .free_request   = pxa2xx_ep_free_request,
1173
1174         .alloc_buffer   = pxa2xx_ep_alloc_buffer,
1175         .free_buffer    = pxa2xx_ep_free_buffer,
1176
1177         .queue          = pxa2xx_ep_queue,
1178         .dequeue        = pxa2xx_ep_dequeue,
1179
1180         .set_halt       = pxa2xx_ep_set_halt,
1181         .fifo_status    = pxa2xx_ep_fifo_status,
1182         .fifo_flush     = pxa2xx_ep_fifo_flush,
1183 };
1184
1185
1186 /* ---------------------------------------------------------------------------
1187  *      device-scoped parts of the api to the usb controller hardware
1188  * ---------------------------------------------------------------------------
1189  */
1190
1191 static int pxa2xx_udc_get_frame(struct usb_gadget *_gadget)
1192 {
1193         return ((UFNRH & 0x07) << 8) | (UFNRL & 0xff);
1194 }
1195
1196 static int pxa2xx_udc_wakeup(struct usb_gadget *_gadget)
1197 {
1198         /* host may not have enabled remote wakeup */
1199         if ((UDCCS0 & UDCCS0_DRWF) == 0)
1200                 return -EHOSTUNREACH;
1201         udc_set_mask_UDCCR(UDCCR_RSM);
1202         return 0;
1203 }
1204
1205 static const struct usb_gadget_ops pxa2xx_udc_ops = {
1206         .get_frame       = pxa2xx_udc_get_frame,
1207         .wakeup          = pxa2xx_udc_wakeup,
1208         // current versions must always be self-powered
1209 };
1210
1211
1212 /*-------------------------------------------------------------------------*/
1213
1214 #ifdef UDC_PROC_FILE
1215
1216 static const char proc_node_name [] = "driver/udc";
1217
1218 static int
1219 udc_proc_read(char *page, char **start, off_t off, int count,
1220                 int *eof, void *_dev)
1221 {
1222         char                    *buf = page;
1223         struct pxa2xx_udc       *dev = _dev;
1224         char                    *next = buf;
1225         unsigned                size = count;
1226         unsigned long           flags;
1227         int                     i, t;
1228         u32                     tmp;
1229
1230         if (off != 0)
1231                 return 0;
1232
1233         local_irq_save(flags);
1234
1235         /* basic device status */
1236         t = scnprintf(next, size, DRIVER_DESC "\n"
1237                 "%s version: %s\nGadget driver: %s\nHost %s\n\n",
1238                 driver_name, DRIVER_VERSION SIZE_STR DMASTR,
1239                 dev->driver ? dev->driver->driver.name : "(none)",
1240                 is_usb_connected() ? "full speed" : "disconnected");
1241         size -= t;
1242         next += t;
1243
1244         /* registers for device and ep0 */
1245         t = scnprintf(next, size,
1246                 "uicr %02X.%02X, usir %02X.%02x, ufnr %02X.%02X\n",
1247                 UICR1, UICR0, USIR1, USIR0, UFNRH, UFNRL);
1248         size -= t;
1249         next += t;
1250
1251         tmp = UDCCR;
1252         t = scnprintf(next, size,
1253                 "udccr %02X =%s%s%s%s%s%s%s%s\n", tmp,
1254                 (tmp & UDCCR_REM) ? " rem" : "",
1255                 (tmp & UDCCR_RSTIR) ? " rstir" : "",
1256                 (tmp & UDCCR_SRM) ? " srm" : "",
1257                 (tmp & UDCCR_SUSIR) ? " susir" : "",
1258                 (tmp & UDCCR_RESIR) ? " resir" : "",
1259                 (tmp & UDCCR_RSM) ? " rsm" : "",
1260                 (tmp & UDCCR_UDA) ? " uda" : "",
1261                 (tmp & UDCCR_UDE) ? " ude" : "");
1262         size -= t;
1263         next += t;
1264
1265         tmp = UDCCS0;
1266         t = scnprintf(next, size,
1267                 "udccs0 %02X =%s%s%s%s%s%s%s%s\n", tmp,
1268                 (tmp & UDCCS0_SA) ? " sa" : "",
1269                 (tmp & UDCCS0_RNE) ? " rne" : "",
1270                 (tmp & UDCCS0_FST) ? " fst" : "",
1271                 (tmp & UDCCS0_SST) ? " sst" : "",
1272                 (tmp & UDCCS0_DRWF) ? " dwrf" : "",
1273                 (tmp & UDCCS0_FTF) ? " ftf" : "",
1274                 (tmp & UDCCS0_IPR) ? " ipr" : "",
1275                 (tmp & UDCCS0_OPR) ? " opr" : "");
1276         size -= t;
1277         next += t;
1278
1279         if (dev->has_cfr) {
1280                 tmp = UDCCFR;
1281                 t = scnprintf(next, size,
1282                         "udccfr %02X =%s%s\n", tmp,
1283                         (tmp & UDCCFR_AREN) ? " aren" : "",
1284                         (tmp & UDCCFR_ACM) ? " acm" : "");
1285                 size -= t;
1286                 next += t;
1287         }
1288
1289         if (!is_usb_connected() || !dev->driver)
1290                 goto done;
1291
1292         t = scnprintf(next, size, "ep0 IN %lu/%lu, OUT %lu/%lu\nirqs %lu\n\n",
1293                 dev->stats.write.bytes, dev->stats.write.ops,
1294                 dev->stats.read.bytes, dev->stats.read.ops,
1295                 dev->stats.irqs);
1296         size -= t;
1297         next += t;
1298
1299         /* dump endpoint queues */
1300         for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1301                 struct pxa2xx_ep        *ep = &dev->ep [i];
1302                 struct pxa2xx_request   *req;
1303                 int                     t;
1304
1305                 if (i != 0) {
1306                         const struct usb_endpoint_descriptor    *d;
1307
1308                         d = ep->desc;
1309                         if (!d)
1310                                 continue;
1311                         tmp = *dev->ep [i].reg_udccs;
1312                         t = scnprintf(next, size,
1313                                 "%s max %d %s udccs %02x irqs %lu/%lu\n",
1314                                 ep->ep.name, le16_to_cpu (d->wMaxPacketSize),
1315                                 (ep->dma >= 0) ? "dma" : "pio", tmp,
1316                                 ep->pio_irqs, ep->dma_irqs);
1317                         /* TODO translate all five groups of udccs bits! */
1318
1319                 } else /* ep0 should only have one transfer queued */
1320                         t = scnprintf(next, size, "ep0 max 16 pio irqs %lu\n",
1321                                 ep->pio_irqs);
1322                 if (t <= 0 || t > size)
1323                         goto done;
1324                 size -= t;
1325                 next += t;
1326
1327                 if (list_empty(&ep->queue)) {
1328                         t = scnprintf(next, size, "\t(nothing queued)\n");
1329                         if (t <= 0 || t > size)
1330                                 goto done;
1331                         size -= t;
1332                         next += t;
1333                         continue;
1334                 }
1335                 list_for_each_entry(req, &ep->queue, queue) {
1336 #ifdef  USE_DMA
1337                         if (ep->dma >= 0 && req->queue.prev == &ep->queue)
1338                                 t = scnprintf(next, size,
1339                                         "\treq %p len %d/%d "
1340                                         "buf %p (dma%d dcmd %08x)\n",
1341                                         &req->req, req->req.actual,
1342                                         req->req.length, req->req.buf,
1343                                         ep->dma, DCMD(ep->dma)
1344                                         // low 13 bits == bytes-to-go
1345                                         );
1346                         else
1347 #endif
1348                                 t = scnprintf(next, size,
1349                                         "\treq %p len %d/%d buf %p\n",
1350                                         &req->req, req->req.actual,
1351                                         req->req.length, req->req.buf);
1352                         if (t <= 0 || t > size)
1353                                 goto done;
1354                         size -= t;
1355                         next += t;
1356                 }
1357         }
1358
1359 done:
1360         local_irq_restore(flags);
1361         *eof = 1;
1362         return count - size;
1363 }
1364
1365 #define create_proc_files() \
1366         create_proc_read_entry(proc_node_name, 0, NULL, udc_proc_read, dev)
1367 #define remove_proc_files() \
1368         remove_proc_entry(proc_node_name, NULL)
1369
1370 #else   /* !UDC_PROC_FILE */
1371 #define create_proc_files() do {} while (0)
1372 #define remove_proc_files() do {} while (0)
1373
1374 #endif  /* UDC_PROC_FILE */
1375
1376 /* "function" sysfs attribute */
1377 static ssize_t
1378 show_function (struct device *_dev, char *buf)
1379 {
1380         struct pxa2xx_udc       *dev = dev_get_drvdata (_dev);
1381
1382         if (!dev->driver
1383                         || !dev->driver->function
1384                         || strlen (dev->driver->function) > PAGE_SIZE)
1385                 return 0;
1386         return scnprintf (buf, PAGE_SIZE, "%s\n", dev->driver->function);
1387 }
1388 static DEVICE_ATTR (function, S_IRUGO, show_function, NULL);
1389
1390 /*-------------------------------------------------------------------------*/
1391
1392 /*
1393  *      udc_disable - disable USB device controller
1394  */
1395 static void udc_disable(struct pxa2xx_udc *dev)
1396 {
1397         /* block all irqs */
1398         udc_set_mask_UDCCR(UDCCR_SRM|UDCCR_REM);
1399         UICR0 = UICR1 = 0xff;
1400         UFNRH = UFNRH_SIM;
1401
1402         /* if hardware supports it, disconnect from usb */
1403         make_usb_disappear();
1404
1405         udc_clear_mask_UDCCR(UDCCR_UDE);
1406
1407 #ifdef  CONFIG_ARCH_PXA
1408         /* Disable clock for USB device */
1409         CKEN &= ~CKEN11_USB;
1410 #endif
1411
1412         ep0_idle (dev);
1413         dev->gadget.speed = USB_SPEED_UNKNOWN;
1414         LED_CONNECTED_OFF;
1415 }
1416
1417
1418 /*
1419  *      udc_reinit - initialize software state
1420  */
1421 static void udc_reinit(struct pxa2xx_udc *dev)
1422 {
1423         u32     i;
1424
1425         /* device/ep0 records init */
1426         INIT_LIST_HEAD (&dev->gadget.ep_list);
1427         INIT_LIST_HEAD (&dev->gadget.ep0->ep_list);
1428         dev->ep0state = EP0_IDLE;
1429
1430         /* basic endpoint records init */
1431         for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1432                 struct pxa2xx_ep *ep = &dev->ep[i];
1433
1434                 if (i != 0)
1435                         list_add_tail (&ep->ep.ep_list, &dev->gadget.ep_list);
1436
1437                 ep->desc = 0;
1438                 ep->stopped = 0;
1439                 INIT_LIST_HEAD (&ep->queue);
1440                 ep->pio_irqs = ep->dma_irqs = 0;
1441         }
1442
1443         /* the rest was statically initialized, and is read-only */
1444 }
1445
1446 /* until it's enabled, this UDC should be completely invisible
1447  * to any USB host.
1448  */
1449 static void udc_enable (struct pxa2xx_udc *dev)
1450 {
1451         udc_clear_mask_UDCCR(UDCCR_UDE);
1452
1453 #ifdef  CONFIG_ARCH_PXA
1454         /* Enable clock for USB device */
1455         CKEN |= CKEN11_USB;
1456 #endif
1457
1458         /* try to clear these bits before we enable the udc */
1459         udc_ack_int_UDCCR(UDCCR_SUSIR|/*UDCCR_RSTIR|*/UDCCR_RESIR);
1460
1461         ep0_idle(dev);
1462         dev->gadget.speed = USB_SPEED_UNKNOWN;
1463         dev->stats.irqs = 0;
1464
1465         /*
1466          * sequence taken from chapter 12.5.10, PXA250 AppProcDevManual:
1467          * - enable UDC
1468          * - if RESET is already in progress, ack interrupt
1469          * - unmask reset interrupt
1470          */
1471         udc_set_mask_UDCCR(UDCCR_UDE);
1472         if (!(UDCCR & UDCCR_UDA))
1473                 udc_ack_int_UDCCR(UDCCR_RSTIR);
1474
1475         if (dev->has_cfr /* UDC_RES2 is defined */) {
1476                 /* pxa255 (a0+) can avoid a set_config race that could
1477                  * prevent gadget drivers from configuring correctly
1478                  */
1479                 UDCCFR = UDCCFR_ACM;
1480         } else {
1481                 /* "USB test mode" for pxa250 errata 40-42 (stepping a0, a1)
1482                  * which could result in missing packets and interrupts.
1483                  * supposedly one bit per endpoint, controlling whether it
1484                  * double buffers or not; ACM/AREN bits fit into the holes.
1485                  * zero bits (like USIR0_IRx) disable double buffering.
1486                  */
1487                 UDC_RES1 = 0x00;
1488                 UDC_RES2 = 0x00;
1489         }
1490
1491 #ifdef  DISABLE_TEST_MODE
1492         /* "test mode" seems to have become the default in later chip
1493          * revs, preventing double buffering (and invalidating docs).
1494          * this EXPERIMENT enables it for bulk endpoints by tweaking
1495          * undefined/reserved register bits (that other drivers clear).
1496          * Belcarra code comments noted this usage.
1497          */
1498         if (fifo_mode & 1) {    /* IN endpoints */
1499                 UDC_RES1 |= USIR0_IR1|USIR0_IR6;
1500                 UDC_RES2 |= USIR1_IR11;
1501         }
1502         if (fifo_mode & 2) {    /* OUT endpoints */
1503                 UDC_RES1 |= USIR0_IR2|USIR0_IR7;
1504                 UDC_RES2 |= USIR1_IR12;
1505         }
1506 #endif
1507
1508         /* caller must be able to sleep in order to cope
1509          * with startup transients.
1510          */
1511         schedule_timeout(HZ/10);
1512
1513         /* enable suspend/resume and reset irqs */
1514         udc_clear_mask_UDCCR(UDCCR_SRM | UDCCR_REM);
1515
1516         /* enable ep0 irqs */
1517         UICR0 &= ~UICR0_IM0;
1518
1519         /* if hardware supports it, connect to usb and wait for host */
1520         let_usb_appear();
1521 }
1522
1523
1524 /* when a driver is successfully registered, it will receive
1525  * control requests including set_configuration(), which enables
1526  * non-control requests.  then usb traffic follows until a
1527  * disconnect is reported.  then a host may connect again, or
1528  * the driver might get unbound.
1529  */
1530 int usb_gadget_register_driver(struct usb_gadget_driver *driver)
1531 {
1532         struct pxa2xx_udc       *dev = the_controller;
1533         int                     retval;
1534
1535         if (!driver
1536                         || driver->speed != USB_SPEED_FULL
1537                         || !driver->bind
1538                         || !driver->unbind
1539                         || !driver->disconnect
1540                         || !driver->setup)
1541                 return -EINVAL;
1542         if (!dev)
1543                 return -ENODEV;
1544         if (dev->driver)
1545                 return -EBUSY;
1546
1547         /* first hook up the driver ... */
1548         dev->driver = driver;
1549         dev->gadget.dev.driver = &driver->driver;
1550
1551         device_add (&dev->gadget.dev);
1552         retval = driver->bind(&dev->gadget);
1553         if (retval) {
1554                 DMSG("bind to driver %s --> error %d\n",
1555                                 driver->driver.name, retval);
1556                 device_del (&dev->gadget.dev);
1557
1558                 dev->driver = 0;
1559                 dev->gadget.dev.driver = 0;
1560                 return retval;
1561         }
1562         device_create_file(dev->dev, &dev_attr_function);
1563
1564         /* ... then enable host detection and ep0; and we're ready
1565          * for set_configuration as well as eventual disconnect.
1566          * NOTE:  this shouldn't power up until later.
1567          */
1568         DMSG("registered gadget driver '%s'\n", driver->driver.name);
1569         udc_enable(dev);
1570         dump_state(dev);
1571         return 0;
1572 }
1573 EXPORT_SYMBOL(usb_gadget_register_driver);
1574
1575 static void
1576 stop_activity(struct pxa2xx_udc *dev, struct usb_gadget_driver *driver)
1577 {
1578         int i;
1579
1580         /* don't disconnect drivers more than once */
1581         if (dev->gadget.speed == USB_SPEED_UNKNOWN)
1582                 driver = 0;
1583         dev->gadget.speed = USB_SPEED_UNKNOWN;
1584
1585         /* prevent new request submissions, kill any outstanding requests  */
1586         for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1587                 struct pxa2xx_ep *ep = &dev->ep[i];
1588
1589                 ep->stopped = 1;
1590                 nuke(ep, -ESHUTDOWN);
1591         }
1592         del_timer_sync(&dev->timer);
1593
1594         /* report disconnect; the driver is already quiesced */
1595         LED_CONNECTED_OFF;
1596         if (driver)
1597                 driver->disconnect(&dev->gadget);
1598
1599         /* re-init driver-visible data structures */
1600         udc_reinit(dev);
1601 }
1602
1603 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
1604 {
1605         struct pxa2xx_udc       *dev = the_controller;
1606
1607         if (!dev)
1608                 return -ENODEV;
1609         if (!driver || driver != dev->driver)
1610                 return -EINVAL;
1611
1612         local_irq_disable();
1613         udc_disable(dev);
1614         stop_activity(dev, driver);
1615         local_irq_enable();
1616
1617         driver->unbind(&dev->gadget);
1618         dev->driver = 0;
1619
1620         device_del (&dev->gadget.dev);
1621         device_remove_file(dev->dev, &dev_attr_function);
1622
1623         DMSG("unregistered gadget driver '%s'\n", driver->driver.name);
1624         dump_state(dev);
1625         return 0;
1626 }
1627 EXPORT_SYMBOL(usb_gadget_unregister_driver);
1628
1629
1630 /*-------------------------------------------------------------------------*/
1631
1632 #ifdef CONFIG_ARCH_LUBBOCK
1633
1634 /* Lubbock can report connect or disconnect irqs.  Likely more hardware
1635  * could support it as a timer callback.
1636  *
1637  * FIXME for better power management, keep the hardware powered down
1638  * until a host is powering the link.  means scheduling work later
1639  * in some task that can udc_enable().
1640  */
1641
1642 #define enable_disconnect_irq() \
1643         if (machine_is_lubbock()) { enable_irq(LUBBOCK_USB_DISC_IRQ); }
1644 #define disable_disconnect_irq() \
1645         if (machine_is_lubbock()) { disable_irq(LUBBOCK_USB_DISC_IRQ); }
1646
1647 static irqreturn_t
1648 usb_connection_irq(int irq, void *_dev, struct pt_regs *r)
1649 {
1650         struct pxa2xx_udc       *dev = _dev;
1651
1652         dev->stats.irqs++;
1653         HEX_DISPLAY(dev->stats.irqs);
1654
1655         if (!is_usb_connected()) {
1656                 LED_CONNECTED_OFF;
1657                 disable_disconnect_irq();
1658                 /* report disconnect just once */
1659                 if (dev->gadget.speed != USB_SPEED_UNKNOWN) {
1660                         DMSG("disconnect %s\n",
1661                                 dev->driver ? dev->driver->driver.name : 0);
1662                         stop_activity(dev, dev->driver);
1663
1664                         // udc_disable (dev);
1665                         // no more udc irqs
1666                         // maybe "ACTION=disconnect /sbin/hotplug gadget".
1667                 }
1668         } else if (dev->gadget.speed == USB_SPEED_UNKNOWN) {
1669                 LED_CONNECTED_ON;
1670
1671                 DMSG("?? connect irq ??\n");
1672
1673                 // if there's no driver bound, ignore; else
1674                 // udc_enable (dev);
1675                 // UDC irqs drive the rest.
1676                 // maybe "ACTION=connect /sbin/hotplug gadget".
1677         }
1678         return IRQ_HANDLED;
1679 }
1680
1681 #endif
1682
1683 #ifndef enable_disconnect_irq
1684 #warning USB disconnect() is not yet reported.
1685 #define enable_disconnect_irq()         do {} while (0)
1686 #define disable_disconnect_irq()        do {} while (0)
1687 #endif
1688
1689
1690 /*-------------------------------------------------------------------------*/
1691
1692 static inline void clear_ep_state (struct pxa2xx_udc *dev)
1693 {
1694         unsigned i;
1695
1696         /* hardware SET_{CONFIGURATION,INTERFACE} automagic resets endpoint
1697          * fifos, and pending transactions mustn't be continued in any case.
1698          */
1699         for (i = 1; i < PXA_UDC_NUM_ENDPOINTS; i++)
1700                 nuke(&dev->ep[i], -ECONNABORTED);
1701 }
1702
1703 static void udc_watchdog(unsigned long _dev)
1704 {
1705         struct pxa2xx_udc       *dev = (void *)_dev;
1706
1707         local_irq_disable();
1708         if (dev->ep0state == EP0_STALL
1709                         && (UDCCS0 & UDCCS0_FST) == 0
1710                         && (UDCCS0 & UDCCS0_SST) == 0) {
1711                 UDCCS0 = UDCCS0_FST|UDCCS0_FTF;
1712                 DBG(DBG_VERBOSE, "ep0 re-stall\n");
1713                 start_watchdog(dev);
1714         }
1715         local_irq_enable();
1716 }
1717
1718 static void handle_ep0 (struct pxa2xx_udc *dev)
1719 {
1720         u32                     udccs0 = UDCCS0;
1721         struct pxa2xx_ep        *ep = &dev->ep [0];
1722         struct pxa2xx_request   *req;
1723         union {
1724                 struct usb_ctrlrequest  r;
1725                 u8                      raw [8];
1726                 u32                     word [2];
1727         } u;
1728
1729         if (list_empty(&ep->queue))
1730                 req = 0;
1731         else
1732                 req = list_entry(ep->queue.next, struct pxa2xx_request, queue);
1733
1734         /* clear stall status */
1735         if (udccs0 & UDCCS0_SST) {
1736                 nuke(ep, -EPIPE);
1737                 UDCCS0 = UDCCS0_SST;
1738                 del_timer(&dev->timer);
1739                 ep0_idle(dev);
1740         }
1741
1742         /* previous request unfinished?  non-error iff back-to-back ... */
1743         if ((udccs0 & UDCCS0_SA) != 0 && dev->ep0state != EP0_IDLE) {
1744                 nuke(ep, 0);
1745                 del_timer(&dev->timer);
1746                 ep0_idle(dev);
1747         }
1748
1749         switch (dev->ep0state) {
1750         case EP0_IDLE:
1751                 /* late-breaking status? */
1752                 udccs0 = UDCCS0;
1753
1754                 /* start control request? */
1755                 if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))
1756                                 == (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))) {
1757                         int i;
1758
1759                         nuke (ep, -EPROTO);
1760
1761                         /* read SETUP packet */
1762                         for (i = 0; i < 8; i++) {
1763                                 if (unlikely(!(UDCCS0 & UDCCS0_RNE))) {
1764 bad_setup:
1765                                         DMSG("SETUP %d!\n", i);
1766                                         goto stall;
1767                                 }
1768                                 u.raw [i] = (u8) UDDR0;
1769                         }
1770                         if (unlikely((UDCCS0 & UDCCS0_RNE) != 0))
1771                                 goto bad_setup;
1772
1773 got_setup:
1774                         le16_to_cpus (&u.r.wValue);
1775                         le16_to_cpus (&u.r.wIndex);
1776                         le16_to_cpus (&u.r.wLength);
1777
1778                         LED_EP0_ON;
1779                         DBG(DBG_VERBOSE, "SETUP %02x.%02x v%04x i%04x l%04x\n",
1780                                 u.r.bRequestType, u.r.bRequest,
1781                                 u.r.wValue, u.r.wIndex, u.r.wLength);
1782
1783                         /* cope with automagic for some standard requests. */
1784                         dev->req_std = (u.r.bRequestType & USB_TYPE_MASK)
1785                                                 == USB_TYPE_STANDARD;
1786                         dev->req_config = 0;
1787                         dev->req_pending = 1;
1788                         switch (u.r.bRequest) {
1789                         /* hardware restricts gadget drivers here! */
1790                         case USB_REQ_SET_CONFIGURATION:
1791                                 if (u.r.bRequestType == USB_RECIP_DEVICE) {
1792                                         /* reflect hardware's automagic
1793                                          * up to the gadget driver.
1794                                          */
1795 config_change:
1796                                         dev->req_config = 1;
1797                                         clear_ep_state(dev);
1798                                         /* if !has_cfr, there's no synch
1799                                          * else use AREN (later) not SA|OPR
1800                                          * USIR0_IR0 acts edge sensitive
1801                                          */
1802                                 }
1803                                 break;
1804                         /* ... and here, even more ... */
1805                         case USB_REQ_SET_INTERFACE:
1806                                 if (u.r.bRequestType == USB_RECIP_INTERFACE) {
1807                                         /* udc hardware is broken by design:
1808                                          *  - altsetting may only be zero;
1809                                          *  - hw resets all interfaces' eps;
1810                                          *  - ep reset doesn't include halt(?).
1811                                          */
1812                                         DMSG("broken set_interface (%d/%d)\n",
1813                                                 u.r.wIndex, u.r.wValue);
1814                                         goto config_change;
1815                                 }
1816                                 break;
1817                         /* hardware was supposed to hide this */
1818                         case USB_REQ_SET_ADDRESS:
1819                                 if (u.r.bRequestType == USB_RECIP_DEVICE) {
1820                                         ep0start(dev, 0, "address");
1821                                         return;
1822                                 }
1823                                 break;
1824                         }
1825
1826                         if (u.r.bRequestType & USB_DIR_IN)
1827                                 dev->ep0state = EP0_IN_DATA_PHASE;
1828                         else
1829                                 dev->ep0state = EP0_OUT_DATA_PHASE;
1830
1831                         i = dev->driver->setup(&dev->gadget, &u.r);
1832                         if (i < 0) {
1833                                 /* hardware automagic preventing STALL... */
1834                                 if (dev->req_config) {
1835                                         /* hardware sometimes neglects to tell
1836                                          * tell us about config change events,
1837                                          * so later ones may fail...
1838                                          */
1839                                         WARN("config change %02x fail %d?\n",
1840                                                 u.r.bRequest, i);
1841                                         return;
1842                                         /* TODO experiment:  if has_cfr,
1843                                          * hardware didn't ACK; maybe we
1844                                          * could actually STALL!
1845                                          */
1846                                 }
1847                                 DBG(DBG_VERBOSE, "protocol STALL, "
1848                                         "%02x err %d\n", UDCCS0, i);
1849 stall:
1850                                 /* the watchdog timer helps deal with cases
1851                                  * where udc seems to clear FST wrongly, and
1852                                  * then NAKs instead of STALLing.
1853                                  */
1854                                 ep0start(dev, UDCCS0_FST|UDCCS0_FTF, "stall");
1855                                 start_watchdog(dev);
1856                                 dev->ep0state = EP0_STALL;
1857                                 LED_EP0_OFF;
1858
1859                         /* deferred i/o == no response yet */
1860                         } else if (dev->req_pending) {
1861                                 if (likely(dev->ep0state == EP0_IN_DATA_PHASE
1862                                                 || dev->req_std || u.r.wLength))
1863                                         ep0start(dev, 0, "defer");
1864                                 else
1865                                         ep0start(dev, UDCCS0_IPR, "defer/IPR");
1866                         }
1867
1868                         /* expect at least one data or status stage irq */
1869                         return;
1870
1871                 } else if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA))
1872                                 == (UDCCS0_OPR|UDCCS0_SA))) {
1873                         unsigned i;
1874
1875                         /* pxa210/250 erratum 131 for B0/B1 says RNE lies.
1876                          * still observed on a pxa255 a0.
1877                          */
1878                         DBG(DBG_VERBOSE, "e131\n");
1879                         nuke(ep, -EPROTO);
1880
1881                         /* read SETUP data, but don't trust it too much */
1882                         for (i = 0; i < 8; i++)
1883                                 u.raw [i] = (u8) UDDR0;
1884                         if ((u.r.bRequestType & USB_RECIP_MASK)
1885                                         > USB_RECIP_OTHER)
1886                                 goto stall;
1887                         if (u.word [0] == 0 && u.word [1] == 0)
1888                                 goto stall;
1889                         goto got_setup;
1890                 } else {
1891                         /* some random early IRQ:
1892                          * - we acked FST
1893                          * - IPR cleared
1894                          * - OPR got set, without SA (likely status stage)
1895                          */
1896                         UDCCS0 = udccs0 & (UDCCS0_SA|UDCCS0_OPR);
1897                 }
1898                 break;
1899         case EP0_IN_DATA_PHASE:                 /* GET_DESCRIPTOR etc */
1900                 if (udccs0 & UDCCS0_OPR) {
1901                         UDCCS0 = UDCCS0_OPR|UDCCS0_FTF;
1902                         DBG(DBG_VERBOSE, "ep0in premature status\n");
1903                         if (req)
1904                                 done(ep, req, 0);
1905                         ep0_idle(dev);
1906                 } else /* irq was IPR clearing */ {
1907                         if (req) {
1908                                 /* this IN packet might finish the request */
1909                                 (void) write_ep0_fifo(ep, req);
1910                         } /* else IN token before response was written */
1911                 }
1912                 break;
1913         case EP0_OUT_DATA_PHASE:                /* SET_DESCRIPTOR etc */
1914                 if (udccs0 & UDCCS0_OPR) {
1915                         if (req) {
1916                                 /* this OUT packet might finish the request */
1917                                 if (read_ep0_fifo(ep, req))
1918                                         done(ep, req, 0);
1919                                 /* else more OUT packets expected */
1920                         } /* else OUT token before read was issued */
1921                 } else /* irq was IPR clearing */ {
1922                         DBG(DBG_VERBOSE, "ep0out premature status\n");
1923                         if (req)
1924                                 done(ep, req, 0);
1925                         ep0_idle(dev);
1926                 }
1927                 break;
1928         case EP0_END_XFER:
1929                 if (req)
1930                         done(ep, req, 0);
1931                 /* ack control-IN status (maybe in-zlp was skipped)
1932                  * also appears after some config change events.
1933                  */
1934                 if (udccs0 & UDCCS0_OPR)
1935                         UDCCS0 = UDCCS0_OPR;
1936                 ep0_idle(dev);
1937                 break;
1938         case EP0_STALL:
1939                 UDCCS0 = UDCCS0_FST;
1940                 break;
1941         }
1942         USIR0 = USIR0_IR0;
1943 }
1944
1945 static void handle_ep(struct pxa2xx_ep *ep)
1946 {
1947         struct pxa2xx_request   *req;
1948         int                     is_in = ep->bEndpointAddress & USB_DIR_IN;
1949         int                     completed;
1950         u32                     udccs, tmp;
1951
1952         do {
1953                 completed = 0;
1954                 if (likely (!list_empty(&ep->queue)))
1955                         req = list_entry(ep->queue.next,
1956                                         struct pxa2xx_request, queue);
1957                 else
1958                         req = 0;
1959
1960                 // TODO check FST handling
1961
1962                 udccs = *ep->reg_udccs;
1963                 if (unlikely(is_in)) {  /* irq from TPC, SST, or (ISO) TUR */
1964                         tmp = UDCCS_BI_TUR;
1965                         if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK))
1966                                 tmp |= UDCCS_BI_SST;
1967                         tmp &= udccs;
1968                         if (likely (tmp))
1969                                 *ep->reg_udccs = tmp;
1970                         if (req && likely ((udccs & UDCCS_BI_TFS) != 0))
1971                                 completed = write_fifo(ep, req);
1972
1973                 } else {        /* irq from RPC (or for ISO, ROF) */
1974                         if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK))
1975                                 tmp = UDCCS_BO_SST | UDCCS_BO_DME;
1976                         else
1977                                 tmp = UDCCS_IO_ROF | UDCCS_IO_DME;
1978                         tmp &= udccs;
1979                         if (likely(tmp))
1980                                 *ep->reg_udccs = tmp;
1981
1982                         /* fifos can hold packets, ready for reading... */
1983                         if (likely(req)) {
1984 #ifdef USE_OUT_DMA
1985 // TODO didn't yet debug out-dma.  this approach assumes
1986 // the worst about short packets and RPC; it might be better.
1987
1988                                 if (likely(ep->dma >= 0)) {
1989                                         if (!(udccs & UDCCS_BO_RSP)) {
1990                                                 *ep->reg_udccs = UDCCS_BO_RPC;
1991                                                 ep->dma_irqs++;
1992                                                 return;
1993                                         }
1994                                 }
1995 #endif
1996                                 completed = read_fifo(ep, req);
1997                         } else
1998                                 pio_irq_disable (ep->bEndpointAddress);
1999                 }
2000                 ep->pio_irqs++;
2001         } while (completed);
2002 }
2003
2004 /*
2005  *      pxa2xx_udc_irq - interrupt handler
2006  *
2007  * avoid delays in ep0 processing. the control handshaking isn't always
2008  * under software control (pxa250c0 and the pxa255 are better), and delays
2009  * could cause usb protocol errors.
2010  */
2011 static irqreturn_t
2012 pxa2xx_udc_irq(int irq, void *_dev, struct pt_regs *r)
2013 {
2014         struct pxa2xx_udc       *dev = _dev;
2015         int                     handled;
2016
2017         dev->stats.irqs++;
2018         HEX_DISPLAY(dev->stats.irqs);
2019         do {
2020                 u32             udccr = UDCCR;
2021
2022                 handled = 0;
2023
2024                 /* SUSpend Interrupt Request */
2025                 if (unlikely(udccr & UDCCR_SUSIR)) {
2026                         udc_ack_int_UDCCR(UDCCR_SUSIR);
2027                         handled = 1;
2028                         DBG(DBG_VERBOSE, "USB suspend%s\n", is_usb_connected()
2029                                 ? "" : "+disconnect");
2030
2031                         if (!is_usb_connected())
2032                                 stop_activity(dev, dev->driver);
2033                         else if (dev->gadget.speed != USB_SPEED_UNKNOWN
2034                                         && dev->driver
2035                                         && dev->driver->suspend)
2036                                 dev->driver->suspend(&dev->gadget);
2037                         ep0_idle (dev);
2038                 }
2039
2040                 /* RESume Interrupt Request */
2041                 if (unlikely(udccr & UDCCR_RESIR)) {
2042                         udc_ack_int_UDCCR(UDCCR_RESIR);
2043                         handled = 1;
2044                         DBG(DBG_VERBOSE, "USB resume\n");
2045
2046                         if (dev->gadget.speed != USB_SPEED_UNKNOWN
2047                                         && dev->driver
2048                                         && dev->driver->resume
2049                                         && is_usb_connected())
2050                                 dev->driver->resume(&dev->gadget);
2051                 }
2052
2053                 /* ReSeT Interrupt Request - USB reset */
2054                 if (unlikely(udccr & UDCCR_RSTIR)) {
2055                         udc_ack_int_UDCCR(UDCCR_RSTIR);
2056                         handled = 1;
2057
2058                         if ((UDCCR & UDCCR_UDA) == 0) {
2059                                 DBG(DBG_VERBOSE, "USB reset start\n");
2060                                 if (dev->gadget.speed != USB_SPEED_UNKNOWN)
2061                                         disable_disconnect_irq();
2062
2063                                 /* reset driver and endpoints,
2064                                  * in case that's not yet done
2065                                  */
2066                                 stop_activity (dev, dev->driver);
2067
2068                         } else {
2069                                 INFO("USB reset\n");
2070                                 dev->gadget.speed = USB_SPEED_FULL;
2071                                 LED_CONNECTED_ON;
2072                                 memset(&dev->stats, 0, sizeof dev->stats);
2073                                 /* driver and endpoints are still reset */
2074                                 enable_disconnect_irq();
2075                         }
2076
2077                 } else {
2078                         u32     usir0 = USIR0 & ~UICR0;
2079                         u32     usir1 = USIR1 & ~UICR1;
2080                         int     i;
2081
2082                         if (unlikely (!usir0 && !usir1))
2083                                 continue;
2084
2085                         DBG(DBG_VERY_NOISY, "irq %02x.%02x\n", usir1, usir0);
2086
2087                         /* control traffic */
2088                         if (usir0 & USIR0_IR0) {
2089                                 dev->ep[0].pio_irqs++;
2090                                 handle_ep0(dev);
2091                                 handled = 1;
2092                         }
2093
2094                         /* endpoint data transfers */
2095                         for (i = 0; i < 8; i++) {
2096                                 u32     tmp = 1 << i;
2097
2098                                 if (i && (usir0 & tmp)) {
2099                                         handle_ep(&dev->ep[i]);
2100                                         USIR0 |= tmp;
2101                                         handled = 1;
2102                                 }
2103                                 if (usir1 & tmp) {
2104                                         handle_ep(&dev->ep[i+8]);
2105                                         USIR1 |= tmp;
2106                                         handled = 1;
2107                                 }
2108                         }
2109                 }
2110
2111                 /* we could also ask for 1 msec SOF (SIR) interrupts */
2112
2113         } while (handled);
2114         return IRQ_HANDLED;
2115 }
2116
2117 /*-------------------------------------------------------------------------*/
2118
2119 static void nop_release (struct device *dev)
2120 {
2121         DMSG("%s %s\n", __FUNCTION__, dev->bus_id);
2122 }
2123
2124 /* this uses load-time allocation and initialization (instead of
2125  * doing it at run-time) to save code, eliminate fault paths, and
2126  * be more obviously correct.
2127  */
2128 static struct pxa2xx_udc memory = {
2129         .gadget = {
2130                 .ops            = &pxa2xx_udc_ops,
2131                 .ep0            = &memory.ep[0].ep,
2132                 .name           = driver_name,
2133                 .dev = {
2134                         .bus_id         = "gadget",
2135                         .release        = nop_release,
2136                 },
2137         },
2138
2139         /* control endpoint */
2140         .ep[0] = {
2141                 .ep = {
2142                         .name           = ep0name,
2143                         .ops            = &pxa2xx_ep_ops,
2144                         .maxpacket      = EP0_FIFO_SIZE,
2145                 },
2146                 .dev            = &memory,
2147                 .reg_udccs      = &UDCCS0,
2148                 .reg_uddr       = &UDDR0,
2149         },
2150
2151         /* first group of endpoints */
2152         .ep[1] = {
2153                 .ep = {
2154                         .name           = "ep1in-bulk",
2155                         .ops            = &pxa2xx_ep_ops,
2156                         .maxpacket      = BULK_FIFO_SIZE,
2157                 },
2158                 .dev            = &memory,
2159                 .fifo_size      = BULK_FIFO_SIZE,
2160                 .bEndpointAddress = USB_DIR_IN | 1,
2161                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
2162                 .reg_udccs      = &UDCCS1,
2163                 .reg_uddr       = &UDDR1,
2164                 drcmr (25)
2165         },
2166         .ep[2] = {
2167                 .ep = {
2168                         .name           = "ep2out-bulk",
2169                         .ops            = &pxa2xx_ep_ops,
2170                         .maxpacket      = BULK_FIFO_SIZE,
2171                 },
2172                 .dev            = &memory,
2173                 .fifo_size      = BULK_FIFO_SIZE,
2174                 .bEndpointAddress = 2,
2175                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
2176                 .reg_udccs      = &UDCCS2,
2177                 .reg_ubcr       = &UBCR2,
2178                 .reg_uddr       = &UDDR2,
2179                 drcmr (26)
2180         },
2181 #ifndef CONFIG_USB_PXA2XX_SMALL
2182         .ep[3] = {
2183                 .ep = {
2184                         .name           = "ep3in-iso",
2185                         .ops            = &pxa2xx_ep_ops,
2186                         .maxpacket      = ISO_FIFO_SIZE,
2187                 },
2188                 .dev            = &memory,
2189                 .fifo_size      = ISO_FIFO_SIZE,
2190                 .bEndpointAddress = USB_DIR_IN | 3,
2191                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
2192                 .reg_udccs      = &UDCCS3,
2193                 .reg_uddr       = &UDDR3,
2194                 drcmr (27)
2195         },
2196         .ep[4] = {
2197                 .ep = {
2198                         .name           = "ep4out-iso",
2199                         .ops            = &pxa2xx_ep_ops,
2200                         .maxpacket      = ISO_FIFO_SIZE,
2201                 },
2202                 .dev            = &memory,
2203                 .fifo_size      = ISO_FIFO_SIZE,
2204                 .bEndpointAddress = 4,
2205                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
2206                 .reg_udccs      = &UDCCS4,
2207                 .reg_ubcr       = &UBCR4,
2208                 .reg_uddr       = &UDDR4,
2209                 drcmr (28)
2210         },
2211         .ep[5] = {
2212                 .ep = {
2213                         .name           = "ep5in-int",
2214                         .ops            = &pxa2xx_ep_ops,
2215                         .maxpacket      = INT_FIFO_SIZE,
2216                 },
2217                 .dev            = &memory,
2218                 .fifo_size      = INT_FIFO_SIZE,
2219                 .bEndpointAddress = USB_DIR_IN | 5,
2220                 .bmAttributes   = USB_ENDPOINT_XFER_INT,
2221                 .reg_udccs      = &UDCCS5,
2222                 .reg_uddr       = &UDDR5,
2223         },
2224
2225         /* second group of endpoints */
2226         .ep[6] = {
2227                 .ep = {
2228                         .name           = "ep6in-bulk",
2229                         .ops            = &pxa2xx_ep_ops,
2230                         .maxpacket      = BULK_FIFO_SIZE,
2231                 },
2232                 .dev            = &memory,
2233                 .fifo_size      = BULK_FIFO_SIZE,
2234                 .bEndpointAddress = USB_DIR_IN | 6,
2235                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
2236                 .reg_udccs      = &UDCCS6,
2237                 .reg_uddr       = &UDDR6,
2238                 drcmr (30)
2239         },
2240         .ep[7] = {
2241                 .ep = {
2242                         .name           = "ep7out-bulk",
2243                         .ops            = &pxa2xx_ep_ops,
2244                         .maxpacket      = BULK_FIFO_SIZE,
2245                 },
2246                 .dev            = &memory,
2247                 .fifo_size      = BULK_FIFO_SIZE,
2248                 .bEndpointAddress = 7,
2249                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
2250                 .reg_udccs      = &UDCCS7,
2251                 .reg_ubcr       = &UBCR7,
2252                 .reg_uddr       = &UDDR7,
2253                 drcmr (31)
2254         },
2255         .ep[8] = {
2256                 .ep = {
2257                         .name           = "ep8in-iso",
2258                         .ops            = &pxa2xx_ep_ops,
2259                         .maxpacket      = ISO_FIFO_SIZE,
2260                 },
2261                 .dev            = &memory,
2262                 .fifo_size      = ISO_FIFO_SIZE,
2263                 .bEndpointAddress = USB_DIR_IN | 8,
2264                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
2265                 .reg_udccs      = &UDCCS8,
2266                 .reg_uddr       = &UDDR8,
2267                 drcmr (32)
2268         },
2269         .ep[9] = {
2270                 .ep = {
2271                         .name           = "ep9out-iso",
2272                         .ops            = &pxa2xx_ep_ops,
2273                         .maxpacket      = ISO_FIFO_SIZE,
2274                 },
2275                 .dev            = &memory,
2276                 .fifo_size      = ISO_FIFO_SIZE,
2277                 .bEndpointAddress = 9,
2278                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
2279                 .reg_udccs      = &UDCCS9,
2280                 .reg_ubcr       = &UBCR9,
2281                 .reg_uddr       = &UDDR9,
2282                 drcmr (33)
2283         },
2284         .ep[10] = {
2285                 .ep = {
2286                         .name           = "ep10in-int",
2287                         .ops            = &pxa2xx_ep_ops,
2288                         .maxpacket      = INT_FIFO_SIZE,
2289                 },
2290                 .dev            = &memory,
2291                 .fifo_size      = INT_FIFO_SIZE,
2292                 .bEndpointAddress = USB_DIR_IN | 10,
2293                 .bmAttributes   = USB_ENDPOINT_XFER_INT,
2294                 .reg_udccs      = &UDCCS10,
2295                 .reg_uddr       = &UDDR10,
2296         },
2297
2298         /* third group of endpoints */
2299         .ep[11] = {
2300                 .ep = {
2301                         .name           = "ep11in-bulk",
2302                         .ops            = &pxa2xx_ep_ops,
2303                         .maxpacket      = BULK_FIFO_SIZE,
2304                 },
2305                 .dev            = &memory,
2306                 .fifo_size      = BULK_FIFO_SIZE,
2307                 .bEndpointAddress = USB_DIR_IN | 11,
2308                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
2309                 .reg_udccs      = &UDCCS11,
2310                 .reg_uddr       = &UDDR11,
2311                 drcmr (35)
2312         },
2313         .ep[12] = {
2314                 .ep = {
2315                         .name           = "ep12out-bulk",
2316                         .ops            = &pxa2xx_ep_ops,
2317                         .maxpacket      = BULK_FIFO_SIZE,
2318                 },
2319                 .dev            = &memory,
2320                 .fifo_size      = BULK_FIFO_SIZE,
2321                 .bEndpointAddress = 12,
2322                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
2323                 .reg_udccs      = &UDCCS12,
2324                 .reg_ubcr       = &UBCR12,
2325                 .reg_uddr       = &UDDR12,
2326                 drcmr (36)
2327         },
2328         .ep[13] = {
2329                 .ep = {
2330                         .name           = "ep13in-iso",
2331                         .ops            = &pxa2xx_ep_ops,
2332                         .maxpacket      = ISO_FIFO_SIZE,
2333                 },
2334                 .dev            = &memory,
2335                 .fifo_size      = ISO_FIFO_SIZE,
2336                 .bEndpointAddress = USB_DIR_IN | 13,
2337                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
2338                 .reg_udccs      = &UDCCS13,
2339                 .reg_uddr       = &UDDR13,
2340                 drcmr (37)
2341         },
2342         .ep[14] = {
2343                 .ep = {
2344                         .name           = "ep14out-iso",
2345                         .ops            = &pxa2xx_ep_ops,
2346                         .maxpacket      = ISO_FIFO_SIZE,
2347                 },
2348                 .dev            = &memory,
2349                 .fifo_size      = ISO_FIFO_SIZE,
2350                 .bEndpointAddress = 14,
2351                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
2352                 .reg_udccs      = &UDCCS14,
2353                 .reg_ubcr       = &UBCR14,
2354                 .reg_uddr       = &UDDR14,
2355                 drcmr (38)
2356         },
2357         .ep[15] = {
2358                 .ep = {
2359                         .name           = "ep15in-int",
2360                         .ops            = &pxa2xx_ep_ops,
2361                         .maxpacket      = INT_FIFO_SIZE,
2362                 },
2363                 .dev            = &memory,
2364                 .fifo_size      = INT_FIFO_SIZE,
2365                 .bEndpointAddress = USB_DIR_IN | 15,
2366                 .bmAttributes   = USB_ENDPOINT_XFER_INT,
2367                 .reg_udccs      = &UDCCS15,
2368                 .reg_uddr       = &UDDR15,
2369         },
2370 #endif /* !CONFIG_USB_PXA2XX_SMALL */
2371 };
2372
2373 #define CP15R0_VENDOR_MASK      0xffffe000
2374
2375 #if     defined(CONFIG_ARCH_PXA)
2376 #define CP15R0_XSCALE_VALUE     0x69052000      /* intel/arm/xscale */
2377
2378 #elif   defined(CONFIG_ARCH_IXP4XX)
2379 #define CP15R0_XSCALE_VALUE     0x69054000      /* intel/arm/ixp4xx */
2380
2381 #endif
2382
2383 #define CP15R0_PROD_MASK        0x000003f0
2384 #define PXA25x                  0x00000100      /* and PXA26x */
2385 #define PXA210                  0x00000120
2386
2387 #define CP15R0_REV_MASK         0x0000000f
2388
2389 #define CP15R0_PRODREV_MASK     (CP15R0_PROD_MASK | CP15R0_REV_MASK)
2390
2391 #define PXA255_A0               0x00000106      /* or PXA260_B1 */
2392 #define PXA250_C0               0x00000105      /* or PXA26x_B0 */
2393 #define PXA250_B2               0x00000104
2394 #define PXA250_B1               0x00000103      /* or PXA260_A0 */
2395 #define PXA250_B0               0x00000102
2396 #define PXA250_A1               0x00000101
2397 #define PXA250_A0               0x00000100
2398
2399 #define PXA210_C0               0x00000125
2400 #define PXA210_B2               0x00000124
2401 #define PXA210_B1               0x00000123
2402 #define PXA210_B0               0x00000122
2403 #define IXP425_A0               0x000001c1
2404
2405 /*
2406  *      probe - binds to the platform device
2407  */
2408 static int __init pxa2xx_udc_probe(struct device *_dev)
2409 {
2410         struct pxa2xx_udc *dev = &memory;
2411         int retval, out_dma = 1;
2412         u32 chiprev;
2413
2414         /* insist on Intel/ARM/XScale */
2415         asm("mrc%? p15, 0, %0, c0, c0" : "=r" (chiprev));
2416         if ((chiprev & CP15R0_VENDOR_MASK) != CP15R0_XSCALE_VALUE) {
2417                 printk(KERN_ERR "%s: not XScale!\n", driver_name);
2418                 return -ENODEV;
2419         }
2420
2421         /* trigger chiprev-specific logic */
2422         switch (chiprev & CP15R0_PRODREV_MASK) {
2423 #if     defined(CONFIG_ARCH_PXA)
2424         case PXA255_A0:
2425                 dev->has_cfr = 1;
2426                 break;
2427         case PXA250_A0:
2428         case PXA250_A1:
2429                 /* A0/A1 "not released"; ep 13, 15 unusable */
2430                 /* fall through */
2431         case PXA250_B2: case PXA210_B2:
2432         case PXA250_B1: case PXA210_B1:
2433         case PXA250_B0: case PXA210_B0:
2434                 out_dma = 0;
2435                 /* fall through */
2436         case PXA250_C0: case PXA210_C0:
2437                 break;
2438 #elif   defined(CONFIG_ARCH_IXP4XX)
2439         case IXP425_A0:
2440                 out_dma = 0;
2441                 break;
2442 #endif
2443         default:
2444                 out_dma = 0;
2445                 printk(KERN_ERR "%s: unrecognized processor: %08x\n",
2446                         driver_name, chiprev);
2447                 /* iop3xx, ixp4xx, ... */
2448                 return -ENODEV;
2449         }
2450
2451         pr_debug("%s: IRQ %d%s%s%s\n", driver_name, IRQ_USB,
2452                 dev->has_cfr ? "" : " (!cfr)",
2453                 out_dma ? "" : " (broken dma-out)",
2454                 SIZE_STR DMASTR
2455                 );
2456
2457 #ifdef  USE_DMA
2458 #ifndef USE_OUT_DMA
2459         out_dma = 0;
2460 #endif
2461         /* pxa 250 erratum 130 prevents using OUT dma (fixed C0) */
2462         if (!out_dma) {
2463                 DMSG("disabled OUT dma\n");
2464                 dev->ep[ 2].reg_drcmr = dev->ep[ 4].reg_drcmr = 0;
2465                 dev->ep[ 7].reg_drcmr = dev->ep[ 9].reg_drcmr = 0;
2466                 dev->ep[12].reg_drcmr = dev->ep[14].reg_drcmr = 0;
2467         }
2468 #endif
2469
2470         /* other non-static parts of init */
2471         dev->dev = _dev;
2472         dev->mach = _dev->platform_data;
2473
2474         init_timer(&dev->timer);
2475         dev->timer.function = udc_watchdog;
2476         dev->timer.data = (unsigned long) dev;
2477
2478         device_initialize(&dev->gadget.dev);
2479         dev->gadget.dev.parent = _dev;
2480         dev->gadget.dev.dma_mask = _dev->dma_mask;
2481
2482         the_controller = dev;
2483         dev_set_drvdata(_dev, dev);
2484
2485         udc_disable(dev);
2486         udc_reinit(dev);
2487
2488         /* irq setup after old hardware state is cleaned up */
2489         retval = request_irq(IRQ_USB, pxa2xx_udc_irq,
2490                         SA_INTERRUPT, driver_name, dev);
2491         if (retval != 0) {
2492                 printk(KERN_ERR "%s: can't get irq %i, err %d\n",
2493                         driver_name, IRQ_USB, retval);
2494                 return -EBUSY;
2495         }
2496         dev->got_irq = 1;
2497
2498 #ifdef CONFIG_ARCH_LUBBOCK
2499         if (machine_is_lubbock()) {
2500                 disable_irq(LUBBOCK_USB_DISC_IRQ);
2501                 retval = request_irq(LUBBOCK_USB_DISC_IRQ,
2502                                 usb_connection_irq,
2503                                 SA_INTERRUPT /* OOPSING | SA_SAMPLE_RANDOM */,
2504                                 driver_name, dev);
2505                 if (retval != 0) {
2506                         enable_irq(LUBBOCK_USB_DISC_IRQ);
2507                         printk(KERN_ERR "%s: can't get irq %i, err %d\n",
2508                                 driver_name, LUBBOCK_USB_DISC_IRQ, retval);
2509                         return -EBUSY;
2510                 }
2511                 dev->got_disc = 1;
2512         }
2513 #endif
2514         create_proc_files();
2515
2516         return 0;
2517 }
2518 static int __exit pxa2xx_udc_remove(struct device *_dev)
2519 {
2520         struct pxa2xx_udc *dev = _dev->driver_data;
2521
2522         udc_disable(dev);
2523         remove_proc_files();
2524         usb_gadget_unregister_driver(dev->driver);
2525
2526         if (dev->got_irq) {
2527                 free_irq(IRQ_USB, dev);
2528                 dev->got_irq = 0;
2529         }
2530         if (machine_is_lubbock() && dev->got_disc) {
2531                 free_irq(LUBBOCK_USB_DISC_IRQ, dev);
2532                 dev->got_disc = 0;
2533         }
2534         dev_set_drvdata(_dev, 0);
2535         the_controller = 0;
2536         return 0;
2537 }
2538
2539 /*-------------------------------------------------------------------------*/
2540
2541 static struct device_driver udc_driver = {
2542         .name           = (char *) driver_name,
2543         .bus            = &platform_bus_type,
2544         .probe          = pxa2xx_udc_probe,
2545         .remove         = __exit_p(pxa2xx_udc_remove),
2546
2547         // FIXME power management support
2548         // .suspend = ... disable UDC
2549         // .resume = ... re-enable UDC
2550 };
2551
2552 static int __init udc_init(void)
2553 {
2554         printk(KERN_INFO "%s: version %s\n", driver_name, DRIVER_VERSION);
2555         return driver_register(&udc_driver);
2556 }
2557 module_init(udc_init);
2558
2559 static void __exit udc_exit(void)
2560 {
2561         driver_unregister(&udc_driver);
2562 }
2563 module_exit(udc_exit);
2564
2565 MODULE_DESCRIPTION(DRIVER_DESC);
2566 MODULE_AUTHOR("Frank Becker, Robert Schwebel, David Brownell");
2567 MODULE_LICENSE("GPL");
2568