drivers/usb/gadget/pxa2xx_udc.c

   1 /*
   2  * linux/drivers/usb/gadget/pxa2xx_udc.c
   3  * Intel PXA2xx and IXP4xx on-chip full speed USB device controllers
   4  *
   5  * Copyright (C) 2002 Intrinsyc, Inc. (Frank Becker)
   6  * Copyright (C) 2003 Robert Schwebel, Pengutronix
   7  * Copyright (C) 2003 Benedikt Spranger, Pengutronix
   8  * Copyright (C) 2003 David Brownell
   9  * Copyright (C) 2003 Joshua Wise
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  24  *
  25  */
  26
  27 #undef  DEBUG
  28 // #define      VERBOSE DBG_VERBOSE
  29
  30 #include <linux/config.h>
  31 #include <linux/module.h>
  32 #include <linux/kernel.h>
  33 #include <linux/ioport.h>
  34 #include <linux/types.h>
  35 #include <linux/version.h>
  36 #include <linux/errno.h>
  37 #include <linux/delay.h>
  38 #include <linux/sched.h>
  39 #include <linux/slab.h>
  40 #include <linux/init.h>
  41 #include <linux/timer.h>
  42 #include <linux/list.h>
  43 #include <linux/interrupt.h>
  44 #include <linux/proc_fs.h>
  45 #include <linux/mm.h>
  46 #include <linux/device.h>
  47 #include <linux/dma-mapping.h>
  48
  49 #include <asm/byteorder.h>
  50 #include <asm/dma.h>
  51 #include <asm/io.h>
  52 #include <asm/irq.h>
  53 #include <asm/system.h>
  54 #include <asm/mach-types.h>
  55 #include <asm/unaligned.h>
  56 #include <asm/hardware.h>
  57 #include <asm/arch/pxa-regs.h>
  58
  59 #include <linux/usb_ch9.h>
  60 #include <linux/usb_gadget.h>
  61
  62 #include <asm/arch/udc.h>
  63
  64
  65 /*
  66  * This driver handles the USB Device Controller (UDC) in Intel's PXA 2xx
  67  * series processors.  The UDC for the IXP 4xx series is very similar.
  68  * There are fifteen endpoints, in addition to ep0.
  69  *
  70  * Such controller drivers work with a gadget driver.  The gadget driver
  71  * returns descriptors, implements configuration and data protocols used
  72  * by the host to interact with this device, and allocates endpoints to
  73  * the different protocol interfaces.  The controller driver virtualizes
  74  * usb hardware so that the gadget drivers will be more portable.
  75  *
  76  * This UDC hardware wants to implement a bit too much USB protocol, so
  77  * it constrains the sorts of USB configuration change events that work.
  78  * The errata for these chips are misleading; some "fixed" bugs from
  79  * pxa250 a0/a1 b0/b1/b2 sure act like they're still there.
  80  */
  81
  82 #define DRIVER_VERSION  "14-Dec-2003"
  83 #define DRIVER_DESC     "PXA 2xx USB Device Controller driver"
  84
  85
  86 static const char driver_name [] = "pxa2xx_udc";
  87
  88 static const char ep0name [] = "ep0";
  89
  90
  91 // #define      USE_DMA
  92 // #define      USE_OUT_DMA
  93 // #define      DISABLE_TEST_MODE
  94
  95 #ifdef CONFIG_ARCH_IXP4XX
  96 #undef USE_DMA
  97
  98 /* cpu-specific register addresses are compiled in to this code */
  99 #ifdef CONFIG_ARCH_PXA
 100 #error "Can't configure both IXP and PXA"
 101 #endif
 102
 103 #endif
 104
 105 #include "pxa2xx_udc.h"
 106
 107
 108 #ifdef  USE_DMA
 109 static int use_dma = 1;
 110 module_param(use_dma, bool, 0);
 111 MODULE_PARM_DESC (use_dma, "true to use dma");
 112
 113 static void dma_nodesc_handler (int dmach, void *_ep, struct pt_regs *r);
 114 static void kick_dma(struct pxa2xx_ep *ep, struct pxa2xx_request *req);
 115
 116 #ifdef USE_OUT_DMA
 117 #define DMASTR " (dma support)"
 118 #else
 119 #define DMASTR " (dma in)"
 120 #endif
 121
 122 #else   /* !USE_DMA */
 123 #define DMASTR " (pio only)"
 124 #undef  USE_OUT_DMA
 125 #endif
 126
 127 #ifdef  CONFIG_USB_PXA2XX_SMALL
 128 #define SIZE_STR        " (small)"
 129 #else
 130 #define SIZE_STR        ""
 131 #endif
 132
 133 #ifdef DISABLE_TEST_MODE
 134 /* (mode == 0) == no undocumented chip tweaks
 135  * (mode & 1)  == double buffer bulk IN
 136  * (mode & 2)  == double buffer bulk OUT
 137  * ... so mode = 3 (or 7, 15, etc) does it for both
 138  */
 139 static ushort fifo_mode = 0;
 140 module_param(fifo_mode, ushort, 0);
 141 MODULE_PARM_DESC (fifo_mode, "pxa2xx udc fifo mode");
 142 #endif
 143
 144 /* ---------------------------------------------------------------------------
 145  *      endpoint related parts of the api to the usb controller hardware,
 146  *      used by gadget driver; and the inner talker-to-hardware core.
 147  * ---------------------------------------------------------------------------
 148  */
 149
 150 static void pxa2xx_ep_fifo_flush (struct usb_ep *ep);
 151 static void nuke (struct pxa2xx_ep *, int status);
 152
 153 static void pio_irq_enable(int bEndpointAddress)
 154 {
 155         bEndpointAddress &= 0xf;
 156         if (bEndpointAddress < 8)
 157                 UICR0 &= ~(1 << bEndpointAddress);
 158         else {
 159                 bEndpointAddress -= 8;
 160                 UICR1 &= ~(1 << bEndpointAddress);
 161         }
 162 }
 163
 164 static void pio_irq_disable(int bEndpointAddress)
 165 {
 166         bEndpointAddress &= 0xf;
 167         if (bEndpointAddress < 8)
 168                 UICR0 |= 1 << bEndpointAddress;
 169         else {
 170                 bEndpointAddress -= 8;
 171                 UICR1 |= 1 << bEndpointAddress;
 172         }
 173 }
 174
 175 /* The UDCCR reg contains mask and interrupt status bits,
 176  * so using '|=' isn't safe as it may ack an interrupt.
 177  */
 178 #define UDCCR_MASK_BITS         (UDCCR_REM | UDCCR_SRM | UDCCR_UDE)
 179
 180 static inline void udc_set_mask_UDCCR(int mask)
 181 {
 182         UDCCR = (UDCCR & UDCCR_MASK_BITS) | (mask & UDCCR_MASK_BITS);
 183 }
 184
 185 static inline void udc_clear_mask_UDCCR(int mask)
 186 {
 187         UDCCR = (UDCCR & UDCCR_MASK_BITS) & ~(mask & UDCCR_MASK_BITS);
 188 }
 189
 190 static inline void udc_ack_int_UDCCR(int mask)
 191 {
 192         /* udccr contains the bits we dont want to change */
 193         __u32 udccr = UDCCR & UDCCR_MASK_BITS;
 194
 195         UDCCR = udccr | (mask & ~UDCCR_MASK_BITS);
 196 }
 197
 198 /*
 199  * endpoint enable/disable
 200  *
 201  * we need to verify the descriptors used to enable endpoints.  since pxa2xx
 202  * endpoint configurations are fixed, and are pretty much always enabled,
 203  * there's not a lot to manage here.
 204  *
 205  * because pxa2xx can't selectively initialize bulk (or interrupt) endpoints,
 206  * (resetting endpoint halt and toggle), SET_INTERFACE is unusable except
 207  * for a single interface (with only the default altsetting) and for gadget
 208  * drivers that don't halt endpoints (not reset by set_interface).  that also
 209  * means that if you use ISO, you must violate the USB spec rule that all
 210  * iso endpoints must be in non-default altsettings.
 211  */
 212 static int pxa2xx_ep_enable (struct usb_ep *_ep,
 213                 const struct usb_endpoint_descriptor *desc)
 214 {
 215         struct pxa2xx_ep        *ep;
 216         struct pxa2xx_udc       *dev;
 217
 218         ep = container_of (_ep, struct pxa2xx_ep, ep);
 219         if (!_ep || !desc || ep->desc || _ep->name == ep0name
 220                         || desc->bDescriptorType != USB_DT_ENDPOINT
 221                         || ep->bEndpointAddress != desc->bEndpointAddress
 222                         || ep->fifo_size < le16_to_cpu
 223                                                 (desc->wMaxPacketSize)) {
 224                 DMSG("%s, bad ep or descriptor\n", __FUNCTION__);
 225                 return -EINVAL;
 226         }
 227
 228         /* xfer types must match, except that interrupt ~= bulk */
 229         if (ep->bmAttributes != desc->bmAttributes
 230                         && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
 231                         && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
 232                 DMSG("%s, %s type mismatch\n", __FUNCTION__, _ep->name);
 233                 return -EINVAL;
 234         }
 235
 236         /* hardware _could_ do smaller, but driver doesn't */
 237         if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
 238                                 && le16_to_cpu (desc->wMaxPacketSize)
 239                                                 != BULK_FIFO_SIZE)
 240                         || !desc->wMaxPacketSize) {
 241                 DMSG("%s, bad %s maxpacket\n", __FUNCTION__, _ep->name);
 242                 return -ERANGE;
 243         }
 244
 245         dev = ep->dev;
 246         if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
 247                 DMSG("%s, bogus device state\n", __FUNCTION__);
 248                 return -ESHUTDOWN;
 249         }
 250
 251         ep->desc = desc;
 252         ep->dma = -1;
 253         ep->stopped = 0;
 254         ep->pio_irqs = ep->dma_irqs = 0;
 255         ep->ep.maxpacket = le16_to_cpu (desc->wMaxPacketSize);
 256
 257         /* flush fifo (mostly for OUT buffers) */
 258         pxa2xx_ep_fifo_flush (_ep);
 259
 260         /* ... reset halt state too, if we could ... */
 261
 262 #ifdef  USE_DMA
 263         /* for (some) bulk and ISO endpoints, try to get a DMA channel and
 264          * bind it to the endpoint.  otherwise use PIO.
 265          */
 266         switch (ep->bmAttributes) {
 267         case USB_ENDPOINT_XFER_ISOC:
 268                 if (le16_to_cpu(desc->wMaxPacketSize) % 32)
 269                         break;
 270                 // fall through
 271         case USB_ENDPOINT_XFER_BULK:
 272                 if (!use_dma || !ep->reg_drcmr)
 273                         break;
 274                 ep->dma = pxa_request_dma ((char *)_ep->name,
 275                                 (le16_to_cpu (desc->wMaxPacketSize) > 64)
 276                                         ? DMA_PRIO_MEDIUM /* some iso */
 277                                         : DMA_PRIO_LOW,
 278                                 dma_nodesc_handler, ep);
 279                 if (ep->dma >= 0) {
 280                         *ep->reg_drcmr = DRCMR_MAPVLD | ep->dma;
 281                         DMSG("%s using dma%d\n", _ep->name, ep->dma);
 282                 }
 283         }
 284 #endif
 285
 286         DBG(DBG_VERBOSE, "enabled %s\n", _ep->name);
 287         return 0;
 288 }
 289
 290 static int pxa2xx_ep_disable (struct usb_ep *_ep)
 291 {
 292         struct pxa2xx_ep        *ep;
 293
 294         ep = container_of (_ep, struct pxa2xx_ep, ep);
 295         if (!_ep || !ep->desc) {
 296                 DMSG("%s, %s not enabled\n", __FUNCTION__,
 297                         _ep ? ep->ep.name : NULL);
 298                 return -EINVAL;
 299         }
 300         nuke (ep, -ESHUTDOWN);
 301
 302 #ifdef  USE_DMA
 303         if (ep->dma >= 0) {
 304                 *ep->reg_drcmr = 0;
 305                 pxa_free_dma (ep->dma);
 306                 ep->dma = -1;
 307         }
 308 #endif
 309
 310         /* flush fifo (mostly for IN buffers) */
 311         pxa2xx_ep_fifo_flush (_ep);
 312
 313         ep->desc = 0;
 314         ep->stopped = 1;
 315
 316         DBG(DBG_VERBOSE, "%s disabled\n", _ep->name);
 317         return 0;
 318 }
 319
 320 /*-------------------------------------------------------------------------*/
 321
 322 /* for the pxa2xx, these can just wrap kmalloc/kfree.  gadget drivers
 323  * must still pass correctly initialized endpoints, since other controller
 324  * drivers may care about how it's currently set up (dma issues etc).
 325  */
 326
 327 /*
 328  *      pxa2xx_ep_alloc_request - allocate a request data structure
 329  */
 330 static struct usb_request *
 331 pxa2xx_ep_alloc_request (struct usb_ep *_ep, int gfp_flags)
 332 {
 333         struct pxa2xx_request *req;
 334
 335         req = kmalloc (sizeof *req, gfp_flags);
 336         if (!req)
 337                 return 0;
 338
 339         memset (req, 0, sizeof *req);
 340         INIT_LIST_HEAD (&req->queue);
 341         return &req->req;
 342 }
 343
 344
 345 /*
 346  *      pxa2xx_ep_free_request - deallocate a request data structure
 347  */
 348 static void
 349 pxa2xx_ep_free_request (struct usb_ep *_ep, struct usb_request *_req)
 350 {
 351         struct pxa2xx_request   *req;
 352
 353         req = container_of (_req, struct pxa2xx_request, req);
 354         WARN_ON (!list_empty (&req->queue));
 355         kfree(req);
 356 }
 357
 358
 359 /* PXA cache needs flushing with DMA I/O (it's dma-incoherent), but there's
 360  * no device-affinity and the heap works perfectly well for i/o buffers.
 361  * It wastes much less memory than dma_alloc_coherent() would, and even
 362  * prevents cacheline (32 bytes wide) sharing problems.
 363  */
 364 static void *
 365 pxa2xx_ep_alloc_buffer(struct usb_ep *_ep, unsigned bytes,
 366         dma_addr_t *dma, int gfp_flags)
 367 {
 368         char                    *retval;
 369
 370         retval = kmalloc (bytes, gfp_flags & ~(__GFP_DMA|__GFP_HIGHMEM));
 371         if (retval)
 372                 *dma = virt_to_bus (retval);
 373         return retval;
 374 }
 375
 376 static void
 377 pxa2xx_ep_free_buffer(struct usb_ep *_ep, void *buf, dma_addr_t dma,
 378                 unsigned bytes)
 379 {
 380         kfree (buf);
 381 }
 382
 383 /*-------------------------------------------------------------------------*/
 384
 385 /*
 386  *      done - retire a request; caller blocked irqs
 387  */
 388 static void done(struct pxa2xx_ep *ep, struct pxa2xx_request *req, int status)
 389 {
 390         unsigned                stopped = ep->stopped;
 391
 392         list_del_init(&req->queue);
 393
 394         if (likely (req->req.status == -EINPROGRESS))
 395                 req->req.status = status;
 396         else
 397                 status = req->req.status;
 398
 399         if (status && status != -ESHUTDOWN)
 400                 DBG(DBG_VERBOSE, "complete %s req %p stat %d len %u/%u\n",
 401                         ep->ep.name, &req->req, status,
 402                         req->req.actual, req->req.length);
 403
 404         /* don't modify queue heads during completion callback */
 405         ep->stopped = 1;
 406         req->req.complete(&ep->ep, &req->req);
 407         ep->stopped = stopped;
 408 }
 409
 410
 411 static inline void ep0_idle (struct pxa2xx_udc *dev)
 412 {
 413         dev->ep0state = EP0_IDLE;
 414         LED_EP0_OFF;
 415 }
 416
 417 static int
 418 write_packet(volatile u32 *uddr, struct pxa2xx_request *req, unsigned max)
 419 {
 420         u8              *buf;
 421         unsigned        length, count;
 422
 423         buf = req->req.buf + req->req.actual;
 424         prefetch(buf);
 425
 426         /* how big will this packet be? */
 427         length = min(req->req.length - req->req.actual, max);
 428         req->req.actual += length;
 429
 430         count = length;
 431         while (likely(count--))
 432                 *uddr = *buf++;
 433
 434         return length;
 435 }
 436
 437 /*
 438  * write to an IN endpoint fifo, as many packets as possible.
 439  * irqs will use this to write the rest later.
 440  * caller guarantees at least one packet buffer is ready (or a zlp).
 441  */
 442 static int
 443 write_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req)
 444 {
 445         unsigned                max;
 446
 447         max = le16_to_cpu(ep->desc->wMaxPacketSize);
 448         do {
 449                 unsigned        count;
 450                 int             is_last, is_short;
 451
 452                 count = write_packet(ep->reg_uddr, req, max);
 453
 454                 /* last packet is usually short (or a zlp) */
 455                 if (unlikely (count != max))
 456                         is_last = is_short = 1;
 457                 else {
 458                         if (likely(req->req.length != req->req.actual)
 459                                         || req->req.zero)
 460                                 is_last = 0;
 461                         else
 462                                 is_last = 1;
 463                         /* interrupt/iso maxpacket may not fill the fifo */
 464                         is_short = unlikely (max < ep->fifo_size);
 465                 }
 466
 467                 DBG(DBG_VERY_NOISY, "wrote %s %d bytes%s%s %d left %p\n",
 468                         ep->ep.name, count,
 469                         is_last ? "/L" : "", is_short ? "/S" : "",
 470                         req->req.length - req->req.actual, req);
 471
 472                 /* let loose that packet. maybe try writing another one,
 473                  * double buffering might work.  TSP, TPC, and TFS
 474                  * bit values are the same for all normal IN endpoints.
 475                  */
 476                 *ep->reg_udccs = UDCCS_BI_TPC;
 477                 if (is_short)
 478                         *ep->reg_udccs = UDCCS_BI_TSP;
 479
 480                 /* requests complete when all IN data is in the FIFO */
 481                 if (is_last) {
 482                         done (ep, req, 0);
 483                         if (list_empty(&ep->queue) || unlikely(ep->dma >= 0)) {
 484                                 pio_irq_disable (ep->bEndpointAddress);
 485 #ifdef USE_DMA
 486                                 /* unaligned data and zlps couldn't use dma */
 487                                 if (unlikely(!list_empty(&ep->queue))) {
 488                                         req = list_entry(ep->queue.next,
 489                                                 struct pxa2xx_request, queue);
 490                                         kick_dma(ep,req);
 491                                         return 0;
 492                                 }
 493 #endif
 494                         }
 495                         return 1;
 496                 }
 497
 498                 // TODO experiment: how robust can fifo mode tweaking be?
 499                 // double buffering is off in the default fifo mode, which
 500                 // prevents TFS from being set here.
 501
 502         } while (*ep->reg_udccs & UDCCS_BI_TFS);
 503         return 0;
 504 }
 505
 506 /* caller asserts req->pending (ep0 irq status nyet cleared); starts
 507  * ep0 data stage.  these chips want very simple state transitions.
 508  */
 509 static inline
 510 void ep0start(struct pxa2xx_udc *dev, u32 flags, const char *tag)
 511 {
 512         UDCCS0 = flags|UDCCS0_SA|UDCCS0_OPR;
 513         USIR0 = USIR0_IR0;
 514         dev->req_pending = 0;
 515         DBG(DBG_VERY_NOISY, "%s %s, %02x/%02x\n",
 516                 __FUNCTION__, tag, UDCCS0, flags);
 517 }
 518
 519 static int
 520 write_ep0_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req)
 521 {
 522         unsigned        count;
 523         int             is_short;
 524
 525         count = write_packet(&UDDR0, req, EP0_FIFO_SIZE);
 526         ep->dev->stats.write.bytes += count;
 527
 528         /* last packet "must be" short (or a zlp) */
 529         is_short = (count != EP0_FIFO_SIZE);
 530
 531         DBG(DBG_VERY_NOISY, "ep0in %d bytes %d left %p\n", count,
 532                 req->req.length - req->req.actual, req);
 533
 534         if (unlikely (is_short)) {
 535                 if (ep->dev->req_pending)
 536                         ep0start(ep->dev, UDCCS0_IPR, "short IN");
 537                 else
 538                         UDCCS0 = UDCCS0_IPR;
 539
 540                 count = req->req.length;
 541                 done (ep, req, 0);
 542                 ep0_idle(ep->dev);
 543 #if 1
 544                 /* This seems to get rid of lost status irqs in some cases:
 545                  * host responds quickly, or next request involves config
 546                  * change automagic, or should have been hidden, or ...
 547                  *
 548                  * FIXME get rid of all udelays possible...
 549                  */
 550                 if (count >= EP0_FIFO_SIZE) {
 551                         count = 100;
 552                         do {
 553                                 if ((UDCCS0 & UDCCS0_OPR) != 0) {
 554                                         /* clear OPR, generate ack */
 555                                         UDCCS0 = UDCCS0_OPR;
 556                                         break;
 557                                 }
 558                                 count--;
 559                                 udelay(1);
 560                         } while (count);
 561                 }
 562 #endif
 563         } else if (ep->dev->req_pending)
 564                 ep0start(ep->dev, 0, "IN");
 565         return is_short;
 566 }
 567
 568
 569 /*
 570  * read_fifo -  unload packet(s) from the fifo we use for usb OUT
 571  * transfers and put them into the request.  caller should have made
 572  * sure there's at least one packet ready.
 573  *
 574  * returns true if the request completed because of short packet or the
 575  * request buffer having filled (and maybe overran till end-of-packet).
 576  */
 577 static int
 578 read_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req)
 579 {
 580         for (;;) {
 581                 u32             udccs;
 582                 u8              *buf;
 583                 unsigned        bufferspace, count, is_short;
 584
 585                 /* make sure there's a packet in the FIFO.
 586                  * UDCCS_{BO,IO}_RPC are all the same bit value.
 587                  * UDCCS_{BO,IO}_RNE are all the same bit value.
 588                  */
 589                 udccs = *ep->reg_udccs;
 590                 if (unlikely ((udccs & UDCCS_BO_RPC) == 0))
 591                         break;
 592                 buf = req->req.buf + req->req.actual;
 593                 prefetchw(buf);
 594                 bufferspace = req->req.length - req->req.actual;
 595
 596                 /* read all bytes from this packet */
 597                 if (likely (udccs & UDCCS_BO_RNE)) {
 598                         count = 1 + (0x0ff & *ep->reg_ubcr);
 599                         req->req.actual += min (count, bufferspace);
 600                 } else /* zlp */
 601                         count = 0;
 602                 is_short = (count < ep->ep.maxpacket);
 603                 DBG(DBG_VERY_NOISY, "read %s %02x, %d bytes%s req %p %d/%d\n",
 604                         ep->ep.name, udccs, count,
 605                         is_short ? "/S" : "",
 606                         req, req->req.actual, req->req.length);
 607                 while (likely (count-- != 0)) {
 608                         u8      byte = (u8) *ep->reg_uddr;
 609
 610                         if (unlikely (bufferspace == 0)) {
 611                                 /* this happens when the driver's buffer
 612                                  * is smaller than what the host sent.
 613                                  * discard the extra data.
 614                                  */
 615                                 if (req->req.status != -EOVERFLOW)
 616                                         DMSG("%s overflow %d\n",
 617                                                 ep->ep.name, count);
 618                                 req->req.status = -EOVERFLOW;
 619                         } else {
 620                                 *buf++ = byte;
 621                                 bufferspace--;
 622                         }
 623                 }
 624                 *ep->reg_udccs =  UDCCS_BO_RPC;
 625                 /* RPC/RSP/RNE could now reflect the other packet buffer */
 626
 627                 /* iso is one request per packet */
 628                 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 629                         if (udccs & UDCCS_IO_ROF)
 630                                 req->req.status = -EHOSTUNREACH;
 631                         /* more like "is_done" */
 632                         is_short = 1;
 633                 }
 634
 635                 /* completion */
 636                 if (is_short || req->req.actual == req->req.length) {
 637                         done (ep, req, 0);
 638                         if (list_empty(&ep->queue))
 639                                 pio_irq_disable (ep->bEndpointAddress);
 640                         return 1;
 641                 }
 642
 643                 /* finished that packet.  the next one may be waiting... */
 644         }
 645         return 0;
 646 }
 647
 648 /*
 649  * special ep0 version of the above.  no UBCR0 or double buffering; status
 650  * handshaking is magic.  most device protocols don't need control-OUT.
 651  * CDC vendor commands (and RNDIS), mass storage CB/CBI, and some other
 652  * protocols do use them.
 653  */
 654 static int
 655 read_ep0_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req)
 656 {
 657         u8              *buf, byte;
 658         unsigned        bufferspace;
 659
 660         buf = req->req.buf + req->req.actual;
 661         bufferspace = req->req.length - req->req.actual;
 662
 663         while (UDCCS0 & UDCCS0_RNE) {
 664                 byte = (u8) UDDR0;
 665
 666                 if (unlikely (bufferspace == 0)) {
 667                         /* this happens when the driver's buffer
 668                          * is smaller than what the host sent.
 669                          * discard the extra data.
 670                          */
 671                         if (req->req.status != -EOVERFLOW)
 672                                 DMSG("%s overflow\n", ep->ep.name);
 673                         req->req.status = -EOVERFLOW;
 674                 } else {
 675                         *buf++ = byte;
 676                         req->req.actual++;
 677                         bufferspace--;
 678                 }
 679         }
 680
 681         UDCCS0 = UDCCS0_OPR | UDCCS0_IPR;
 682
 683         /* completion */
 684         if (req->req.actual >= req->req.length)
 685                 return 1;
 686
 687         /* finished that packet.  the next one may be waiting... */
 688         return 0;
 689 }
 690
 691 #ifdef  USE_DMA
 692
 693 #define MAX_IN_DMA      ((DCMD_LENGTH + 1) - BULK_FIFO_SIZE)
 694
 695 static void
 696 start_dma_nodesc(struct pxa2xx_ep *ep, struct pxa2xx_request *req, int is_in)
 697 {
 698         u32     dcmd = req->req.length;
 699         u32     buf = req->req.dma;
 700         u32     fifo = io_v2p ((u32)ep->reg_uddr);
 701
 702         /* caller guarantees there's a packet or more remaining
 703          *  - IN may end with a short packet (TSP set separately),
 704          *  - OUT is always full length
 705          */
 706         buf += req->req.actual;
 707         dcmd -= req->req.actual;
 708         ep->dma_fixup = 0;
 709
 710         /* no-descriptor mode can be simple for bulk-in, iso-in, iso-out */
 711         DCSR(ep->dma) = DCSR_NODESC;
 712         if (is_in) {
 713                 DSADR(ep->dma) = buf;
 714                 DTADR(ep->dma) = fifo;
 715                 if (dcmd > MAX_IN_DMA)
 716                         dcmd = MAX_IN_DMA;
 717                 else
 718                         ep->dma_fixup = (dcmd % ep->ep.maxpacket) != 0;
 719                 dcmd |= DCMD_BURST32 | DCMD_WIDTH1
 720                         | DCMD_FLOWTRG | DCMD_INCSRCADDR;
 721         } else {
 722 #ifdef USE_OUT_DMA
 723                 DSADR(ep->dma) = fifo;
 724                 DTADR(ep->dma) = buf;
 725                 if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
 726                         dcmd = ep->ep.maxpacket;
 727                 dcmd |= DCMD_BURST32 | DCMD_WIDTH1
 728                         | DCMD_FLOWSRC | DCMD_INCTRGADDR;
 729 #endif
 730         }
 731         DCMD(ep->dma) = dcmd;
 732         DCSR(ep->dma) = DCSR_RUN | DCSR_NODESC
 733                 | (unlikely(is_in)
 734                         ? DCSR_STOPIRQEN        /* use dma_nodesc_handler() */
 735                         : 0);                   /* use handle_ep() */
 736 }
 737
 738 static void kick_dma(struct pxa2xx_ep *ep, struct pxa2xx_request *req)
 739 {
 740         int     is_in = ep->bEndpointAddress & USB_DIR_IN;
 741
 742         if (is_in) {
 743                 /* unaligned tx buffers and zlps only work with PIO */
 744                 if ((req->req.dma & 0x0f) != 0
 745                                 || unlikely((req->req.length - req->req.actual)
 746                                                 == 0)) {
 747                         pio_irq_enable(ep->bEndpointAddress);
 748                         if ((*ep->reg_udccs & UDCCS_BI_TFS) != 0)
 749                                 (void) write_fifo(ep, req);
 750                 } else {
 751                         start_dma_nodesc(ep, req, USB_DIR_IN);
 752                 }
 753         } else {
 754                 if ((req->req.length - req->req.actual) < ep->ep.maxpacket) {
 755                         DMSG("%s short dma read...\n", ep->ep.name);
 756                         /* we're always set up for pio out */
 757                         read_fifo (ep, req);
 758                 } else {
 759                         *ep->reg_udccs = UDCCS_BO_DME
 760                                 | (*ep->reg_udccs & UDCCS_BO_FST);
 761                         start_dma_nodesc(ep, req, USB_DIR_OUT);
 762                 }
 763         }
 764 }
 765
 766 static void cancel_dma(struct pxa2xx_ep *ep)
 767 {
 768         struct pxa2xx_request   *req;
 769         u32                     tmp;
 770
 771         if (DCSR(ep->dma) == 0 || list_empty(&ep->queue))
 772                 return;
 773
 774         DCSR(ep->dma) = 0;
 775         while ((DCSR(ep->dma) & DCSR_STOPSTATE) == 0)
 776                 cpu_relax();
 777
 778         req = list_entry(ep->queue.next, struct pxa2xx_request, queue);
 779         tmp = DCMD(ep->dma) & DCMD_LENGTH;
 780         req->req.actual = req->req.length - (tmp & DCMD_LENGTH);
 781
 782         /* the last tx packet may be incomplete, so flush the fifo.
 783          * FIXME correct req.actual if we can
 784          */
 785         if (ep->bEndpointAddress & USB_DIR_IN)
 786                 *ep->reg_udccs = UDCCS_BI_FTF;
 787 }
 788
 789 /* dma channel stopped ... normal tx end (IN), or on error (IN/OUT) */
 790 static void dma_nodesc_handler(int dmach, void *_ep, struct pt_regs *r)
 791 {
 792         struct pxa2xx_ep        *ep = _ep;
 793         struct pxa2xx_request   *req;
 794         u32                     tmp, completed;
 795
 796         local_irq_disable();
 797
 798         req = list_entry(ep->queue.next, struct pxa2xx_request, queue);
 799
 800         ep->dma_irqs++;
 801         ep->dev->stats.irqs++;
 802         HEX_DISPLAY(ep->dev->stats.irqs);
 803
 804         /* ack/clear */
 805         tmp = DCSR(ep->dma);
 806         DCSR(ep->dma) = tmp;
 807         if ((tmp & DCSR_STOPSTATE) == 0
 808                         || (DDADR(ep->dma) & DDADR_STOP) != 0) {
 809                 DBG(DBG_VERBOSE, "%s, dcsr %08x ddadr %08x\n",
 810                         ep->ep.name, DCSR(ep->dma), DDADR(ep->dma));
 811                 goto done;
 812         }
 813         DCSR(ep->dma) = 0;      /* clear DCSR_STOPSTATE */
 814
 815         /* update transfer status */
 816         completed = tmp & DCSR_BUSERR;
 817         if (ep->bEndpointAddress & USB_DIR_IN)
 818                 tmp = DSADR(ep->dma);
 819         else
 820                 tmp = DTADR(ep->dma);
 821         req->req.actual = tmp - req->req.dma;
 822
 823         /* FIXME seems we sometimes see partial transfers... */
 824
 825         if (unlikely(completed != 0))
 826                 req->req.status = -EIO;
 827         else if (req->req.actual) {
 828                 /* these registers have zeroes in low bits; they miscount
 829                  * some (end-of-transfer) short packets:  tx 14 as tx 12
 830                  */
 831                 if (ep->dma_fixup)
 832                         req->req.actual = min(req->req.actual + 3,
 833                                                 req->req.length);
 834
 835                 tmp = (req->req.length - req->req.actual);
 836                 completed = (tmp == 0);
 837                 if (completed && (ep->bEndpointAddress & USB_DIR_IN)) {
 838
 839                         /* maybe validate final short packet ... */
 840                         if ((req->req.actual % ep->ep.maxpacket) != 0)
 841                                 *ep->reg_udccs = UDCCS_BI_TSP/*|UDCCS_BI_TPC*/;
 842
 843                         /* ... or zlp, using pio fallback */
 844                         else if (ep->bmAttributes == USB_ENDPOINT_XFER_BULK
 845                                         && req->req.zero) {
 846                                 DMSG("%s zlp terminate ...\n", ep->ep.name);
 847                                 completed = 0;
 848                         }
 849                 }
 850         }
 851
 852         if (likely(completed)) {
 853                 done(ep, req, 0);
 854
 855                 /* maybe re-activate after completion */
 856                 if (ep->stopped || list_empty(&ep->queue))
 857                         goto done;
 858                 req = list_entry(ep->queue.next, struct pxa2xx_request, queue);
 859         }
 860         kick_dma(ep, req);
 861 done:
 862         local_irq_enable();
 863 }
 864
 865 #endif
 866
 867 /*-------------------------------------------------------------------------*/
 868
 869 static int
 870 pxa2xx_ep_queue(struct usb_ep *_ep, struct usb_request *_req, int gfp_flags)
 871 {
 872         struct pxa2xx_request   *req;
 873         struct pxa2xx_ep        *ep;
 874         struct pxa2xx_udc       *dev;
 875         unsigned long           flags;
 876
 877         req = container_of(_req, struct pxa2xx_request, req);
 878         if (unlikely (!_req || !_req->complete || !_req->buf
 879                         || !list_empty(&req->queue))) {
 880                 DMSG("%s, bad params\n", __FUNCTION__);
 881                 return -EINVAL;
 882         }
 883
 884         ep = container_of(_ep, struct pxa2xx_ep, ep);
 885         if (unlikely (!_ep || (!ep->desc && ep->ep.name != ep0name))) {
 886                 DMSG("%s, bad ep\n", __FUNCTION__);
 887                 return -EINVAL;
 888         }
 889
 890         dev = ep->dev;
 891         if (unlikely (!dev->driver
 892                         || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
 893                 DMSG("%s, bogus device state\n", __FUNCTION__);
 894                 return -ESHUTDOWN;
 895         }
 896
 897         /* iso is always one packet per request, that's the only way
 898          * we can report per-packet status.  that also helps with dma.
 899          */
 900         if (unlikely (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
 901                         && req->req.length > le16_to_cpu
 902                                                 (ep->desc->wMaxPacketSize)))
 903                 return -EMSGSIZE;
 904
 905 #ifdef  USE_DMA
 906         // FIXME caller may already have done the dma mapping
 907         if (ep->dma >= 0) {
 908                 _req->dma = dma_map_single(dev->dev,
 909                         _req->buf, _req->length,
 910                         ((ep->bEndpointAddress & USB_DIR_IN) != 0)
 911                                 ? DMA_TO_DEVICE
 912                                 : DMA_FROM_DEVICE);
 913         }
 914 #endif
 915
 916         DBG(DBG_NOISY, "%s queue req %p, len %d buf %p\n",
 917              _ep->name, _req, _req->length, _req->buf);
 918
 919         local_irq_save(flags);
 920
 921         _req->status = -EINPROGRESS;
 922         _req->actual = 0;
 923
 924         /* kickstart this i/o queue? */
 925         if (list_empty(&ep->queue) && !ep->stopped) {
 926                 if (ep->desc == 0 /* ep0 */) {
 927                         unsigned        length = _req->length;
 928
 929                         switch (dev->ep0state) {
 930                         case EP0_IN_DATA_PHASE:
 931                                 dev->stats.write.ops++;
 932                                 if (write_ep0_fifo(ep, req))
 933                                         req = 0;
 934                                 break;
 935
 936                         case EP0_OUT_DATA_PHASE:
 937                                 dev->stats.read.ops++;
 938                                 /* messy ... */
 939                                 if (dev->req_config) {
 940                                         DBG(DBG_VERBOSE, "ep0 config ack%s\n",
 941                                                 dev->has_cfr ?  "" : " raced");
 942                                         if (dev->has_cfr)
 943                                                 UDCCFR = UDCCFR_AREN|UDCCFR_ACM;
 944                                         done(ep, req, 0);
 945                                         dev->ep0state = EP0_END_XFER;
 946                                         return 0;
 947                                 }
 948                                 if (dev->req_pending)
 949                                         ep0start(dev, UDCCS0_IPR, "OUT");
 950                                 if (length == 0 || ((UDCCS0 & UDCCS0_RNE) != 0
 951                                                 && read_ep0_fifo(ep, req))) {
 952                                         ep0_idle(dev);
 953                                         done(ep, req, 0);
 954                                         req = 0;
 955                                 }
 956                                 break;
 957
 958                         default:
 959                                 DMSG("ep0 i/o, odd state %d\n", dev->ep0state);
 960                                 local_irq_restore (flags);
 961                                 return -EL2HLT;
 962                         }
 963 #ifdef  USE_DMA
 964                 /* either start dma or prime pio pump */
 965                 } else if (ep->dma >= 0) {
 966                         kick_dma(ep, req);
 967 #endif
 968                 /* can the FIFO can satisfy the request immediately? */
 969                 } else if ((ep->bEndpointAddress & USB_DIR_IN) != 0
 970                                 && (*ep->reg_udccs & UDCCS_BI_TFS) != 0
 971                                 && write_fifo(ep, req)) {
 972                         req = 0;
 973                 } else if ((*ep->reg_udccs & UDCCS_BO_RFS) != 0
 974                                 && read_fifo(ep, req)) {
 975                         req = 0;
 976                 }
 977
 978                 if (likely (req && ep->desc) && ep->dma < 0)
 979                         pio_irq_enable(ep->bEndpointAddress);
 980         }
 981
 982         /* pio or dma irq handler advances the queue. */
 983         if (likely (req != 0))
 984                 list_add_tail(&req->queue, &ep->queue);
 985         local_irq_restore(flags);
 986
 987         return 0;
 988 }
 989
 990
 991 /*
 992  *      nuke - dequeue ALL requests
 993  */
 994 static void nuke(struct pxa2xx_ep *ep, int status)
 995 {
 996         struct pxa2xx_request *req;
 997
 998         /* called with irqs blocked */
 999 #ifdef  USE_DMA
1000         if (ep->dma >= 0 && !ep->stopped)
1001                 cancel_dma(ep);
1002 #endif
1003         while (!list_empty(&ep->queue)) {
1004                 req = list_entry(ep->queue.next,
1005                                 struct pxa2xx_request,
1006                                 queue);
1007                 done(ep, req, status);
1008         }
1009         if (ep->desc)
1010                 pio_irq_disable (ep->bEndpointAddress);
1011 }
1012
1013
1014 /* dequeue JUST ONE request */
1015 static int pxa2xx_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1016 {
1017         struct pxa2xx_ep        *ep;
1018         struct pxa2xx_request   *req;
1019         unsigned long           flags;
1020
1021         ep = container_of(_ep, struct pxa2xx_ep, ep);
1022         if (!_ep || ep->ep.name == ep0name)
1023                 return -EINVAL;
1024
1025         local_irq_save(flags);
1026
1027         /* make sure it's actually queued on this endpoint */
1028         list_for_each_entry (req, &ep->queue, queue) {
1029                 if (&req->req == _req)
1030                         break;
1031         }
1032         if (&req->req != _req) {
1033                 local_irq_restore(flags);
1034                 return -EINVAL;
1035         }
1036
1037 #ifdef  USE_DMA
1038         if (ep->dma >= 0 && ep->queue.next == &req->queue && !ep->stopped) {
1039                 cancel_dma(ep);
1040                 done(ep, req, -ECONNRESET);
1041                 /* restart i/o */
1042                 if (!list_empty(&ep->queue)) {
1043                         req = list_entry(ep->queue.next,
1044                                         struct pxa2xx_request, queue);
1045                         kick_dma(ep, req);
1046                 }
1047         } else
1048 #endif
1049                 done(ep, req, -ECONNRESET);
1050
1051         local_irq_restore(flags);
1052         return 0;
1053 }
1054
1055 /*-------------------------------------------------------------------------*/
1056
1057 static int pxa2xx_ep_set_halt(struct usb_ep *_ep, int value)
1058 {
1059         struct pxa2xx_ep        *ep;
1060         unsigned long           flags;
1061
1062         ep = container_of(_ep, struct pxa2xx_ep, ep);
1063         if (unlikely (!_ep
1064                         || (!ep->desc && ep->ep.name != ep0name))
1065                         || ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
1066                 DMSG("%s, bad ep\n", __FUNCTION__);
1067                 return -EINVAL;
1068         }
1069         if (value == 0) {
1070                 /* this path (reset toggle+halt) is needed to implement
1071                  * SET_INTERFACE on normal hardware.  but it can't be
1072                  * done from software on the PXA UDC, and the hardware
1073                  * forgets to do it as part of SET_INTERFACE automagic.
1074                  */
1075                 DMSG("only host can clear %s halt\n", _ep->name);
1076                 return -EROFS;
1077         }
1078
1079         local_irq_save(flags);
1080
1081         if ((ep->bEndpointAddress & USB_DIR_IN) != 0
1082                         && ((*ep->reg_udccs & UDCCS_BI_TFS) == 0
1083                            || !list_empty(&ep->queue))) {
1084                 local_irq_restore(flags);
1085                 return -EAGAIN;
1086         }
1087
1088         /* FST bit is the same for control, bulk in, bulk out, interrupt in */
1089         *ep->reg_udccs = UDCCS_BI_FST|UDCCS_BI_FTF;
1090
1091         /* ep0 needs special care */
1092         if (!ep->desc) {
1093                 start_watchdog(ep->dev);
1094                 ep->dev->req_pending = 0;
1095                 ep->dev->ep0state = EP0_STALL;
1096                 LED_EP0_OFF;
1097
1098         /* and bulk/intr endpoints like dropping stalls too */
1099         } else {
1100                 unsigned i;
1101                 for (i = 0; i < 1000; i += 20) {
1102                         if (*ep->reg_udccs & UDCCS_BI_SST)
1103                                 break;
1104                         udelay(20);
1105                 }
1106         }
1107         local_irq_restore(flags);
1108
1109         DBG(DBG_VERBOSE, "%s halt\n", _ep->name);
1110         return 0;
1111 }
1112
1113 static int pxa2xx_ep_fifo_status(struct usb_ep *_ep)
1114 {
1115         struct pxa2xx_ep        *ep;
1116
1117         ep = container_of(_ep, struct pxa2xx_ep, ep);
1118         if (!_ep) {
1119                 DMSG("%s, bad ep\n", __FUNCTION__);
1120                 return -ENODEV;
1121         }
1122         /* pxa can't report unclaimed bytes from IN fifos */
1123         if ((ep->bEndpointAddress & USB_DIR_IN) != 0)
1124                 return -EOPNOTSUPP;
1125         if (ep->dev->gadget.speed == USB_SPEED_UNKNOWN
1126                         || (*ep->reg_udccs & UDCCS_BO_RFS) == 0)
1127                 return 0;
1128         else
1129                 return (*ep->reg_ubcr & 0xfff) + 1;
1130 }
1131
1132 static void pxa2xx_ep_fifo_flush(struct usb_ep *_ep)
1133 {
1134         struct pxa2xx_ep        *ep;
1135
1136         ep = container_of(_ep, struct pxa2xx_ep, ep);
1137         if (!_ep || ep->ep.name == ep0name || !list_empty(&ep->queue)) {
1138                 DMSG("%s, bad ep\n", __FUNCTION__);
1139                 return;
1140         }
1141
1142         /* toggle and halt bits stay unchanged */
1143
1144         /* for OUT, just read and discard the FIFO contents. */
1145         if ((ep->bEndpointAddress & USB_DIR_IN) == 0) {
1146                 while (((*ep->reg_udccs) & UDCCS_BO_RNE) != 0)
1147                         (void) *ep->reg_uddr;
1148                 return;
1149         }
1150
1151         /* most IN status is the same, but ISO can't stall */
1152         *ep->reg_udccs = UDCCS_BI_TPC|UDCCS_BI_FTF|UDCCS_BI_TUR
1153                 | (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
1154                         ? 0 : UDCCS_BI_SST;
1155 }
1156
1157
1158 static struct usb_ep_ops pxa2xx_ep_ops = {
1159         .enable         = pxa2xx_ep_enable,
1160         .disable        = pxa2xx_ep_disable,
1161
1162         .alloc_request  = pxa2xx_ep_alloc_request,
1163         .free_request   = pxa2xx_ep_free_request,
1164
1165         .alloc_buffer   = pxa2xx_ep_alloc_buffer,
1166         .free_buffer    = pxa2xx_ep_free_buffer,
1167
1168         .queue          = pxa2xx_ep_queue,
1169         .dequeue        = pxa2xx_ep_dequeue,
1170
1171         .set_halt       = pxa2xx_ep_set_halt,
1172         .fifo_status    = pxa2xx_ep_fifo_status,
1173         .fifo_flush     = pxa2xx_ep_fifo_flush,
1174 };
1175
1176
1177 /* ---------------------------------------------------------------------------
1178  *      device-scoped parts of the api to the usb controller hardware
1179  * ---------------------------------------------------------------------------
1180  */
1181
1182 static int pxa2xx_udc_get_frame(struct usb_gadget *_gadget)
1183 {
1184         return ((UFNRH & 0x07) << 8) | (UFNRL & 0xff);
1185 }
1186
1187 static int pxa2xx_udc_wakeup(struct usb_gadget *_gadget)
1188 {
1189         /* host may not have enabled remote wakeup */
1190         if ((UDCCS0 & UDCCS0_DRWF) == 0)
1191                 return -EHOSTUNREACH;
1192         udc_set_mask_UDCCR(UDCCR_RSM);
1193         return 0;
1194 }
1195
1196 static const struct usb_gadget_ops pxa2xx_udc_ops = {
1197         .get_frame       = pxa2xx_udc_get_frame,
1198         .wakeup          = pxa2xx_udc_wakeup,
1199         // current versions must always be self-powered
1200 };
1201
1202
1203 /*-------------------------------------------------------------------------*/
1204
1205 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
1206
1207 static const char proc_node_name [] = "driver/udc";
1208
1209 static int
1210 udc_proc_read(char *page, char **start, off_t off, int count,
1211                 int *eof, void *_dev)
1212 {
1213         char                    *buf = page;
1214         struct pxa2xx_udc       *dev = _dev;
1215         char                    *next = buf;
1216         unsigned                size = count;
1217         unsigned long           flags;
1218         int                     i, t;
1219         u32                     tmp;
1220
1221         if (off != 0)
1222                 return 0;
1223
1224         local_irq_save(flags);
1225
1226         /* basic device status */
1227         t = scnprintf(next, size, DRIVER_DESC "\n"
1228                 "%s version: %s\nGadget driver: %s\nHost %s\n\n",
1229                 driver_name, DRIVER_VERSION SIZE_STR DMASTR,
1230                 dev->driver ? dev->driver->driver.name : "(none)",
1231                 is_usb_connected() ? "full speed" : "disconnected");
1232         size -= t;
1233         next += t;
1234
1235         /* registers for device and ep0 */
1236         t = scnprintf(next, size,
1237                 "uicr %02X.%02X, usir %02X.%02x, ufnr %02X.%02X\n",
1238                 UICR1, UICR0, USIR1, USIR0, UFNRH, UFNRL);
1239         size -= t;
1240         next += t;
1241
1242         tmp = UDCCR;
1243         t = scnprintf(next, size,
1244                 "udccr %02X =%s%s%s%s%s%s%s%s\n", tmp,
1245                 (tmp & UDCCR_REM) ? " rem" : "",
1246                 (tmp & UDCCR_RSTIR) ? " rstir" : "",
1247                 (tmp & UDCCR_SRM) ? " srm" : "",
1248                 (tmp & UDCCR_SUSIR) ? " susir" : "",
1249                 (tmp & UDCCR_RESIR) ? " resir" : "",
1250                 (tmp & UDCCR_RSM) ? " rsm" : "",
1251                 (tmp & UDCCR_UDA) ? " uda" : "",
1252                 (tmp & UDCCR_UDE) ? " ude" : "");
1253         size -= t;
1254         next += t;
1255
1256         tmp = UDCCS0;
1257         t = scnprintf(next, size,
1258                 "udccs0 %02X =%s%s%s%s%s%s%s%s\n", tmp,
1259                 (tmp & UDCCS0_SA) ? " sa" : "",
1260                 (tmp & UDCCS0_RNE) ? " rne" : "",
1261                 (tmp & UDCCS0_FST) ? " fst" : "",
1262                 (tmp & UDCCS0_SST) ? " sst" : "",
1263                 (tmp & UDCCS0_DRWF) ? " dwrf" : "",
1264                 (tmp & UDCCS0_FTF) ? " ftf" : "",
1265                 (tmp & UDCCS0_IPR) ? " ipr" : "",
1266                 (tmp & UDCCS0_OPR) ? " opr" : "");
1267         size -= t;
1268         next += t;
1269
1270         if (dev->has_cfr) {
1271                 tmp = UDCCFR;
1272                 t = scnprintf(next, size,
1273                         "udccfr %02X =%s%s\n", tmp,
1274                         (tmp & UDCCFR_AREN) ? " aren" : "",
1275                         (tmp & UDCCFR_ACM) ? " acm" : "");
1276                 size -= t;
1277                 next += t;
1278         }
1279
1280         if (!is_usb_connected() || !dev->driver)
1281                 goto done;
1282
1283         t = scnprintf(next, size, "ep0 IN %lu/%lu, OUT %lu/%lu\nirqs %lu\n\n",
1284                 dev->stats.write.bytes, dev->stats.write.ops,
1285                 dev->stats.read.bytes, dev->stats.read.ops,
1286                 dev->stats.irqs);
1287         size -= t;
1288         next += t;
1289
1290         /* dump endpoint queues */
1291         for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1292                 struct pxa2xx_ep        *ep = &dev->ep [i];
1293                 struct pxa2xx_request   *req;
1294                 int                     t;
1295
1296                 if (i != 0) {
1297                         const struct usb_endpoint_descriptor    *d;
1298
1299                         d = ep->desc;
1300                         if (!d)
1301                                 continue;
1302                         tmp = *dev->ep [i].reg_udccs;
1303                         t = scnprintf(next, size,
1304                                 "%s max %d %s udccs %02x irqs %lu/%lu\n",
1305                                 ep->ep.name, le16_to_cpu (d->wMaxPacketSize),
1306                                 (ep->dma >= 0) ? "dma" : "pio", tmp,
1307                                 ep->pio_irqs, ep->dma_irqs);
1308                         /* TODO translate all five groups of udccs bits! */
1309
1310                 } else /* ep0 should only have one transfer queued */
1311                         t = scnprintf(next, size, "ep0 max 16 pio irqs %lu\n",
1312                                 ep->pio_irqs);
1313                 if (t <= 0 || t > size)
1314                         goto done;
1315                 size -= t;
1316                 next += t;
1317
1318                 if (list_empty(&ep->queue)) {
1319                         t = scnprintf(next, size, "\t(nothing queued)\n");
1320                         if (t <= 0 || t > size)
1321                                 goto done;
1322                         size -= t;
1323                         next += t;
1324                         continue;
1325                 }
1326                 list_for_each_entry(req, &ep->queue, queue) {
1327 #ifdef  USE_DMA
1328                         if (ep->dma >= 0 && req->queue.prev == &ep->queue)
1329                                 t = scnprintf(next, size,
1330                                         "\treq %p len %d/%d "
1331                                         "buf %p (dma%d dcmd %08x)\n",
1332                                         &req->req, req->req.actual,
1333                                         req->req.length, req->req.buf,
1334                                         ep->dma, DCMD(ep->dma)
1335                                         // low 13 bits == bytes-to-go
1336                                         );
1337                         else
1338 #endif
1339                                 t = scnprintf(next, size,
1340                                         "\treq %p len %d/%d buf %p\n",
1341                                         &req->req, req->req.actual,
1342                                         req->req.length, req->req.buf);
1343                         if (t <= 0 || t > size)
1344                                 goto done;
1345                         size -= t;
1346                         next += t;
1347                 }
1348         }
1349
1350 done:
1351         local_irq_restore(flags);
1352         *eof = 1;
1353         return count - size;
1354 }
1355
1356 #define create_proc_files() \
1357         create_proc_read_entry(proc_node_name, 0, NULL, udc_proc_read, dev)
1358 #define remove_proc_files() \
1359         remove_proc_entry(proc_node_name, NULL)
1360
1361 #else   /* !CONFIG_USB_GADGET_DEBUG_FILES */
1362
1363 #define create_proc_files() do {} while (0)
1364 #define remove_proc_files() do {} while (0)
1365
1366 #endif  /* CONFIG_USB_GADGET_DEBUG_FILES */
1367
1368 /* "function" sysfs attribute */
1369 static ssize_t
1370 show_function (struct device *_dev, char *buf)
1371 {
1372         struct pxa2xx_udc       *dev = dev_get_drvdata (_dev);
1373
1374         if (!dev->driver
1375                         || !dev->driver->function
1376                         || strlen (dev->driver->function) > PAGE_SIZE)
1377                 return 0;
1378         return scnprintf (buf, PAGE_SIZE, "%s\n", dev->driver->function);
1379 }
1380 static DEVICE_ATTR (function, S_IRUGO, show_function, NULL);
1381
1382 /*-------------------------------------------------------------------------*/
1383
1384 /*
1385  *      udc_disable - disable USB device controller
1386  */
1387 static void udc_disable(struct pxa2xx_udc *dev)
1388 {
1389         /* block all irqs */
1390         udc_set_mask_UDCCR(UDCCR_SRM|UDCCR_REM);
1391         UICR0 = UICR1 = 0xff;
1392         UFNRH = UFNRH_SIM;
1393
1394         /* if hardware supports it, disconnect from usb */
1395         make_usb_disappear();
1396
1397         udc_clear_mask_UDCCR(UDCCR_UDE);
1398
1399 #ifdef  CONFIG_ARCH_PXA
1400         /* Disable clock for USB device */
1401         pxa_set_cken(CKEN11_USB, 0);
1402 #endif
1403
1404         ep0_idle (dev);
1405         dev->gadget.speed = USB_SPEED_UNKNOWN;
1406         LED_CONNECTED_OFF;
1407 }
1408
1409
1410 /*
1411  *      udc_reinit - initialize software state
1412  */
1413 static void udc_reinit(struct pxa2xx_udc *dev)
1414 {
1415         u32     i;
1416
1417         /* device/ep0 records init */
1418         INIT_LIST_HEAD (&dev->gadget.ep_list);
1419         INIT_LIST_HEAD (&dev->gadget.ep0->ep_list);
1420         dev->ep0state = EP0_IDLE;
1421
1422         /* basic endpoint records init */
1423         for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1424                 struct pxa2xx_ep *ep = &dev->ep[i];
1425
1426                 if (i != 0)
1427                         list_add_tail (&ep->ep.ep_list, &dev->gadget.ep_list);
1428
1429                 ep->desc = 0;
1430                 ep->stopped = 0;
1431                 INIT_LIST_HEAD (&ep->queue);
1432                 ep->pio_irqs = ep->dma_irqs = 0;
1433         }
1434
1435         /* the rest was statically initialized, and is read-only */
1436 }
1437
1438 /* until it's enabled, this UDC should be completely invisible
1439  * to any USB host.
1440  */
1441 static void udc_enable (struct pxa2xx_udc *dev)
1442 {
1443         udc_clear_mask_UDCCR(UDCCR_UDE);
1444
1445 #ifdef  CONFIG_ARCH_PXA
1446         /* Enable clock for USB device */
1447         pxa_set_cken(CKEN11_USB, 1);
1448 #endif
1449
1450         /* try to clear these bits before we enable the udc */
1451         udc_ack_int_UDCCR(UDCCR_SUSIR|/*UDCCR_RSTIR|*/UDCCR_RESIR);
1452
1453         ep0_idle(dev);
1454         dev->gadget.speed = USB_SPEED_UNKNOWN;
1455         dev->stats.irqs = 0;
1456
1457         /*
1458          * sequence taken from chapter 12.5.10, PXA250 AppProcDevManual:
1459          * - enable UDC
1460          * - if RESET is already in progress, ack interrupt
1461          * - unmask reset interrupt
1462          */
1463         udc_set_mask_UDCCR(UDCCR_UDE);
1464         if (!(UDCCR & UDCCR_UDA))
1465                 udc_ack_int_UDCCR(UDCCR_RSTIR);
1466
1467         if (dev->has_cfr /* UDC_RES2 is defined */) {
1468                 /* pxa255 (a0+) can avoid a set_config race that could
1469                  * prevent gadget drivers from configuring correctly
1470                  */
1471                 UDCCFR = UDCCFR_ACM;
1472         } else {
1473                 /* "USB test mode" for pxa250 errata 40-42 (stepping a0, a1)
1474                  * which could result in missing packets and interrupts.
1475                  * supposedly one bit per endpoint, controlling whether it
1476                  * double buffers or not; ACM/AREN bits fit into the holes.
1477                  * zero bits (like USIR0_IRx) disable double buffering.
1478                  */
1479                 UDC_RES1 = 0x00;
1480                 UDC_RES2 = 0x00;
1481         }
1482
1483 #ifdef  DISABLE_TEST_MODE
1484         /* "test mode" seems to have become the default in later chip
1485          * revs, preventing double buffering (and invalidating docs).
1486          * this EXPERIMENT enables it for bulk endpoints by tweaking
1487          * undefined/reserved register bits (that other drivers clear).
1488          * Belcarra code comments noted this usage.
1489          */
1490         if (fifo_mode & 1) {    /* IN endpoints */
1491                 UDC_RES1 |= USIR0_IR1|USIR0_IR6;
1492                 UDC_RES2 |= USIR1_IR11;
1493         }
1494         if (fifo_mode & 2) {    /* OUT endpoints */
1495                 UDC_RES1 |= USIR0_IR2|USIR0_IR7;
1496                 UDC_RES2 |= USIR1_IR12;
1497         }
1498 #endif
1499
1500         /* caller must be able to sleep in order to cope
1501          * with startup transients.
1502          */
1503         msleep(100);
1504
1505         /* enable suspend/resume and reset irqs */
1506         udc_clear_mask_UDCCR(UDCCR_SRM | UDCCR_REM);
1507
1508         /* enable ep0 irqs */
1509         UICR0 &= ~UICR0_IM0;
1510
1511         /* if hardware supports it, connect to usb and wait for host */
1512         let_usb_appear();
1513 }
1514
1515
1516 /* when a driver is successfully registered, it will receive
1517  * control requests including set_configuration(), which enables
1518  * non-control requests.  then usb traffic follows until a
1519  * disconnect is reported.  then a host may connect again, or
1520  * the driver might get unbound.
1521  */
1522 int usb_gadget_register_driver(struct usb_gadget_driver *driver)
1523 {
1524         struct pxa2xx_udc       *dev = the_controller;
1525         int                     retval;
1526
1527         if (!driver
1528                         || driver->speed != USB_SPEED_FULL
1529                         || !driver->bind
1530                         || !driver->unbind
1531                         || !driver->disconnect
1532                         || !driver->setup)
1533                 return -EINVAL;
1534         if (!dev)
1535                 return -ENODEV;
1536         if (dev->driver)
1537                 return -EBUSY;
1538
1539         /* first hook up the driver ... */
1540         dev->driver = driver;
1541         dev->gadget.dev.driver = &driver->driver;
1542
1543         device_add (&dev->gadget.dev);
1544         retval = driver->bind(&dev->gadget);
1545         if (retval) {
1546                 DMSG("bind to driver %s --> error %d\n",
1547                                 driver->driver.name, retval);
1548                 device_del (&dev->gadget.dev);
1549
1550                 dev->driver = 0;
1551                 dev->gadget.dev.driver = 0;
1552                 return retval;
1553         }
1554         device_create_file(dev->dev, &dev_attr_function);
1555
1556         /* ... then enable host detection and ep0; and we're ready
1557          * for set_configuration as well as eventual disconnect.
1558          * NOTE:  this shouldn't power up until later.
1559          */
1560         DMSG("registered gadget driver '%s'\n", driver->driver.name);
1561         udc_enable(dev);
1562         dump_state(dev);
1563         return 0;
1564 }
1565 EXPORT_SYMBOL(usb_gadget_register_driver);
1566
1567 static void
1568 stop_activity(struct pxa2xx_udc *dev, struct usb_gadget_driver *driver)
1569 {
1570         int i;
1571
1572         /* don't disconnect drivers more than once */
1573         if (dev->gadget.speed == USB_SPEED_UNKNOWN)
1574                 driver = 0;
1575         dev->gadget.speed = USB_SPEED_UNKNOWN;
1576
1577         /* prevent new request submissions, kill any outstanding requests  */
1578         for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1579                 struct pxa2xx_ep *ep = &dev->ep[i];
1580
1581                 ep->stopped = 1;
1582                 nuke(ep, -ESHUTDOWN);
1583         }
1584         del_timer_sync(&dev->timer);
1585
1586         /* report disconnect; the driver is already quiesced */
1587         LED_CONNECTED_OFF;
1588         if (driver)
1589                 driver->disconnect(&dev->gadget);
1590
1591         /* re-init driver-visible data structures */
1592         udc_reinit(dev);
1593 }
1594
1595 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
1596 {
1597         struct pxa2xx_udc       *dev = the_controller;
1598
1599         if (!dev)
1600                 return -ENODEV;
1601         if (!driver || driver != dev->driver)
1602                 return -EINVAL;
1603
1604         local_irq_disable();
1605         udc_disable(dev);
1606         stop_activity(dev, driver);
1607         local_irq_enable();
1608
1609         driver->unbind(&dev->gadget);
1610         dev->driver = 0;
1611
1612         device_del (&dev->gadget.dev);
1613         device_remove_file(dev->dev, &dev_attr_function);
1614
1615         DMSG("unregistered gadget driver '%s'\n", driver->driver.name);
1616         dump_state(dev);
1617         return 0;
1618 }
1619 EXPORT_SYMBOL(usb_gadget_unregister_driver);
1620
1621
1622 /*-------------------------------------------------------------------------*/
1623
1624 #ifdef CONFIG_ARCH_LUBBOCK
1625
1626 /* Lubbock can report connect or disconnect irqs.  Likely more hardware
1627  * could support it as a timer callback.
1628  *
1629  * FIXME for better power management, keep the hardware powered down
1630  * until a host is powering the link.  means scheduling work later
1631  * in some task that can udc_enable().
1632  */
1633
1634 #define enable_disconnect_irq() \
1635         if (machine_is_lubbock()) { enable_irq(LUBBOCK_USB_DISC_IRQ); }
1636 #define disable_disconnect_irq() \
1637         if (machine_is_lubbock()) { disable_irq(LUBBOCK_USB_DISC_IRQ); }
1638
1639 static irqreturn_t
1640 usb_connection_irq(int irq, void *_dev, struct pt_regs *r)
1641 {
1642         struct pxa2xx_udc       *dev = _dev;
1643
1644         dev->stats.irqs++;
1645         HEX_DISPLAY(dev->stats.irqs);
1646
1647         if (!is_usb_connected()) {
1648                 LED_CONNECTED_OFF;
1649                 disable_disconnect_irq();
1650                 /* report disconnect just once */
1651                 if (dev->gadget.speed != USB_SPEED_UNKNOWN) {
1652                         DMSG("disconnect %s\n",
1653                                 dev->driver ? dev->driver->driver.name : 0);
1654                         stop_activity(dev, dev->driver);
1655
1656                         // udc_disable (dev);
1657                         // no more udc irqs
1658                         // maybe "ACTION=disconnect /sbin/hotplug gadget".
1659                 }
1660         } else if (dev->gadget.speed == USB_SPEED_UNKNOWN) {
1661                 LED_CONNECTED_ON;
1662
1663                 DMSG("?? connect irq ??\n");
1664
1665                 // if there's no driver bound, ignore; else
1666                 // udc_enable (dev);
1667                 // UDC irqs drive the rest.
1668                 // maybe "ACTION=connect /sbin/hotplug gadget".
1669         }
1670         return IRQ_HANDLED;
1671 }
1672
1673 #endif
1674
1675 #ifndef enable_disconnect_irq
1676 #warning USB disconnect() is not yet reported.
1677 #define enable_disconnect_irq()         do {} while (0)
1678 #define disable_disconnect_irq()        do {} while (0)
1679 #endif
1680
1681
1682 /*-------------------------------------------------------------------------*/
1683
1684 static inline void clear_ep_state (struct pxa2xx_udc *dev)
1685 {
1686         unsigned i;
1687
1688         /* hardware SET_{CONFIGURATION,INTERFACE} automagic resets endpoint
1689          * fifos, and pending transactions mustn't be continued in any case.
1690          */
1691         for (i = 1; i < PXA_UDC_NUM_ENDPOINTS; i++)
1692                 nuke(&dev->ep[i], -ECONNABORTED);
1693 }
1694
1695 static void udc_watchdog(unsigned long _dev)
1696 {
1697         struct pxa2xx_udc       *dev = (void *)_dev;
1698
1699         local_irq_disable();
1700         if (dev->ep0state == EP0_STALL
1701                         && (UDCCS0 & UDCCS0_FST) == 0
1702                         && (UDCCS0 & UDCCS0_SST) == 0) {
1703                 UDCCS0 = UDCCS0_FST|UDCCS0_FTF;
1704                 DBG(DBG_VERBOSE, "ep0 re-stall\n");
1705                 start_watchdog(dev);
1706         }
1707         local_irq_enable();
1708 }
1709
1710 static void handle_ep0 (struct pxa2xx_udc *dev)
1711 {
1712         u32                     udccs0 = UDCCS0;
1713         struct pxa2xx_ep        *ep = &dev->ep [0];
1714         struct pxa2xx_request   *req;
1715         union {
1716                 struct usb_ctrlrequest  r;
1717                 u8                      raw [8];
1718                 u32                     word [2];
1719         } u;
1720
1721         if (list_empty(&ep->queue))
1722                 req = 0;
1723         else
1724                 req = list_entry(ep->queue.next, struct pxa2xx_request, queue);
1725
1726         /* clear stall status */
1727         if (udccs0 & UDCCS0_SST) {
1728                 nuke(ep, -EPIPE);
1729                 UDCCS0 = UDCCS0_SST;
1730                 del_timer(&dev->timer);
1731                 ep0_idle(dev);
1732         }
1733
1734         /* previous request unfinished?  non-error iff back-to-back ... */
1735         if ((udccs0 & UDCCS0_SA) != 0 && dev->ep0state != EP0_IDLE) {
1736                 nuke(ep, 0);
1737                 del_timer(&dev->timer);
1738                 ep0_idle(dev);
1739         }
1740
1741         switch (dev->ep0state) {
1742         case EP0_IDLE:
1743                 /* late-breaking status? */
1744                 udccs0 = UDCCS0;
1745
1746                 /* start control request? */
1747                 if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))
1748                                 == (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))) {
1749                         int i;
1750
1751                         nuke (ep, -EPROTO);
1752
1753                         /* read SETUP packet */
1754                         for (i = 0; i < 8; i++) {
1755                                 if (unlikely(!(UDCCS0 & UDCCS0_RNE))) {
1756 bad_setup:
1757                                         DMSG("SETUP %d!\n", i);
1758                                         goto stall;
1759                                 }
1760                                 u.raw [i] = (u8) UDDR0;
1761                         }
1762                         if (unlikely((UDCCS0 & UDCCS0_RNE) != 0))
1763                                 goto bad_setup;
1764
1765 got_setup:
1766                         le16_to_cpus (&u.r.wValue);
1767                         le16_to_cpus (&u.r.wIndex);
1768                         le16_to_cpus (&u.r.wLength);
1769
1770                         LED_EP0_ON;
1771                         DBG(DBG_VERBOSE, "SETUP %02x.%02x v%04x i%04x l%04x\n",
1772                                 u.r.bRequestType, u.r.bRequest,
1773                                 u.r.wValue, u.r.wIndex, u.r.wLength);
1774
1775                         /* cope with automagic for some standard requests. */
1776                         dev->req_std = (u.r.bRequestType & USB_TYPE_MASK)
1777                                                 == USB_TYPE_STANDARD;
1778                         dev->req_config = 0;
1779                         dev->req_pending = 1;
1780                         switch (u.r.bRequest) {
1781                         /* hardware restricts gadget drivers here! */
1782                         case USB_REQ_SET_CONFIGURATION:
1783                                 if (u.r.bRequestType == USB_RECIP_DEVICE) {
1784                                         /* reflect hardware's automagic
1785                                          * up to the gadget driver.
1786                                          */
1787 config_change:
1788                                         dev->req_config = 1;
1789                                         clear_ep_state(dev);
1790                                         /* if !has_cfr, there's no synch
1791                                          * else use AREN (later) not SA|OPR
1792                                          * USIR0_IR0 acts edge sensitive
1793                                          */
1794                                 }
1795                                 break;
1796                         /* ... and here, even more ... */
1797                         case USB_REQ_SET_INTERFACE:
1798                                 if (u.r.bRequestType == USB_RECIP_INTERFACE) {
1799                                         /* udc hardware is broken by design:
1800                                          *  - altsetting may only be zero;
1801                                          *  - hw resets all interfaces' eps;
1802                                          *  - ep reset doesn't include halt(?).
1803                                          */
1804                                         DMSG("broken set_interface (%d/%d)\n",
1805                                                 u.r.wIndex, u.r.wValue);
1806                                         goto config_change;
1807                                 }
1808                                 break;
1809                         /* hardware was supposed to hide this */
1810                         case USB_REQ_SET_ADDRESS:
1811                                 if (u.r.bRequestType == USB_RECIP_DEVICE) {
1812                                         ep0start(dev, 0, "address");
1813                                         return;
1814                                 }
1815                                 break;
1816                         }
1817
1818                         if (u.r.bRequestType & USB_DIR_IN)
1819                                 dev->ep0state = EP0_IN_DATA_PHASE;
1820                         else
1821                                 dev->ep0state = EP0_OUT_DATA_PHASE;
1822
1823                         i = dev->driver->setup(&dev->gadget, &u.r);
1824                         if (i < 0) {
1825                                 /* hardware automagic preventing STALL... */
1826                                 if (dev->req_config) {
1827                                         /* hardware sometimes neglects to tell
1828                                          * tell us about config change events,
1829                                          * so later ones may fail...
1830                                          */
1831                                         WARN("config change %02x fail %d?\n",
1832                                                 u.r.bRequest, i);
1833                                         return;
1834                                         /* TODO experiment:  if has_cfr,
1835                                          * hardware didn't ACK; maybe we
1836                                          * could actually STALL!
1837                                          */
1838                                 }
1839                                 DBG(DBG_VERBOSE, "protocol STALL, "
1840                                         "%02x err %d\n", UDCCS0, i);
1841 stall:
1842                                 /* the watchdog timer helps deal with cases
1843                                  * where udc seems to clear FST wrongly, and
1844                                  * then NAKs instead of STALLing.
1845                                  */
1846                                 ep0start(dev, UDCCS0_FST|UDCCS0_FTF, "stall");
1847                                 start_watchdog(dev);
1848                                 dev->ep0state = EP0_STALL;
1849                                 LED_EP0_OFF;
1850
1851                         /* deferred i/o == no response yet */
1852                         } else if (dev->req_pending) {
1853                                 if (likely(dev->ep0state == EP0_IN_DATA_PHASE
1854                                                 || dev->req_std || u.r.wLength))
1855                                         ep0start(dev, 0, "defer");
1856                                 else
1857                                         ep0start(dev, UDCCS0_IPR, "defer/IPR");
1858                         }
1859
1860                         /* expect at least one data or status stage irq */
1861                         return;
1862
1863                 } else if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA))
1864                                 == (UDCCS0_OPR|UDCCS0_SA))) {
1865                         unsigned i;
1866
1867                         /* pxa210/250 erratum 131 for B0/B1 says RNE lies.
1868                          * still observed on a pxa255 a0.
1869                          */
1870                         DBG(DBG_VERBOSE, "e131\n");
1871                         nuke(ep, -EPROTO);
1872
1873                         /* read SETUP data, but don't trust it too much */
1874                         for (i = 0; i < 8; i++)
1875                                 u.raw [i] = (u8) UDDR0;
1876                         if ((u.r.bRequestType & USB_RECIP_MASK)
1877                                         > USB_RECIP_OTHER)
1878                                 goto stall;
1879                         if (u.word [0] == 0 && u.word [1] == 0)
1880                                 goto stall;
1881                         goto got_setup;
1882                 } else {
1883                         /* some random early IRQ:
1884                          * - we acked FST
1885                          * - IPR cleared
1886                          * - OPR got set, without SA (likely status stage)
1887                          */
1888                         UDCCS0 = udccs0 & (UDCCS0_SA|UDCCS0_OPR);
1889                 }
1890                 break;
1891         case EP0_IN_DATA_PHASE:                 /* GET_DESCRIPTOR etc */
1892                 if (udccs0 & UDCCS0_OPR) {
1893                         UDCCS0 = UDCCS0_OPR|UDCCS0_FTF;
1894                         DBG(DBG_VERBOSE, "ep0in premature status\n");
1895                         if (req)
1896                                 done(ep, req, 0);
1897                         ep0_idle(dev);
1898                 } else /* irq was IPR clearing */ {
1899                         if (req) {
1900                                 /* this IN packet might finish the request */
1901                                 (void) write_ep0_fifo(ep, req);
1902                         } /* else IN token before response was written */
1903                 }
1904                 break;
1905         case EP0_OUT_DATA_PHASE:                /* SET_DESCRIPTOR etc */
1906                 if (udccs0 & UDCCS0_OPR) {
1907                         if (req) {
1908                                 /* this OUT packet might finish the request */
1909                                 if (read_ep0_fifo(ep, req))
1910                                         done(ep, req, 0);
1911                                 /* else more OUT packets expected */
1912                         } /* else OUT token before read was issued */
1913                 } else /* irq was IPR clearing */ {
1914                         DBG(DBG_VERBOSE, "ep0out premature status\n");
1915                         if (req)
1916                                 done(ep, req, 0);
1917                         ep0_idle(dev);
1918                 }
1919                 break;
1920         case EP0_END_XFER:
1921                 if (req)
1922                         done(ep, req, 0);
1923                 /* ack control-IN status (maybe in-zlp was skipped)
1924                  * also appears after some config change events.
1925                  */
1926                 if (udccs0 & UDCCS0_OPR)
1927                         UDCCS0 = UDCCS0_OPR;
1928                 ep0_idle(dev);
1929                 break;
1930         case EP0_STALL:
1931                 UDCCS0 = UDCCS0_FST;
1932                 break;
1933         }
1934         USIR0 = USIR0_IR0;
1935 }
1936
1937 static void handle_ep(struct pxa2xx_ep *ep)
1938 {
1939         struct pxa2xx_request   *req;
1940         int                     is_in = ep->bEndpointAddress & USB_DIR_IN;
1941         int                     completed;
1942         u32                     udccs, tmp;
1943
1944         do {
1945                 completed = 0;
1946                 if (likely (!list_empty(&ep->queue)))
1947                         req = list_entry(ep->queue.next,
1948                                         struct pxa2xx_request, queue);
1949                 else
1950                         req = 0;
1951
1952                 // TODO check FST handling
1953
1954                 udccs = *ep->reg_udccs;
1955                 if (unlikely(is_in)) {  /* irq from TPC, SST, or (ISO) TUR */
1956                         tmp = UDCCS_BI_TUR;
1957                         if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK))
1958                                 tmp |= UDCCS_BI_SST;
1959                         tmp &= udccs;
1960                         if (likely (tmp))
1961                                 *ep->reg_udccs = tmp;
1962                         if (req && likely ((udccs & UDCCS_BI_TFS) != 0))
1963                                 completed = write_fifo(ep, req);
1964
1965                 } else {        /* irq from RPC (or for ISO, ROF) */
1966                         if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK))
1967                                 tmp = UDCCS_BO_SST | UDCCS_BO_DME;
1968                         else
1969                                 tmp = UDCCS_IO_ROF | UDCCS_IO_DME;
1970                         tmp &= udccs;
1971                         if (likely(tmp))
1972                                 *ep->reg_udccs = tmp;
1973
1974                         /* fifos can hold packets, ready for reading... */
1975                         if (likely(req)) {
1976 #ifdef USE_OUT_DMA
1977 // TODO didn't yet debug out-dma.  this approach assumes
1978 // the worst about short packets and RPC; it might be better.
1979
1980                                 if (likely(ep->dma >= 0)) {
1981                                         if (!(udccs & UDCCS_BO_RSP)) {
1982                                                 *ep->reg_udccs = UDCCS_BO_RPC;
1983                                                 ep->dma_irqs++;
1984                                                 return;
1985                                         }
1986                                 }
1987 #endif
1988                                 completed = read_fifo(ep, req);
1989                         } else
1990                                 pio_irq_disable (ep->bEndpointAddress);
1991                 }
1992                 ep->pio_irqs++;
1993         } while (completed);
1994 }
1995
1996 /*
1997  *      pxa2xx_udc_irq - interrupt handler
1998  *
1999  * avoid delays in ep0 processing. the control handshaking isn't always
2000  * under software control (pxa250c0 and the pxa255 are better), and delays
2001  * could cause usb protocol errors.
2002  */
2003 static irqreturn_t
2004 pxa2xx_udc_irq(int irq, void *_dev, struct pt_regs *r)
2005 {
2006         struct pxa2xx_udc       *dev = _dev;
2007         int                     handled;
2008
2009         dev->stats.irqs++;
2010         HEX_DISPLAY(dev->stats.irqs);
2011         do {
2012                 u32             udccr = UDCCR;
2013
2014                 handled = 0;
2015
2016                 /* SUSpend Interrupt Request */
2017                 if (unlikely(udccr & UDCCR_SUSIR)) {
2018                         udc_ack_int_UDCCR(UDCCR_SUSIR);
2019                         handled = 1;
2020                         DBG(DBG_VERBOSE, "USB suspend%s\n", is_usb_connected()
2021                                 ? "" : "+disconnect");
2022
2023                         if (!is_usb_connected())
2024                                 stop_activity(dev, dev->driver);
2025                         else if (dev->gadget.speed != USB_SPEED_UNKNOWN
2026                                         && dev->driver
2027                                         && dev->driver->suspend)
2028                                 dev->driver->suspend(&dev->gadget);
2029                         ep0_idle (dev);
2030                 }
2031
2032                 /* RESume Interrupt Request */
2033                 if (unlikely(udccr & UDCCR_RESIR)) {
2034                         udc_ack_int_UDCCR(UDCCR_RESIR);
2035                         handled = 1;
2036                         DBG(DBG_VERBOSE, "USB resume\n");
2037
2038                         if (dev->gadget.speed != USB_SPEED_UNKNOWN
2039                                         && dev->driver
2040                                         && dev->driver->resume
2041                                         && is_usb_connected())
2042                                 dev->driver->resume(&dev->gadget);
2043                 }
2044
2045                 /* ReSeT Interrupt Request - USB reset */
2046                 if (unlikely(udccr & UDCCR_RSTIR)) {
2047                         udc_ack_int_UDCCR(UDCCR_RSTIR);
2048                         handled = 1;
2049
2050                         if ((UDCCR & UDCCR_UDA) == 0) {
2051                                 DBG(DBG_VERBOSE, "USB reset start\n");
2052                                 if (dev->gadget.speed != USB_SPEED_UNKNOWN)
2053                                         disable_disconnect_irq();
2054
2055                                 /* reset driver and endpoints,
2056                                  * in case that's not yet done
2057                                  */
2058                                 stop_activity (dev, dev->driver);
2059
2060                         } else {
2061                                 INFO("USB reset\n");
2062                                 dev->gadget.speed = USB_SPEED_FULL;
2063                                 LED_CONNECTED_ON;
2064                                 memset(&dev->stats, 0, sizeof dev->stats);
2065                                 /* driver and endpoints are still reset */
2066                                 enable_disconnect_irq();
2067                         }
2068
2069                 } else {
2070                         u32     usir0 = USIR0 & ~UICR0;
2071                         u32     usir1 = USIR1 & ~UICR1;
2072                         int     i;
2073
2074                         if (unlikely (!usir0 && !usir1))
2075                                 continue;
2076
2077                         DBG(DBG_VERY_NOISY, "irq %02x.%02x\n", usir1, usir0);
2078
2079                         /* control traffic */
2080                         if (usir0 & USIR0_IR0) {
2081                                 dev->ep[0].pio_irqs++;
2082                                 handle_ep0(dev);
2083                                 handled = 1;
2084                         }
2085
2086                         /* endpoint data transfers */
2087                         for (i = 0; i < 8; i++) {
2088                                 u32     tmp = 1 << i;
2089
2090                                 if (i && (usir0 & tmp)) {
2091                                         handle_ep(&dev->ep[i]);
2092                                         USIR0 |= tmp;
2093                                         handled = 1;
2094                                 }
2095                                 if (usir1 & tmp) {
2096                                         handle_ep(&dev->ep[i+8]);
2097                                         USIR1 |= tmp;
2098                                         handled = 1;
2099                                 }
2100                         }
2101                 }
2102
2103                 /* we could also ask for 1 msec SOF (SIR) interrupts */
2104
2105         } while (handled);
2106         return IRQ_HANDLED;
2107 }
2108
2109 /*-------------------------------------------------------------------------*/
2110
2111 static void nop_release (struct device *dev)
2112 {
2113         DMSG("%s %s\n", __FUNCTION__, dev->bus_id);
2114 }
2115
2116 /* this uses load-time allocation and initialization (instead of
2117  * doing it at run-time) to save code, eliminate fault paths, and
2118  * be more obviously correct.
2119  */
2120 static struct pxa2xx_udc memory = {
2121         .gadget = {
2122                 .ops            = &pxa2xx_udc_ops,
2123                 .ep0            = &memory.ep[0].ep,
2124                 .name           = driver_name,
2125                 .dev = {
2126                         .bus_id         = "gadget",
2127                         .release        = nop_release,
2128                 },
2129         },
2130
2131         /* control endpoint */
2132         .ep[0] = {
2133                 .ep = {
2134                         .name           = ep0name,
2135                         .ops            = &pxa2xx_ep_ops,
2136                         .maxpacket      = EP0_FIFO_SIZE,
2137                 },
2138                 .dev            = &memory,
2139                 .reg_udccs      = &UDCCS0,
2140                 .reg_uddr       = &UDDR0,
2141         },
2142
2143         /* first group of endpoints */
2144         .ep[1] = {
2145                 .ep = {
2146                         .name           = "ep1in-bulk",
2147                         .ops            = &pxa2xx_ep_ops,
2148                         .maxpacket      = BULK_FIFO_SIZE,
2149                 },
2150                 .dev            = &memory,
2151                 .fifo_size      = BULK_FIFO_SIZE,
2152                 .bEndpointAddress = USB_DIR_IN | 1,
2153                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
2154                 .reg_udccs      = &UDCCS1,
2155                 .reg_uddr       = &UDDR1,
2156                 drcmr (25)
2157         },
2158         .ep[2] = {
2159                 .ep = {
2160                         .name           = "ep2out-bulk",
2161                         .ops            = &pxa2xx_ep_ops,
2162                         .maxpacket      = BULK_FIFO_SIZE,
2163                 },
2164                 .dev            = &memory,
2165                 .fifo_size      = BULK_FIFO_SIZE,
2166                 .bEndpointAddress = 2,
2167                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
2168                 .reg_udccs      = &UDCCS2,
2169                 .reg_ubcr       = &UBCR2,
2170                 .reg_uddr       = &UDDR2,
2171                 drcmr (26)
2172         },
2173 #ifndef CONFIG_USB_PXA2XX_SMALL
2174         .ep[3] = {
2175                 .ep = {
2176                         .name           = "ep3in-iso",
2177                         .ops            = &pxa2xx_ep_ops,
2178                         .maxpacket      = ISO_FIFO_SIZE,
2179                 },
2180                 .dev            = &memory,
2181                 .fifo_size      = ISO_FIFO_SIZE,
2182                 .bEndpointAddress = USB_DIR_IN | 3,
2183                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
2184                 .reg_udccs      = &UDCCS3,
2185                 .reg_uddr       = &UDDR3,
2186                 drcmr (27)
2187         },
2188         .ep[4] = {
2189                 .ep = {
2190                         .name           = "ep4out-iso",
2191                         .ops            = &pxa2xx_ep_ops,
2192                         .maxpacket      = ISO_FIFO_SIZE,
2193                 },
2194                 .dev            = &memory,
2195                 .fifo_size      = ISO_FIFO_SIZE,
2196                 .bEndpointAddress = 4,
2197                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
2198                 .reg_udccs      = &UDCCS4,
2199                 .reg_ubcr       = &UBCR4,
2200                 .reg_uddr       = &UDDR4,
2201                 drcmr (28)
2202         },
2203         .ep[5] = {
2204                 .ep = {
2205                         .name           = "ep5in-int",
2206                         .ops            = &pxa2xx_ep_ops,
2207                         .maxpacket      = INT_FIFO_SIZE,
2208                 },
2209                 .dev            = &memory,
2210                 .fifo_size      = INT_FIFO_SIZE,
2211                 .bEndpointAddress = USB_DIR_IN | 5,
2212                 .bmAttributes   = USB_ENDPOINT_XFER_INT,
2213                 .reg_udccs      = &UDCCS5,
2214                 .reg_uddr       = &UDDR5,
2215         },
2216
2217         /* second group of endpoints */
2218         .ep[6] = {
2219                 .ep = {
2220                         .name           = "ep6in-bulk",
2221                         .ops            = &pxa2xx_ep_ops,
2222                         .maxpacket      = BULK_FIFO_SIZE,
2223                 },
2224                 .dev            = &memory,
2225                 .fifo_size      = BULK_FIFO_SIZE,
2226                 .bEndpointAddress = USB_DIR_IN | 6,
2227                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
2228                 .reg_udccs      = &UDCCS6,
2229                 .reg_uddr       = &UDDR6,
2230                 drcmr (30)
2231         },
2232         .ep[7] = {
2233                 .ep = {
2234                         .name           = "ep7out-bulk",
2235                         .ops            = &pxa2xx_ep_ops,
2236                         .maxpacket      = BULK_FIFO_SIZE,
2237                 },
2238                 .dev            = &memory,
2239                 .fifo_size      = BULK_FIFO_SIZE,
2240                 .bEndpointAddress = 7,
2241                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
2242                 .reg_udccs      = &UDCCS7,
2243                 .reg_ubcr       = &UBCR7,
2244                 .reg_uddr       = &UDDR7,
2245                 drcmr (31)
2246         },
2247         .ep[8] = {
2248                 .ep = {
2249                         .name           = "ep8in-iso",
2250                         .ops            = &pxa2xx_ep_ops,
2251                         .maxpacket      = ISO_FIFO_SIZE,
2252                 },
2253                 .dev            = &memory,
2254                 .fifo_size      = ISO_FIFO_SIZE,
2255                 .bEndpointAddress = USB_DIR_IN | 8,
2256                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
2257                 .reg_udccs      = &UDCCS8,
2258                 .reg_uddr       = &UDDR8,
2259                 drcmr (32)
2260         },
2261         .ep[9] = {
2262                 .ep = {
2263                         .name           = "ep9out-iso",
2264                         .ops            = &pxa2xx_ep_ops,
2265                         .maxpacket      = ISO_FIFO_SIZE,
2266                 },
2267                 .dev            = &memory,
2268                 .fifo_size      = ISO_FIFO_SIZE,
2269                 .bEndpointAddress = 9,
2270                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
2271                 .reg_udccs      = &UDCCS9,
2272                 .reg_ubcr       = &UBCR9,
2273                 .reg_uddr       = &UDDR9,
2274                 drcmr (33)
2275         },
2276         .ep[10] = {
2277                 .ep = {
2278                         .name           = "ep10in-int",
2279                         .ops            = &pxa2xx_ep_ops,
2280                         .maxpacket      = INT_FIFO_SIZE,
2281                 },
2282                 .dev            = &memory,
2283                 .fifo_size      = INT_FIFO_SIZE,
2284                 .bEndpointAddress = USB_DIR_IN | 10,
2285                 .bmAttributes   = USB_ENDPOINT_XFER_INT,
2286                 .reg_udccs      = &UDCCS10,
2287                 .reg_uddr       = &UDDR10,
2288         },
2289
2290         /* third group of endpoints */
2291         .ep[11] = {
2292                 .ep = {
2293                         .name           = "ep11in-bulk",
2294                         .ops            = &pxa2xx_ep_ops,
2295                         .maxpacket      = BULK_FIFO_SIZE,
2296                 },
2297                 .dev            = &memory,
2298                 .fifo_size      = BULK_FIFO_SIZE,
2299                 .bEndpointAddress = USB_DIR_IN | 11,
2300                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
2301                 .reg_udccs      = &UDCCS11,
2302                 .reg_uddr       = &UDDR11,
2303                 drcmr (35)
2304         },
2305         .ep[12] = {
2306                 .ep = {
2307                         .name           = "ep12out-bulk",
2308                         .ops            = &pxa2xx_ep_ops,
2309                         .maxpacket      = BULK_FIFO_SIZE,
2310                 },
2311                 .dev            = &memory,
2312                 .fifo_size      = BULK_FIFO_SIZE,
2313                 .bEndpointAddress = 12,
2314                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
2315                 .reg_udccs      = &UDCCS12,
2316                 .reg_ubcr       = &UBCR12,
2317                 .reg_uddr       = &UDDR12,
2318                 drcmr (36)
2319         },
2320         .ep[13] = {
2321                 .ep = {
2322                         .name           = "ep13in-iso",
2323                         .ops            = &pxa2xx_ep_ops,
2324                         .maxpacket      = ISO_FIFO_SIZE,
2325                 },
2326                 .dev            = &memory,
2327                 .fifo_size      = ISO_FIFO_SIZE,
2328                 .bEndpointAddress = USB_DIR_IN | 13,
2329                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
2330                 .reg_udccs      = &UDCCS13,
2331                 .reg_uddr       = &UDDR13,
2332                 drcmr (37)
2333         },
2334         .ep[14] = {
2335                 .ep = {
2336                         .name           = "ep14out-iso",
2337                         .ops            = &pxa2xx_ep_ops,
2338                         .maxpacket      = ISO_FIFO_SIZE,
2339                 },
2340                 .dev            = &memory,
2341                 .fifo_size      = ISO_FIFO_SIZE,
2342                 .bEndpointAddress = 14,
2343                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
2344                 .reg_udccs      = &UDCCS14,
2345                 .reg_ubcr       = &UBCR14,
2346                 .reg_uddr       = &UDDR14,
2347                 drcmr (38)
2348         },
2349         .ep[15] = {
2350                 .ep = {
2351                         .name           = "ep15in-int",
2352                         .ops            = &pxa2xx_ep_ops,
2353                         .maxpacket      = INT_FIFO_SIZE,
2354                 },
2355                 .dev            = &memory,
2356                 .fifo_size      = INT_FIFO_SIZE,
2357                 .bEndpointAddress = USB_DIR_IN | 15,
2358                 .bmAttributes   = USB_ENDPOINT_XFER_INT,
2359                 .reg_udccs      = &UDCCS15,
2360                 .reg_uddr       = &UDDR15,
2361         },
2362 #endif /* !CONFIG_USB_PXA2XX_SMALL */
2363 };
2364
2365 #define CP15R0_VENDOR_MASK      0xffffe000
2366
2367 #if     defined(CONFIG_ARCH_PXA)
2368 #define CP15R0_XSCALE_VALUE     0x69052000      /* intel/arm/xscale */
2369
2370 #elif   defined(CONFIG_ARCH_IXP4XX)
2371 #define CP15R0_XSCALE_VALUE     0x69054000      /* intel/arm/ixp4xx */
2372
2373 #endif
2374
2375 #define CP15R0_PROD_MASK        0x000003f0
2376 #define PXA25x                  0x00000100      /* and PXA26x */
2377 #define PXA210                  0x00000120
2378
2379 #define CP15R0_REV_MASK         0x0000000f
2380
2381 #define CP15R0_PRODREV_MASK     (CP15R0_PROD_MASK | CP15R0_REV_MASK)
2382
2383 #define PXA255_A0               0x00000106      /* or PXA260_B1 */
2384 #define PXA250_C0               0x00000105      /* or PXA26x_B0 */
2385 #define PXA250_B2               0x00000104
2386 #define PXA250_B1               0x00000103      /* or PXA260_A0 */
2387 #define PXA250_B0               0x00000102
2388 #define PXA250_A1               0x00000101
2389 #define PXA250_A0               0x00000100
2390
2391 #define PXA210_C0               0x00000125
2392 #define PXA210_B2               0x00000124
2393 #define PXA210_B1               0x00000123
2394 #define PXA210_B0               0x00000122
2395 #define IXP425_A0               0x000001c1
2396
2397 /*
2398  *      probe - binds to the platform device
2399  */
2400 static int __init pxa2xx_udc_probe(struct device *_dev)
2401 {
2402         struct pxa2xx_udc *dev = &memory;
2403         int retval, out_dma = 1;
2404         u32 chiprev;
2405
2406         /* insist on Intel/ARM/XScale */
2407         asm("mrc%? p15, 0, %0, c0, c0" : "=r" (chiprev));
2408         if ((chiprev & CP15R0_VENDOR_MASK) != CP15R0_XSCALE_VALUE) {
2409                 printk(KERN_ERR "%s: not XScale!\n", driver_name);
2410                 return -ENODEV;
2411         }
2412
2413         /* trigger chiprev-specific logic */
2414         switch (chiprev & CP15R0_PRODREV_MASK) {
2415 #if     defined(CONFIG_ARCH_PXA)
2416         case PXA255_A0:
2417                 dev->has_cfr = 1;
2418                 break;
2419         case PXA250_A0:
2420         case PXA250_A1:
2421                 /* A0/A1 "not released"; ep 13, 15 unusable */
2422                 /* fall through */
2423         case PXA250_B2: case PXA210_B2:
2424         case PXA250_B1: case PXA210_B1:
2425         case PXA250_B0: case PXA210_B0:
2426                 out_dma = 0;
2427                 /* fall through */
2428         case PXA250_C0: case PXA210_C0:
2429                 break;
2430 #elif   defined(CONFIG_ARCH_IXP4XX)
2431         case IXP425_A0:
2432                 out_dma = 0;
2433                 break;
2434 #endif
2435         default:
2436                 out_dma = 0;
2437                 printk(KERN_ERR "%s: unrecognized processor: %08x\n",
2438                         driver_name, chiprev);
2439                 /* iop3xx, ixp4xx, ... */
2440                 return -ENODEV;
2441         }
2442
2443         pr_debug("%s: IRQ %d%s%s%s\n", driver_name, IRQ_USB,
2444                 dev->has_cfr ? "" : " (!cfr)",
2445                 out_dma ? "" : " (broken dma-out)",
2446                 SIZE_STR DMASTR
2447                 );
2448
2449 #ifdef  USE_DMA
2450 #ifndef USE_OUT_DMA
2451         out_dma = 0;
2452 #endif
2453         /* pxa 250 erratum 130 prevents using OUT dma (fixed C0) */
2454         if (!out_dma) {
2455                 DMSG("disabled OUT dma\n");
2456                 dev->ep[ 2].reg_drcmr = dev->ep[ 4].reg_drcmr = 0;
2457                 dev->ep[ 7].reg_drcmr = dev->ep[ 9].reg_drcmr = 0;
2458                 dev->ep[12].reg_drcmr = dev->ep[14].reg_drcmr = 0;
2459         }
2460 #endif
2461
2462         /* other non-static parts of init */
2463         dev->dev = _dev;
2464         dev->mach = _dev->platform_data;
2465
2466         init_timer(&dev->timer);
2467         dev->timer.function = udc_watchdog;
2468         dev->timer.data = (unsigned long) dev;
2469
2470         device_initialize(&dev->gadget.dev);
2471         dev->gadget.dev.parent = _dev;
2472         dev->gadget.dev.dma_mask = _dev->dma_mask;
2473
2474         the_controller = dev;
2475         dev_set_drvdata(_dev, dev);
2476
2477         udc_disable(dev);
2478         udc_reinit(dev);
2479
2480         /* irq setup after old hardware state is cleaned up */
2481         retval = request_irq(IRQ_USB, pxa2xx_udc_irq,
2482                         SA_INTERRUPT, driver_name, dev);
2483         if (retval != 0) {
2484                 printk(KERN_ERR "%s: can't get irq %i, err %d\n",
2485                         driver_name, IRQ_USB, retval);
2486                 return -EBUSY;
2487         }
2488         dev->got_irq = 1;
2489
2490 #ifdef CONFIG_ARCH_LUBBOCK
2491         if (machine_is_lubbock()) {
2492                 disable_irq(LUBBOCK_USB_DISC_IRQ);
2493                 retval = request_irq(LUBBOCK_USB_DISC_IRQ,
2494                                 usb_connection_irq,
2495                                 SA_INTERRUPT /* OOPSING | SA_SAMPLE_RANDOM */,
2496                                 driver_name, dev);
2497                 if (retval != 0) {
2498                         enable_irq(LUBBOCK_USB_DISC_IRQ);
2499                         printk(KERN_ERR "%s: can't get irq %i, err %d\n",
2500                                 driver_name, LUBBOCK_USB_DISC_IRQ, retval);
2501                         return -EBUSY;
2502                 }
2503                 dev->got_disc = 1;
2504         }
2505 #endif
2506         create_proc_files();
2507
2508         return 0;
2509 }
2510 static int __exit pxa2xx_udc_remove(struct device *_dev)
2511 {
2512         struct pxa2xx_udc *dev = _dev->driver_data;
2513
2514         udc_disable(dev);
2515         remove_proc_files();
2516         usb_gadget_unregister_driver(dev->driver);
2517
2518         if (dev->got_irq) {
2519                 free_irq(IRQ_USB, dev);
2520                 dev->got_irq = 0;
2521         }
2522         if (machine_is_lubbock() && dev->got_disc) {
2523                 free_irq(LUBBOCK_USB_DISC_IRQ, dev);
2524                 dev->got_disc = 0;
2525         }
2526         dev_set_drvdata(_dev, 0);
2527         the_controller = 0;
2528         return 0;
2529 }
2530
2531 /*-------------------------------------------------------------------------*/
2532
2533 static struct device_driver udc_driver = {
2534         .name           = "pxa2xx-udc",
2535         .bus            = &platform_bus_type,
2536         .probe          = pxa2xx_udc_probe,
2537         .remove         = __exit_p(pxa2xx_udc_remove),
2538
2539         // FIXME power management support
2540         // .suspend = ... disable UDC
2541         // .resume = ... re-enable UDC
2542 };
2543
2544 static int __init udc_init(void)
2545 {
2546         printk(KERN_INFO "%s: version %s\n", driver_name, DRIVER_VERSION);
2547         return driver_register(&udc_driver);
2548 }
2549 module_init(udc_init);
2550
2551 static void __exit udc_exit(void)
2552 {
2553         driver_unregister(&udc_driver);
2554 }
2555 module_exit(udc_exit);
2556
2557 MODULE_DESCRIPTION(DRIVER_DESC);
2558 MODULE_AUTHOR("Frank Becker, Robert Schwebel, David Brownell");
2559 MODULE_LICENSE("GPL");
2560