drivers/usb/gadget/pxa2xx_udc.c

   1 /*
   2  * linux/drivers/usb/gadget/pxa2xx_udc.c
   3  * Intel PXA2xx and IXP4xx on-chip full speed USB device controllers
   4  *
   5  * Copyright (C) 2002 Intrinsyc, Inc. (Frank Becker)
   6  * Copyright (C) 2003 Robert Schwebel, Pengutronix
   7  * Copyright (C) 2003 Benedikt Spranger, Pengutronix
   8  * Copyright (C) 2003 David Brownell
   9  * Copyright (C) 2003 Joshua Wise
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  24  *
  25  */
  26
  27 #undef  DEBUG
  28 // #define      VERBOSE DBG_VERBOSE
  29
  30 #include <linux/config.h>
  31 #include <linux/module.h>
  32 #include <linux/kernel.h>
  33 #include <linux/ioport.h>
  34 #include <linux/types.h>
  35 #include <linux/version.h>
  36 #include <linux/errno.h>
  37 #include <linux/delay.h>
  38 #include <linux/sched.h>
  39 #include <linux/slab.h>
  40 #include <linux/init.h>
  41 #include <linux/timer.h>
  42 #include <linux/list.h>
  43 #include <linux/interrupt.h>
  44 #include <linux/proc_fs.h>
  45 #include <linux/mm.h>
  46 #include <linux/device.h>
  47 #include <linux/dma-mapping.h>
  48
  49 #include <asm/byteorder.h>
  50 #include <asm/dma.h>
  51 #include <asm/io.h>
  52 #include <asm/irq.h>
  53 #include <asm/system.h>
  54 #include <asm/mach-types.h>
  55 #include <asm/unaligned.h>
  56 #include <asm/hardware.h>
  57 #include <asm/arch/pxa-regs.h>
  58
  59 #include <linux/usb_ch9.h>
  60 #include <linux/usb_gadget.h>
  61
  62 #include <asm/arch/udc.h>
  63
  64
  65 /*
  66  * This driver handles the USB Device Controller (UDC) in Intel's PXA 2xx
  67  * series processors.  The UDC for the IXP 4xx series is very similar.
  68  * There are fifteen endpoints, in addition to ep0.
  69  *
  70  * Such controller drivers work with a gadget driver.  The gadget driver
  71  * returns descriptors, implements configuration and data protocols used
  72  * by the host to interact with this device, and allocates endpoints to
  73  * the different protocol interfaces.  The controller driver virtualizes
  74  * usb hardware so that the gadget drivers will be more portable.
  75  *
  76  * This UDC hardware wants to implement a bit too much USB protocol, so
  77  * it constrains the sorts of USB configuration change events that work.
  78  * The errata for these chips are misleading; some "fixed" bugs from
  79  * pxa250 a0/a1 b0/b1/b2 sure act like they're still there.
  80  */
  81
  82 #define DRIVER_VERSION  "14-Dec-2003"
  83 #define DRIVER_DESC     "PXA 2xx USB Device Controller driver"
  84
  85
  86 static const char driver_name [] = "pxa2xx_udc";
  87
  88 static const char ep0name [] = "ep0";
  89
  90
  91 // #define      USE_DMA
  92 // #define      USE_OUT_DMA
  93 // #define      DISABLE_TEST_MODE
  94
  95 #ifdef CONFIG_PROC_FS
  96 #define UDC_PROC_FILE
  97 #endif
  98
  99 #ifdef CONFIG_ARCH_IXP4XX
 100 #undef USE_DMA
 101
 102 /* cpu-specific register addresses are compiled in to this code */
 103 #ifdef CONFIG_ARCH_PXA
 104 #error "Can't configure both IXP and PXA"
 105 #endif
 106
 107 #endif
 108
 109 #include "pxa2xx_udc.h"
 110
 111
 112 #ifdef CONFIG_EMBEDDED
 113 /* few strings, and little code to use them */
 114 #undef  DEBUG
 115 #undef  UDC_PROC_FILE
 116 #endif
 117
 118 #ifdef  USE_DMA
 119 static int use_dma = 1;
 120 module_param(use_dma, bool, 0);
 121 MODULE_PARM_DESC (use_dma, "true to use dma");
 122
 123 static void dma_nodesc_handler (int dmach, void *_ep, struct pt_regs *r);
 124 static void kick_dma(struct pxa2xx_ep *ep, struct pxa2xx_request *req);
 125
 126 #ifdef USE_OUT_DMA
 127 #define DMASTR " (dma support)"
 128 #else
 129 #define DMASTR " (dma in)"
 130 #endif
 131
 132 #else   /* !USE_DMA */
 133 #define DMASTR " (pio only)"
 134 #undef  USE_OUT_DMA
 135 #endif
 136
 137 #ifdef  CONFIG_USB_PXA2XX_SMALL
 138 #define SIZE_STR        " (small)"
 139 #else
 140 #define SIZE_STR        ""
 141 #endif
 142
 143 #ifdef DISABLE_TEST_MODE
 144 /* (mode == 0) == no undocumented chip tweaks
 145  * (mode & 1)  == double buffer bulk IN
 146  * (mode & 2)  == double buffer bulk OUT
 147  * ... so mode = 3 (or 7, 15, etc) does it for both
 148  */
 149 static ushort fifo_mode = 0;
 150 module_param(fifo_mode, ushort, 0);
 151 MODULE_PARM_DESC (fifo_mode, "pxa2xx udc fifo mode");
 152 #endif
 153
 154 /* ---------------------------------------------------------------------------
 155  *      endpoint related parts of the api to the usb controller hardware,
 156  *      used by gadget driver; and the inner talker-to-hardware core.
 157  * ---------------------------------------------------------------------------
 158  */
 159
 160 static void pxa2xx_ep_fifo_flush (struct usb_ep *ep);
 161 static void nuke (struct pxa2xx_ep *, int status);
 162
 163 static void pio_irq_enable(int bEndpointAddress)
 164 {
 165         bEndpointAddress &= 0xf;
 166         if (bEndpointAddress < 8)
 167                 UICR0 &= ~(1 << bEndpointAddress);
 168         else {
 169                 bEndpointAddress -= 8;
 170                 UICR1 &= ~(1 << bEndpointAddress);
 171         }
 172 }
 173
 174 static void pio_irq_disable(int bEndpointAddress)
 175 {
 176         bEndpointAddress &= 0xf;
 177         if (bEndpointAddress < 8)
 178                 UICR0 |= 1 << bEndpointAddress;
 179         else {
 180                 bEndpointAddress -= 8;
 181                 UICR1 |= 1 << bEndpointAddress;
 182         }
 183 }
 184
 185 /* The UDCCR reg contains mask and interrupt status bits,
 186  * so using '|=' isn't safe as it may ack an interrupt.
 187  */
 188 #define UDCCR_MASK_BITS         (UDCCR_REM | UDCCR_SRM | UDCCR_UDE)
 189
 190 static inline void udc_set_mask_UDCCR(int mask)
 191 {
 192         UDCCR = (UDCCR & UDCCR_MASK_BITS) | (mask & UDCCR_MASK_BITS);
 193 }
 194
 195 static inline void udc_clear_mask_UDCCR(int mask)
 196 {
 197         UDCCR = (UDCCR & UDCCR_MASK_BITS) & ~(mask & UDCCR_MASK_BITS);
 198 }
 199
 200 static inline void udc_ack_int_UDCCR(int mask)
 201 {
 202         /* udccr contains the bits we dont want to change */
 203         __u32 udccr = UDCCR & UDCCR_MASK_BITS;
 204
 205         UDCCR = udccr | (mask & ~UDCCR_MASK_BITS);
 206 }
 207
 208 /*
 209  * endpoint enable/disable
 210  *
 211  * we need to verify the descriptors used to enable endpoints.  since pxa2xx
 212  * endpoint configurations are fixed, and are pretty much always enabled,
 213  * there's not a lot to manage here.
 214  *
 215  * because pxa2xx can't selectively initialize bulk (or interrupt) endpoints,
 216  * (resetting endpoint halt and toggle), SET_INTERFACE is unusable except
 217  * for a single interface (with only the default altsetting) and for gadget
 218  * drivers that don't halt endpoints (not reset by set_interface).  that also
 219  * means that if you use ISO, you must violate the USB spec rule that all
 220  * iso endpoints must be in non-default altsettings.
 221  */
 222 static int pxa2xx_ep_enable (struct usb_ep *_ep,
 223                 const struct usb_endpoint_descriptor *desc)
 224 {
 225         struct pxa2xx_ep        *ep;
 226         struct pxa2xx_udc       *dev;
 227
 228         ep = container_of (_ep, struct pxa2xx_ep, ep);
 229         if (!_ep || !desc || ep->desc || _ep->name == ep0name
 230                         || desc->bDescriptorType != USB_DT_ENDPOINT
 231                         || ep->bEndpointAddress != desc->bEndpointAddress
 232                         || ep->fifo_size < le16_to_cpu
 233                                                 (desc->wMaxPacketSize)) {
 234                 DMSG("%s, bad ep or descriptor\n", __FUNCTION__);
 235                 return -EINVAL;
 236         }
 237
 238         /* xfer types must match, except that interrupt ~= bulk */
 239         if (ep->bmAttributes != desc->bmAttributes
 240                         && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
 241                         && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
 242                 DMSG("%s, %s type mismatch\n", __FUNCTION__, _ep->name);
 243                 return -EINVAL;
 244         }
 245
 246         /* hardware _could_ do smaller, but driver doesn't */
 247         if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
 248                                 && le16_to_cpu (desc->wMaxPacketSize)
 249                                                 != BULK_FIFO_SIZE)
 250                         || !desc->wMaxPacketSize) {
 251                 DMSG("%s, bad %s maxpacket\n", __FUNCTION__, _ep->name);
 252                 return -ERANGE;
 253         }
 254
 255         dev = ep->dev;
 256         if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
 257                 DMSG("%s, bogus device state\n", __FUNCTION__);
 258                 return -ESHUTDOWN;
 259         }
 260
 261         ep->desc = desc;
 262         ep->dma = -1;
 263         ep->stopped = 0;
 264         ep->pio_irqs = ep->dma_irqs = 0;
 265         ep->ep.maxpacket = le16_to_cpu (desc->wMaxPacketSize);
 266
 267         /* flush fifo (mostly for OUT buffers) */
 268         pxa2xx_ep_fifo_flush (_ep);
 269
 270         /* ... reset halt state too, if we could ... */
 271
 272 #ifdef  USE_DMA
 273         /* for (some) bulk and ISO endpoints, try to get a DMA channel and
 274          * bind it to the endpoint.  otherwise use PIO.
 275          */
 276         switch (ep->bmAttributes) {
 277         case USB_ENDPOINT_XFER_ISOC:
 278                 if (le16_to_cpu(desc->wMaxPacketSize) % 32)
 279                         break;
 280                 // fall through
 281         case USB_ENDPOINT_XFER_BULK:
 282                 if (!use_dma || !ep->reg_drcmr)
 283                         break;
 284                 ep->dma = pxa_request_dma ((char *)_ep->name,
 285                                 (le16_to_cpu (desc->wMaxPacketSize) > 64)
 286                                         ? DMA_PRIO_MEDIUM /* some iso */
 287                                         : DMA_PRIO_LOW,
 288                                 dma_nodesc_handler, ep);
 289                 if (ep->dma >= 0) {
 290                         *ep->reg_drcmr = DRCMR_MAPVLD | ep->dma;
 291                         DMSG("%s using dma%d\n", _ep->name, ep->dma);
 292                 }
 293         }
 294 #endif
 295
 296         DBG(DBG_VERBOSE, "enabled %s\n", _ep->name);
 297         return 0;
 298 }
 299
 300 static int pxa2xx_ep_disable (struct usb_ep *_ep)
 301 {
 302         struct pxa2xx_ep        *ep;
 303
 304         ep = container_of (_ep, struct pxa2xx_ep, ep);
 305         if (!_ep || !ep->desc) {
 306                 DMSG("%s, %s not enabled\n", __FUNCTION__,
 307                         _ep ? ep->ep.name : NULL);
 308                 return -EINVAL;
 309         }
 310         nuke (ep, -ESHUTDOWN);
 311
 312 #ifdef  USE_DMA
 313         if (ep->dma >= 0) {
 314                 *ep->reg_drcmr = 0;
 315                 pxa_free_dma (ep->dma);
 316                 ep->dma = -1;
 317         }
 318 #endif
 319
 320         /* flush fifo (mostly for IN buffers) */
 321         pxa2xx_ep_fifo_flush (_ep);
 322
 323         ep->desc = 0;
 324         ep->stopped = 1;
 325
 326         DBG(DBG_VERBOSE, "%s disabled\n", _ep->name);
 327         return 0;
 328 }
 329
 330 /*-------------------------------------------------------------------------*/
 331
 332 /* for the pxa2xx, these can just wrap kmalloc/kfree.  gadget drivers
 333  * must still pass correctly initialized endpoints, since other controller
 334  * drivers may care about how it's currently set up (dma issues etc).
 335  */
 336
 337 /*
 338  *      pxa2xx_ep_alloc_request - allocate a request data structure
 339  */
 340 static struct usb_request *
 341 pxa2xx_ep_alloc_request (struct usb_ep *_ep, int gfp_flags)
 342 {
 343         struct pxa2xx_request *req;
 344
 345         req = kmalloc (sizeof *req, gfp_flags);
 346         if (!req)
 347                 return 0;
 348
 349         memset (req, 0, sizeof *req);
 350         INIT_LIST_HEAD (&req->queue);
 351         return &req->req;
 352 }
 353
 354
 355 /*
 356  *      pxa2xx_ep_free_request - deallocate a request data structure
 357  */
 358 static void
 359 pxa2xx_ep_free_request (struct usb_ep *_ep, struct usb_request *_req)
 360 {
 361         struct pxa2xx_request   *req;
 362
 363         req = container_of (_req, struct pxa2xx_request, req);
 364         WARN_ON (!list_empty (&req->queue));
 365         kfree(req);
 366 }
 367
 368
 369 /* PXA cache needs flushing with DMA I/O (it's dma-incoherent), but there's
 370  * no device-affinity and the heap works perfectly well for i/o buffers.
 371  * It wastes much less memory than dma_alloc_coherent() would, and even
 372  * prevents cacheline (32 bytes wide) sharing problems.
 373  */
 374 static void *
 375 pxa2xx_ep_alloc_buffer(struct usb_ep *_ep, unsigned bytes,
 376         dma_addr_t *dma, int gfp_flags)
 377 {
 378         char                    *retval;
 379
 380         retval = kmalloc (bytes, gfp_flags & ~(__GFP_DMA|__GFP_HIGHMEM));
 381         if (retval)
 382                 *dma = virt_to_bus (retval);
 383         return retval;
 384 }
 385
 386 static void
 387 pxa2xx_ep_free_buffer(struct usb_ep *_ep, void *buf, dma_addr_t dma,
 388                 unsigned bytes)
 389 {
 390         kfree (buf);
 391 }
 392
 393 /*-------------------------------------------------------------------------*/
 394
 395 /*
 396  *      done - retire a request; caller blocked irqs
 397  */
 398 static void done(struct pxa2xx_ep *ep, struct pxa2xx_request *req, int status)
 399 {
 400         unsigned                stopped = ep->stopped;
 401
 402         list_del_init(&req->queue);
 403
 404         if (likely (req->req.status == -EINPROGRESS))
 405                 req->req.status = status;
 406         else
 407                 status = req->req.status;
 408
 409         if (status && status != -ESHUTDOWN)
 410                 DBG(DBG_VERBOSE, "complete %s req %p stat %d len %u/%u\n",
 411                         ep->ep.name, &req->req, status,
 412                         req->req.actual, req->req.length);
 413
 414         /* don't modify queue heads during completion callback */
 415         ep->stopped = 1;
 416         req->req.complete(&ep->ep, &req->req);
 417         ep->stopped = stopped;
 418 }
 419
 420
 421 static inline void ep0_idle (struct pxa2xx_udc *dev)
 422 {
 423         dev->ep0state = EP0_IDLE;
 424         LED_EP0_OFF;
 425 }
 426
 427 static int
 428 write_packet(volatile u32 *uddr, struct pxa2xx_request *req, unsigned max)
 429 {
 430         u8              *buf;
 431         unsigned        length, count;
 432
 433         buf = req->req.buf + req->req.actual;
 434         prefetch(buf);
 435
 436         /* how big will this packet be? */
 437         length = min(req->req.length - req->req.actual, max);
 438         req->req.actual += length;
 439
 440         count = length;
 441         while (likely(count--))
 442                 *uddr = *buf++;
 443
 444         return length;
 445 }
 446
 447 /*
 448  * write to an IN endpoint fifo, as many packets as possible.
 449  * irqs will use this to write the rest later.
 450  * caller guarantees at least one packet buffer is ready (or a zlp).
 451  */
 452 static int
 453 write_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req)
 454 {
 455         unsigned                max;
 456
 457         max = le16_to_cpu(ep->desc->wMaxPacketSize);
 458         do {
 459                 unsigned        count;
 460                 int             is_last, is_short;
 461
 462                 count = write_packet(ep->reg_uddr, req, max);
 463
 464                 /* last packet is usually short (or a zlp) */
 465                 if (unlikely (count != max))
 466                         is_last = is_short = 1;
 467                 else {
 468                         if (likely(req->req.length != req->req.actual)
 469                                         || req->req.zero)
 470                                 is_last = 0;
 471                         else
 472                                 is_last = 1;
 473                         /* interrupt/iso maxpacket may not fill the fifo */
 474                         is_short = unlikely (max < ep->fifo_size);
 475                 }
 476
 477                 DBG(DBG_VERY_NOISY, "wrote %s %d bytes%s%s %d left %p\n",
 478                         ep->ep.name, count,
 479                         is_last ? "/L" : "", is_short ? "/S" : "",
 480                         req->req.length - req->req.actual, req);
 481
 482                 /* let loose that packet. maybe try writing another one,
 483                  * double buffering might work.  TSP, TPC, and TFS
 484                  * bit values are the same for all normal IN endpoints.
 485                  */
 486                 *ep->reg_udccs = UDCCS_BI_TPC;
 487                 if (is_short)
 488                         *ep->reg_udccs = UDCCS_BI_TSP;
 489
 490                 /* requests complete when all IN data is in the FIFO */
 491                 if (is_last) {
 492                         done (ep, req, 0);
 493                         if (list_empty(&ep->queue) || unlikely(ep->dma >= 0)) {
 494                                 pio_irq_disable (ep->bEndpointAddress);
 495 #ifdef USE_DMA
 496                                 /* unaligned data and zlps couldn't use dma */
 497                                 if (unlikely(!list_empty(&ep->queue))) {
 498                                         req = list_entry(ep->queue.next,
 499                                                 struct pxa2xx_request, queue);
 500                                         kick_dma(ep,req);
 501                                         return 0;
 502                                 }
 503 #endif
 504                         }
 505                         return 1;
 506                 }
 507
 508                 // TODO experiment: how robust can fifo mode tweaking be?
 509                 // double buffering is off in the default fifo mode, which
 510                 // prevents TFS from being set here.
 511
 512         } while (*ep->reg_udccs & UDCCS_BI_TFS);
 513         return 0;
 514 }
 515
 516 /* caller asserts req->pending (ep0 irq status nyet cleared); starts
 517  * ep0 data stage.  these chips want very simple state transitions.
 518  */
 519 static inline
 520 void ep0start(struct pxa2xx_udc *dev, u32 flags, const char *tag)
 521 {
 522         UDCCS0 = flags|UDCCS0_SA|UDCCS0_OPR;
 523         USIR0 = USIR0_IR0;
 524         dev->req_pending = 0;
 525         DBG(DBG_VERY_NOISY, "%s %s, %02x/%02x\n",
 526                 __FUNCTION__, tag, UDCCS0, flags);
 527 }
 528
 529 static int
 530 write_ep0_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req)
 531 {
 532         unsigned        count;
 533         int             is_short;
 534
 535         count = write_packet(&UDDR0, req, EP0_FIFO_SIZE);
 536         ep->dev->stats.write.bytes += count;
 537
 538         /* last packet "must be" short (or a zlp) */
 539         is_short = (count != EP0_FIFO_SIZE);
 540
 541         DBG(DBG_VERY_NOISY, "ep0in %d bytes %d left %p\n", count,
 542                 req->req.length - req->req.actual, req);
 543
 544         if (unlikely (is_short)) {
 545                 if (ep->dev->req_pending)
 546                         ep0start(ep->dev, UDCCS0_IPR, "short IN");
 547                 else
 548                         UDCCS0 = UDCCS0_IPR;
 549
 550                 count = req->req.length;
 551                 done (ep, req, 0);
 552                 ep0_idle(ep->dev);
 553 #if 1
 554                 /* This seems to get rid of lost status irqs in some cases:
 555                  * host responds quickly, or next request involves config
 556                  * change automagic, or should have been hidden, or ...
 557                  *
 558                  * FIXME get rid of all udelays possible...
 559                  */
 560                 if (count >= EP0_FIFO_SIZE) {
 561                         count = 100;
 562                         do {
 563                                 if ((UDCCS0 & UDCCS0_OPR) != 0) {
 564                                         /* clear OPR, generate ack */
 565                                         UDCCS0 = UDCCS0_OPR;
 566                                         break;
 567                                 }
 568                                 count--;
 569                                 udelay(1);
 570                         } while (count);
 571                 }
 572 #endif
 573         } else if (ep->dev->req_pending)
 574                 ep0start(ep->dev, 0, "IN");
 575         return is_short;
 576 }
 577
 578
 579 /*
 580  * read_fifo -  unload packet(s) from the fifo we use for usb OUT
 581  * transfers and put them into the request.  caller should have made
 582  * sure there's at least one packet ready.
 583  *
 584  * returns true if the request completed because of short packet or the
 585  * request buffer having filled (and maybe overran till end-of-packet).
 586  */
 587 static int
 588 read_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req)
 589 {
 590         for (;;) {
 591                 u32             udccs;
 592                 u8              *buf;
 593                 unsigned        bufferspace, count, is_short;
 594
 595                 /* make sure there's a packet in the FIFO.
 596                  * UDCCS_{BO,IO}_RPC are all the same bit value.
 597                  * UDCCS_{BO,IO}_RNE are all the same bit value.
 598                  */
 599                 udccs = *ep->reg_udccs;
 600                 if (unlikely ((udccs & UDCCS_BO_RPC) == 0))
 601                         break;
 602                 buf = req->req.buf + req->req.actual;
 603                 prefetchw(buf);
 604                 bufferspace = req->req.length - req->req.actual;
 605
 606                 /* read all bytes from this packet */
 607                 if (likely (udccs & UDCCS_BO_RNE)) {
 608                         count = 1 + (0x0ff & *ep->reg_ubcr);
 609                         req->req.actual += min (count, bufferspace);
 610                 } else /* zlp */
 611                         count = 0;
 612                 is_short = (count < ep->ep.maxpacket);
 613                 DBG(DBG_VERY_NOISY, "read %s %02x, %d bytes%s req %p %d/%d\n",
 614                         ep->ep.name, udccs, count,
 615                         is_short ? "/S" : "",
 616                         req, req->req.actual, req->req.length);
 617                 while (likely (count-- != 0)) {
 618                         u8      byte = (u8) *ep->reg_uddr;
 619
 620                         if (unlikely (bufferspace == 0)) {
 621                                 /* this happens when the driver's buffer
 622                                  * is smaller than what the host sent.
 623                                  * discard the extra data.
 624                                  */
 625                                 if (req->req.status != -EOVERFLOW)
 626                                         DMSG("%s overflow %d\n",
 627                                                 ep->ep.name, count);
 628                                 req->req.status = -EOVERFLOW;
 629                         } else {
 630                                 *buf++ = byte;
 631                                 bufferspace--;
 632                         }
 633                 }
 634                 *ep->reg_udccs =  UDCCS_BO_RPC;
 635                 /* RPC/RSP/RNE could now reflect the other packet buffer */
 636
 637                 /* iso is one request per packet */
 638                 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 639                         if (udccs & UDCCS_IO_ROF)
 640                                 req->req.status = -EHOSTUNREACH;
 641                         /* more like "is_done" */
 642                         is_short = 1;
 643                 }
 644
 645                 /* completion */
 646                 if (is_short || req->req.actual == req->req.length) {
 647                         done (ep, req, 0);
 648                         if (list_empty(&ep->queue))
 649                                 pio_irq_disable (ep->bEndpointAddress);
 650                         return 1;
 651                 }
 652
 653                 /* finished that packet.  the next one may be waiting... */
 654         }
 655         return 0;
 656 }
 657
 658 /*
 659  * special ep0 version of the above.  no UBCR0 or double buffering; status
 660  * handshaking is magic.  most device protocols don't need control-OUT.
 661  * CDC vendor commands (and RNDIS), mass storage CB/CBI, and some other
 662  * protocols do use them.
 663  */
 664 static int
 665 read_ep0_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req)
 666 {
 667         u8              *buf, byte;
 668         unsigned        bufferspace;
 669
 670         buf = req->req.buf + req->req.actual;
 671         bufferspace = req->req.length - req->req.actual;
 672
 673         while (UDCCS0 & UDCCS0_RNE) {
 674                 byte = (u8) UDDR0;
 675
 676                 if (unlikely (bufferspace == 0)) {
 677                         /* this happens when the driver's buffer
 678                          * is smaller than what the host sent.
 679                          * discard the extra data.
 680                          */
 681                         if (req->req.status != -EOVERFLOW)
 682                                 DMSG("%s overflow\n", ep->ep.name);
 683                         req->req.status = -EOVERFLOW;
 684                 } else {
 685                         *buf++ = byte;
 686                         req->req.actual++;
 687                         bufferspace--;
 688                 }
 689         }
 690
 691         UDCCS0 = UDCCS0_OPR | UDCCS0_IPR;
 692
 693         /* completion */
 694         if (req->req.actual >= req->req.length)
 695                 return 1;
 696
 697         /* finished that packet.  the next one may be waiting... */
 698         return 0;
 699 }
 700
 701 #ifdef  USE_DMA
 702
 703 #define MAX_IN_DMA      ((DCMD_LENGTH + 1) - BULK_FIFO_SIZE)
 704
 705 static void
 706 start_dma_nodesc(struct pxa2xx_ep *ep, struct pxa2xx_request *req, int is_in)
 707 {
 708         u32     dcmd = req->req.length;
 709         u32     buf = req->req.dma;
 710         u32     fifo = io_v2p ((u32)ep->reg_uddr);
 711
 712         /* caller guarantees there's a packet or more remaining
 713          *  - IN may end with a short packet (TSP set separately),
 714          *  - OUT is always full length
 715          */
 716         buf += req->req.actual;
 717         dcmd -= req->req.actual;
 718         ep->dma_fixup = 0;
 719
 720         /* no-descriptor mode can be simple for bulk-in, iso-in, iso-out */
 721         DCSR(ep->dma) = DCSR_NODESC;
 722         if (is_in) {
 723                 DSADR(ep->dma) = buf;
 724                 DTADR(ep->dma) = fifo;
 725                 if (dcmd > MAX_IN_DMA)
 726                         dcmd = MAX_IN_DMA;
 727                 else
 728                         ep->dma_fixup = (dcmd % ep->ep.maxpacket) != 0;
 729                 dcmd |= DCMD_BURST32 | DCMD_WIDTH1
 730                         | DCMD_FLOWTRG | DCMD_INCSRCADDR;
 731         } else {
 732 #ifdef USE_OUT_DMA
 733                 DSADR(ep->dma) = fifo;
 734                 DTADR(ep->dma) = buf;
 735                 if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
 736                         dcmd = ep->ep.maxpacket;
 737                 dcmd |= DCMD_BURST32 | DCMD_WIDTH1
 738                         | DCMD_FLOWSRC | DCMD_INCTRGADDR;
 739 #endif
 740         }
 741         DCMD(ep->dma) = dcmd;
 742         DCSR(ep->dma) = DCSR_RUN | DCSR_NODESC
 743                 | (unlikely(is_in)
 744                         ? DCSR_STOPIRQEN        /* use dma_nodesc_handler() */
 745                         : 0);                   /* use handle_ep() */
 746 }
 747
 748 static void kick_dma(struct pxa2xx_ep *ep, struct pxa2xx_request *req)
 749 {
 750         int     is_in = ep->bEndpointAddress & USB_DIR_IN;
 751
 752         if (is_in) {
 753                 /* unaligned tx buffers and zlps only work with PIO */
 754                 if ((req->req.dma & 0x0f) != 0
 755                                 || unlikely((req->req.length - req->req.actual)
 756                                                 == 0)) {
 757                         pio_irq_enable(ep->bEndpointAddress);
 758                         if ((*ep->reg_udccs & UDCCS_BI_TFS) != 0)
 759                                 (void) write_fifo(ep, req);
 760                 } else {
 761                         start_dma_nodesc(ep, req, USB_DIR_IN);
 762                 }
 763         } else {
 764                 if ((req->req.length - req->req.actual) < ep->ep.maxpacket) {
 765                         DMSG("%s short dma read...\n", ep->ep.name);
 766                         /* we're always set up for pio out */
 767                         read_fifo (ep, req);
 768                 } else {
 769                         *ep->reg_udccs = UDCCS_BO_DME
 770                                 | (*ep->reg_udccs & UDCCS_BO_FST);
 771                         start_dma_nodesc(ep, req, USB_DIR_OUT);
 772                 }
 773         }
 774 }
 775
 776 static void cancel_dma(struct pxa2xx_ep *ep)
 777 {
 778         struct pxa2xx_request   *req;
 779         u32                     tmp;
 780
 781         if (DCSR(ep->dma) == 0 || list_empty(&ep->queue))
 782                 return;
 783
 784         DCSR(ep->dma) = 0;
 785         while ((DCSR(ep->dma) & DCSR_STOPSTATE) == 0)
 786                 cpu_relax();
 787
 788         req = list_entry(ep->queue.next, struct pxa2xx_request, queue);
 789         tmp = DCMD(ep->dma) & DCMD_LENGTH;
 790         req->req.actual = req->req.length - (tmp & DCMD_LENGTH);
 791
 792         /* the last tx packet may be incomplete, so flush the fifo.
 793          * FIXME correct req.actual if we can
 794          */
 795         if (ep->bEndpointAddress & USB_DIR_IN)
 796                 *ep->reg_udccs = UDCCS_BI_FTF;
 797 }
 798
 799 /* dma channel stopped ... normal tx end (IN), or on error (IN/OUT) */
 800 static void dma_nodesc_handler(int dmach, void *_ep, struct pt_regs *r)
 801 {
 802         struct pxa2xx_ep        *ep = _ep;
 803         struct pxa2xx_request   *req;
 804         u32                     tmp, completed;
 805
 806         local_irq_disable();
 807
 808         req = list_entry(ep->queue.next, struct pxa2xx_request, queue);
 809
 810         ep->dma_irqs++;
 811         ep->dev->stats.irqs++;
 812         HEX_DISPLAY(ep->dev->stats.irqs);
 813
 814         /* ack/clear */
 815         tmp = DCSR(ep->dma);
 816         DCSR(ep->dma) = tmp;
 817         if ((tmp & DCSR_STOPSTATE) == 0
 818                         || (DDADR(ep->dma) & DDADR_STOP) != 0) {
 819                 DBG(DBG_VERBOSE, "%s, dcsr %08x ddadr %08x\n",
 820                         ep->ep.name, DCSR(ep->dma), DDADR(ep->dma));
 821                 goto done;
 822         }
 823         DCSR(ep->dma) = 0;      /* clear DCSR_STOPSTATE */
 824
 825         /* update transfer status */
 826         completed = tmp & DCSR_BUSERR;
 827         if (ep->bEndpointAddress & USB_DIR_IN)
 828                 tmp = DSADR(ep->dma);
 829         else
 830                 tmp = DTADR(ep->dma);
 831         req->req.actual = tmp - req->req.dma;
 832
 833         /* FIXME seems we sometimes see partial transfers... */
 834
 835         if (unlikely(completed != 0))
 836                 req->req.status = -EIO;
 837         else if (req->req.actual) {
 838                 /* these registers have zeroes in low bits; they miscount
 839                  * some (end-of-transfer) short packets:  tx 14 as tx 12
 840                  */
 841                 if (ep->dma_fixup)
 842                         req->req.actual = min(req->req.actual + 3,
 843                                                 req->req.length);
 844
 845                 tmp = (req->req.length - req->req.actual);
 846                 completed = (tmp == 0);
 847                 if (completed && (ep->bEndpointAddress & USB_DIR_IN)) {
 848
 849                         /* maybe validate final short packet ... */
 850                         if ((req->req.actual % ep->ep.maxpacket) != 0)
 851                                 *ep->reg_udccs = UDCCS_BI_TSP/*|UDCCS_BI_TPC*/;
 852
 853                         /* ... or zlp, using pio fallback */
 854                         else if (ep->bmAttributes == USB_ENDPOINT_XFER_BULK
 855                                         && req->req.zero) {
 856                                 DMSG("%s zlp terminate ...\n", ep->ep.name);
 857                                 completed = 0;
 858                         }
 859                 }
 860         }
 861
 862         if (likely(completed)) {
 863                 done(ep, req, 0);
 864
 865                 /* maybe re-activate after completion */
 866                 if (ep->stopped || list_empty(&ep->queue))
 867                         goto done;
 868                 req = list_entry(ep->queue.next, struct pxa2xx_request, queue);
 869         }
 870         kick_dma(ep, req);
 871 done:
 872         local_irq_enable();
 873 }
 874
 875 #endif
 876
 877 /*-------------------------------------------------------------------------*/
 878
 879 static int
 880 pxa2xx_ep_queue(struct usb_ep *_ep, struct usb_request *_req, int gfp_flags)
 881 {
 882         struct pxa2xx_request   *req;
 883         struct pxa2xx_ep        *ep;
 884         struct pxa2xx_udc       *dev;
 885         unsigned long           flags;
 886
 887         req = container_of(_req, struct pxa2xx_request, req);
 888         if (unlikely (!_req || !_req->complete || !_req->buf
 889                         || !list_empty(&req->queue))) {
 890                 DMSG("%s, bad params\n", __FUNCTION__);
 891                 return -EINVAL;
 892         }
 893
 894         ep = container_of(_ep, struct pxa2xx_ep, ep);
 895         if (unlikely (!_ep || (!ep->desc && ep->ep.name != ep0name))) {
 896                 DMSG("%s, bad ep\n", __FUNCTION__);
 897                 return -EINVAL;
 898         }
 899
 900         dev = ep->dev;
 901         if (unlikely (!dev->driver
 902                         || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
 903                 DMSG("%s, bogus device state\n", __FUNCTION__);
 904                 return -ESHUTDOWN;
 905         }
 906
 907         /* iso is always one packet per request, that's the only way
 908          * we can report per-packet status.  that also helps with dma.
 909          */
 910         if (unlikely (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
 911                         && req->req.length > le16_to_cpu
 912                                                 (ep->desc->wMaxPacketSize)))
 913                 return -EMSGSIZE;
 914
 915 #ifdef  USE_DMA
 916         // FIXME caller may already have done the dma mapping
 917         if (ep->dma >= 0) {
 918                 _req->dma = dma_map_single(dev->dev,
 919                         _req->buf, _req->length,
 920                         ((ep->bEndpointAddress & USB_DIR_IN) != 0)
 921                                 ? DMA_TO_DEVICE
 922                                 : DMA_FROM_DEVICE);
 923         }
 924 #endif
 925
 926         DBG(DBG_NOISY, "%s queue req %p, len %d buf %p\n",
 927              _ep->name, _req, _req->length, _req->buf);
 928
 929         local_irq_save(flags);
 930
 931         _req->status = -EINPROGRESS;
 932         _req->actual = 0;
 933
 934         /* kickstart this i/o queue? */
 935         if (list_empty(&ep->queue) && !ep->stopped) {
 936                 if (ep->desc == 0 /* ep0 */) {
 937                         unsigned        length = _req->length;
 938
 939                         switch (dev->ep0state) {
 940                         case EP0_IN_DATA_PHASE:
 941                                 dev->stats.write.ops++;
 942                                 if (write_ep0_fifo(ep, req))
 943                                         req = 0;
 944                                 break;
 945
 946                         case EP0_OUT_DATA_PHASE:
 947                                 dev->stats.read.ops++;
 948                                 /* messy ... */
 949                                 if (dev->req_config) {
 950                                         DBG(DBG_VERBOSE, "ep0 config ack%s\n",
 951                                                 dev->has_cfr ?  "" : " raced");
 952                                         if (dev->has_cfr)
 953                                                 UDCCFR = UDCCFR_AREN|UDCCFR_ACM;
 954                                         done(ep, req, 0);
 955                                         dev->ep0state = EP0_END_XFER;
 956                                         return 0;
 957                                 }
 958                                 if (dev->req_pending)
 959                                         ep0start(dev, UDCCS0_IPR, "OUT");
 960                                 if (length == 0 || ((UDCCS0 & UDCCS0_RNE) != 0
 961                                                 && read_ep0_fifo(ep, req))) {
 962                                         ep0_idle(dev);
 963                                         done(ep, req, 0);
 964                                         req = 0;
 965                                 }
 966                                 break;
 967
 968                         default:
 969                                 DMSG("ep0 i/o, odd state %d\n", dev->ep0state);
 970                                 local_irq_restore (flags);
 971                                 return -EL2HLT;
 972                         }
 973 #ifdef  USE_DMA
 974                 /* either start dma or prime pio pump */
 975                 } else if (ep->dma >= 0) {
 976                         kick_dma(ep, req);
 977 #endif
 978                 /* can the FIFO can satisfy the request immediately? */
 979                 } else if ((ep->bEndpointAddress & USB_DIR_IN) != 0
 980                                 && (*ep->reg_udccs & UDCCS_BI_TFS) != 0
 981                                 && write_fifo(ep, req)) {
 982                         req = 0;
 983                 } else if ((*ep->reg_udccs & UDCCS_BO_RFS) != 0
 984                                 && read_fifo(ep, req)) {
 985                         req = 0;
 986                 }
 987
 988                 if (likely (req && ep->desc) && ep->dma < 0)
 989                         pio_irq_enable(ep->bEndpointAddress);
 990         }
 991
 992         /* pio or dma irq handler advances the queue. */
 993         if (likely (req != 0))
 994                 list_add_tail(&req->queue, &ep->queue);
 995         local_irq_restore(flags);
 996
 997         return 0;
 998 }
 999
1000
1001 /*
1002  *      nuke - dequeue ALL requests
1003  */
1004 static void nuke(struct pxa2xx_ep *ep, int status)
1005 {
1006         struct pxa2xx_request *req;
1007
1008         /* called with irqs blocked */
1009 #ifdef  USE_DMA
1010         if (ep->dma >= 0 && !ep->stopped)
1011                 cancel_dma(ep);
1012 #endif
1013         while (!list_empty(&ep->queue)) {
1014                 req = list_entry(ep->queue.next,
1015                                 struct pxa2xx_request,
1016                                 queue);
1017                 done(ep, req, status);
1018         }
1019         if (ep->desc)
1020                 pio_irq_disable (ep->bEndpointAddress);
1021 }
1022
1023
1024 /* dequeue JUST ONE request */
1025 static int pxa2xx_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1026 {
1027         struct pxa2xx_ep        *ep;
1028         struct pxa2xx_request   *req;
1029         unsigned long           flags;
1030
1031         ep = container_of(_ep, struct pxa2xx_ep, ep);
1032         if (!_ep || ep->ep.name == ep0name)
1033                 return -EINVAL;
1034
1035         local_irq_save(flags);
1036
1037         /* make sure it's actually queued on this endpoint */
1038         list_for_each_entry (req, &ep->queue, queue) {
1039                 if (&req->req == _req)
1040                         break;
1041         }
1042         if (&req->req != _req) {
1043                 local_irq_restore(flags);
1044                 return -EINVAL;
1045         }
1046
1047 #ifdef  USE_DMA
1048         if (ep->dma >= 0 && ep->queue.next == &req->queue && !ep->stopped) {
1049                 cancel_dma(ep);
1050                 done(ep, req, -ECONNRESET);
1051                 /* restart i/o */
1052                 if (!list_empty(&ep->queue)) {
1053                         req = list_entry(ep->queue.next,
1054                                         struct pxa2xx_request, queue);
1055                         kick_dma(ep, req);
1056                 }
1057         } else
1058 #endif
1059                 done(ep, req, -ECONNRESET);
1060
1061         local_irq_restore(flags);
1062         return 0;
1063 }
1064
1065 /*-------------------------------------------------------------------------*/
1066
1067 static int pxa2xx_ep_set_halt(struct usb_ep *_ep, int value)
1068 {
1069         struct pxa2xx_ep        *ep;
1070         unsigned long           flags;
1071
1072         ep = container_of(_ep, struct pxa2xx_ep, ep);
1073         if (unlikely (!_ep
1074                         || (!ep->desc && ep->ep.name != ep0name))
1075                         || ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
1076                 DMSG("%s, bad ep\n", __FUNCTION__);
1077                 return -EINVAL;
1078         }
1079         if (value == 0) {
1080                 /* this path (reset toggle+halt) is needed to implement
1081                  * SET_INTERFACE on normal hardware.  but it can't be
1082                  * done from software on the PXA UDC, and the hardware
1083                  * forgets to do it as part of SET_INTERFACE automagic.
1084                  */
1085                 DMSG("only host can clear %s halt\n", _ep->name);
1086                 return -EROFS;
1087         }
1088
1089         local_irq_save(flags);
1090
1091         if ((ep->bEndpointAddress & USB_DIR_IN) != 0
1092                         && ((*ep->reg_udccs & UDCCS_BI_TFS) == 0
1093                            || !list_empty(&ep->queue))) {
1094                 local_irq_restore(flags);
1095                 return -EAGAIN;
1096         }
1097
1098         /* FST bit is the same for control, bulk in, bulk out, interrupt in */
1099         *ep->reg_udccs = UDCCS_BI_FST|UDCCS_BI_FTF;
1100
1101         /* ep0 needs special care */
1102         if (!ep->desc) {
1103                 start_watchdog(ep->dev);
1104                 ep->dev->req_pending = 0;
1105                 ep->dev->ep0state = EP0_STALL;
1106                 LED_EP0_OFF;
1107
1108         /* and bulk/intr endpoints like dropping stalls too */
1109         } else {
1110                 unsigned i;
1111                 for (i = 0; i < 1000; i += 20) {
1112                         if (*ep->reg_udccs & UDCCS_BI_SST)
1113                                 break;
1114                         udelay(20);
1115                 }
1116         }
1117         local_irq_restore(flags);
1118
1119         DBG(DBG_VERBOSE, "%s halt\n", _ep->name);
1120         return 0;
1121 }
1122
1123 static int pxa2xx_ep_fifo_status(struct usb_ep *_ep)
1124 {
1125         struct pxa2xx_ep        *ep;
1126
1127         ep = container_of(_ep, struct pxa2xx_ep, ep);
1128         if (!_ep) {
1129                 DMSG("%s, bad ep\n", __FUNCTION__);
1130                 return -ENODEV;
1131         }
1132         /* pxa can't report unclaimed bytes from IN fifos */
1133         if ((ep->bEndpointAddress & USB_DIR_IN) != 0)
1134                 return -EOPNOTSUPP;
1135         if (ep->dev->gadget.speed == USB_SPEED_UNKNOWN
1136                         || (*ep->reg_udccs & UDCCS_BO_RFS) == 0)
1137                 return 0;
1138         else
1139                 return (*ep->reg_ubcr & 0xfff) + 1;
1140 }
1141
1142 static void pxa2xx_ep_fifo_flush(struct usb_ep *_ep)
1143 {
1144         struct pxa2xx_ep        *ep;
1145
1146         ep = container_of(_ep, struct pxa2xx_ep, ep);
1147         if (!_ep || ep->ep.name == ep0name || !list_empty(&ep->queue)) {
1148                 DMSG("%s, bad ep\n", __FUNCTION__);
1149                 return;
1150         }
1151
1152         /* toggle and halt bits stay unchanged */
1153
1154         /* for OUT, just read and discard the FIFO contents. */
1155         if ((ep->bEndpointAddress & USB_DIR_IN) == 0) {
1156                 while (((*ep->reg_udccs) & UDCCS_BO_RNE) != 0)
1157                         (void) *ep->reg_uddr;
1158                 return;
1159         }
1160
1161         /* most IN status is the same, but ISO can't stall */
1162         *ep->reg_udccs = UDCCS_BI_TPC|UDCCS_BI_FTF|UDCCS_BI_TUR
1163                 | (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
1164                         ? 0 : UDCCS_BI_SST;
1165 }
1166
1167
1168 static struct usb_ep_ops pxa2xx_ep_ops = {
1169         .enable         = pxa2xx_ep_enable,
1170         .disable        = pxa2xx_ep_disable,
1171
1172         .alloc_request  = pxa2xx_ep_alloc_request,
1173         .free_request   = pxa2xx_ep_free_request,
1174
1175         .alloc_buffer   = pxa2xx_ep_alloc_buffer,
1176         .free_buffer    = pxa2xx_ep_free_buffer,
1177
1178         .queue          = pxa2xx_ep_queue,
1179         .dequeue        = pxa2xx_ep_dequeue,
1180
1181         .set_halt       = pxa2xx_ep_set_halt,
1182         .fifo_status    = pxa2xx_ep_fifo_status,
1183         .fifo_flush     = pxa2xx_ep_fifo_flush,
1184 };
1185
1186
1187 /* ---------------------------------------------------------------------------
1188  *      device-scoped parts of the api to the usb controller hardware
1189  * ---------------------------------------------------------------------------
1190  */
1191
1192 static int pxa2xx_udc_get_frame(struct usb_gadget *_gadget)
1193 {
1194         return ((UFNRH & 0x07) << 8) | (UFNRL & 0xff);
1195 }
1196
1197 static int pxa2xx_udc_wakeup(struct usb_gadget *_gadget)
1198 {
1199         /* host may not have enabled remote wakeup */
1200         if ((UDCCS0 & UDCCS0_DRWF) == 0)
1201                 return -EHOSTUNREACH;
1202         udc_set_mask_UDCCR(UDCCR_RSM);
1203         return 0;
1204 }
1205
1206 static const struct usb_gadget_ops pxa2xx_udc_ops = {
1207         .get_frame       = pxa2xx_udc_get_frame,
1208         .wakeup          = pxa2xx_udc_wakeup,
1209         // current versions must always be self-powered
1210 };
1211
1212
1213 /*-------------------------------------------------------------------------*/
1214
1215 #ifdef UDC_PROC_FILE
1216
1217 static const char proc_node_name [] = "driver/udc";
1218
1219 static int
1220 udc_proc_read(char *page, char **start, off_t off, int count,
1221                 int *eof, void *_dev)
1222 {
1223         char                    *buf = page;
1224         struct pxa2xx_udc       *dev = _dev;
1225         char                    *next = buf;
1226         unsigned                size = count;
1227         unsigned long           flags;
1228         int                     i, t;
1229         u32                     tmp;
1230
1231         if (off != 0)
1232                 return 0;
1233
1234         local_irq_save(flags);
1235
1236         /* basic device status */
1237         t = scnprintf(next, size, DRIVER_DESC "\n"
1238                 "%s version: %s\nGadget driver: %s\nHost %s\n\n",
1239                 driver_name, DRIVER_VERSION SIZE_STR DMASTR,
1240                 dev->driver ? dev->driver->driver.name : "(none)",
1241                 is_usb_connected() ? "full speed" : "disconnected");
1242         size -= t;
1243         next += t;
1244
1245         /* registers for device and ep0 */
1246         t = scnprintf(next, size,
1247                 "uicr %02X.%02X, usir %02X.%02x, ufnr %02X.%02X\n",
1248                 UICR1, UICR0, USIR1, USIR0, UFNRH, UFNRL);
1249         size -= t;
1250         next += t;
1251
1252         tmp = UDCCR;
1253         t = scnprintf(next, size,
1254                 "udccr %02X =%s%s%s%s%s%s%s%s\n", tmp,
1255                 (tmp & UDCCR_REM) ? " rem" : "",
1256                 (tmp & UDCCR_RSTIR) ? " rstir" : "",
1257                 (tmp & UDCCR_SRM) ? " srm" : "",
1258                 (tmp & UDCCR_SUSIR) ? " susir" : "",
1259                 (tmp & UDCCR_RESIR) ? " resir" : "",
1260                 (tmp & UDCCR_RSM) ? " rsm" : "",
1261                 (tmp & UDCCR_UDA) ? " uda" : "",
1262                 (tmp & UDCCR_UDE) ? " ude" : "");
1263         size -= t;
1264         next += t;
1265
1266         tmp = UDCCS0;
1267         t = scnprintf(next, size,
1268                 "udccs0 %02X =%s%s%s%s%s%s%s%s\n", tmp,
1269                 (tmp & UDCCS0_SA) ? " sa" : "",
1270                 (tmp & UDCCS0_RNE) ? " rne" : "",
1271                 (tmp & UDCCS0_FST) ? " fst" : "",
1272                 (tmp & UDCCS0_SST) ? " sst" : "",
1273                 (tmp & UDCCS0_DRWF) ? " dwrf" : "",
1274                 (tmp & UDCCS0_FTF) ? " ftf" : "",
1275                 (tmp & UDCCS0_IPR) ? " ipr" : "",
1276                 (tmp & UDCCS0_OPR) ? " opr" : "");
1277         size -= t;
1278         next += t;
1279
1280         if (dev->has_cfr) {
1281                 tmp = UDCCFR;
1282                 t = scnprintf(next, size,
1283                         "udccfr %02X =%s%s\n", tmp,
1284                         (tmp & UDCCFR_AREN) ? " aren" : "",
1285                         (tmp & UDCCFR_ACM) ? " acm" : "");
1286                 size -= t;
1287                 next += t;
1288         }
1289
1290         if (!is_usb_connected() || !dev->driver)
1291                 goto done;
1292
1293         t = scnprintf(next, size, "ep0 IN %lu/%lu, OUT %lu/%lu\nirqs %lu\n\n",
1294                 dev->stats.write.bytes, dev->stats.write.ops,
1295                 dev->stats.read.bytes, dev->stats.read.ops,
1296                 dev->stats.irqs);
1297         size -= t;
1298         next += t;
1299
1300         /* dump endpoint queues */
1301         for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1302                 struct pxa2xx_ep        *ep = &dev->ep [i];
1303                 struct pxa2xx_request   *req;
1304                 int                     t;
1305
1306                 if (i != 0) {
1307                         const struct usb_endpoint_descriptor    *d;
1308
1309                         d = ep->desc;
1310                         if (!d)
1311                                 continue;
1312                         tmp = *dev->ep [i].reg_udccs;
1313                         t = scnprintf(next, size,
1314                                 "%s max %d %s udccs %02x irqs %lu/%lu\n",
1315                                 ep->ep.name, le16_to_cpu (d->wMaxPacketSize),
1316                                 (ep->dma >= 0) ? "dma" : "pio", tmp,
1317                                 ep->pio_irqs, ep->dma_irqs);
1318                         /* TODO translate all five groups of udccs bits! */
1319
1320                 } else /* ep0 should only have one transfer queued */
1321                         t = scnprintf(next, size, "ep0 max 16 pio irqs %lu\n",
1322                                 ep->pio_irqs);
1323                 if (t <= 0 || t > size)
1324                         goto done;
1325                 size -= t;
1326                 next += t;
1327
1328                 if (list_empty(&ep->queue)) {
1329                         t = scnprintf(next, size, "\t(nothing queued)\n");
1330                         if (t <= 0 || t > size)
1331                                 goto done;
1332                         size -= t;
1333                         next += t;
1334                         continue;
1335                 }
1336                 list_for_each_entry(req, &ep->queue, queue) {
1337 #ifdef  USE_DMA
1338                         if (ep->dma >= 0 && req->queue.prev == &ep->queue)
1339                                 t = scnprintf(next, size,
1340                                         "\treq %p len %d/%d "
1341                                         "buf %p (dma%d dcmd %08x)\n",
1342                                         &req->req, req->req.actual,
1343                                         req->req.length, req->req.buf,
1344                                         ep->dma, DCMD(ep->dma)
1345                                         // low 13 bits == bytes-to-go
1346                                         );
1347                         else
1348 #endif
1349                                 t = scnprintf(next, size,
1350                                         "\treq %p len %d/%d buf %p\n",
1351                                         &req->req, req->req.actual,
1352                                         req->req.length, req->req.buf);
1353                         if (t <= 0 || t > size)
1354                                 goto done;
1355                         size -= t;
1356                         next += t;
1357                 }
1358         }
1359
1360 done:
1361         local_irq_restore(flags);
1362         *eof = 1;
1363         return count - size;
1364 }
1365
1366 #define create_proc_files() \
1367         create_proc_read_entry(proc_node_name, 0, NULL, udc_proc_read, dev)
1368 #define remove_proc_files() \
1369         remove_proc_entry(proc_node_name, NULL)
1370
1371 #else   /* !UDC_PROC_FILE */
1372 #define create_proc_files() do {} while (0)
1373 #define remove_proc_files() do {} while (0)
1374
1375 #endif  /* UDC_PROC_FILE */
1376
1377 /* "function" sysfs attribute */
1378 static ssize_t
1379 show_function (struct device *_dev, char *buf)
1380 {
1381         struct pxa2xx_udc       *dev = dev_get_drvdata (_dev);
1382
1383         if (!dev->driver
1384                         || !dev->driver->function
1385                         || strlen (dev->driver->function) > PAGE_SIZE)
1386                 return 0;
1387         return scnprintf (buf, PAGE_SIZE, "%s\n", dev->driver->function);
1388 }
1389 static DEVICE_ATTR (function, S_IRUGO, show_function, NULL);
1390
1391 /*-------------------------------------------------------------------------*/
1392
1393 /*
1394  *      udc_disable - disable USB device controller
1395  */
1396 static void udc_disable(struct pxa2xx_udc *dev)
1397 {
1398         /* block all irqs */
1399         udc_set_mask_UDCCR(UDCCR_SRM|UDCCR_REM);
1400         UICR0 = UICR1 = 0xff;
1401         UFNRH = UFNRH_SIM;
1402
1403         /* if hardware supports it, disconnect from usb */
1404         make_usb_disappear();
1405
1406         udc_clear_mask_UDCCR(UDCCR_UDE);
1407
1408 #ifdef  CONFIG_ARCH_PXA
1409         /* Disable clock for USB device */
1410         pxa_set_cken(CKEN11_USB, 0);
1411 #endif
1412
1413         ep0_idle (dev);
1414         dev->gadget.speed = USB_SPEED_UNKNOWN;
1415         LED_CONNECTED_OFF;
1416 }
1417
1418
1419 /*
1420  *      udc_reinit - initialize software state
1421  */
1422 static void udc_reinit(struct pxa2xx_udc *dev)
1423 {
1424         u32     i;
1425
1426         /* device/ep0 records init */
1427         INIT_LIST_HEAD (&dev->gadget.ep_list);
1428         INIT_LIST_HEAD (&dev->gadget.ep0->ep_list);
1429         dev->ep0state = EP0_IDLE;
1430
1431         /* basic endpoint records init */
1432         for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1433                 struct pxa2xx_ep *ep = &dev->ep[i];
1434
1435                 if (i != 0)
1436                         list_add_tail (&ep->ep.ep_list, &dev->gadget.ep_list);
1437
1438                 ep->desc = 0;
1439                 ep->stopped = 0;
1440                 INIT_LIST_HEAD (&ep->queue);
1441                 ep->pio_irqs = ep->dma_irqs = 0;
1442         }
1443
1444         /* the rest was statically initialized, and is read-only */
1445 }
1446
1447 /* until it's enabled, this UDC should be completely invisible
1448  * to any USB host.
1449  */
1450 static void udc_enable (struct pxa2xx_udc *dev)
1451 {
1452         udc_clear_mask_UDCCR(UDCCR_UDE);
1453
1454 #ifdef  CONFIG_ARCH_PXA
1455         /* Enable clock for USB device */
1456         pxa_set_cken(CKEN11_USB, 1);
1457 #endif
1458
1459         /* try to clear these bits before we enable the udc */
1460         udc_ack_int_UDCCR(UDCCR_SUSIR|/*UDCCR_RSTIR|*/UDCCR_RESIR);
1461
1462         ep0_idle(dev);
1463         dev->gadget.speed = USB_SPEED_UNKNOWN;
1464         dev->stats.irqs = 0;
1465
1466         /*
1467          * sequence taken from chapter 12.5.10, PXA250 AppProcDevManual:
1468          * - enable UDC
1469          * - if RESET is already in progress, ack interrupt
1470          * - unmask reset interrupt
1471          */
1472         udc_set_mask_UDCCR(UDCCR_UDE);
1473         if (!(UDCCR & UDCCR_UDA))
1474                 udc_ack_int_UDCCR(UDCCR_RSTIR);
1475
1476         if (dev->has_cfr /* UDC_RES2 is defined */) {
1477                 /* pxa255 (a0+) can avoid a set_config race that could
1478                  * prevent gadget drivers from configuring correctly
1479                  */
1480                 UDCCFR = UDCCFR_ACM;
1481         } else {
1482                 /* "USB test mode" for pxa250 errata 40-42 (stepping a0, a1)
1483                  * which could result in missing packets and interrupts.
1484                  * supposedly one bit per endpoint, controlling whether it
1485                  * double buffers or not; ACM/AREN bits fit into the holes.
1486                  * zero bits (like USIR0_IRx) disable double buffering.
1487                  */
1488                 UDC_RES1 = 0x00;
1489                 UDC_RES2 = 0x00;
1490         }
1491
1492 #ifdef  DISABLE_TEST_MODE
1493         /* "test mode" seems to have become the default in later chip
1494          * revs, preventing double buffering (and invalidating docs).
1495          * this EXPERIMENT enables it for bulk endpoints by tweaking
1496          * undefined/reserved register bits (that other drivers clear).
1497          * Belcarra code comments noted this usage.
1498          */
1499         if (fifo_mode & 1) {    /* IN endpoints */
1500                 UDC_RES1 |= USIR0_IR1|USIR0_IR6;
1501                 UDC_RES2 |= USIR1_IR11;
1502         }
1503         if (fifo_mode & 2) {    /* OUT endpoints */
1504                 UDC_RES1 |= USIR0_IR2|USIR0_IR7;
1505                 UDC_RES2 |= USIR1_IR12;
1506         }
1507 #endif
1508
1509         /* caller must be able to sleep in order to cope
1510          * with startup transients.
1511          */
1512         msleep(100);
1513
1514         /* enable suspend/resume and reset irqs */
1515         udc_clear_mask_UDCCR(UDCCR_SRM | UDCCR_REM);
1516
1517         /* enable ep0 irqs */
1518         UICR0 &= ~UICR0_IM0;
1519
1520         /* if hardware supports it, connect to usb and wait for host */
1521         let_usb_appear();
1522 }
1523
1524
1525 /* when a driver is successfully registered, it will receive
1526  * control requests including set_configuration(), which enables
1527  * non-control requests.  then usb traffic follows until a
1528  * disconnect is reported.  then a host may connect again, or
1529  * the driver might get unbound.
1530  */
1531 int usb_gadget_register_driver(struct usb_gadget_driver *driver)
1532 {
1533         struct pxa2xx_udc       *dev = the_controller;
1534         int                     retval;
1535
1536         if (!driver
1537                         || driver->speed != USB_SPEED_FULL
1538                         || !driver->bind
1539                         || !driver->unbind
1540                         || !driver->disconnect
1541                         || !driver->setup)
1542                 return -EINVAL;
1543         if (!dev)
1544                 return -ENODEV;
1545         if (dev->driver)
1546                 return -EBUSY;
1547
1548         /* first hook up the driver ... */
1549         dev->driver = driver;
1550         dev->gadget.dev.driver = &driver->driver;
1551
1552         device_add (&dev->gadget.dev);
1553         retval = driver->bind(&dev->gadget);
1554         if (retval) {
1555                 DMSG("bind to driver %s --> error %d\n",
1556                                 driver->driver.name, retval);
1557                 device_del (&dev->gadget.dev);
1558
1559                 dev->driver = 0;
1560                 dev->gadget.dev.driver = 0;
1561                 return retval;
1562         }
1563         device_create_file(dev->dev, &dev_attr_function);
1564
1565         /* ... then enable host detection and ep0; and we're ready
1566          * for set_configuration as well as eventual disconnect.
1567          * NOTE:  this shouldn't power up until later.
1568          */
1569         DMSG("registered gadget driver '%s'\n", driver->driver.name);
1570         udc_enable(dev);
1571         dump_state(dev);
1572         return 0;
1573 }
1574 EXPORT_SYMBOL(usb_gadget_register_driver);
1575
1576 static void
1577 stop_activity(struct pxa2xx_udc *dev, struct usb_gadget_driver *driver)
1578 {
1579         int i;
1580
1581         /* don't disconnect drivers more than once */
1582         if (dev->gadget.speed == USB_SPEED_UNKNOWN)
1583                 driver = 0;
1584         dev->gadget.speed = USB_SPEED_UNKNOWN;
1585
1586         /* prevent new request submissions, kill any outstanding requests  */
1587         for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1588                 struct pxa2xx_ep *ep = &dev->ep[i];
1589
1590                 ep->stopped = 1;
1591                 nuke(ep, -ESHUTDOWN);
1592         }
1593         del_timer_sync(&dev->timer);
1594
1595         /* report disconnect; the driver is already quiesced */
1596         LED_CONNECTED_OFF;
1597         if (driver)
1598                 driver->disconnect(&dev->gadget);
1599
1600         /* re-init driver-visible data structures */
1601         udc_reinit(dev);
1602 }
1603
1604 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
1605 {
1606         struct pxa2xx_udc       *dev = the_controller;
1607
1608         if (!dev)
1609                 return -ENODEV;
1610         if (!driver || driver != dev->driver)
1611                 return -EINVAL;
1612
1613         local_irq_disable();
1614         udc_disable(dev);
1615         stop_activity(dev, driver);
1616         local_irq_enable();
1617
1618         driver->unbind(&dev->gadget);
1619         dev->driver = 0;
1620
1621         device_del (&dev->gadget.dev);
1622         device_remove_file(dev->dev, &dev_attr_function);
1623
1624         DMSG("unregistered gadget driver '%s'\n", driver->driver.name);
1625         dump_state(dev);
1626         return 0;
1627 }
1628 EXPORT_SYMBOL(usb_gadget_unregister_driver);
1629
1630
1631 /*-------------------------------------------------------------------------*/
1632
1633 #ifdef CONFIG_ARCH_LUBBOCK
1634
1635 /* Lubbock can report connect or disconnect irqs.  Likely more hardware
1636  * could support it as a timer callback.
1637  *
1638  * FIXME for better power management, keep the hardware powered down
1639  * until a host is powering the link.  means scheduling work later
1640  * in some task that can udc_enable().
1641  */
1642
1643 #define enable_disconnect_irq() \
1644         if (machine_is_lubbock()) { enable_irq(LUBBOCK_USB_DISC_IRQ); }
1645 #define disable_disconnect_irq() \
1646         if (machine_is_lubbock()) { disable_irq(LUBBOCK_USB_DISC_IRQ); }
1647
1648 static irqreturn_t
1649 usb_connection_irq(int irq, void *_dev, struct pt_regs *r)
1650 {
1651         struct pxa2xx_udc       *dev = _dev;
1652
1653         dev->stats.irqs++;
1654         HEX_DISPLAY(dev->stats.irqs);
1655
1656         if (!is_usb_connected()) {
1657                 LED_CONNECTED_OFF;
1658                 disable_disconnect_irq();
1659                 /* report disconnect just once */
1660                 if (dev->gadget.speed != USB_SPEED_UNKNOWN) {
1661                         DMSG("disconnect %s\n",
1662                                 dev->driver ? dev->driver->driver.name : 0);
1663                         stop_activity(dev, dev->driver);
1664
1665                         // udc_disable (dev);
1666                         // no more udc irqs
1667                         // maybe "ACTION=disconnect /sbin/hotplug gadget".
1668                 }
1669         } else if (dev->gadget.speed == USB_SPEED_UNKNOWN) {
1670                 LED_CONNECTED_ON;
1671
1672                 DMSG("?? connect irq ??\n");
1673
1674                 // if there's no driver bound, ignore; else
1675                 // udc_enable (dev);
1676                 // UDC irqs drive the rest.
1677                 // maybe "ACTION=connect /sbin/hotplug gadget".
1678         }
1679         return IRQ_HANDLED;
1680 }
1681
1682 #endif
1683
1684 #ifndef enable_disconnect_irq
1685 #warning USB disconnect() is not yet reported.
1686 #define enable_disconnect_irq()         do {} while (0)
1687 #define disable_disconnect_irq()        do {} while (0)
1688 #endif
1689
1690
1691 /*-------------------------------------------------------------------------*/
1692
1693 static inline void clear_ep_state (struct pxa2xx_udc *dev)
1694 {
1695         unsigned i;
1696
1697         /* hardware SET_{CONFIGURATION,INTERFACE} automagic resets endpoint
1698          * fifos, and pending transactions mustn't be continued in any case.
1699          */
1700         for (i = 1; i < PXA_UDC_NUM_ENDPOINTS; i++)
1701                 nuke(&dev->ep[i], -ECONNABORTED);
1702 }
1703
1704 static void udc_watchdog(unsigned long _dev)
1705 {
1706         struct pxa2xx_udc       *dev = (void *)_dev;
1707
1708         local_irq_disable();
1709         if (dev->ep0state == EP0_STALL
1710                         && (UDCCS0 & UDCCS0_FST) == 0
1711                         && (UDCCS0 & UDCCS0_SST) == 0) {
1712                 UDCCS0 = UDCCS0_FST|UDCCS0_FTF;
1713                 DBG(DBG_VERBOSE, "ep0 re-stall\n");
1714                 start_watchdog(dev);
1715         }
1716         local_irq_enable();
1717 }
1718
1719 static void handle_ep0 (struct pxa2xx_udc *dev)
1720 {
1721         u32                     udccs0 = UDCCS0;
1722         struct pxa2xx_ep        *ep = &dev->ep [0];
1723         struct pxa2xx_request   *req;
1724         union {
1725                 struct usb_ctrlrequest  r;
1726                 u8                      raw [8];
1727                 u32                     word [2];
1728         } u;
1729
1730         if (list_empty(&ep->queue))
1731                 req = 0;
1732         else
1733                 req = list_entry(ep->queue.next, struct pxa2xx_request, queue);
1734
1735         /* clear stall status */
1736         if (udccs0 & UDCCS0_SST) {
1737                 nuke(ep, -EPIPE);
1738                 UDCCS0 = UDCCS0_SST;
1739                 del_timer(&dev->timer);
1740                 ep0_idle(dev);
1741         }
1742
1743         /* previous request unfinished?  non-error iff back-to-back ... */
1744         if ((udccs0 & UDCCS0_SA) != 0 && dev->ep0state != EP0_IDLE) {
1745                 nuke(ep, 0);
1746                 del_timer(&dev->timer);
1747                 ep0_idle(dev);
1748         }
1749
1750         switch (dev->ep0state) {
1751         case EP0_IDLE:
1752                 /* late-breaking status? */
1753                 udccs0 = UDCCS0;
1754
1755                 /* start control request? */
1756                 if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))
1757                                 == (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))) {
1758                         int i;
1759
1760                         nuke (ep, -EPROTO);
1761
1762                         /* read SETUP packet */
1763                         for (i = 0; i < 8; i++) {
1764                                 if (unlikely(!(UDCCS0 & UDCCS0_RNE))) {
1765 bad_setup:
1766                                         DMSG("SETUP %d!\n", i);
1767                                         goto stall;
1768                                 }
1769                                 u.raw [i] = (u8) UDDR0;
1770                         }
1771                         if (unlikely((UDCCS0 & UDCCS0_RNE) != 0))
1772                                 goto bad_setup;
1773
1774 got_setup:
1775                         le16_to_cpus (&u.r.wValue);
1776                         le16_to_cpus (&u.r.wIndex);
1777                         le16_to_cpus (&u.r.wLength);
1778
1779                         LED_EP0_ON;
1780                         DBG(DBG_VERBOSE, "SETUP %02x.%02x v%04x i%04x l%04x\n",
1781                                 u.r.bRequestType, u.r.bRequest,
1782                                 u.r.wValue, u.r.wIndex, u.r.wLength);
1783
1784                         /* cope with automagic for some standard requests. */
1785                         dev->req_std = (u.r.bRequestType & USB_TYPE_MASK)
1786                                                 == USB_TYPE_STANDARD;
1787                         dev->req_config = 0;
1788                         dev->req_pending = 1;
1789                         switch (u.r.bRequest) {
1790                         /* hardware restricts gadget drivers here! */
1791                         case USB_REQ_SET_CONFIGURATION:
1792                                 if (u.r.bRequestType == USB_RECIP_DEVICE) {
1793                                         /* reflect hardware's automagic
1794                                          * up to the gadget driver.
1795                                          */
1796 config_change:
1797                                         dev->req_config = 1;
1798                                         clear_ep_state(dev);
1799                                         /* if !has_cfr, there's no synch
1800                                          * else use AREN (later) not SA|OPR
1801                                          * USIR0_IR0 acts edge sensitive
1802                                          */
1803                                 }
1804                                 break;
1805                         /* ... and here, even more ... */
1806                         case USB_REQ_SET_INTERFACE:
1807                                 if (u.r.bRequestType == USB_RECIP_INTERFACE) {
1808                                         /* udc hardware is broken by design:
1809                                          *  - altsetting may only be zero;
1810                                          *  - hw resets all interfaces' eps;
1811                                          *  - ep reset doesn't include halt(?).
1812                                          */
1813                                         DMSG("broken set_interface (%d/%d)\n",
1814                                                 u.r.wIndex, u.r.wValue);
1815                                         goto config_change;
1816                                 }
1817                                 break;
1818                         /* hardware was supposed to hide this */
1819                         case USB_REQ_SET_ADDRESS:
1820                                 if (u.r.bRequestType == USB_RECIP_DEVICE) {
1821                                         ep0start(dev, 0, "address");
1822                                         return;
1823                                 }
1824                                 break;
1825                         }
1826
1827                         if (u.r.bRequestType & USB_DIR_IN)
1828                                 dev->ep0state = EP0_IN_DATA_PHASE;
1829                         else
1830                                 dev->ep0state = EP0_OUT_DATA_PHASE;
1831
1832                         i = dev->driver->setup(&dev->gadget, &u.r);
1833                         if (i < 0) {
1834                                 /* hardware automagic preventing STALL... */
1835                                 if (dev->req_config) {
1836                                         /* hardware sometimes neglects to tell
1837                                          * tell us about config change events,
1838                                          * so later ones may fail...
1839                                          */
1840                                         WARN("config change %02x fail %d?\n",
1841                                                 u.r.bRequest, i);
1842                                         return;
1843                                         /* TODO experiment:  if has_cfr,
1844                                          * hardware didn't ACK; maybe we
1845                                          * could actually STALL!
1846                                          */
1847                                 }
1848                                 DBG(DBG_VERBOSE, "protocol STALL, "
1849                                         "%02x err %d\n", UDCCS0, i);
1850 stall:
1851                                 /* the watchdog timer helps deal with cases
1852                                  * where udc seems to clear FST wrongly, and
1853                                  * then NAKs instead of STALLing.
1854                                  */
1855                                 ep0start(dev, UDCCS0_FST|UDCCS0_FTF, "stall");
1856                                 start_watchdog(dev);
1857                                 dev->ep0state = EP0_STALL;
1858                                 LED_EP0_OFF;
1859
1860                         /* deferred i/o == no response yet */
1861                         } else if (dev->req_pending) {
1862                                 if (likely(dev->ep0state == EP0_IN_DATA_PHASE
1863                                                 || dev->req_std || u.r.wLength))
1864                                         ep0start(dev, 0, "defer");
1865                                 else
1866                                         ep0start(dev, UDCCS0_IPR, "defer/IPR");
1867                         }
1868
1869                         /* expect at least one data or status stage irq */
1870                         return;
1871
1872                 } else if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA))
1873                                 == (UDCCS0_OPR|UDCCS0_SA))) {
1874                         unsigned i;
1875
1876                         /* pxa210/250 erratum 131 for B0/B1 says RNE lies.
1877                          * still observed on a pxa255 a0.
1878                          */
1879                         DBG(DBG_VERBOSE, "e131\n");
1880                         nuke(ep, -EPROTO);
1881
1882                         /* read SETUP data, but don't trust it too much */
1883                         for (i = 0; i < 8; i++)
1884                                 u.raw [i] = (u8) UDDR0;
1885                         if ((u.r.bRequestType & USB_RECIP_MASK)
1886                                         > USB_RECIP_OTHER)
1887                                 goto stall;
1888                         if (u.word [0] == 0 && u.word [1] == 0)
1889                                 goto stall;
1890                         goto got_setup;
1891                 } else {
1892                         /* some random early IRQ:
1893                          * - we acked FST
1894                          * - IPR cleared
1895                          * - OPR got set, without SA (likely status stage)
1896                          */
1897                         UDCCS0 = udccs0 & (UDCCS0_SA|UDCCS0_OPR);
1898                 }
1899                 break;
1900         case EP0_IN_DATA_PHASE:                 /* GET_DESCRIPTOR etc */
1901                 if (udccs0 & UDCCS0_OPR) {
1902                         UDCCS0 = UDCCS0_OPR|UDCCS0_FTF;
1903                         DBG(DBG_VERBOSE, "ep0in premature status\n");
1904                         if (req)
1905                                 done(ep, req, 0);
1906                         ep0_idle(dev);
1907                 } else /* irq was IPR clearing */ {
1908                         if (req) {
1909                                 /* this IN packet might finish the request */
1910                                 (void) write_ep0_fifo(ep, req);
1911                         } /* else IN token before response was written */
1912                 }
1913                 break;
1914         case EP0_OUT_DATA_PHASE:                /* SET_DESCRIPTOR etc */
1915                 if (udccs0 & UDCCS0_OPR) {
1916                         if (req) {
1917                                 /* this OUT packet might finish the request */
1918                                 if (read_ep0_fifo(ep, req))
1919                                         done(ep, req, 0);
1920                                 /* else more OUT packets expected */
1921                         } /* else OUT token before read was issued */
1922                 } else /* irq was IPR clearing */ {
1923                         DBG(DBG_VERBOSE, "ep0out premature status\n");
1924                         if (req)
1925                                 done(ep, req, 0);
1926                         ep0_idle(dev);
1927                 }
1928                 break;
1929         case EP0_END_XFER:
1930                 if (req)
1931                         done(ep, req, 0);
1932                 /* ack control-IN status (maybe in-zlp was skipped)
1933                  * also appears after some config change events.
1934                  */
1935                 if (udccs0 & UDCCS0_OPR)
1936                         UDCCS0 = UDCCS0_OPR;
1937                 ep0_idle(dev);
1938                 break;
1939         case EP0_STALL:
1940                 UDCCS0 = UDCCS0_FST;
1941                 break;
1942         }
1943         USIR0 = USIR0_IR0;
1944 }
1945
1946 static void handle_ep(struct pxa2xx_ep *ep)
1947 {
1948         struct pxa2xx_request   *req;
1949         int                     is_in = ep->bEndpointAddress & USB_DIR_IN;
1950         int                     completed;
1951         u32                     udccs, tmp;
1952
1953         do {
1954                 completed = 0;
1955                 if (likely (!list_empty(&ep->queue)))
1956                         req = list_entry(ep->queue.next,
1957                                         struct pxa2xx_request, queue);
1958                 else
1959                         req = 0;
1960
1961                 // TODO check FST handling
1962
1963                 udccs = *ep->reg_udccs;
1964                 if (unlikely(is_in)) {  /* irq from TPC, SST, or (ISO) TUR */
1965                         tmp = UDCCS_BI_TUR;
1966                         if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK))
1967                                 tmp |= UDCCS_BI_SST;
1968                         tmp &= udccs;
1969                         if (likely (tmp))
1970                                 *ep->reg_udccs = tmp;
1971                         if (req && likely ((udccs & UDCCS_BI_TFS) != 0))
1972                                 completed = write_fifo(ep, req);
1973
1974                 } else {        /* irq from RPC (or for ISO, ROF) */
1975                         if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK))
1976                                 tmp = UDCCS_BO_SST | UDCCS_BO_DME;
1977                         else
1978                                 tmp = UDCCS_IO_ROF | UDCCS_IO_DME;
1979                         tmp &= udccs;
1980                         if (likely(tmp))
1981                                 *ep->reg_udccs = tmp;
1982
1983                         /* fifos can hold packets, ready for reading... */
1984                         if (likely(req)) {
1985 #ifdef USE_OUT_DMA
1986 // TODO didn't yet debug out-dma.  this approach assumes
1987 // the worst about short packets and RPC; it might be better.
1988
1989                                 if (likely(ep->dma >= 0)) {
1990                                         if (!(udccs & UDCCS_BO_RSP)) {
1991                                                 *ep->reg_udccs = UDCCS_BO_RPC;
1992                                                 ep->dma_irqs++;
1993                                                 return;
1994                                         }
1995                                 }
1996 #endif
1997                                 completed = read_fifo(ep, req);
1998                         } else
1999                                 pio_irq_disable (ep->bEndpointAddress);
2000                 }
2001                 ep->pio_irqs++;
2002         } while (completed);
2003 }
2004
2005 /*
2006  *      pxa2xx_udc_irq - interrupt handler
2007  *
2008  * avoid delays in ep0 processing. the control handshaking isn't always
2009  * under software control (pxa250c0 and the pxa255 are better), and delays
2010  * could cause usb protocol errors.
2011  */
2012 static irqreturn_t
2013 pxa2xx_udc_irq(int irq, void *_dev, struct pt_regs *r)
2014 {
2015         struct pxa2xx_udc       *dev = _dev;
2016         int                     handled;
2017
2018         dev->stats.irqs++;
2019         HEX_DISPLAY(dev->stats.irqs);
2020         do {
2021                 u32             udccr = UDCCR;
2022
2023                 handled = 0;
2024
2025                 /* SUSpend Interrupt Request */
2026                 if (unlikely(udccr & UDCCR_SUSIR)) {
2027                         udc_ack_int_UDCCR(UDCCR_SUSIR);
2028                         handled = 1;
2029                         DBG(DBG_VERBOSE, "USB suspend%s\n", is_usb_connected()
2030                                 ? "" : "+disconnect");
2031
2032                         if (!is_usb_connected())
2033                                 stop_activity(dev, dev->driver);
2034                         else if (dev->gadget.speed != USB_SPEED_UNKNOWN
2035                                         && dev->driver
2036                                         && dev->driver->suspend)
2037                                 dev->driver->suspend(&dev->gadget);
2038                         ep0_idle (dev);
2039                 }
2040
2041                 /* RESume Interrupt Request */
2042                 if (unlikely(udccr & UDCCR_RESIR)) {
2043                         udc_ack_int_UDCCR(UDCCR_RESIR);
2044                         handled = 1;
2045                         DBG(DBG_VERBOSE, "USB resume\n");
2046
2047                         if (dev->gadget.speed != USB_SPEED_UNKNOWN
2048                                         && dev->driver
2049                                         && dev->driver->resume
2050                                         && is_usb_connected())
2051                                 dev->driver->resume(&dev->gadget);
2052                 }
2053
2054                 /* ReSeT Interrupt Request - USB reset */
2055                 if (unlikely(udccr & UDCCR_RSTIR)) {
2056                         udc_ack_int_UDCCR(UDCCR_RSTIR);
2057                         handled = 1;
2058
2059                         if ((UDCCR & UDCCR_UDA) == 0) {
2060                                 DBG(DBG_VERBOSE, "USB reset start\n");
2061                                 if (dev->gadget.speed != USB_SPEED_UNKNOWN)
2062                                         disable_disconnect_irq();
2063
2064                                 /* reset driver and endpoints,
2065                                  * in case that's not yet done
2066                                  */
2067                                 stop_activity (dev, dev->driver);
2068
2069                         } else {
2070                                 INFO("USB reset\n");
2071                                 dev->gadget.speed = USB_SPEED_FULL;
2072                                 LED_CONNECTED_ON;
2073                                 memset(&dev->stats, 0, sizeof dev->stats);
2074                                 /* driver and endpoints are still reset */
2075                                 enable_disconnect_irq();
2076                         }
2077
2078                 } else {
2079                         u32     usir0 = USIR0 & ~UICR0;
2080                         u32     usir1 = USIR1 & ~UICR1;
2081                         int     i;
2082
2083                         if (unlikely (!usir0 && !usir1))
2084                                 continue;
2085
2086                         DBG(DBG_VERY_NOISY, "irq %02x.%02x\n", usir1, usir0);
2087
2088                         /* control traffic */
2089                         if (usir0 & USIR0_IR0) {
2090                                 dev->ep[0].pio_irqs++;
2091                                 handle_ep0(dev);
2092                                 handled = 1;
2093                         }
2094
2095                         /* endpoint data transfers */
2096                         for (i = 0; i < 8; i++) {
2097                                 u32     tmp = 1 << i;
2098
2099                                 if (i && (usir0 & tmp)) {
2100                                         handle_ep(&dev->ep[i]);
2101                                         USIR0 |= tmp;
2102                                         handled = 1;
2103                                 }
2104                                 if (usir1 & tmp) {
2105                                         handle_ep(&dev->ep[i+8]);
2106                                         USIR1 |= tmp;
2107                                         handled = 1;
2108                                 }
2109                         }
2110                 }
2111
2112                 /* we could also ask for 1 msec SOF (SIR) interrupts */
2113
2114         } while (handled);
2115         return IRQ_HANDLED;
2116 }
2117
2118 /*-------------------------------------------------------------------------*/
2119
2120 static void nop_release (struct device *dev)
2121 {
2122         DMSG("%s %s\n", __FUNCTION__, dev->bus_id);
2123 }
2124
2125 /* this uses load-time allocation and initialization (instead of
2126  * doing it at run-time) to save code, eliminate fault paths, and
2127  * be more obviously correct.
2128  */
2129 static struct pxa2xx_udc memory = {
2130         .gadget = {
2131                 .ops            = &pxa2xx_udc_ops,
2132                 .ep0            = &memory.ep[0].ep,
2133                 .name           = driver_name,
2134                 .dev = {
2135                         .bus_id         = "gadget",
2136                         .release        = nop_release,
2137                 },
2138         },
2139
2140         /* control endpoint */
2141         .ep[0] = {
2142                 .ep = {
2143                         .name           = ep0name,
2144                         .ops            = &pxa2xx_ep_ops,
2145                         .maxpacket      = EP0_FIFO_SIZE,
2146                 },
2147                 .dev            = &memory,
2148                 .reg_udccs      = &UDCCS0,
2149                 .reg_uddr       = &UDDR0,
2150         },
2151
2152         /* first group of endpoints */
2153         .ep[1] = {
2154                 .ep = {
2155                         .name           = "ep1in-bulk",
2156                         .ops            = &pxa2xx_ep_ops,
2157                         .maxpacket      = BULK_FIFO_SIZE,
2158                 },
2159                 .dev            = &memory,
2160                 .fifo_size      = BULK_FIFO_SIZE,
2161                 .bEndpointAddress = USB_DIR_IN | 1,
2162                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
2163                 .reg_udccs      = &UDCCS1,
2164                 .reg_uddr       = &UDDR1,
2165                 drcmr (25)
2166         },
2167         .ep[2] = {
2168                 .ep = {
2169                         .name           = "ep2out-bulk",
2170                         .ops            = &pxa2xx_ep_ops,
2171                         .maxpacket      = BULK_FIFO_SIZE,
2172                 },
2173                 .dev            = &memory,
2174                 .fifo_size      = BULK_FIFO_SIZE,
2175                 .bEndpointAddress = 2,
2176                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
2177                 .reg_udccs      = &UDCCS2,
2178                 .reg_ubcr       = &UBCR2,
2179                 .reg_uddr       = &UDDR2,
2180                 drcmr (26)
2181         },
2182 #ifndef CONFIG_USB_PXA2XX_SMALL
2183         .ep[3] = {
2184                 .ep = {
2185                         .name           = "ep3in-iso",
2186                         .ops            = &pxa2xx_ep_ops,
2187                         .maxpacket      = ISO_FIFO_SIZE,
2188                 },
2189                 .dev            = &memory,
2190                 .fifo_size      = ISO_FIFO_SIZE,
2191                 .bEndpointAddress = USB_DIR_IN | 3,
2192                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
2193                 .reg_udccs      = &UDCCS3,
2194                 .reg_uddr       = &UDDR3,
2195                 drcmr (27)
2196         },
2197         .ep[4] = {
2198                 .ep = {
2199                         .name           = "ep4out-iso",
2200                         .ops            = &pxa2xx_ep_ops,
2201                         .maxpacket      = ISO_FIFO_SIZE,
2202                 },
2203                 .dev            = &memory,
2204                 .fifo_size      = ISO_FIFO_SIZE,
2205                 .bEndpointAddress = 4,
2206                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
2207                 .reg_udccs      = &UDCCS4,
2208                 .reg_ubcr       = &UBCR4,
2209                 .reg_uddr       = &UDDR4,
2210                 drcmr (28)
2211         },
2212         .ep[5] = {
2213                 .ep = {
2214                         .name           = "ep5in-int",
2215                         .ops            = &pxa2xx_ep_ops,
2216                         .maxpacket      = INT_FIFO_SIZE,
2217                 },
2218                 .dev            = &memory,
2219                 .fifo_size      = INT_FIFO_SIZE,
2220                 .bEndpointAddress = USB_DIR_IN | 5,
2221                 .bmAttributes   = USB_ENDPOINT_XFER_INT,
2222                 .reg_udccs      = &UDCCS5,
2223                 .reg_uddr       = &UDDR5,
2224         },
2225
2226         /* second group of endpoints */
2227         .ep[6] = {
2228                 .ep = {
2229                         .name           = "ep6in-bulk",
2230                         .ops            = &pxa2xx_ep_ops,
2231                         .maxpacket      = BULK_FIFO_SIZE,
2232                 },
2233                 .dev            = &memory,
2234                 .fifo_size      = BULK_FIFO_SIZE,
2235                 .bEndpointAddress = USB_DIR_IN | 6,
2236                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
2237                 .reg_udccs      = &UDCCS6,
2238                 .reg_uddr       = &UDDR6,
2239                 drcmr (30)
2240         },
2241         .ep[7] = {
2242                 .ep = {
2243                         .name           = "ep7out-bulk",
2244                         .ops            = &pxa2xx_ep_ops,
2245                         .maxpacket      = BULK_FIFO_SIZE,
2246                 },
2247                 .dev            = &memory,
2248                 .fifo_size      = BULK_FIFO_SIZE,
2249                 .bEndpointAddress = 7,
2250                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
2251                 .reg_udccs      = &UDCCS7,
2252                 .reg_ubcr       = &UBCR7,
2253                 .reg_uddr       = &UDDR7,
2254                 drcmr (31)
2255         },
2256         .ep[8] = {
2257                 .ep = {
2258                         .name           = "ep8in-iso",
2259                         .ops            = &pxa2xx_ep_ops,
2260                         .maxpacket      = ISO_FIFO_SIZE,
2261                 },
2262                 .dev            = &memory,
2263                 .fifo_size      = ISO_FIFO_SIZE,
2264                 .bEndpointAddress = USB_DIR_IN | 8,
2265                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
2266                 .reg_udccs      = &UDCCS8,
2267                 .reg_uddr       = &UDDR8,
2268                 drcmr (32)
2269         },
2270         .ep[9] = {
2271                 .ep = {
2272                         .name           = "ep9out-iso",
2273                         .ops            = &pxa2xx_ep_ops,
2274                         .maxpacket      = ISO_FIFO_SIZE,
2275                 },
2276                 .dev            = &memory,
2277                 .fifo_size      = ISO_FIFO_SIZE,
2278                 .bEndpointAddress = 9,
2279                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
2280                 .reg_udccs      = &UDCCS9,
2281                 .reg_ubcr       = &UBCR9,
2282                 .reg_uddr       = &UDDR9,
2283                 drcmr (33)
2284         },
2285         .ep[10] = {
2286                 .ep = {
2287                         .name           = "ep10in-int",
2288                         .ops            = &pxa2xx_ep_ops,
2289                         .maxpacket      = INT_FIFO_SIZE,
2290                 },
2291                 .dev            = &memory,
2292                 .fifo_size      = INT_FIFO_SIZE,
2293                 .bEndpointAddress = USB_DIR_IN | 10,
2294                 .bmAttributes   = USB_ENDPOINT_XFER_INT,
2295                 .reg_udccs      = &UDCCS10,
2296                 .reg_uddr       = &UDDR10,
2297         },
2298
2299         /* third group of endpoints */
2300         .ep[11] = {
2301                 .ep = {
2302                         .name           = "ep11in-bulk",
2303                         .ops            = &pxa2xx_ep_ops,
2304                         .maxpacket      = BULK_FIFO_SIZE,
2305                 },
2306                 .dev            = &memory,
2307                 .fifo_size      = BULK_FIFO_SIZE,
2308                 .bEndpointAddress = USB_DIR_IN | 11,
2309                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
2310                 .reg_udccs      = &UDCCS11,
2311                 .reg_uddr       = &UDDR11,
2312                 drcmr (35)
2313         },
2314         .ep[12] = {
2315                 .ep = {
2316                         .name           = "ep12out-bulk",
2317                         .ops            = &pxa2xx_ep_ops,
2318                         .maxpacket      = BULK_FIFO_SIZE,
2319                 },
2320                 .dev            = &memory,
2321                 .fifo_size      = BULK_FIFO_SIZE,
2322                 .bEndpointAddress = 12,
2323                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
2324                 .reg_udccs      = &UDCCS12,
2325                 .reg_ubcr       = &UBCR12,
2326                 .reg_uddr       = &UDDR12,
2327                 drcmr (36)
2328         },
2329         .ep[13] = {
2330                 .ep = {
2331                         .name           = "ep13in-iso",
2332                         .ops            = &pxa2xx_ep_ops,
2333                         .maxpacket      = ISO_FIFO_SIZE,
2334                 },
2335                 .dev            = &memory,
2336                 .fifo_size      = ISO_FIFO_SIZE,
2337                 .bEndpointAddress = USB_DIR_IN | 13,
2338                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
2339                 .reg_udccs      = &UDCCS13,
2340                 .reg_uddr       = &UDDR13,
2341                 drcmr (37)
2342         },
2343         .ep[14] = {
2344                 .ep = {
2345                         .name           = "ep14out-iso",
2346                         .ops            = &pxa2xx_ep_ops,
2347                         .maxpacket      = ISO_FIFO_SIZE,
2348                 },
2349                 .dev            = &memory,
2350                 .fifo_size      = ISO_FIFO_SIZE,
2351                 .bEndpointAddress = 14,
2352                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
2353                 .reg_udccs      = &UDCCS14,
2354                 .reg_ubcr       = &UBCR14,
2355                 .reg_uddr       = &UDDR14,
2356                 drcmr (38)
2357         },
2358         .ep[15] = {
2359                 .ep = {
2360                         .name           = "ep15in-int",
2361                         .ops            = &pxa2xx_ep_ops,
2362                         .maxpacket      = INT_FIFO_SIZE,
2363                 },
2364                 .dev            = &memory,
2365                 .fifo_size      = INT_FIFO_SIZE,
2366                 .bEndpointAddress = USB_DIR_IN | 15,
2367                 .bmAttributes   = USB_ENDPOINT_XFER_INT,
2368                 .reg_udccs      = &UDCCS15,
2369                 .reg_uddr       = &UDDR15,
2370         },
2371 #endif /* !CONFIG_USB_PXA2XX_SMALL */
2372 };
2373
2374 #define CP15R0_VENDOR_MASK      0xffffe000
2375
2376 #if     defined(CONFIG_ARCH_PXA)
2377 #define CP15R0_XSCALE_VALUE     0x69052000      /* intel/arm/xscale */
2378
2379 #elif   defined(CONFIG_ARCH_IXP4XX)
2380 #define CP15R0_XSCALE_VALUE     0x69054000      /* intel/arm/ixp4xx */
2381
2382 #endif
2383
2384 #define CP15R0_PROD_MASK        0x000003f0
2385 #define PXA25x                  0x00000100      /* and PXA26x */
2386 #define PXA210                  0x00000120
2387
2388 #define CP15R0_REV_MASK         0x0000000f
2389
2390 #define CP15R0_PRODREV_MASK     (CP15R0_PROD_MASK | CP15R0_REV_MASK)
2391
2392 #define PXA255_A0               0x00000106      /* or PXA260_B1 */
2393 #define PXA250_C0               0x00000105      /* or PXA26x_B0 */
2394 #define PXA250_B2               0x00000104
2395 #define PXA250_B1               0x00000103      /* or PXA260_A0 */
2396 #define PXA250_B0               0x00000102
2397 #define PXA250_A1               0x00000101
2398 #define PXA250_A0               0x00000100
2399
2400 #define PXA210_C0               0x00000125
2401 #define PXA210_B2               0x00000124
2402 #define PXA210_B1               0x00000123
2403 #define PXA210_B0               0x00000122
2404 #define IXP425_A0               0x000001c1
2405
2406 /*
2407  *      probe - binds to the platform device
2408  */
2409 static int __init pxa2xx_udc_probe(struct device *_dev)
2410 {
2411         struct pxa2xx_udc *dev = &memory;
2412         int retval, out_dma = 1;
2413         u32 chiprev;
2414
2415         /* insist on Intel/ARM/XScale */
2416         asm("mrc%? p15, 0, %0, c0, c0" : "=r" (chiprev));
2417         if ((chiprev & CP15R0_VENDOR_MASK) != CP15R0_XSCALE_VALUE) {
2418                 printk(KERN_ERR "%s: not XScale!\n", driver_name);
2419                 return -ENODEV;
2420         }
2421
2422         /* trigger chiprev-specific logic */
2423         switch (chiprev & CP15R0_PRODREV_MASK) {
2424 #if     defined(CONFIG_ARCH_PXA)
2425         case PXA255_A0:
2426                 dev->has_cfr = 1;
2427                 break;
2428         case PXA250_A0:
2429         case PXA250_A1:
2430                 /* A0/A1 "not released"; ep 13, 15 unusable */
2431                 /* fall through */
2432         case PXA250_B2: case PXA210_B2:
2433         case PXA250_B1: case PXA210_B1:
2434         case PXA250_B0: case PXA210_B0:
2435                 out_dma = 0;
2436                 /* fall through */
2437         case PXA250_C0: case PXA210_C0:
2438                 break;
2439 #elif   defined(CONFIG_ARCH_IXP4XX)
2440         case IXP425_A0:
2441                 out_dma = 0;
2442                 break;
2443 #endif
2444         default:
2445                 out_dma = 0;
2446                 printk(KERN_ERR "%s: unrecognized processor: %08x\n",
2447                         driver_name, chiprev);
2448                 /* iop3xx, ixp4xx, ... */
2449                 return -ENODEV;
2450         }
2451
2452         pr_debug("%s: IRQ %d%s%s%s\n", driver_name, IRQ_USB,
2453                 dev->has_cfr ? "" : " (!cfr)",
2454                 out_dma ? "" : " (broken dma-out)",
2455                 SIZE_STR DMASTR
2456                 );
2457
2458 #ifdef  USE_DMA
2459 #ifndef USE_OUT_DMA
2460         out_dma = 0;
2461 #endif
2462         /* pxa 250 erratum 130 prevents using OUT dma (fixed C0) */
2463         if (!out_dma) {
2464                 DMSG("disabled OUT dma\n");
2465                 dev->ep[ 2].reg_drcmr = dev->ep[ 4].reg_drcmr = 0;
2466                 dev->ep[ 7].reg_drcmr = dev->ep[ 9].reg_drcmr = 0;
2467                 dev->ep[12].reg_drcmr = dev->ep[14].reg_drcmr = 0;
2468         }
2469 #endif
2470
2471         /* other non-static parts of init */
2472         dev->dev = _dev;
2473         dev->mach = _dev->platform_data;
2474
2475         init_timer(&dev->timer);
2476         dev->timer.function = udc_watchdog;
2477         dev->timer.data = (unsigned long) dev;
2478
2479         device_initialize(&dev->gadget.dev);
2480         dev->gadget.dev.parent = _dev;
2481         dev->gadget.dev.dma_mask = _dev->dma_mask;
2482
2483         the_controller = dev;
2484         dev_set_drvdata(_dev, dev);
2485
2486         udc_disable(dev);
2487         udc_reinit(dev);
2488
2489         /* irq setup after old hardware state is cleaned up */
2490         retval = request_irq(IRQ_USB, pxa2xx_udc_irq,
2491                         SA_INTERRUPT, driver_name, dev);
2492         if (retval != 0) {
2493                 printk(KERN_ERR "%s: can't get irq %i, err %d\n",
2494                         driver_name, IRQ_USB, retval);
2495                 return -EBUSY;
2496         }
2497         dev->got_irq = 1;
2498
2499 #ifdef CONFIG_ARCH_LUBBOCK
2500         if (machine_is_lubbock()) {
2501                 disable_irq(LUBBOCK_USB_DISC_IRQ);
2502                 retval = request_irq(LUBBOCK_USB_DISC_IRQ,
2503                                 usb_connection_irq,
2504                                 SA_INTERRUPT /* OOPSING | SA_SAMPLE_RANDOM */,
2505                                 driver_name, dev);
2506                 if (retval != 0) {
2507                         enable_irq(LUBBOCK_USB_DISC_IRQ);
2508                         printk(KERN_ERR "%s: can't get irq %i, err %d\n",
2509                                 driver_name, LUBBOCK_USB_DISC_IRQ, retval);
2510                         return -EBUSY;
2511                 }
2512                 dev->got_disc = 1;
2513         }
2514 #endif
2515         create_proc_files();
2516
2517         return 0;
2518 }
2519 static int __exit pxa2xx_udc_remove(struct device *_dev)
2520 {
2521         struct pxa2xx_udc *dev = _dev->driver_data;
2522
2523         udc_disable(dev);
2524         remove_proc_files();
2525         usb_gadget_unregister_driver(dev->driver);
2526
2527         if (dev->got_irq) {
2528                 free_irq(IRQ_USB, dev);
2529                 dev->got_irq = 0;
2530         }
2531         if (machine_is_lubbock() && dev->got_disc) {
2532                 free_irq(LUBBOCK_USB_DISC_IRQ, dev);
2533                 dev->got_disc = 0;
2534         }
2535         dev_set_drvdata(_dev, 0);
2536         the_controller = 0;
2537         return 0;
2538 }
2539
2540 /*-------------------------------------------------------------------------*/
2541
2542 static struct device_driver udc_driver = {
2543         .name           = "pxa2xx-udc",
2544         .bus            = &platform_bus_type,
2545         .probe          = pxa2xx_udc_probe,
2546         .remove         = __exit_p(pxa2xx_udc_remove),
2547
2548         // FIXME power management support
2549         // .suspend = ... disable UDC
2550         // .resume = ... re-enable UDC
2551 };
2552
2553 static int __init udc_init(void)
2554 {
2555         printk(KERN_INFO "%s: version %s\n", driver_name, DRIVER_VERSION);
2556         return driver_register(&udc_driver);
2557 }
2558 module_init(udc_init);
2559
2560 static void __exit udc_exit(void)
2561 {
2562         driver_unregister(&udc_driver);
2563 }
2564 module_exit(udc_exit);
2565
2566 MODULE_DESCRIPTION(DRIVER_DESC);
2567 MODULE_AUTHOR("Frank Becker, Robert Schwebel, David Brownell");
2568 MODULE_LICENSE("GPL");
2569