2 * OHCI HCD (Host Controller Driver) for USB.
4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
5 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
7 * This file is licenced under the GPL.
11 * OHCI Endpoint Descriptor (ED) ... holds TD queue
12 * See OHCI spec, section 4.2
14 * This is a "Queue Head" for those transfers, which is why
15 * both EHCI and UHCI call similar structures a "QH".
18 /* first fields are hardware-specified, le32 */
19 __u32 hwINFO; /* endpoint config bitmap */
20 /* info bits defined by hcd */
21 #define ED_DEQUEUE __constant_cpu_to_le32(1 << 27)
22 /* info bits defined by the hardware */
23 #define ED_ISO __constant_cpu_to_le32(1 << 15)
24 #define ED_SKIP __constant_cpu_to_le32(1 << 14)
25 #define ED_LOWSPEED __constant_cpu_to_le32(1 << 13)
26 #define ED_OUT __constant_cpu_to_le32(0x01 << 11)
27 #define ED_IN __constant_cpu_to_le32(0x02 << 11)
28 __u32 hwTailP; /* tail of TD list */
29 __u32 hwHeadP; /* head of TD list (hc r/w) */
30 #define ED_C __constant_cpu_to_le32(0x02) /* toggle carry */
31 #define ED_H __constant_cpu_to_le32(0x01) /* halted */
32 __u32 hwNextED; /* next ED in list */
34 /* rest are purely for the driver's use */
35 dma_addr_t dma; /* addr of ED */
36 struct td *dummy; /* next TD to activate */
38 /* host's view of schedule */
39 struct ed *ed_next; /* on schedule or rm_list */
40 struct ed *ed_prev; /* for non-interrupt EDs */
41 struct list_head td_list; /* "shadow list" of our TDs */
43 /* create --> IDLE --> OPER --> ... --> IDLE --> destroy
44 * usually: OPER --> UNLINK --> (IDLE | OPER) --> ...
45 * some special cases : OPER --> IDLE ...
47 u8 state; /* ED_{IDLE,UNLINK,OPER} */
48 #define ED_IDLE 0x00 /* NOT linked to HC */
49 #define ED_UNLINK 0x01 /* being unlinked from hc */
50 #define ED_OPER 0x02 /* IS linked to hc */
52 u8 type; /* PIPE_{BULK,...} */
54 /* periodic scheduling params (for intr and iso) */
58 u16 last_iso; /* iso only */
60 /* HC may see EDs on rm_list until next frame (frame_no == tick) */
62 } __attribute__ ((aligned(16)));
64 #define ED_MASK ((u32)~0x0f) /* strip hw status in low addr bits */
68 * OHCI Transfer Descriptor (TD) ... one per transfer segment
69 * See OHCI spec, sections 4.3.1 (general = control/bulk/interrupt)
73 /* first fields are hardware-specified, le32 */
74 __u32 hwINFO; /* transfer info bitmask */
76 /* hwINFO bits for both general and iso tds: */
77 #define TD_CC 0xf0000000 /* condition code */
78 #define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
79 //#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
80 #define TD_DI 0x00E00000 /* frames before interrupt */
81 #define TD_DI_SET(X) (((X) & 0x07)<< 21)
82 /* these two bits are available for definition/use by HCDs in both
83 * general and iso tds ... others are available for only one type
85 #define TD_DONE 0x00020000 /* retired to donelist */
86 #define TD_ISO 0x00010000 /* copy of ED_ISO */
88 /* hwINFO bits for general tds: */
89 #define TD_EC 0x0C000000 /* error count */
90 #define TD_T 0x03000000 /* data toggle state */
91 #define TD_T_DATA0 0x02000000 /* DATA0 */
92 #define TD_T_DATA1 0x03000000 /* DATA1 */
93 #define TD_T_TOGGLE 0x00000000 /* uses ED_C */
94 #define TD_DP 0x00180000 /* direction/pid */
95 #define TD_DP_SETUP 0x00000000 /* SETUP pid */
96 #define TD_DP_IN 0x00100000 /* IN pid */
97 #define TD_DP_OUT 0x00080000 /* OUT pid */
99 #define TD_R 0x00040000 /* round: short packets OK? */
101 /* (no hwINFO #defines yet for iso tds) */
103 __u32 hwCBP; /* Current Buffer Pointer (or 0) */
104 __u32 hwNextTD; /* Next TD Pointer */
105 __u32 hwBE; /* Memory Buffer End Pointer */
107 /* PSW is only for ISO */
108 #define MAXPSW 1 /* hardware allows 8 */
109 __u16 hwPSW [MAXPSW];
111 /* rest are purely for the driver's use */
114 struct td *td_hash; /* dma-->td hashtable */
115 struct td *next_dl_td;
118 dma_addr_t td_dma; /* addr of this TD */
119 dma_addr_t data_dma; /* addr of data it points to */
121 struct list_head td_list; /* "shadow list", TDs on same ED */
122 } __attribute__ ((aligned(32))); /* c/b/i need 16; only iso needs 32 */
124 #define TD_MASK ((u32)~0x1f) /* strip hw status in low addr bits */
127 * Hardware transfer status codes -- CC from td->hwINFO or td->hwPSW
129 #define TD_CC_NOERROR 0x00
130 #define TD_CC_CRC 0x01
131 #define TD_CC_BITSTUFFING 0x02
132 #define TD_CC_DATATOGGLEM 0x03
133 #define TD_CC_STALL 0x04
134 #define TD_DEVNOTRESP 0x05
135 #define TD_PIDCHECKFAIL 0x06
136 #define TD_UNEXPECTEDPID 0x07
137 #define TD_DATAOVERRUN 0x08
138 #define TD_DATAUNDERRUN 0x09
139 /* 0x0A, 0x0B reserved for hardware */
140 #define TD_BUFFEROVERRUN 0x0C
141 #define TD_BUFFERUNDERRUN 0x0D
142 /* 0x0E, 0x0F reserved for HCD */
143 #define TD_NOTACCESSED 0x0F
146 /* map OHCI TD status codes (CC) to errno values */
147 static const int cc_to_error [16] = {
149 /* CRC Error */ -EILSEQ,
150 /* Bit Stuff */ -EPROTO,
151 /* Data Togg */ -EILSEQ,
153 /* DevNotResp */ -ETIMEDOUT,
154 /* PIDCheck */ -EPROTO,
155 /* UnExpPID */ -EPROTO,
156 /* DataOver */ -EOVERFLOW,
157 /* DataUnder */ -EREMOTEIO,
160 /* BufferOver */ -ECOMM,
161 /* BuffUnder */ -ENOSR,
162 /* (for HCD) */ -EALREADY,
163 /* (for HCD) */ -EALREADY
168 * The HCCA (Host Controller Communications Area) is a 256 byte
169 * structure defined section 4.4.1 of the OHCI spec. The HC is
170 * told the base address of it. It must be 256-byte aligned.
174 __u32 int_table [NUM_INTS]; /* periodic schedule */
177 * OHCI defines u16 frame_no, followed by u16 zero pad.
178 * Since some processors can't do 16 bit bus accesses,
179 * portable access must be a 32 bit byteswapped access.
181 u32 frame_no; /* current frame number */
182 #define OHCI_FRAME_NO(hccap) ((u16)le32_to_cpup(&(hccap)->frame_no))
183 __u32 done_head; /* info returned for an interrupt */
184 u8 reserved_for_hc [116];
185 u8 what [4]; /* spec only identifies 252 bytes :) */
186 } __attribute__ ((aligned(256)));
190 * This is the structure of the OHCI controller's memory mapped I/O region.
191 * You must use readl() and writel() (in <asm/io.h>) to access these fields!!
192 * Layout is in section 7 (and appendix B) of the spec.
195 /* control and status registers (section 7.1) */
203 /* memory pointers (section 7.2) */
205 __u32 ed_periodcurrent;
206 __u32 ed_controlhead;
207 __u32 ed_controlcurrent;
209 __u32 ed_bulkcurrent;
212 /* frame counters (section 7.3) */
219 /* Root hub ports (section 7.4) */
220 struct ohci_roothub_regs {
224 #define MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports (RH_A_NDP) */
225 __u32 portstatus [MAX_ROOT_PORTS];
228 /* and optional "legacy support" registers (appendix B) at 0x0100 */
230 } __attribute__ ((aligned(32)));
233 /* OHCI CONTROL AND STATUS REGISTER MASKS */
236 * HcControl (control) register masks
238 #define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */
239 #define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */
240 #define OHCI_CTRL_IE (1 << 3) /* isochronous enable */
241 #define OHCI_CTRL_CLE (1 << 4) /* control list enable */
242 #define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */
243 #define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */
244 #define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
245 #define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */
246 #define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */
248 /* pre-shifted values for HCFS */
249 # define OHCI_USB_RESET (0 << 6)
250 # define OHCI_USB_RESUME (1 << 6)
251 # define OHCI_USB_OPER (2 << 6)
252 # define OHCI_USB_SUSPEND (3 << 6)
255 * HcCommandStatus (cmdstatus) register masks
257 #define OHCI_HCR (1 << 0) /* host controller reset */
258 #define OHCI_CLF (1 << 1) /* control list filled */
259 #define OHCI_BLF (1 << 2) /* bulk list filled */
260 #define OHCI_OCR (1 << 3) /* ownership change request */
261 #define OHCI_SOC (3 << 16) /* scheduling overrun count */
264 * masks used with interrupt registers:
265 * HcInterruptStatus (intrstatus)
266 * HcInterruptEnable (intrenable)
267 * HcInterruptDisable (intrdisable)
269 #define OHCI_INTR_SO (1 << 0) /* scheduling overrun */
270 #define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */
271 #define OHCI_INTR_SF (1 << 2) /* start frame */
272 #define OHCI_INTR_RD (1 << 3) /* resume detect */
273 #define OHCI_INTR_UE (1 << 4) /* unrecoverable error */
274 #define OHCI_INTR_FNO (1 << 5) /* frame number overflow */
275 #define OHCI_INTR_RHSC (1 << 6) /* root hub status change */
276 #define OHCI_INTR_OC (1 << 30) /* ownership change */
277 #define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */
280 /* OHCI ROOT HUB REGISTER MASKS */
282 /* roothub.portstatus [i] bits */
283 #define RH_PS_CCS 0x00000001 /* current connect status */
284 #define RH_PS_PES 0x00000002 /* port enable status*/
285 #define RH_PS_PSS 0x00000004 /* port suspend status */
286 #define RH_PS_POCI 0x00000008 /* port over current indicator */
287 #define RH_PS_PRS 0x00000010 /* port reset status */
288 #define RH_PS_PPS 0x00000100 /* port power status */
289 #define RH_PS_LSDA 0x00000200 /* low speed device attached */
290 #define RH_PS_CSC 0x00010000 /* connect status change */
291 #define RH_PS_PESC 0x00020000 /* port enable status change */
292 #define RH_PS_PSSC 0x00040000 /* port suspend status change */
293 #define RH_PS_OCIC 0x00080000 /* over current indicator change */
294 #define RH_PS_PRSC 0x00100000 /* port reset status change */
296 /* roothub.status bits */
297 #define RH_HS_LPS 0x00000001 /* local power status */
298 #define RH_HS_OCI 0x00000002 /* over current indicator */
299 #define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */
300 #define RH_HS_LPSC 0x00010000 /* local power status change */
301 #define RH_HS_OCIC 0x00020000 /* over current indicator change */
302 #define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */
304 /* roothub.b masks */
305 #define RH_B_DR 0x0000ffff /* device removable flags */
306 #define RH_B_PPCM 0xffff0000 /* port power control mask */
308 /* roothub.a masks */
309 #define RH_A_NDP (0xff << 0) /* number of downstream ports */
310 #define RH_A_PSM (1 << 8) /* power switching mode */
311 #define RH_A_NPS (1 << 9) /* no power switching */
312 #define RH_A_DT (1 << 10) /* device type (mbz) */
313 #define RH_A_OCPM (1 << 11) /* over current protection mode */
314 #define RH_A_NOCP (1 << 12) /* no over current protection */
315 #define RH_A_POTPGT (0xff << 24) /* power on to power good time */
318 /* hcd-private per-urb state */
319 typedef struct urb_priv {
321 u16 length; // # tds in this request
322 u16 td_cnt; // tds already serviced
323 struct list_head pending;
324 struct td *td [0]; // all TDs in this request
328 #define TD_HASH_SIZE 64 /* power'o'two */
329 // sizeof (struct td) ~= 64 == 2^6 ...
330 #define TD_HASH_FUNC(td_dma) ((td_dma ^ (td_dma >> 6)) % TD_HASH_SIZE)
334 * This is the full ohci controller description
336 * Note how the "proper" USB information is just
337 * a subset of what the full implementation needs. (Linus)
344 * I/O memory used to communicate with the HC (dma-consistent)
346 struct ohci_regs *regs;
349 * main memory used to communicate with the HC (dma-consistent).
350 * hcd adds to schedule for a live hc any time, but removals finish
351 * only at the start of the next frame.
353 struct ohci_hcca *hcca;
356 struct ed *ed_rm_list; /* to be removed */
358 struct ed *ed_bulktail; /* last in bulk list */
359 struct ed *ed_controltail; /* last in ctrl list */
360 struct ed *periodic [NUM_INTS]; /* shadow int_table */
363 * memory management for queue data structures
365 struct dma_pool *td_cache;
366 struct dma_pool *ed_cache;
367 struct td *td_hash [TD_HASH_SIZE];
368 struct list_head pending;
374 u32 hc_control; /* copy of hc control reg */
375 unsigned long next_statechange; /* suspend/resume */
376 u32 fminterval; /* saved register */
378 struct work_struct rh_resume;
380 unsigned long flags; /* for HC bugs */
381 #define OHCI_QUIRK_AMD756 0x01 /* erratum #4 */
382 #define OHCI_QUIRK_SUPERIO 0x02 /* natsemi */
383 // there are also chip quirks/bugs in init logic
391 #define hcd_to_ohci(hcd_ptr) container_of(hcd_ptr, struct ohci_hcd, hcd)
393 /*-------------------------------------------------------------------------*/
395 static inline void disable (struct ohci_hcd *ohci)
397 ohci->hcd.state = USB_STATE_HALT;
400 #define FI 0x2edf /* 12000 bits per frame (-1) */
401 #define DEFAULT_FMINTERVAL ((((6 * (FI - 210)) / 7) << 16) | FI)
402 #define LSTHRESH 0x628 /* lowspeed bit threshold */
404 static inline void periodic_reinit (struct ohci_hcd *ohci)
406 writel (ohci->fminterval, &ohci->regs->fminterval);
407 writel (((9 * FI) / 10) & 0x3fff, &ohci->regs->periodicstart);
408 writel (LSTHRESH, &ohci->regs->lsthresh);
411 /*-------------------------------------------------------------------------*/
414 #define STUB_DEBUG_FILES
417 #define ohci_dbg(ohci, fmt, args...) \
418 dev_dbg ((ohci)->hcd.self.controller , fmt , ## args )
419 #define ohci_err(ohci, fmt, args...) \
420 dev_err ((ohci)->hcd.self.controller , fmt , ## args )
421 #define ohci_info(ohci, fmt, args...) \
422 dev_info ((ohci)->hcd.self.controller , fmt , ## args )
423 #define ohci_warn(ohci, fmt, args...) \
424 dev_warn ((ohci)->hcd.self.controller , fmt , ## args )
426 #ifdef OHCI_VERBOSE_DEBUG
427 # define ohci_vdbg ohci_dbg
429 # define ohci_vdbg(ohci, fmt, args...) do { } while (0)
432 #ifdef CONFIG_ARCH_LH7A404
433 /* Marc Singer: at the time this code was written, the LH7A404
434 * had a problem reading the USB host registers. This
435 * implementation of the ohci_readl function performs the read
436 * twice as a work-around.
438 static inline unsigned int ohci_readl (void* regs)
440 *(volatile unsigned int*) regs;
441 return *(volatile unsigned int*) regs;
444 /* Standard version of ohci_readl uses standard, platform
445 * specific implementation. */
446 static inline unsigned int ohci_readl (void* regs)