This commit was manufactured by cvs2svn to create branch 'vserver'.
[linux-2.6.git] / drivers / video / amba-clcd.c
1 /*
2  *  linux/drivers/video/amba-clcd.c
3  *
4  * Copyright (C) 2001 ARM Limited, by David A Rusling
5  * Updated to 2.5, Deep Blue Solutions Ltd.
6  *
7  * This file is subject to the terms and conditions of the GNU General Public
8  * License.  See the file COPYING in the main directory of this archive
9  * for more details.
10  *
11  *  ARM PrimeCell PL110 Color LCD Controller
12  */
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/errno.h>
16 #include <linux/string.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
19 #include <linux/fb.h>
20 #include <linux/init.h>
21 #include <linux/ioport.h>
22 #include <linux/list.h>
23
24 #include <asm/hardware/amba.h>
25 #include <asm/hardware/clock.h>
26
27 #include <asm/hardware/amba_clcd.h>
28
29 #define to_clcd(info)   container_of(info, struct clcd_fb, fb)
30
31 /* This is limited to 16 characters when displayed by X startup */
32 static const char *clcd_name = "CLCD FB";
33
34 /*
35  * Unfortunately, the enable/disable functions may be called either from
36  * process or IRQ context, and we _need_ to delay.  This is _not_ good.
37  */
38 static inline void clcdfb_sleep(unsigned int ms)
39 {
40         if (in_atomic()) {
41                 mdelay(ms);
42         } else {
43                 msleep(ms);
44         }
45 }
46
47 static inline void clcdfb_set_start(struct clcd_fb *fb)
48 {
49         unsigned long ustart = fb->fb.fix.smem_start;
50         unsigned long lstart;
51
52         ustart += fb->fb.var.yoffset * fb->fb.fix.line_length;
53         lstart = ustart + fb->fb.var.yres * fb->fb.fix.line_length / 2;
54
55         writel(ustart, fb->regs + CLCD_UBAS);
56         writel(lstart, fb->regs + CLCD_LBAS);
57 }
58
59 static void clcdfb_disable(struct clcd_fb *fb)
60 {
61         u32 val;
62
63         if (fb->board->disable)
64                 fb->board->disable(fb);
65
66         val = readl(fb->regs + CLCD_CNTL);
67         if (val & CNTL_LCDPWR) {
68                 val &= ~CNTL_LCDPWR;
69                 writel(val, fb->regs + CLCD_CNTL);
70
71                 clcdfb_sleep(20);
72         }
73         if (val & CNTL_LCDEN) {
74                 val &= ~CNTL_LCDEN;
75                 writel(val, fb->regs + CLCD_CNTL);
76         }
77
78         /*
79          * Disable CLCD clock source.
80          */
81         clk_disable(fb->clk);
82 }
83
84 static void clcdfb_enable(struct clcd_fb *fb, u32 cntl)
85 {
86         /*
87          * Enable the CLCD clock source.
88          */
89         clk_enable(fb->clk);
90
91         /*
92          * Bring up by first enabling..
93          */
94         cntl |= CNTL_LCDEN;
95         writel(cntl, fb->regs + CLCD_CNTL);
96
97         clcdfb_sleep(20);
98
99         /*
100          * and now apply power.
101          */
102         cntl |= CNTL_LCDPWR;
103         writel(cntl, fb->regs + CLCD_CNTL);
104
105         /*
106          * finally, enable the interface.
107          */
108         if (fb->board->enable)
109                 fb->board->enable(fb);
110 }
111
112 static int
113 clcdfb_set_bitfields(struct clcd_fb *fb, struct fb_var_screeninfo *var)
114 {
115         int ret = 0;
116
117         memset(&var->transp, 0, sizeof(var->transp));
118         memset(&var->red, 0, sizeof(var->red));
119         memset(&var->green, 0, sizeof(var->green));
120         memset(&var->blue, 0, sizeof(var->blue));
121
122         switch (var->bits_per_pixel) {
123         case 1:
124         case 2:
125         case 4:
126         case 8:
127                 var->red.length         = 8;
128                 var->red.offset         = 0;
129                 var->green.length       = 8;
130                 var->green.offset       = 0;
131                 var->blue.length        = 8;
132                 var->blue.offset        = 0;
133                 break;
134         case 16:
135                 var->red.length         = 5;
136                 var->green.length       = 5;
137                 var->blue.length        = 5;
138                 if (fb->panel->cntl & CNTL_BGR) {
139                         var->red.offset         = 10;
140                         var->green.offset       = 5;
141                         var->blue.offset        = 0;
142                 } else {
143                         var->red.offset         = 0;
144                         var->green.offset       = 5;
145                         var->blue.offset        = 10;
146                 }
147                 break;
148         case 24:
149                 if (fb->panel->cntl & CNTL_LCDTFT) {
150                         var->red.length         = 8;
151                         var->green.length       = 8;
152                         var->blue.length        = 8;
153
154                         if (fb->panel->cntl & CNTL_BGR) {
155                                 var->red.offset         = 16;
156                                 var->green.offset       = 8;
157                                 var->blue.offset        = 0;
158                         } else {
159                                 var->red.offset         = 0;
160                                 var->green.offset       = 8;
161                                 var->blue.offset        = 16;
162                         }
163                         break;
164                 }
165         default:
166                 ret = -EINVAL;
167                 break;
168         }
169
170         return ret;
171 }
172
173 static int clcdfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
174 {
175         struct clcd_fb *fb = to_clcd(info);
176         int ret = -EINVAL;
177
178         if (fb->board->check)
179                 ret = fb->board->check(fb, var);
180         if (ret == 0)
181                 ret = clcdfb_set_bitfields(fb, var);
182
183         return ret;
184 }
185
186 static int clcdfb_set_par(struct fb_info *info)
187 {
188         struct clcd_fb *fb = to_clcd(info);
189         struct clcd_regs regs;
190
191         fb->fb.fix.line_length = fb->fb.var.xres_virtual *
192                                  fb->fb.var.bits_per_pixel / 8;
193
194         if (fb->fb.var.bits_per_pixel <= 8)
195                 fb->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
196         else
197                 fb->fb.fix.visual = FB_VISUAL_TRUECOLOR;
198
199         fb->board->decode(fb, &regs);
200
201         clcdfb_disable(fb);
202
203         writel(regs.tim0, fb->regs + CLCD_TIM0);
204         writel(regs.tim1, fb->regs + CLCD_TIM1);
205         writel(regs.tim2, fb->regs + CLCD_TIM2);
206         writel(regs.tim3, fb->regs + CLCD_TIM3);
207
208         clcdfb_set_start(fb);
209
210         clk_set_rate(fb->clk, (1000000000 / regs.pixclock) * 1000);
211
212         fb->clcd_cntl = regs.cntl;
213
214         clcdfb_enable(fb, regs.cntl);
215
216 #ifdef DEBUG
217         printk(KERN_INFO "CLCD: Registers set to\n"
218                KERN_INFO "  %08x %08x %08x %08x\n"
219                KERN_INFO "  %08x %08x %08x %08x\n",
220                 readl(fb->regs + CLCD_TIM0), readl(fb->regs + CLCD_TIM1),
221                 readl(fb->regs + CLCD_TIM2), readl(fb->regs + CLCD_TIM3),
222                 readl(fb->regs + CLCD_UBAS), readl(fb->regs + CLCD_LBAS),
223                 readl(fb->regs + CLCD_IENB), readl(fb->regs + CLCD_CNTL));
224 #endif
225
226         return 0;
227 }
228
229 static inline u32 convert_bitfield(int val, struct fb_bitfield *bf)
230 {
231         unsigned int mask = (1 << bf->length) - 1;
232
233         return (val >> (16 - bf->length) & mask) << bf->offset;
234 }
235
236 /*
237  *  Set a single color register. The values supplied have a 16 bit
238  *  magnitude.  Return != 0 for invalid regno.
239  */
240 static int
241 clcdfb_setcolreg(unsigned int regno, unsigned int red, unsigned int green,
242                  unsigned int blue, unsigned int transp, struct fb_info *info)
243 {
244         struct clcd_fb *fb = to_clcd(info);
245
246         if (regno < 16)
247                 fb->cmap[regno] = convert_bitfield(transp, &fb->fb.var.transp) |
248                                   convert_bitfield(blue, &fb->fb.var.blue) |
249                                   convert_bitfield(green, &fb->fb.var.green) |
250                                   convert_bitfield(red, &fb->fb.var.red);
251
252         if (fb->fb.var.bits_per_pixel == 8 && regno < 256) {
253                 int hw_reg = CLCD_PALETTE + ((regno * 2) & ~3);
254                 u32 val, mask, newval;
255
256                 newval  = (red >> 11)  & 0x001f;
257                 newval |= (green >> 6) & 0x03e0;
258                 newval |= (blue >> 1)  & 0x7c00;
259
260                 /*
261                  * 3.2.11: if we're configured for big endian
262                  * byte order, the palette entries are swapped.
263                  */
264                 if (fb->clcd_cntl & CNTL_BEBO)
265                         regno ^= 1;
266
267                 if (regno & 1) {
268                         newval <<= 16;
269                         mask = 0x0000ffff;
270                 } else {
271                         mask = 0xffff0000;
272                 }
273
274                 val = readl(fb->regs + hw_reg) & mask;
275                 writel(val | newval, fb->regs + hw_reg);
276         }
277
278         return regno > 255;
279 }
280
281 /*
282  *  Blank the screen if blank_mode != 0, else unblank. If blank == NULL
283  *  then the caller blanks by setting the CLUT (Color Look Up Table) to all
284  *  black. Return 0 if blanking succeeded, != 0 if un-/blanking failed due
285  *  to e.g. a video mode which doesn't support it. Implements VESA suspend
286  *  and powerdown modes on hardware that supports disabling hsync/vsync:
287  *    blank_mode == 2: suspend vsync
288  *    blank_mode == 3: suspend hsync
289  *    blank_mode == 4: powerdown
290  */
291 static int clcdfb_blank(int blank_mode, struct fb_info *info)
292 {
293         struct clcd_fb *fb = to_clcd(info);
294
295         if (blank_mode != 0) {
296                 clcdfb_disable(fb);
297         } else {
298                 clcdfb_enable(fb, fb->clcd_cntl);
299         }
300         return 0;
301 }
302
303 static struct fb_ops clcdfb_ops = {
304         .owner          = THIS_MODULE,
305         .fb_check_var   = clcdfb_check_var,
306         .fb_set_par     = clcdfb_set_par,
307         .fb_setcolreg   = clcdfb_setcolreg,
308         .fb_blank       = clcdfb_blank,
309         .fb_fillrect    = cfb_fillrect,
310         .fb_copyarea    = cfb_copyarea,
311         .fb_imageblit   = cfb_imageblit,
312         .fb_cursor      = soft_cursor,
313 };
314
315 static int clcdfb_register(struct clcd_fb *fb)
316 {
317         int ret;
318
319         fb->clk = clk_get(&fb->dev->dev, "CLCDCLK");
320         if (IS_ERR(fb->clk)) {
321                 ret = PTR_ERR(fb->clk);
322                 goto out;
323         }
324
325         ret = clk_use(fb->clk);
326         if (ret)
327                 goto free_clk;
328
329         fb->fb.fix.mmio_start   = fb->dev->res.start;
330         fb->fb.fix.mmio_len     = SZ_4K;
331
332         fb->regs = ioremap(fb->fb.fix.mmio_start, fb->fb.fix.mmio_len);
333         if (!fb->regs) {
334                 printk(KERN_ERR "CLCD: unable to remap registers\n");
335                 ret = -ENOMEM;
336                 goto unuse_clk;
337         }
338
339         fb->fb.fbops            = &clcdfb_ops;
340         fb->fb.flags            = FBINFO_FLAG_DEFAULT;
341         fb->fb.pseudo_palette   = fb->cmap;
342
343         strncpy(fb->fb.fix.id, clcd_name, sizeof(fb->fb.fix.id));
344         fb->fb.fix.type         = FB_TYPE_PACKED_PIXELS;
345         fb->fb.fix.type_aux     = 0;
346         fb->fb.fix.xpanstep     = 0;
347         fb->fb.fix.ypanstep     = 0;
348         fb->fb.fix.ywrapstep    = 0;
349         fb->fb.fix.accel        = FB_ACCEL_NONE;
350
351         fb->fb.var.xres         = fb->panel->mode.xres;
352         fb->fb.var.yres         = fb->panel->mode.yres;
353         fb->fb.var.xres_virtual = fb->panel->mode.xres;
354         fb->fb.var.yres_virtual = fb->panel->mode.yres;
355         fb->fb.var.bits_per_pixel = fb->panel->bpp;
356         fb->fb.var.grayscale    = fb->panel->grayscale;
357         fb->fb.var.pixclock     = fb->panel->mode.pixclock;
358         fb->fb.var.left_margin  = fb->panel->mode.left_margin;
359         fb->fb.var.right_margin = fb->panel->mode.right_margin;
360         fb->fb.var.upper_margin = fb->panel->mode.upper_margin;
361         fb->fb.var.lower_margin = fb->panel->mode.lower_margin;
362         fb->fb.var.hsync_len    = fb->panel->mode.hsync_len;
363         fb->fb.var.vsync_len    = fb->panel->mode.vsync_len;
364         fb->fb.var.sync         = fb->panel->mode.sync;
365         fb->fb.var.vmode        = fb->panel->mode.vmode;
366         fb->fb.var.activate     = FB_ACTIVATE_NOW;
367         fb->fb.var.nonstd       = 0;
368         fb->fb.var.height       = fb->panel->height;
369         fb->fb.var.width        = fb->panel->width;
370         fb->fb.var.accel_flags  = 0;
371
372         fb->fb.monspecs.hfmin   = 0;
373         fb->fb.monspecs.hfmax   = 100000;
374         fb->fb.monspecs.vfmin   = 0;
375         fb->fb.monspecs.vfmax   = 400;
376         fb->fb.monspecs.dclkmin = 1000000;
377         fb->fb.monspecs.dclkmax = 100000000;
378
379         /*
380          * Make sure that the bitfields are set appropriately.
381          */
382         clcdfb_set_bitfields(fb, &fb->fb.var);
383
384         /*
385          * Allocate colourmap.
386          */
387         fb_alloc_cmap(&fb->fb.cmap, 256, 0);
388
389         /*
390          * Ensure interrupts are disabled.
391          */
392         writel(0, fb->regs + CLCD_IENB);
393
394         fb_set_var(&fb->fb, &fb->fb.var);
395
396         printk(KERN_INFO "CLCD: %s hardware, %s display\n",
397                fb->board->name, fb->panel->mode.name);
398
399         ret = register_framebuffer(&fb->fb);
400         if (ret == 0)
401                 goto out;
402
403         printk(KERN_ERR "CLCD: cannot register framebuffer (%d)\n", ret);
404
405         iounmap(fb->regs);
406  unuse_clk:
407         clk_unuse(fb->clk);
408  free_clk:
409         clk_put(fb->clk);
410  out:
411         return ret;
412 }
413
414 static int clcdfb_probe(struct amba_device *dev, void *id)
415 {
416         struct clcd_board *board = dev->dev.platform_data;
417         struct clcd_fb *fb;
418         int ret;
419
420         if (!board)
421                 return -EINVAL;
422
423         ret = amba_request_regions(dev, NULL);
424         if (ret) {
425                 printk(KERN_ERR "CLCD: unable to reserve regs region\n");
426                 goto out;
427         }
428
429         fb = (struct clcd_fb *) kmalloc(sizeof(struct clcd_fb), GFP_KERNEL);
430         if (!fb) {
431                 printk(KERN_INFO "CLCD: could not allocate new clcd_fb struct\n");
432                 ret = -ENOMEM;
433                 goto free_region;
434         }
435         memset(fb, 0, sizeof(struct clcd_fb));
436
437         fb->dev = dev;
438         fb->board = board;
439
440         ret = fb->board->setup(fb);
441         if (ret)
442                 goto free_fb;
443
444         ret = clcdfb_register(fb); 
445         if (ret == 0) {
446                 amba_set_drvdata(dev, fb);
447                 goto out;
448         }
449
450         fb->board->remove(fb);
451  free_fb:
452         kfree(fb);
453  free_region:
454         amba_release_regions(dev);
455  out:
456         return ret;
457 }
458
459 static int clcdfb_remove(struct amba_device *dev)
460 {
461         struct clcd_fb *fb = amba_get_drvdata(dev);
462
463         amba_set_drvdata(dev, NULL);
464
465         clcdfb_disable(fb);
466         unregister_framebuffer(&fb->fb);
467         iounmap(fb->regs);
468         clk_unuse(fb->clk);
469         clk_put(fb->clk);
470
471         fb->board->remove(fb);
472
473         kfree(fb);
474
475         amba_release_regions(dev);
476
477         return 0;
478 }
479
480 static struct amba_id clcdfb_id_table[] = {
481         {
482                 .id     = 0x00041110,
483                 .mask   = 0x000fffff,
484         },
485         { 0, 0 },
486 };
487
488 static struct amba_driver clcd_driver = {
489         .drv            = {
490                 .name   = "clcd-pl110",
491         },
492         .probe          = clcdfb_probe,
493         .remove         = clcdfb_remove,
494         .id_table       = clcdfb_id_table,
495 };
496
497 int __init amba_clcdfb_init(void)
498 {
499         if (fb_get_options("ambafb", NULL))
500                 return -ENODEV;
501
502         return amba_driver_register(&clcd_driver);
503 }
504
505 module_init(amba_clcdfb_init);
506
507 static void __exit amba_clcdfb_exit(void)
508 {
509         amba_driver_unregister(&clcd_driver);
510 }
511
512 module_exit(amba_clcdfb_exit);
513
514 MODULE_DESCRIPTION("ARM PrimeCell PL110 CLCD core driver");
515 MODULE_LICENSE("GPL");