drivers/video/aty/atyfb_base.c

   1 /*
   2  *  ATI Frame Buffer Device Driver Core
   3  *
   4  *      Copyright (C) 2004  Alex Kern <alex.kern@gmx.de>
   5  *      Copyright (C) 1997-2001  Geert Uytterhoeven
   6  *      Copyright (C) 1998  Bernd Harries
   7  *      Copyright (C) 1998  Eddie C. Dost  (ecd@skynet.be)
   8  *
   9  *  This driver supports the following ATI graphics chips:
  10  *    - ATI Mach64
  11  *
  12  *  To do: add support for
  13  *    - ATI Rage128 (from aty128fb.c)
  14  *    - ATI Radeon (from radeonfb.c)
  15  *
  16  *  This driver is partly based on the PowerMac console driver:
  17  *
  18  *      Copyright (C) 1996 Paul Mackerras
  19  *
  20  *  and on the PowerMac ATI/mach64 display driver:
  21  *
  22  *      Copyright (C) 1997 Michael AK Tesch
  23  *
  24  *            with work by Jon Howell
  25  *                         Harry AC Eaton
  26  *                         Anthony Tong <atong@uiuc.edu>
  27  *
  28  *  Generic LCD support written by Daniel Mantione, ported from 2.4.20 by Alex Kern
  29  *  Many Thanks to Ville Syrjälä for patches and fixing nasting 16 bit color bug.
  30  *
  31  *  This file is subject to the terms and conditions of the GNU General Public
  32  *  License. See the file COPYING in the main directory of this archive for
  33  *  more details.
  34  *
  35  *  Many thanks to Nitya from ATI devrel for support and patience !
  36  */
  37
  38 /******************************************************************************
  39
  40   TODO:
  41
  42     - cursor support on all cards and all ramdacs.
  43     - cursor parameters controlable via ioctl()s.
  44     - guess PLL and MCLK based on the original PLL register values initialized
  45       by Open Firmware (if they are initialized). BIOS is done
  46
  47     (Anyone with Mac to help with this?)
  48
  49 ******************************************************************************/
  50
  51
  52 #include <linux/config.h>
  53 #include <linux/module.h>
  54 #include <linux/moduleparam.h>
  55 #include <linux/kernel.h>
  56 #include <linux/errno.h>
  57 #include <linux/string.h>
  58 #include <linux/mm.h>
  59 #include <linux/slab.h>
  60 #include <linux/vmalloc.h>
  61 #include <linux/delay.h>
  62 #include <linux/console.h>
  63 #include <linux/fb.h>
  64 #include <linux/init.h>
  65 #include <linux/pci.h>
  66 #include <linux/interrupt.h>
  67 #include <linux/spinlock.h>
  68 #include <linux/wait.h>
  69
  70 #include <asm/io.h>
  71 #include <asm/uaccess.h>
  72
  73 #include <video/mach64.h>
  74 #include "atyfb.h"
  75 #include "ati_ids.h"
  76
  77 #ifdef __powerpc__
  78 #include <asm/prom.h>
  79 #include "../macmodes.h"
  80 #endif
  81 #ifdef __sparc__
  82 #include <asm/pbm.h>
  83 #include <asm/fbio.h>
  84 #endif
  85
  86 #ifdef CONFIG_ADB_PMU
  87 #include <linux/adb.h>
  88 #include <linux/pmu.h>
  89 #endif
  90 #ifdef CONFIG_BOOTX_TEXT
  91 #include <asm/btext.h>
  92 #endif
  93 #ifdef CONFIG_PMAC_BACKLIGHT
  94 #include <asm/backlight.h>
  95 #endif
  96 #ifdef CONFIG_MTRR
  97 #include <asm/mtrr.h>
  98 #endif
  99
 100 /*
 101  * Debug flags.
 102  */
 103 /*#undef DEBUG*/
 104 #define DEBUG
 105
 106 /* Make sure n * PAGE_SIZE is protected at end of Aperture for GUI-regs */
 107 /*  - must be large enough to catch all GUI-Regs   */
 108 /*  - must be aligned to a PAGE boundary           */
 109 #define GUI_RESERVE     (1 * PAGE_SIZE)
 110
 111 /* FIXME: remove the FAIL definition */
 112 #define FAIL(msg) do { printk(KERN_CRIT "atyfb: " msg "\n"); return -EINVAL; } while (0)
 113 #define FAIL_MAX(msg, x, _max_) do { if(x > _max_) { printk(KERN_CRIT "atyfb: " msg " %x(%x)\n", x, _max_); return -EINVAL; } } while (0)
 114
 115 #ifdef DEBUG
 116 #define DPRINTK(fmt, args...)   printk(KERN_DEBUG "atyfb: " fmt, ## args)
 117 #else
 118 #define DPRINTK(fmt, args...)
 119 #endif
 120
 121 #define PRINTKI(fmt, args...)   printk(KERN_INFO "atyfb: " fmt, ## args)
 122 #define PRINTKE(fmt, args...)    printk(KERN_ERR "atyfb: " fmt, ## args)
 123
 124 #if defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD)
 125 static const u32 lt_lcd_regs[] = {
 126         CONFIG_PANEL_LG,
 127         LCD_GEN_CNTL_LG,
 128         DSTN_CONTROL_LG,
 129         HFB_PITCH_ADDR_LG,
 130         HORZ_STRETCHING_LG,
 131         VERT_STRETCHING_LG,
 132         0, /* EXT_VERT_STRETCH */
 133         LT_GIO_LG,
 134         POWER_MANAGEMENT_LG
 135 };
 136
 137 void aty_st_lcd(int index, u32 val, const struct atyfb_par *par)
 138 {
 139         if (M64_HAS(LT_LCD_REGS)) {
 140                 aty_st_le32(lt_lcd_regs[index], val, par);
 141         } else {
 142                 unsigned long temp;
 143
 144                 /* write addr byte */
 145                 temp = aty_ld_le32(LCD_INDEX, par);
 146                 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
 147                 /* write the register value */
 148                 aty_st_le32(LCD_DATA, val, par);
 149         }
 150 }
 151
 152 u32 aty_ld_lcd(int index, const struct atyfb_par *par)
 153 {
 154         if (M64_HAS(LT_LCD_REGS)) {
 155                 return aty_ld_le32(lt_lcd_regs[index], par);
 156         } else {
 157                 unsigned long temp;
 158
 159                 /* write addr byte */
 160                 temp = aty_ld_le32(LCD_INDEX, par);
 161                 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
 162                 /* read the register value */
 163                 return aty_ld_le32(LCD_DATA, par);
 164         }
 165 }
 166 #endif /* defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD) */
 167
 168 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 169 /*
 170  * ATIReduceRatio --
 171  *
 172  * Reduce a fraction by factoring out the largest common divider of the
 173  * fraction's numerator and denominator.
 174  */
 175 static void ATIReduceRatio(int *Numerator, int *Denominator)
 176 {
 177     int Multiplier, Divider, Remainder;
 178
 179     Multiplier = *Numerator;
 180     Divider = *Denominator;
 181
 182     while ((Remainder = Multiplier % Divider))
 183     {
 184         Multiplier = Divider;
 185         Divider = Remainder;
 186     }
 187
 188     *Numerator /= Divider;
 189     *Denominator /= Divider;
 190 }
 191 #endif
 192     /*
 193      *  The Hardware parameters for each card
 194      */
 195
 196 struct aty_cmap_regs {
 197         u8 windex;
 198         u8 lut;
 199         u8 mask;
 200         u8 rindex;
 201         u8 cntl;
 202 };
 203
 204 struct pci_mmap_map {
 205         unsigned long voff;
 206         unsigned long poff;
 207         unsigned long size;
 208         unsigned long prot_flag;
 209         unsigned long prot_mask;
 210 };
 211
 212 static struct fb_fix_screeninfo atyfb_fix __initdata = {
 213         .id             = "ATY Mach64",
 214         .type           = FB_TYPE_PACKED_PIXELS,
 215         .visual         = FB_VISUAL_PSEUDOCOLOR,
 216         .xpanstep       = 8,
 217         .ypanstep       = 1,
 218 };
 219
 220     /*
 221      *  Frame buffer device API
 222      */
 223
 224 static int atyfb_open(struct fb_info *info, int user);
 225 static int atyfb_release(struct fb_info *info, int user);
 226 static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info);
 227 static int atyfb_set_par(struct fb_info *info);
 228 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
 229         u_int transp, struct fb_info *info);
 230 static int atyfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info);
 231 static int atyfb_blank(int blank, struct fb_info *info);
 232 static int atyfb_ioctl(struct inode *inode, struct file *file, u_int cmd,
 233         u_long arg, struct fb_info *info);
 234 extern void atyfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect);
 235 extern void atyfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
 236 extern void atyfb_imageblit(struct fb_info *info, const struct fb_image *image);
 237 #ifdef __sparc__
 238 static int atyfb_mmap(struct fb_info *info, struct file *file, struct vm_area_struct *vma);
 239 #endif
 240 static int atyfb_sync(struct fb_info *info);
 241
 242     /*
 243      *  Internal routines
 244      */
 245
 246 static int aty_init(struct fb_info *info, const char *name);
 247 #ifdef CONFIG_ATARI
 248 static int store_video_par(char *videopar, unsigned char m64_num);
 249 #endif
 250
 251 static struct crtc saved_crtc;
 252 static union aty_pll saved_pll;
 253 static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc);
 254
 255 static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc);
 256 static int aty_var_to_crtc(const struct fb_info *info, const struct fb_var_screeninfo *var, struct crtc *crtc);
 257 static int aty_crtc_to_var(const struct crtc *crtc, struct fb_var_screeninfo *var);
 258 static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info);
 259 #ifdef CONFIG_PPC
 260 static int read_aty_sense(const struct atyfb_par *par);
 261 #endif
 262
 263
 264     /*
 265      *  Interface used by the world
 266      */
 267
 268 struct fb_var_screeninfo default_var = {
 269         /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
 270         640, 480, 640, 480, 0, 0, 8, 0,
 271         {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
 272         0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
 273         0, FB_VMODE_NONINTERLACED
 274 };
 275
 276 static struct fb_videomode defmode = {
 277         /* 640x480 @ 60 Hz, 31.5 kHz hsync */
 278         NULL, 60, 640, 480, 39721, 40, 24, 32, 11, 96, 2,
 279         0, FB_VMODE_NONINTERLACED
 280 };
 281
 282 static struct fb_ops atyfb_ops = {
 283         .owner          = THIS_MODULE,
 284         .fb_open        = atyfb_open,
 285         .fb_release     = atyfb_release,
 286         .fb_check_var   = atyfb_check_var,
 287         .fb_set_par     = atyfb_set_par,
 288         .fb_setcolreg   = atyfb_setcolreg,
 289         .fb_pan_display = atyfb_pan_display,
 290         .fb_blank       = atyfb_blank,
 291         .fb_ioctl       = atyfb_ioctl,
 292         .fb_fillrect    = atyfb_fillrect,
 293         .fb_copyarea    = atyfb_copyarea,
 294         .fb_imageblit   = atyfb_imageblit,
 295         .fb_cursor      = soft_cursor,
 296 #ifdef __sparc__
 297         .fb_mmap        = atyfb_mmap,
 298 #endif
 299         .fb_sync        = atyfb_sync,
 300 };
 301
 302 static int noaccel;
 303 #ifdef CONFIG_MTRR
 304 static int nomtrr;
 305 #endif
 306 static int vram;
 307 static int pll;
 308 static int mclk;
 309 static int xclk;
 310 static char *mode;
 311
 312 #ifdef CONFIG_PPC
 313 static int default_vmode __initdata = VMODE_CHOOSE;
 314 static int default_cmode __initdata = CMODE_CHOOSE;
 315
 316 module_param_named(vmode, default_vmode, int, 0);
 317 MODULE_PARM_DESC(vmode, "int: video mode for mac");
 318 module_param_named(cmode, default_cmode, int, 0);
 319 MODULE_PARM_DESC(cmode, "int: color mode for mac");
 320 #endif
 321
 322 #ifdef CONFIG_ATARI
 323 static unsigned int mach64_count __initdata = 0;
 324 static unsigned long phys_vmembase[FB_MAX] __initdata = { 0, };
 325 static unsigned long phys_size[FB_MAX] __initdata = { 0, };
 326 static unsigned long phys_guiregbase[FB_MAX] __initdata = { 0, };
 327 #endif
 328
 329 /* top -> down is an evolution of mach64 chipset, any corrections? */
 330 #define ATI_CHIP_88800GX   (M64F_GX)
 331 #define ATI_CHIP_88800CX   (M64F_GX)
 332
 333 #define ATI_CHIP_264CT     (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
 334 #define ATI_CHIP_264ET     (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
 335
 336 #define ATI_CHIP_264VT     (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_MAGIC_FIFO)
 337 #define ATI_CHIP_264GT     (M64F_GT | M64F_INTEGRATED               | M64F_MAGIC_FIFO | M64F_EXTRA_BRIGHT)
 338
 339 #define ATI_CHIP_264VTB    (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP)
 340 #define ATI_CHIP_264VT3    (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL)
 341 #define ATI_CHIP_264VT4    (M64F_VT | M64F_INTEGRATED               | M64F_GTB_DSP)
 342
 343 #define ATI_CHIP_264LT     (M64F_GT | M64F_INTEGRATED               | M64F_GTB_DSP)
 344
 345 /* make sets shorter */
 346 #define ATI_MODERN_SET     (M64F_GT | M64F_INTEGRATED               | M64F_GTB_DSP | M64F_EXTRA_BRIGHT)
 347
 348 #define ATI_CHIP_264GTB    (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
 349 /*#define ATI_CHIP_264GTDVD  ?*/
 350 #define ATI_CHIP_264LTG    (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
 351
 352 #define ATI_CHIP_264GT2C   (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE)
 353 #define ATI_CHIP_264GTPRO  (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
 354 #define ATI_CHIP_264LTPRO  (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
 355
 356 #define ATI_CHIP_264XL     (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4)
 357 #define ATI_CHIP_MOBILITY  (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4 | M64F_MOBIL_BUS)
 358
 359 static struct {
 360         u16 pci_id;
 361         const char *name;
 362         int pll, mclk, xclk;
 363         u32 features;
 364 } aty_chips[] __initdata = {
 365 #ifdef CONFIG_FB_ATY_GX
 366         /* Mach64 GX */
 367         { PCI_CHIP_MACH64GX, "ATI888GX00 (Mach64 GX)", 135, 50, 50, ATI_CHIP_88800GX },
 368         { PCI_CHIP_MACH64CX, "ATI888CX00 (Mach64 CX)", 135, 50, 50, ATI_CHIP_88800CX },
 369 #endif /* CONFIG_FB_ATY_GX */
 370
 371 #ifdef CONFIG_FB_ATY_CT
 372         { PCI_CHIP_MACH64CT, "ATI264CT (Mach64 CT)", 135, 60, 60, ATI_CHIP_264CT },
 373         { PCI_CHIP_MACH64ET, "ATI264ET (Mach64 ET)", 135, 60, 60, ATI_CHIP_264ET },
 374         { PCI_CHIP_MACH64VT, "ATI264VT? (Mach64 VT)", 170, 67, 67, ATI_CHIP_264VT },
 375         { PCI_CHIP_MACH64GT, "3D RAGE (Mach64 GT)", 135, 63, 63, ATI_CHIP_264GT },
 376         /* FIXME { ...ATI_264GU, maybe ATI_CHIP_264GTDVD }, */
 377         { PCI_CHIP_MACH64GU, "3D RAGE II+ (Mach64 GTB)", 200, 67, 67, ATI_CHIP_264GTB  },
 378         { PCI_CHIP_MACH64VU, "ATI264VTB (Mach64 VU)", 200, 67, 67, ATI_CHIP_264VT3 },
 379
 380         { PCI_CHIP_MACH64LT, "3D RAGE LT (Mach64 LT)", 135, 63, 63, ATI_CHIP_264LT },
 381          /* FIXME chipset maybe ATI_CHIP_264LTPRO ? */
 382         { PCI_CHIP_MACH64LG, "3D RAGE LT-G (Mach64 LG)", 230, 63, 63, ATI_CHIP_264LTG | M64F_LT_LCD_REGS | M64F_G3_PB_1024x768 },
 383
 384         { PCI_CHIP_MACH64VV, "ATI264VT4 (Mach64 VV)", 230, 83, 83, ATI_CHIP_264VT4 },
 385
 386         { PCI_CHIP_MACH64GV, "3D RAGE IIC (Mach64 GV, PCI)", 230, 83, 83, ATI_CHIP_264GT2C },
 387         { PCI_CHIP_MACH64GW, "3D RAGE IIC (Mach64 GW, AGP)", 230, 83, 83, ATI_CHIP_264GT2C },
 388         { PCI_CHIP_MACH64GY, "3D RAGE IIC (Mach64 GY, PCI)", 230, 83, 83, ATI_CHIP_264GT2C },
 389         { PCI_CHIP_MACH64GZ, "3D RAGE IIC (Mach64 GZ, AGP)", 230, 83, 83, ATI_CHIP_264GT2C },
 390
 391         { PCI_CHIP_MACH64GB, "3D RAGE PRO (Mach64 GB, BGA, AGP)", 230, 100, 100, ATI_CHIP_264GTPRO },
 392         { PCI_CHIP_MACH64GD, "3D RAGE PRO (Mach64 GD, BGA, AGP 1x)", 230, 100, 100, ATI_CHIP_264GTPRO },
 393         { PCI_CHIP_MACH64GI, "3D RAGE PRO (Mach64 GI, BGA, PCI)", 230, 100, 100, ATI_CHIP_264GTPRO | M64F_MAGIC_VRAM_SIZE },
 394         { PCI_CHIP_MACH64GP, "3D RAGE PRO (Mach64 GP, PQFP, PCI)", 230, 100, 100, ATI_CHIP_264GTPRO },
 395         { PCI_CHIP_MACH64GQ, "3D RAGE PRO (Mach64 GQ, PQFP, PCI, limited 3D)", 230, 100, 100, ATI_CHIP_264GTPRO },
 396
 397         { PCI_CHIP_MACH64LB, "3D RAGE LT PRO (Mach64 LB, AGP)", 236, 75, 100, ATI_CHIP_264LTPRO },
 398         { PCI_CHIP_MACH64LD, "3D RAGE LT PRO (Mach64 LD, AGP)", 230, 100, 100, ATI_CHIP_264LTPRO },
 399         { PCI_CHIP_MACH64LI, "3D RAGE LT PRO (Mach64 LI, PCI)", 230, 100, 100, ATI_CHIP_264LTPRO | M64F_G3_PB_1_1 | M64F_G3_PB_1024x768 },
 400         { PCI_CHIP_MACH64LP, "3D RAGE LT PRO (Mach64 LP, PCI)", 230, 100, 100, ATI_CHIP_264LTPRO },
 401         { PCI_CHIP_MACH64LQ, "3D RAGE LT PRO (Mach64 LQ, PCI)", 230, 100, 100, ATI_CHIP_264LTPRO },
 402
 403         { PCI_CHIP_MACH64GM, "3D RAGE XL (Mach64 GM, AGP)", 230, 83, 63, ATI_CHIP_264XL },
 404         { PCI_CHIP_MACH64GN, "3D RAGE XL (Mach64 GN, AGP)", 230, 83, 63, ATI_CHIP_264XL },
 405         { PCI_CHIP_MACH64GO, "3D RAGE XL (Mach64 GO, PCI-66/BGA)", 230, 83, 63, ATI_CHIP_264XL },
 406         { PCI_CHIP_MACH64GR, "3D RAGE XL (Mach64 GR, PCI-33MHz)", 230, 83, 63, ATI_CHIP_264XL },
 407         { PCI_CHIP_MACH64GL, "3D RAGE XL (Mach64 GL, PCI)", 230, 83, 63, ATI_CHIP_264XL },
 408         { PCI_CHIP_MACH64GS, "3D RAGE XL (Mach64 GS, PCI)", 230, 83, 63, ATI_CHIP_264XL },
 409
 410         { PCI_CHIP_MACH64LM, "3D RAGE Mobility P/M (Mach64 LM, AGP 2x)", 230, 83, 125, ATI_CHIP_MOBILITY },
 411         { PCI_CHIP_MACH64LN, "3D RAGE Mobility L (Mach64 LN, AGP 2x)", 230, 83, 125, ATI_CHIP_MOBILITY },
 412         { PCI_CHIP_MACH64LR, "3D RAGE Mobility P/M (Mach64 LR, PCI)", 230, 83, 125, ATI_CHIP_MOBILITY },
 413         { PCI_CHIP_MACH64LS, "3D RAGE Mobility L (Mach64 LS, PCI)", 230, 83, 125, ATI_CHIP_MOBILITY },
 414 #endif /* CONFIG_FB_ATY_CT */
 415 };
 416
 417 /* can not fail */
 418 static int __devinit correct_chipset(struct atyfb_par *par)
 419 {
 420         u8 rev;
 421         u16 type;
 422         u32 chip_id;
 423         const char *name;
 424         int i;
 425
 426         for (i = sizeof(aty_chips) / sizeof(*aty_chips) - 1; i >= 0; i--)
 427                 if (par->pci_id == aty_chips[i].pci_id)
 428                         break;
 429
 430         name = aty_chips[i].name;
 431         par->pll_limits.pll_max = aty_chips[i].pll;
 432         par->pll_limits.mclk = aty_chips[i].mclk;
 433         par->pll_limits.xclk = aty_chips[i].xclk;
 434         par->features = aty_chips[i].features;
 435
 436         chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
 437         type = chip_id & CFG_CHIP_TYPE;
 438         rev = (chip_id & CFG_CHIP_REV) >> 24;
 439
 440         switch(par->pci_id) {
 441 #ifdef CONFIG_FB_ATY_GX
 442         case PCI_CHIP_MACH64GX:
 443                 if(type != 0x00d7)
 444                         return -ENODEV;
 445                 break;
 446         case PCI_CHIP_MACH64CX:
 447                 if(type != 0x0057)
 448                         return -ENODEV;
 449                 break;
 450 #endif
 451 #ifdef CONFIG_FB_ATY_CT
 452         case PCI_CHIP_MACH64VT:
 453                 rev &= 0xc7;
 454                 if(rev == 0x00) {
 455                         name = "ATI264VTA3 (Mach64 VT)";
 456                         par->pll_limits.pll_max = 170;
 457                         par->pll_limits.mclk = 67;
 458                         par->pll_limits.xclk = 67;
 459                         par->features = ATI_CHIP_264VT;
 460                 } else if(rev == 0x40) {
 461                         name = "ATI264VTA4 (Mach64 VT)";
 462                         par->pll_limits.pll_max = 200;
 463                         par->pll_limits.mclk = 67;
 464                         par->pll_limits.xclk = 67;
 465                         par->features = ATI_CHIP_264VT | M64F_MAGIC_POSTDIV;
 466                 } else {
 467                         name = "ATI264VTB (Mach64 VT)";
 468                         par->pll_limits.pll_max = 200;
 469                         par->pll_limits.mclk = 67;
 470                         par->pll_limits.xclk = 67;
 471                         par->features = ATI_CHIP_264VTB;
 472                 }
 473                 break;
 474         case PCI_CHIP_MACH64GT:
 475                 rev &= 0x07;
 476                 if(rev == 0x01) {
 477                         par->pll_limits.pll_max = 170;
 478                         par->pll_limits.mclk = 67;
 479                         par->pll_limits.xclk = 67;
 480                         par->features = ATI_CHIP_264GTB;
 481                 } else if(rev == 0x02) {
 482                         par->pll_limits.pll_max = 200;
 483                         par->pll_limits.mclk = 67;
 484                         par->pll_limits.xclk = 67;
 485                         par->features = ATI_CHIP_264GTB;
 486                 }
 487                 break;
 488 #endif
 489         }
 490
 491         PRINTKI("%s [0x%04x rev 0x%02x]\n", name, type, rev);
 492         return 0;
 493 }
 494
 495 static char ram_dram[] __initdata = "DRAM";
 496 static char ram_resv[] __initdata = "RESV";
 497 #ifdef CONFIG_FB_ATY_GX
 498 static char ram_vram[] __initdata = "VRAM";
 499 #endif /* CONFIG_FB_ATY_GX */
 500 #ifdef CONFIG_FB_ATY_CT
 501 static char ram_edo[] __initdata = "EDO";
 502 static char ram_sdram[] __initdata = "SDRAM (1:1)";
 503 static char ram_sgram[] __initdata = "SGRAM (1:1)";
 504 static char ram_sdram32[] __initdata = "SDRAM (2:1) (32-bit)";
 505 static char ram_off[] __initdata = "OFF";
 506 #endif /* CONFIG_FB_ATY_CT */
 507
 508
 509 static u32 pseudo_palette[17];
 510
 511 #ifdef CONFIG_FB_ATY_GX
 512 static char *aty_gx_ram[8] __initdata = {
 513         ram_dram, ram_vram, ram_vram, ram_dram,
 514         ram_dram, ram_vram, ram_vram, ram_resv
 515 };
 516 #endif /* CONFIG_FB_ATY_GX */
 517
 518 #ifdef CONFIG_FB_ATY_CT
 519 static char *aty_ct_ram[8] __initdata = {
 520         ram_off, ram_dram, ram_edo, ram_edo,
 521         ram_sdram, ram_sgram, ram_sdram32, ram_resv
 522 };
 523 #endif /* CONFIG_FB_ATY_CT */
 524
 525 static u32 atyfb_get_pixclock(struct fb_var_screeninfo *var, struct atyfb_par *par)
 526 {
 527         u32 pixclock = var->pixclock;
 528 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 529         u32 lcd_on_off;
 530         par->pll.ct.xres = 0;
 531         if (par->lcd_table != 0) {
 532                 lcd_on_off = aty_ld_lcd(LCD_GEN_CNTL, par);
 533                 if(lcd_on_off & LCD_ON) {
 534                         par->pll.ct.xres = var->xres;
 535                         pixclock = par->lcd_pixclock;
 536                 }
 537         }
 538 #endif
 539         return pixclock;
 540 }
 541
 542 #if defined(CONFIG_PPC)
 543
 544 /*
 545  *  Apple monitor sense
 546  */
 547
 548 static int __init read_aty_sense(const struct atyfb_par *par)
 549 {
 550         int sense, i;
 551
 552         aty_st_le32(GP_IO, 0x31003100, par); /* drive outputs high */
 553         __delay(200);
 554         aty_st_le32(GP_IO, 0, par); /* turn off outputs */
 555         __delay(2000);
 556         i = aty_ld_le32(GP_IO, par); /* get primary sense value */
 557         sense = ((i & 0x3000) >> 3) | (i & 0x100);
 558
 559         /* drive each sense line low in turn and collect the other 2 */
 560         aty_st_le32(GP_IO, 0x20000000, par); /* drive A low */
 561         __delay(2000);
 562         i = aty_ld_le32(GP_IO, par);
 563         sense |= ((i & 0x1000) >> 7) | ((i & 0x100) >> 4);
 564         aty_st_le32(GP_IO, 0x20002000, par); /* drive A high again */
 565         __delay(200);
 566
 567         aty_st_le32(GP_IO, 0x10000000, par); /* drive B low */
 568         __delay(2000);
 569         i = aty_ld_le32(GP_IO, par);
 570         sense |= ((i & 0x2000) >> 10) | ((i & 0x100) >> 6);
 571         aty_st_le32(GP_IO, 0x10001000, par); /* drive B high again */
 572         __delay(200);
 573
 574         aty_st_le32(GP_IO, 0x01000000, par); /* drive C low */
 575         __delay(2000);
 576         sense |= (aty_ld_le32(GP_IO, par) & 0x3000) >> 12;
 577         aty_st_le32(GP_IO, 0, par); /* turn off outputs */
 578         return sense;
 579 }
 580
 581 #endif /* defined(CONFIG_PPC) */
 582
 583 /* ------------------------------------------------------------------------- */
 584
 585 /*
 586  *  CRTC programming
 587  */
 588
 589 static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc)
 590 {
 591 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 592         if (par->lcd_table != 0) {
 593                 if(!M64_HAS(LT_LCD_REGS)) {
 594                     crtc->lcd_index = aty_ld_le32(LCD_INDEX, par);
 595                     aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
 596                 }
 597                 crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par);
 598                 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par);
 599
 600
 601                 /* switch to non shadow registers */
 602                 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
 603                     ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
 604
 605                 /* save stretching */
 606                 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
 607                 crtc->vert_stretching = aty_ld_lcd(VERT_STRETCHING, par);
 608                 if (!M64_HAS(LT_LCD_REGS))
 609                         crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par);
 610         }
 611 #endif
 612         crtc->h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
 613         crtc->h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
 614         crtc->v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
 615         crtc->v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
 616         crtc->vline_crnt_vline = aty_ld_le32(CRTC_VLINE_CRNT_VLINE, par);
 617         crtc->off_pitch = aty_ld_le32(CRTC_OFF_PITCH, par);
 618         crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
 619
 620 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 621         if (par->lcd_table != 0) {
 622                 /* switch to shadow registers */
 623                 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
 624                         SHADOW_EN | SHADOW_RW_EN, par);
 625
 626                 crtc->shadow_h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
 627                 crtc->shadow_h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
 628                 crtc->shadow_v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
 629                 crtc->shadow_v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
 630
 631                 aty_st_le32(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
 632         }
 633 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
 634 }
 635
 636 static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc)
 637 {
 638 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 639         if (par->lcd_table != 0) {
 640                 /* stop CRTC */
 641                 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~(CRTC_EXT_DISP_EN | CRTC_EN), par);
 642
 643                 /* update non-shadow registers first */
 644                 aty_st_lcd(CONFIG_PANEL, crtc->lcd_config_panel, par);
 645                 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
 646                         ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
 647
 648                 /* temporarily disable stretching */
 649                 aty_st_lcd(HORZ_STRETCHING,
 650                         crtc->horz_stretching &
 651                         ~(HORZ_STRETCH_MODE | HORZ_STRETCH_EN), par);
 652                 aty_st_lcd(VERT_STRETCHING,
 653                         crtc->vert_stretching &
 654                         ~(VERT_STRETCH_RATIO1 | VERT_STRETCH_RATIO2 |
 655                         VERT_STRETCH_USE0 | VERT_STRETCH_EN), par);
 656         }
 657 #endif
 658         /* turn off CRT */
 659         aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~CRTC_EN, par);
 660
 661         DPRINTK("setting up CRTC\n");
 662         DPRINTK("set primary CRT to %ix%i %c%c composite %c\n",
 663             ((((crtc->h_tot_disp>>16) & 0xff) + 1)<<3), (((crtc->v_tot_disp>>16) & 0x7ff) + 1),
 664             (crtc->h_sync_strt_wid & 0x200000)?'N':'P', (crtc->v_sync_strt_wid & 0x200000)?'N':'P',
 665             (crtc->gen_cntl & CRTC_CSYNC_EN)?'P':'N');
 666
 667         DPRINTK("CRTC_H_TOTAL_DISP: %x\n",crtc->h_tot_disp);
 668         DPRINTK("CRTC_H_SYNC_STRT_WID: %x\n",crtc->h_sync_strt_wid);
 669         DPRINTK("CRTC_V_TOTAL_DISP: %x\n",crtc->v_tot_disp);
 670         DPRINTK("CRTC_V_SYNC_STRT_WID: %x\n",crtc->v_sync_strt_wid);
 671         DPRINTK("CRTC_OFF_PITCH: %x\n", crtc->off_pitch);
 672         DPRINTK("CRTC_VLINE_CRNT_VLINE: %x\n", crtc->vline_crnt_vline);
 673         DPRINTK("CRTC_GEN_CNTL: %x\n",crtc->gen_cntl);
 674
 675         aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_tot_disp, par);
 676         aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid, par);
 677         aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_tot_disp, par);
 678         aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid, par);
 679         aty_st_le32(CRTC_OFF_PITCH, crtc->off_pitch, par);
 680         aty_st_le32(CRTC_VLINE_CRNT_VLINE, crtc->vline_crnt_vline, par);
 681
 682         aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl, par);
 683 #if 0
 684         FIXME
 685         if (par->accel_flags & FB_ACCELF_TEXT)
 686                 aty_init_engine(par, info);
 687 #endif
 688 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 689         /* after setting the CRTC registers we should set the LCD registers. */
 690         if (par->lcd_table != 0) {
 691                 /* switch to shadow registers */
 692                 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
 693                         (SHADOW_EN | SHADOW_RW_EN), par);
 694
 695                 DPRINTK("set secondary CRT to %ix%i %c%c\n",
 696                     ((((crtc->shadow_h_tot_disp>>16) & 0xff) + 1)<<3), (((crtc->shadow_v_tot_disp>>16) & 0x7ff) + 1),
 697                     (crtc->shadow_h_sync_strt_wid & 0x200000)?'N':'P', (crtc->shadow_v_sync_strt_wid & 0x200000)?'N':'P');
 698
 699                 DPRINTK("SHADOW CRTC_H_TOTAL_DISP: %x\n", crtc->shadow_h_tot_disp);
 700                 DPRINTK("SHADOW CRTC_H_SYNC_STRT_WID: %x\n", crtc->shadow_h_sync_strt_wid);
 701                 DPRINTK("SHADOW CRTC_V_TOTAL_DISP: %x\n", crtc->shadow_v_tot_disp);
 702                 DPRINTK("SHADOW CRTC_V_SYNC_STRT_WID: %x\n", crtc->shadow_v_sync_strt_wid);
 703
 704                 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->shadow_h_tot_disp, par);
 705                 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->shadow_h_sync_strt_wid, par);
 706                 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->shadow_v_tot_disp, par);
 707                 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->shadow_v_sync_strt_wid, par);
 708
 709                 /* restore CRTC selection & shadow state and enable stretching */
 710                 DPRINTK("LCD_GEN_CNTL: %x\n", crtc->lcd_gen_cntl);
 711                 DPRINTK("HORZ_STRETCHING: %x\n", crtc->horz_stretching);
 712                 DPRINTK("VERT_STRETCHING: %x\n", crtc->vert_stretching);
 713                 if(!M64_HAS(LT_LCD_REGS))
 714                     DPRINTK("EXT_VERT_STRETCH: %x\n", crtc->ext_vert_stretch);
 715
 716                 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
 717                 aty_st_lcd(HORZ_STRETCHING, crtc->horz_stretching, par);
 718                 aty_st_lcd(VERT_STRETCHING, crtc->vert_stretching, par);
 719                 if(!M64_HAS(LT_LCD_REGS)) {
 720                     aty_st_lcd(EXT_VERT_STRETCH, crtc->ext_vert_stretch, par);
 721                     aty_ld_le32(LCD_INDEX, par);
 722                     aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
 723                 }
 724         }
 725 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
 726 }
 727
 728 static int aty_var_to_crtc(const struct fb_info *info,
 729         const struct fb_var_screeninfo *var, struct crtc *crtc)
 730 {
 731         struct atyfb_par *par = (struct atyfb_par *) info->par;
 732         u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp;
 733         u32 sync, vmode, vdisplay;
 734         u32 h_total, h_disp, h_sync_strt, h_sync_end, h_sync_dly, h_sync_wid, h_sync_pol;
 735         u32 v_total, v_disp, v_sync_strt, v_sync_end, v_sync_wid, v_sync_pol, c_sync;
 736         u32 pix_width, dp_pix_width, dp_chain_mask;
 737
 738         /* input */
 739         xres = var->xres;
 740         yres = var->yres;
 741         vxres = var->xres_virtual;
 742         vyres = var->yres_virtual;
 743         xoffset = var->xoffset;
 744         yoffset = var->yoffset;
 745         bpp = var->bits_per_pixel;
 746         if (bpp == 16)
 747                 bpp = (var->green.length == 5) ? 15 : 16;
 748         sync = var->sync;
 749         vmode = var->vmode;
 750
 751         /* convert (and round up) and validate */
 752         if (vxres < xres + xoffset)
 753                 vxres = xres + xoffset;
 754         h_disp = xres;
 755
 756         if (vyres < yres + yoffset)
 757                 vyres = yres + yoffset;
 758         v_disp = yres;
 759
 760         if (bpp <= 8) {
 761                 bpp = 8;
 762                 pix_width = CRTC_PIX_WIDTH_8BPP;
 763                 dp_pix_width =
 764                     HOST_8BPP | SRC_8BPP | DST_8BPP |
 765                     BYTE_ORDER_LSB_TO_MSB;
 766                 dp_chain_mask = DP_CHAIN_8BPP;
 767         } else if (bpp <= 15) {
 768                 bpp = 16;
 769                 pix_width = CRTC_PIX_WIDTH_15BPP;
 770                 dp_pix_width = HOST_15BPP | SRC_15BPP | DST_15BPP |
 771                     BYTE_ORDER_LSB_TO_MSB;
 772                 dp_chain_mask = DP_CHAIN_15BPP;
 773         } else if (bpp <= 16) {
 774                 bpp = 16;
 775                 pix_width = CRTC_PIX_WIDTH_16BPP;
 776                 dp_pix_width = HOST_16BPP | SRC_16BPP | DST_16BPP |
 777                     BYTE_ORDER_LSB_TO_MSB;
 778                 dp_chain_mask = DP_CHAIN_16BPP;
 779         } else if (bpp <= 24 && M64_HAS(INTEGRATED)) {
 780                 bpp = 24;
 781                 pix_width = CRTC_PIX_WIDTH_24BPP;
 782                 dp_pix_width =
 783                     HOST_8BPP | SRC_8BPP | DST_8BPP |
 784                     BYTE_ORDER_LSB_TO_MSB;
 785                 dp_chain_mask = DP_CHAIN_24BPP;
 786         } else if (bpp <= 32) {
 787                 bpp = 32;
 788                 pix_width = CRTC_PIX_WIDTH_32BPP;
 789                 dp_pix_width = HOST_32BPP | SRC_32BPP | DST_32BPP |
 790                     BYTE_ORDER_LSB_TO_MSB;
 791                 dp_chain_mask = DP_CHAIN_32BPP;
 792         } else
 793                 FAIL("invalid bpp");
 794
 795         if (vxres * vyres * bpp / 8 > info->fix.smem_len)
 796                 FAIL("not enough video RAM");
 797
 798         h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
 799         v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
 800
 801         if((xres > 1600) || (yres > 1200)) {
 802                 FAIL("MACH64 chips are designed for max 1600x1200\n"
 803                 "select anoter resolution.");
 804         }
 805         h_sync_strt = h_disp + var->right_margin;
 806         h_sync_end = h_sync_strt + var->hsync_len;
 807         h_sync_dly  = var->right_margin & 7;
 808         h_total = h_sync_end + h_sync_dly + var->left_margin;
 809
 810         v_sync_strt = v_disp + var->lower_margin;
 811         v_sync_end = v_sync_strt + var->vsync_len;
 812         v_total = v_sync_end + var->upper_margin;
 813
 814 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 815         if (par->lcd_table != 0) {
 816                 if(!M64_HAS(LT_LCD_REGS)) {
 817                     u32 lcd_index = aty_ld_le32(LCD_INDEX, par);
 818                     crtc->lcd_index = lcd_index &
 819                         ~(LCD_INDEX_MASK | LCD_DISPLAY_DIS | LCD_SRC_SEL | CRTC2_DISPLAY_DIS);
 820                     aty_st_le32(LCD_INDEX, lcd_index, par);
 821                 }
 822
 823                 if (!M64_HAS(MOBIL_BUS))
 824                         crtc->lcd_index |= CRTC2_DISPLAY_DIS;
 825
 826                 crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par) | 0x4000;
 827                 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par) & ~CRTC_RW_SELECT;
 828
 829                 crtc->lcd_gen_cntl &=
 830                         ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 | TVCLK_PM_EN |
 831                         /*VCLK_DAC_PM_EN | USE_SHADOWED_VEND |*/
 832                         USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
 833                 crtc->lcd_gen_cntl |= DONT_SHADOW_VPAR | LOCK_8DOT;
 834
 835                 if((crtc->lcd_gen_cntl & LCD_ON) &&
 836                         ((xres > par->lcd_width) || (yres > par->lcd_height))) {
 837                         /* We cannot display the mode on the LCD. If the CRT is enabled
 838                            we can turn off the LCD.
 839                            If the CRT is off, it isn't a good idea to switch it on; we don't
 840                            know if one is connected. So it's better to fail then.
 841                          */
 842                         if (crtc->lcd_gen_cntl & CRT_ON) {
 843                                 PRINTKI("Disable lcd panel, because video mode does not fit.\n");
 844                                 crtc->lcd_gen_cntl &= ~LCD_ON;
 845                                 /*aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);*/
 846                         } else {
 847                                 FAIL("Video mode exceeds size of lcd panel.\nConnect this computer to a conventional monitor if you really need this mode.");
 848                         }
 849                 }
 850         }
 851
 852         if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON)) {
 853                 int VScan = 1;
 854                 /* bpp -> bytespp, 1,4 -> 0; 8 -> 2; 15,16 -> 1; 24 -> 6; 32 -> 5
 855                 const u8 DFP_h_sync_dly_LT[] = { 0, 2, 1, 6, 5 };
 856                 const u8 ADD_to_strt_wid_and_dly_LT_DAC[] = { 0, 5, 6, 9, 9, 12, 12 };  */
 857
 858                 vmode &= ~(FB_VMODE_DOUBLE | FB_VMODE_INTERLACED);
 859
 860                 /* This is horror! When we simulate, say 640x480 on an 800x600
 861                    lcd monitor, the CRTC should be programmed 800x600 values for
 862                    the non visible part, but 640x480 for the visible part.
 863                    This code has been tested on a laptop with it's 1400x1050 lcd
 864                    monitor and a conventional monitor both switched on.
 865                    Tested modes: 1280x1024, 1152x864, 1024x768, 800x600,
 866                     works with little glitches also with DOUBLESCAN modes
 867                  */
 868                 if (yres < par->lcd_height) {
 869                         VScan = par->lcd_height / yres;
 870                         if(VScan > 1) {
 871                                 VScan = 2;
 872                                 vmode |= FB_VMODE_DOUBLE;
 873                         }
 874                 }
 875
 876                 h_sync_strt = h_disp + par->lcd_right_margin;
 877                 h_sync_end = h_sync_strt + par->lcd_hsync_len;
 878                 h_sync_dly = /*DFP_h_sync_dly[ ( bpp + 1 ) / 3 ]; */par->lcd_hsync_dly;
 879                 h_total = h_disp + par->lcd_hblank_len;
 880
 881                 v_sync_strt = v_disp + par->lcd_lower_margin / VScan;
 882                 v_sync_end = v_sync_strt + par->lcd_vsync_len / VScan;
 883                 v_total = v_disp + par->lcd_vblank_len / VScan;
 884         }
 885 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
 886
 887         h_disp = (h_disp >> 3) - 1;
 888         h_sync_strt = (h_sync_strt >> 3) - 1;
 889         h_sync_end = (h_sync_end >> 3) - 1;
 890         h_total = (h_total >> 3) - 1;
 891         h_sync_wid = h_sync_end - h_sync_strt;
 892
 893         FAIL_MAX("h_disp too large", h_disp, 0xff);
 894         FAIL_MAX("h_sync_strt too large", h_sync_strt, 0x1ff);
 895         /*FAIL_MAX("h_sync_wid too large", h_sync_wid, 0x1f);*/
 896         if(h_sync_wid > 0x1f)
 897                 h_sync_wid = 0x1f;
 898         FAIL_MAX("h_total too large", h_total, 0x1ff);
 899
 900         if (vmode & FB_VMODE_DOUBLE) {
 901                 v_disp <<= 1;
 902                 v_sync_strt <<= 1;
 903                 v_sync_end <<= 1;
 904                 v_total <<= 1;
 905         }
 906
 907         vdisplay = yres;
 908 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 909         if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON))
 910                 vdisplay  = par->lcd_height;
 911 #endif
 912
 913         if(vdisplay < 400) {
 914                 h_sync_pol = 1;
 915                 v_sync_pol = 0;
 916         } else if(vdisplay < 480) {
 917                 h_sync_pol = 0;
 918                 v_sync_pol = 1;
 919         } else if(vdisplay < 768) {
 920                 h_sync_pol = 0;
 921                 v_sync_pol = 0;
 922         } else {
 923                 h_sync_pol = 1;
 924                 v_sync_pol = 1;
 925         }
 926
 927         v_disp--;
 928         v_sync_strt--;
 929         v_sync_end--;
 930         v_total--;
 931         v_sync_wid = v_sync_end - v_sync_strt;
 932
 933         FAIL_MAX("v_disp too large", v_disp, 0x7ff);
 934         FAIL_MAX("v_sync_stsrt too large", v_sync_strt, 0x7ff);
 935         /*FAIL_MAX("v_sync_wid too large", v_sync_wid, 0x1f);*/
 936         if(v_sync_wid > 0x1f)
 937                 v_sync_wid = 0x1f;
 938         FAIL_MAX("v_total too large", v_total, 0x7ff);
 939
 940         c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? CRTC_CSYNC_EN : 0;
 941
 942         /* output */
 943         crtc->vxres = vxres;
 944         crtc->vyres = vyres;
 945         crtc->xoffset = xoffset;
 946         crtc->yoffset = yoffset;
 947         crtc->bpp = bpp;
 948         crtc->off_pitch = ((yoffset*vxres+xoffset)*bpp/64) | (vxres<<19);
 949         crtc->vline_crnt_vline = 0;
 950
 951         crtc->h_tot_disp = h_total | (h_disp<<16);
 952         crtc->h_sync_strt_wid = (h_sync_strt & 0xff) | (h_sync_dly<<8) |
 953                 ((h_sync_strt & 0x100)<<4) | (h_sync_wid<<16) | (h_sync_pol<<21);
 954         crtc->v_tot_disp = v_total | (v_disp<<16);
 955         crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid<<16) | (v_sync_pol<<21);
 956
 957         /* crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_PRESERVED_MASK; */
 958         crtc->gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN | pix_width | c_sync;
 959         crtc->gen_cntl |= CRTC_VGA_LINEAR;
 960
 961         /* Enable doublescan mode if requested */
 962         if (vmode & FB_VMODE_DOUBLE)
 963                 crtc->gen_cntl |= CRTC_DBL_SCAN_EN;
 964         /* Enable interlaced mode if requested */
 965         if (vmode & FB_VMODE_INTERLACED)
 966                 crtc->gen_cntl |= CRTC_INTERLACE_EN;
 967 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 968         if (par->lcd_table != 0) {
 969                 vdisplay = yres;
 970                 if(vmode & FB_VMODE_DOUBLE)
 971                         vdisplay <<= 1;
 972                 if(vmode & FB_VMODE_INTERLACED) {
 973                         vdisplay >>= 1;
 974
 975                         /* The prefered mode for the lcd is not interlaced, so disable it if
 976                            it was enabled. For doublescan there is no problem, because we can
 977                            compensate for it in the hardware stretching (we stretch half as much)
 978                          */
 979                         vmode &= ~FB_VMODE_INTERLACED;
 980                         /*crtc->gen_cntl &= ~CRTC_INTERLACE_EN;*/
 981                 }
 982                 crtc->gen_cntl &= ~(CRTC2_EN | CRTC2_PIX_WIDTH);
 983                 crtc->lcd_gen_cntl &= ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 |
 984                         /*TVCLK_PM_EN | VCLK_DAC_PM_EN |*/
 985                         USE_SHADOWED_VEND | USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
 986                 crtc->lcd_gen_cntl |= (DONT_SHADOW_VPAR/* | LOCK_8DOT*/);
 987
 988                 /* MOBILITY M1 tested, FIXME: LT */
 989                 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
 990                 if (!M64_HAS(LT_LCD_REGS))
 991                         crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par) &
 992                                 ~(AUTO_VERT_RATIO | VERT_STRETCH_MODE | VERT_STRETCH_RATIO3);
 993
 994                 crtc->horz_stretching &=
 995                         ~(HORZ_STRETCH_RATIO | HORZ_STRETCH_LOOP | AUTO_HORZ_RATIO |
 996                         HORZ_STRETCH_MODE | HORZ_STRETCH_EN);
 997                 if (xres < par->lcd_width) {
 998                         do {
 999                                 /*
1000                                 * The horizontal blender misbehaves when HDisplay is less than a
1001                                 * a certain threshold (440 for a 1024-wide panel).  It doesn't
1002                                 * stretch such modes enough.  Use pixel replication instead of
1003                                 * blending to stretch modes that can be made to exactly fit the
1004                                 * panel width.  The undocumented "NoLCDBlend" option allows the
1005                                 * pixel-replicated mode to be slightly wider or narrower than the
1006                                 * panel width.  It also causes a mode that is exactly half as wide
1007                                 * as the panel to be pixel-replicated, rather than blended.
1008                                 */
1009                                 int HDisplay  = xres & ~7;
1010                                 int nStretch  = par->lcd_width / HDisplay;
1011                                 int Remainder = par->lcd_width % HDisplay;
1012
1013                                 if ((!Remainder && ((nStretch > 2))) ||
1014                                         (((HDisplay * 16) / par->lcd_width) < 7)) {
1015                                         static const char StretchLoops[] = {10, 12, 13, 15, 16};
1016                                         int horz_stretch_loop = -1, BestRemainder;
1017                                         int Numerator = HDisplay, Denominator = par->lcd_width;
1018                                         int Index = 5;
1019                                         ATIReduceRatio(&Numerator, &Denominator);
1020
1021                                         BestRemainder = (Numerator * 16) / Denominator;
1022                                         while (--Index >= 0) {
1023                                                 Remainder = ((Denominator - Numerator) * StretchLoops[Index]) %
1024                                                         Denominator;
1025                                                 if (Remainder < BestRemainder) {
1026                                                         horz_stretch_loop = Index;
1027                                                         if (!(BestRemainder = Remainder))
1028                                                                 break;
1029                                                 }
1030                                         }
1031
1032                                         if ((horz_stretch_loop >= 0) && !BestRemainder) {
1033                                                 int horz_stretch_ratio = 0, Accumulator = 0;
1034                                                 int reuse_previous = 1;
1035
1036                                                 Index = StretchLoops[horz_stretch_loop];
1037
1038                                                 while (--Index >= 0) {
1039                                                         if (Accumulator > 0)
1040                                                                 horz_stretch_ratio |= reuse_previous;
1041                                                         else
1042                                                                 Accumulator += Denominator;
1043                                                         Accumulator -= Numerator;
1044                                                         reuse_previous <<= 1;
1045                                                 }
1046
1047                                                 crtc->horz_stretching |= (HORZ_STRETCH_EN |
1048                                                         ((horz_stretch_loop & HORZ_STRETCH_LOOP) << 16) |
1049                                                         (horz_stretch_ratio & HORZ_STRETCH_RATIO));
1050                                                 break;      /* Out of the do { ... } while (0) */
1051                                         }
1052                                 }
1053
1054                                 crtc->horz_stretching |= (HORZ_STRETCH_MODE | HORZ_STRETCH_EN |
1055                                         (((HDisplay * (HORZ_STRETCH_BLEND + 1)) / par->lcd_width) & HORZ_STRETCH_BLEND));
1056                         } while (0);
1057                 }
1058
1059                 if (vdisplay < par->lcd_height) {
1060                         crtc->vert_stretching = (VERT_STRETCH_USE0 | VERT_STRETCH_EN |
1061                                 (((vdisplay * (VERT_STRETCH_RATIO0 + 1)) / par->lcd_height) & VERT_STRETCH_RATIO0));
1062
1063                         if (!M64_HAS(LT_LCD_REGS) &&
1064                             xres <= (M64_HAS(MOBIL_BUS)?1024:800))
1065                                 crtc->ext_vert_stretch |= VERT_STRETCH_MODE;
1066                 } else {
1067                         /*
1068                          * Don't use vertical blending if the mode is too wide or not
1069                          * vertically stretched.
1070                          */
1071                         crtc->vert_stretching = 0;
1072                 }
1073                 /* copy to shadow crtc */
1074                 crtc->shadow_h_tot_disp = crtc->h_tot_disp;
1075                 crtc->shadow_h_sync_strt_wid = crtc->h_sync_strt_wid;
1076                 crtc->shadow_v_tot_disp = crtc->v_tot_disp;
1077                 crtc->shadow_v_sync_strt_wid = crtc->v_sync_strt_wid;
1078         }
1079 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
1080
1081         if (M64_HAS(MAGIC_FIFO)) {
1082                 /* Not VTB/GTB */
1083                 /* FIXME: magic FIFO values */
1084                 crtc->gen_cntl |= (aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC2_PIX_WIDTH);
1085         }
1086         crtc->dp_pix_width = dp_pix_width;
1087         crtc->dp_chain_mask = dp_chain_mask;
1088
1089         return 0;
1090 }
1091
1092 static int aty_crtc_to_var(const struct crtc *crtc, struct fb_var_screeninfo *var)
1093 {
1094         u32 xres, yres, bpp, left, right, upper, lower, hslen, vslen, sync;
1095         u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid,
1096             h_sync_pol;
1097         u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1098         u32 pix_width;
1099         u32 double_scan, interlace;
1100
1101         /* input */
1102         h_total = crtc->h_tot_disp & 0x1ff;
1103         h_disp = (crtc->h_tot_disp >> 16) & 0xff;
1104         h_sync_strt = (crtc->h_sync_strt_wid & 0xff) | ((crtc->h_sync_strt_wid >> 4) & 0x100);
1105         h_sync_dly = (crtc->h_sync_strt_wid >> 8) & 0x7;
1106         h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x1f;
1107         h_sync_pol = (crtc->h_sync_strt_wid >> 21) & 0x1;
1108         v_total = crtc->v_tot_disp & 0x7ff;
1109         v_disp = (crtc->v_tot_disp >> 16) & 0x7ff;
1110         v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
1111         v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f;
1112         v_sync_pol = (crtc->v_sync_strt_wid >> 21) & 0x1;
1113         c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
1114         pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
1115         double_scan = crtc->gen_cntl & CRTC_DBL_SCAN_EN;
1116         interlace = crtc->gen_cntl & CRTC_INTERLACE_EN;
1117
1118         /* convert */
1119         xres = (h_disp + 1) * 8;
1120         yres = v_disp + 1;
1121         left = (h_total - h_sync_strt - h_sync_wid) * 8 - h_sync_dly;
1122         right = (h_sync_strt - h_disp) * 8 + h_sync_dly;
1123         hslen = h_sync_wid * 8;
1124         upper = v_total - v_sync_strt - v_sync_wid;
1125         lower = v_sync_strt - v_disp;
1126         vslen = v_sync_wid;
1127         sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
1128             (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
1129             (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
1130
1131         switch (pix_width) {
1132 #if 0
1133         case CRTC_PIX_WIDTH_4BPP:
1134                 bpp = 4;
1135                 var->red.offset = 0;
1136                 var->red.length = 8;
1137                 var->green.offset = 0;
1138                 var->green.length = 8;
1139                 var->blue.offset = 0;
1140                 var->blue.length = 8;
1141                 var->transp.offset = 0;
1142                 var->transp.length = 0;
1143                 break;
1144 #endif
1145         case CRTC_PIX_WIDTH_8BPP:
1146                 bpp = 8;
1147                 var->red.offset = 0;
1148                 var->red.length = 8;
1149                 var->green.offset = 0;
1150                 var->green.length = 8;
1151                 var->blue.offset = 0;
1152                 var->blue.length = 8;
1153                 var->transp.offset = 0;
1154                 var->transp.length = 0;
1155                 break;
1156         case CRTC_PIX_WIDTH_15BPP:      /* RGB 555 */
1157                 bpp = 16;
1158                 var->red.offset = 10;
1159                 var->red.length = 5;
1160                 var->green.offset = 5;
1161                 var->green.length = 5;
1162                 var->blue.offset = 0;
1163                 var->blue.length = 5;
1164                 var->transp.offset = 0;
1165                 var->transp.length = 0;
1166                 break;
1167         case CRTC_PIX_WIDTH_16BPP:      /* RGB 565 */
1168                 bpp = 16;
1169                 var->red.offset = 11;
1170                 var->red.length = 5;
1171                 var->green.offset = 5;
1172                 var->green.length = 6;
1173                 var->blue.offset = 0;
1174                 var->blue.length = 5;
1175                 var->transp.offset = 0;
1176                 var->transp.length = 0;
1177                 break;
1178         case CRTC_PIX_WIDTH_24BPP:      /* RGB 888 */
1179                 bpp = 24;
1180                 var->red.offset = 16;
1181                 var->red.length = 8;
1182                 var->green.offset = 8;
1183                 var->green.length = 8;
1184                 var->blue.offset = 0;
1185                 var->blue.length = 8;
1186                 var->transp.offset = 0;
1187                 var->transp.length = 0;
1188                 break;
1189         case CRTC_PIX_WIDTH_32BPP:      /* ARGB 8888 */
1190                 bpp = 32;
1191                 var->red.offset = 16;
1192                 var->red.length = 8;
1193                 var->green.offset = 8;
1194                 var->green.length = 8;
1195                 var->blue.offset = 0;
1196                 var->blue.length = 8;
1197                 var->transp.offset = 24;
1198                 var->transp.length = 8;
1199                 break;
1200         default:
1201                 FAIL("Invalid pixel width");
1202         }
1203
1204         /* output */
1205         var->xres = xres;
1206         var->yres = yres;
1207         var->xres_virtual = crtc->vxres;
1208         var->yres_virtual = crtc->vyres;
1209         var->bits_per_pixel = bpp;
1210         var->left_margin = left;
1211         var->right_margin = right;
1212         var->upper_margin = upper;
1213         var->lower_margin = lower;
1214         var->hsync_len = hslen;
1215         var->vsync_len = vslen;
1216         var->sync = sync;
1217         var->vmode = FB_VMODE_NONINTERLACED;
1218         /* In double scan mode, the vertical parameters are doubled, so we need to
1219            half them to get the right values.
1220            In interlaced mode the values are already correct, so no correction is
1221            necessary.
1222          */
1223         if (interlace)
1224                 var->vmode = FB_VMODE_INTERLACED;
1225
1226         if (double_scan) {
1227                 var->vmode = FB_VMODE_DOUBLE;
1228                 var->yres>>=1;
1229                 var->upper_margin>>=1;
1230                 var->lower_margin>>=1;
1231                 var->vsync_len>>=1;
1232         }
1233
1234         return 0;
1235 }
1236
1237 /* ------------------------------------------------------------------------- */
1238
1239 static int atyfb_set_par(struct fb_info *info)
1240 {
1241         struct atyfb_par *par = (struct atyfb_par *) info->par;
1242         struct fb_var_screeninfo *var = &info->var;
1243         u32 tmp, pixclock;
1244         int err;
1245 #ifdef DEBUG
1246         struct fb_var_screeninfo debug;
1247         u32 pixclock_in_ps;
1248 #endif
1249         if (par->asleep)
1250                 return 0;
1251
1252         if ((err = aty_var_to_crtc(info, var, &par->crtc)))
1253                 return err;
1254
1255         pixclock = atyfb_get_pixclock(var, par);
1256
1257         if (pixclock == 0) {
1258                 FAIL("Invalid pixclock");
1259         } else {
1260                 if((err = par->pll_ops->var_to_pll(info, pixclock, var->bits_per_pixel, &par->pll)))
1261                         return err;
1262         }
1263
1264         par->accel_flags = var->accel_flags; /* hack */
1265
1266         if (par->blitter_may_be_busy)
1267                 wait_for_idle(par);
1268
1269         aty_set_crtc(par, &par->crtc);
1270         par->dac_ops->set_dac(info, &par->pll, var->bits_per_pixel, par->accel_flags);
1271         par->pll_ops->set_pll(info, &par->pll);
1272
1273 #ifdef DEBUG
1274         if(par->pll_ops && par->pll_ops->pll_to_var)
1275                 pixclock_in_ps = par->pll_ops->pll_to_var(info, &(par->pll));
1276         else
1277                 pixclock_in_ps = 0;
1278
1279         if(0 == pixclock_in_ps) {
1280                 PRINTKE("ALERT ops->pll_to_var get 0\n");
1281                 pixclock_in_ps = pixclock;
1282         }
1283
1284         memset(&debug, 0, sizeof(debug));
1285         if(!aty_crtc_to_var(&(par->crtc), &debug)) {
1286                 u32 hSync, vRefresh;
1287                 u32 h_disp, h_sync_strt, h_sync_end, h_total;
1288                 u32 v_disp, v_sync_strt, v_sync_end, v_total;
1289
1290                 h_disp = debug.xres;
1291                 h_sync_strt = h_disp + debug.right_margin;
1292                 h_sync_end = h_sync_strt + debug.hsync_len;
1293                 h_total = h_sync_end + debug.left_margin;
1294                 v_disp = debug.yres;
1295                 v_sync_strt = v_disp + debug.lower_margin;
1296                 v_sync_end = v_sync_strt + debug.vsync_len;
1297                 v_total = v_sync_end + debug.upper_margin;
1298
1299                 hSync = 1000000000 / (pixclock_in_ps * h_total);
1300                 vRefresh = (hSync * 1000) / v_total;
1301                 if (par->crtc.gen_cntl & CRTC_INTERLACE_EN)
1302                 vRefresh *= 2;
1303                 if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1304                 vRefresh /= 2;
1305
1306                 DPRINTK("atyfb_set_par\n");
1307                 DPRINTK(" Set Visible Mode to %ix%i-%i\n", var->xres, var->yres, var->bits_per_pixel);
1308                 DPRINTK(" Virtual resolution %ix%i, pixclock_in_ps %i (calculated %i)\n",
1309                         var->xres_virtual, var->yres_virtual, pixclock, pixclock_in_ps);
1310                 DPRINTK(" Dot clock:           %i MHz\n", 1000000 / pixclock_in_ps);
1311                 DPRINTK(" Horizontal sync:     %i kHz\n", hSync);
1312                 DPRINTK(" Vertical refresh:    %i Hz\n", vRefresh);
1313                 DPRINTK(" x  style: %i.%03i %i %i %i %i   %i %i %i %i\n",
1314                         1000000 / pixclock_in_ps, 1000000 % pixclock_in_ps,
1315                         h_disp, h_sync_strt, h_sync_end, h_total,
1316                         v_disp, v_sync_strt, v_sync_end, v_total);
1317                 DPRINTK(" fb style: %i  %i %i %i %i %i %i %i %i\n",
1318                         pixclock_in_ps,
1319                         debug.left_margin, h_disp, debug.right_margin, debug.hsync_len,
1320                         debug.upper_margin, v_disp, debug.lower_margin, debug.vsync_len);
1321         }
1322 #endif /* DEBUG */
1323
1324         if (!M64_HAS(INTEGRATED)) {
1325                 /* Don't forget MEM_CNTL */
1326                 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf0ffffff;
1327                 switch (var->bits_per_pixel) {
1328                 case 8:
1329                         tmp |= 0x02000000;
1330                         break;
1331                 case 16:
1332                         tmp |= 0x03000000;
1333                         break;
1334                 case 32:
1335                         tmp |= 0x06000000;
1336                         break;
1337                 }
1338                 aty_st_le32(MEM_CNTL, tmp, par);
1339         } else {
1340                 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf00fffff;
1341                 if (!M64_HAS(MAGIC_POSTDIV))
1342                         tmp |= par->mem_refresh_rate << 20;
1343                 switch (var->bits_per_pixel) {
1344                 case 8:
1345                 case 24:
1346                         tmp |= 0x00000000;
1347                         break;
1348                 case 16:
1349                         tmp |= 0x04000000;
1350                         break;
1351                 case 32:
1352                         tmp |= 0x08000000;
1353                         break;
1354                 }
1355                 if (M64_HAS(CT_BUS)) {
1356                         aty_st_le32(DAC_CNTL, 0x87010184, par);
1357                         aty_st_le32(BUS_CNTL, 0x680000f9, par);
1358                 } else if (M64_HAS(VT_BUS)) {
1359                         aty_st_le32(DAC_CNTL, 0x87010184, par);
1360                         aty_st_le32(BUS_CNTL, 0x680000f9, par);
1361                 } else if (M64_HAS(MOBIL_BUS)) {
1362                         aty_st_le32(DAC_CNTL, 0x80010102, par);
1363                         aty_st_le32(BUS_CNTL, 0x7b33a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1364                 } else {
1365                         /* GT */
1366                         aty_st_le32(DAC_CNTL, 0x86010102, par);
1367                         aty_st_le32(BUS_CNTL, 0x7b23a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1368                         aty_st_le32(EXT_MEM_CNTL, aty_ld_le32(EXT_MEM_CNTL, par) | 0x5000001, par);
1369                 }
1370                 aty_st_le32(MEM_CNTL, tmp, par);
1371         }
1372         aty_st_8(DAC_MASK, 0xff, par);
1373
1374         info->fix.line_length = var->xres_virtual * var->bits_per_pixel/8;
1375         info->fix.visual = var->bits_per_pixel <= 8 ?
1376                 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1377
1378         /* Initialize the graphics engine */
1379         if (par->accel_flags & FB_ACCELF_TEXT)
1380                 aty_init_engine(par, info);
1381
1382 #ifdef CONFIG_BOOTX_TEXT
1383         btext_update_display(info->fix.smem_start,
1384                 (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8,
1385                 ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1,
1386                 var->bits_per_pixel,
1387                 par->crtc.vxres * var->bits_per_pixel / 8);
1388 #endif /* CONFIG_BOOTX_TEXT */
1389 #if 0
1390         /* switch to accelerator mode */
1391         if (!(par->crtc.gen_cntl & CRTC_EXT_DISP_EN))
1392                 aty_st_le32(CRTC_GEN_CNTL, par->crtc.gen_cntl | CRTC_EXT_DISP_EN, par);
1393 #endif
1394 #ifdef DEBUG
1395 {
1396         /* dump non shadow CRTC, pll, LCD registers */
1397         int i; u32 base;
1398
1399         /* CRTC registers */
1400         base = 0x2000;
1401         printk("debug atyfb: Mach64 non-shadow register values:");
1402         for (i = 0; i < 256; i = i+4) {
1403                 if(i%16 == 0) printk("\ndebug atyfb: 0x%04X: ", base + i);
1404                 printk(" %08X", aty_ld_le32(i, par));
1405         }
1406         printk("\n\n");
1407
1408 #ifdef CONFIG_FB_ATY_CT
1409         /* PLL registers */
1410         base = 0x00;
1411         printk("debug atyfb: Mach64 PLL register values:");
1412         for (i = 0; i < 64; i++) {
1413                 if(i%16 == 0) printk("\ndebug atyfb: 0x%02X: ", base + i);
1414                 if(i%4 == 0)  printk(" ");
1415                 printk("%02X", aty_ld_pll_ct(i, par));
1416         }
1417         printk("\n\n");
1418 #endif  /* CONFIG_FB_ATY_CT */
1419
1420 #ifdef CONFIG_FB_ATY_GENERIC_LCD
1421         if (par->lcd_table != 0) {
1422                 /* LCD registers */
1423                 base = 0x00;
1424                 printk("debug atyfb: LCD register values:");
1425                 if(M64_HAS(LT_LCD_REGS)) {
1426                     for(i = 0; i <= POWER_MANAGEMENT; i++) {
1427                         if(i == EXT_VERT_STRETCH)
1428                             continue;
1429                         printk("\ndebug atyfb: 0x%04X: ", lt_lcd_regs[i]);
1430                         printk(" %08X", aty_ld_lcd(i, par));
1431                     }
1432
1433                 } else {
1434                     for (i = 0; i < 64; i++) {
1435                         if(i%4 == 0) printk("\ndebug atyfb: 0x%02X: ", base + i);
1436                         printk(" %08X", aty_ld_lcd(i, par));
1437                     }
1438                 }
1439                 printk("\n\n");
1440         }
1441 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
1442 }
1443 #endif /* DEBUG */
1444         return 0;
1445 }
1446
1447 static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1448 {
1449         struct atyfb_par *par = (struct atyfb_par *) info->par;
1450         int err;
1451         struct crtc crtc;
1452         union aty_pll pll;
1453         u32 pixclock;
1454
1455         memcpy(&pll, &(par->pll), sizeof(pll));
1456
1457         if((err = aty_var_to_crtc(info, var, &crtc)))
1458                 return err;
1459
1460         pixclock = atyfb_get_pixclock(var, par);
1461
1462         if (pixclock == 0) {
1463                 FAIL("Invalid pixclock");
1464         } else {
1465                 if((err = par->pll_ops->var_to_pll(info, pixclock, var->bits_per_pixel, &pll)))
1466                         return err;
1467         }
1468
1469         if (var->accel_flags & FB_ACCELF_TEXT)
1470                 info->var.accel_flags = FB_ACCELF_TEXT;
1471         else
1472                 info->var.accel_flags = 0;
1473
1474 #if 0 /* fbmon is not done. uncomment for 2.5.x -brad */
1475         if (!fbmon_valid_timings(pixclock, htotal, vtotal, info))
1476                 return -EINVAL;
1477 #endif
1478         aty_crtc_to_var(&crtc, var);
1479         var->pixclock = par->pll_ops->pll_to_var(info, &pll);
1480         return 0;
1481 }
1482
1483 static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info)
1484 {
1485         u32 xoffset = info->var.xoffset;
1486         u32 yoffset = info->var.yoffset;
1487         u32 vxres = par->crtc.vxres;
1488         u32 bpp = info->var.bits_per_pixel;
1489
1490         par->crtc.off_pitch = ((yoffset * vxres + xoffset) * bpp / 64) | (vxres << 19);
1491 }
1492
1493
1494     /*
1495      *  Open/Release the frame buffer device
1496      */
1497
1498 static int atyfb_open(struct fb_info *info, int user)
1499 {
1500         struct atyfb_par *par = (struct atyfb_par *) info->par;
1501
1502         if (user) {
1503                 par->open++;
1504 #ifdef __sparc__
1505                 par->mmaped = 0;
1506 #endif
1507         }
1508         return (0);
1509 }
1510
1511 static irqreturn_t aty_irq(int irq, void *dev_id, struct pt_regs *fp)
1512 {
1513         struct atyfb_par *par = dev_id;
1514         int handled = 0;
1515         u32 int_cntl;
1516
1517         spin_lock(&par->int_lock);
1518
1519         int_cntl = aty_ld_le32(CRTC_INT_CNTL, par);
1520
1521         if (int_cntl & CRTC_VBLANK_INT) {
1522                 /* clear interrupt */
1523                 aty_st_le32(CRTC_INT_CNTL, (int_cntl & CRTC_INT_EN_MASK) | CRTC_VBLANK_INT_AK, par);
1524                 par->vblank.count++;
1525                 if (par->vblank.pan_display) {
1526                         par->vblank.pan_display = 0;
1527                         aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1528                 }
1529                 wake_up_interruptible(&par->vblank.wait);
1530                 handled = 1;
1531         }
1532
1533         spin_unlock(&par->int_lock);
1534
1535         return IRQ_RETVAL(handled);
1536 }
1537
1538 static int aty_enable_irq(struct atyfb_par *par, int reenable)
1539 {
1540         u32 int_cntl;
1541
1542         if (!test_and_set_bit(0, &par->irq_flags)) {
1543                 if (request_irq(par->irq, aty_irq, SA_SHIRQ, "atyfb", par)) {
1544                         clear_bit(0, &par->irq_flags);
1545                         return -EINVAL;
1546                 }
1547                 spin_lock_irq(&par->int_lock);
1548                 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1549                 /* clear interrupt */
1550                 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_AK, par);
1551                 /* enable interrupt */
1552                 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par);
1553                 spin_unlock_irq(&par->int_lock);
1554         } else if (reenable) {
1555                 spin_lock_irq(&par->int_lock);
1556                 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1557                 if (!(int_cntl & CRTC_VBLANK_INT_EN)) {
1558                         printk("atyfb: someone disabled IRQ [%08x]\n", int_cntl);
1559                         /* re-enable interrupt */
1560                         aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par );
1561                 }
1562                 spin_unlock_irq(&par->int_lock);
1563         }
1564
1565         return 0;
1566 }
1567
1568 static int aty_disable_irq(struct atyfb_par *par)
1569 {
1570         u32 int_cntl;
1571
1572         if (test_and_clear_bit(0, &par->irq_flags)) {
1573                 if (par->vblank.pan_display) {
1574                         par->vblank.pan_display = 0;
1575                         aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1576                 }
1577                 spin_lock_irq(&par->int_lock);
1578                 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1579                 /* disable interrupt */
1580                 aty_st_le32(CRTC_INT_CNTL, int_cntl & ~CRTC_VBLANK_INT_EN, par );
1581                 spin_unlock_irq(&par->int_lock);
1582                 free_irq(par->irq, par);
1583         }
1584
1585         return 0;
1586 }
1587
1588 static int atyfb_release(struct fb_info *info, int user)
1589 {
1590         struct atyfb_par *par = (struct atyfb_par *) info->par;
1591         if (user) {
1592                 par->open--;
1593                 mdelay(1);
1594                 wait_for_idle(par);
1595                 if (!par->open) {
1596 #ifdef __sparc__
1597                         int was_mmaped = par->mmaped;
1598
1599                         par->mmaped = 0;
1600
1601                         if (was_mmaped) {
1602                                 struct fb_var_screeninfo var;
1603
1604                                 /* Now reset the default display config, we have no
1605                                  * idea what the program(s) which mmap'd the chip did
1606                                  * to the configuration, nor whether it restored it
1607                                  * correctly.
1608                                  */
1609                                 var = default_var;
1610                                 if (noaccel)
1611                                         var.accel_flags &= ~FB_ACCELF_TEXT;
1612                                 else
1613                                         var.accel_flags |= FB_ACCELF_TEXT;
1614                                 if (var.yres == var.yres_virtual) {
1615                                         u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
1616                                         var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual;
1617                                         if (var.yres_virtual < var.yres)
1618                                                 var.yres_virtual = var.yres;
1619                                 }
1620                         }
1621 #endif
1622                         aty_disable_irq(par);
1623                 }
1624         }
1625         return (0);
1626 }
1627
1628     /*
1629      *  Pan or Wrap the Display
1630      *
1631      *  This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1632      */
1633
1634 static int atyfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
1635 {
1636         struct atyfb_par *par = (struct atyfb_par *) info->par;
1637         u32 xres, yres, xoffset, yoffset;
1638
1639         xres = (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8;
1640         yres = ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1;
1641         if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1642                 yres >>= 1;
1643         xoffset = (var->xoffset + 7) & ~7;
1644         yoffset = var->yoffset;
1645         if (xoffset + xres > par->crtc.vxres || yoffset + yres > par->crtc.vyres)
1646                 return -EINVAL;
1647         info->var.xoffset = xoffset;
1648         info->var.yoffset = yoffset;
1649         if (par->asleep)
1650                 return 0;
1651
1652         set_off_pitch(par, info);
1653         if ((var->activate & FB_ACTIVATE_VBL) && !aty_enable_irq(par, 0)) {
1654                 par->vblank.pan_display = 1;
1655         } else {
1656                 par->vblank.pan_display = 0;
1657                 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1658         }
1659
1660         return 0;
1661 }
1662
1663 static int aty_waitforvblank(struct atyfb_par *par, u32 crtc)
1664 {
1665         struct aty_interrupt *vbl;
1666         unsigned int count;
1667         int ret;
1668
1669         switch (crtc) {
1670         case 0:
1671                 vbl = &par->vblank;
1672                 break;
1673         default:
1674                 return -ENODEV;
1675         }
1676
1677         ret = aty_enable_irq(par, 0);
1678         if (ret)
1679                 return ret;
1680
1681         count = vbl->count;
1682         ret = wait_event_interruptible_timeout(vbl->wait, count != vbl->count, HZ/10);
1683         if (ret < 0) {
1684                 return ret;
1685         }
1686         if (ret == 0) {
1687                 aty_enable_irq(par, 1);
1688                 return -ETIMEDOUT;
1689         }
1690
1691         return 0;
1692 }
1693
1694
1695 #ifdef DEBUG
1696 #define ATYIO_CLKR              0x41545900      /* ATY\00 */
1697 #define ATYIO_CLKW              0x41545901      /* ATY\01 */
1698
1699 struct atyclk {
1700         u32 ref_clk_per;
1701         u8 pll_ref_div;
1702         u8 mclk_fb_div;
1703         u8 mclk_post_div;       /* 1,2,3,4,8 */
1704         u8 mclk_fb_mult;        /* 2 or 4 */
1705         u8 xclk_post_div;       /* 1,2,3,4,8 */
1706         u8 vclk_fb_div;
1707         u8 vclk_post_div;       /* 1,2,3,4,6,8,12 */
1708         u32 dsp_xclks_per_row;  /* 0-16383 */
1709         u32 dsp_loop_latency;   /* 0-15 */
1710         u32 dsp_precision;      /* 0-7 */
1711         u32 dsp_on;             /* 0-2047 */
1712         u32 dsp_off;            /* 0-2047 */
1713 };
1714
1715 #define ATYIO_FEATR             0x41545902      /* ATY\02 */
1716 #define ATYIO_FEATW             0x41545903      /* ATY\03 */
1717 #endif
1718
1719 #ifndef FBIO_WAITFORVSYNC
1720 #define FBIO_WAITFORVSYNC _IOW('F', 0x20, __u32)
1721 #endif
1722
1723 static int atyfb_ioctl(struct inode *inode, struct file *file, u_int cmd,
1724         u_long arg, struct fb_info *info)
1725 {
1726         struct atyfb_par *par = (struct atyfb_par *) info->par;
1727 #ifdef __sparc__
1728         struct fbtype fbtyp;
1729 #endif
1730
1731         switch (cmd) {
1732 #ifdef __sparc__
1733         case FBIOGTYPE:
1734                 fbtyp.fb_type = FBTYPE_PCI_GENERIC;
1735                 fbtyp.fb_width = par->crtc.vxres;
1736                 fbtyp.fb_height = par->crtc.vyres;
1737                 fbtyp.fb_depth = info->var.bits_per_pixel;
1738                 fbtyp.fb_cmsize = info->cmap.len;
1739                 fbtyp.fb_size = info->fix.smem_len;
1740                 if (copy_to_user((struct fbtype __user *) arg, &fbtyp, sizeof(fbtyp)))
1741                         return -EFAULT;
1742                 break;
1743 #endif /* __sparc__ */
1744
1745         case FBIO_WAITFORVSYNC:
1746                 {
1747                         u32 crtc;
1748
1749                         if (get_user(crtc, (__u32 __user *) arg))
1750                                 return -EFAULT;
1751
1752                         return aty_waitforvblank(par, crtc);
1753                 }
1754                 break;
1755
1756 #if defined(DEBUG) && defined(CONFIG_FB_ATY_CT)
1757         case ATYIO_CLKR:
1758                 if (M64_HAS(INTEGRATED)) {
1759                         struct atyclk clk;
1760                         union aty_pll *pll = &(par->pll);
1761                         u32 dsp_config = pll->ct.dsp_config;
1762                         u32 dsp_on_off = pll->ct.dsp_on_off;
1763                         clk.ref_clk_per = par->ref_clk_per;
1764                         clk.pll_ref_div = pll->ct.pll_ref_div;
1765                         clk.mclk_fb_div = pll->ct.mclk_fb_div;
1766                         clk.mclk_post_div = pll->ct.mclk_post_div_real;
1767                         clk.mclk_fb_mult = pll->ct.mclk_fb_mult;
1768                         clk.xclk_post_div = pll->ct.xclk_post_div_real;
1769                         clk.vclk_fb_div = pll->ct.vclk_fb_div;
1770                         clk.vclk_post_div = pll->ct.vclk_post_div_real;
1771                         clk.dsp_xclks_per_row = dsp_config & 0x3fff;
1772                         clk.dsp_loop_latency = (dsp_config >> 16) & 0xf;
1773                         clk.dsp_precision = (dsp_config >> 20) & 7;
1774                         clk.dsp_off = dsp_on_off & 0x7ff;
1775                         clk.dsp_on = (dsp_on_off >> 16) & 0x7ff;
1776                         if (copy_to_user((struct atyclk __user *) arg, &clk,
1777                                          sizeof(clk)))
1778                                 return -EFAULT;
1779                 } else
1780                         return -EINVAL;
1781                 break;
1782         case ATYIO_CLKW:
1783                 if (M64_HAS(INTEGRATED)) {
1784                         struct atyclk clk;
1785                         union aty_pll *pll = &(par->pll);
1786                         if (copy_from_user(&clk, (struct atyclk __user *) arg, sizeof(clk)))
1787                                 return -EFAULT;
1788                         par->ref_clk_per = clk.ref_clk_per;
1789                         pll->ct.pll_ref_div = clk.pll_ref_div;
1790                         pll->ct.mclk_fb_div = clk.mclk_fb_div;
1791                         pll->ct.mclk_post_div_real = clk.mclk_post_div;
1792                         pll->ct.mclk_fb_mult = clk.mclk_fb_mult;
1793                         pll->ct.xclk_post_div_real = clk.xclk_post_div;
1794                         pll->ct.vclk_fb_div = clk.vclk_fb_div;
1795                         pll->ct.vclk_post_div_real = clk.vclk_post_div;
1796                         pll->ct.dsp_config = (clk.dsp_xclks_per_row & 0x3fff) |
1797                                 ((clk.dsp_loop_latency & 0xf)<<16)| ((clk.dsp_precision & 7)<<20);
1798                         pll->ct.dsp_on_off = (clk.dsp_off & 0x7ff) | ((clk.dsp_on & 0x7ff)<<16);
1799                         /*aty_calc_pll_ct(info, &pll->ct);*/
1800                         aty_set_pll_ct(info, pll);
1801                 } else
1802                         return -EINVAL;
1803                 break;
1804         case ATYIO_FEATR:
1805                 if (get_user(par->features, (u32 __user *) arg))
1806                         return -EFAULT;
1807                 break;
1808         case ATYIO_FEATW:
1809                 if (put_user(par->features, (u32 __user *) arg))
1810                         return -EFAULT;
1811                 break;
1812 #endif /* DEBUG && CONFIG_FB_ATY_CT */
1813         default:
1814                 return -EINVAL;
1815         }
1816         return 0;
1817 }
1818
1819 static int atyfb_sync(struct fb_info *info)
1820 {
1821         struct atyfb_par *par = (struct atyfb_par *) info->par;
1822
1823         if (par->blitter_may_be_busy)
1824                 wait_for_idle(par);
1825         return 0;
1826 }
1827
1828 #ifdef __sparc__
1829 static int atyfb_mmap(struct fb_info *info, struct file *file, struct vm_area_struct *vma)
1830 {
1831         struct atyfb_par *par = (struct atyfb_par *) info->par;
1832         unsigned int size, page, map_size = 0;
1833         unsigned long map_offset = 0;
1834         unsigned long off;
1835         int i;
1836
1837         if (!par->mmap_map)
1838                 return -ENXIO;
1839
1840         if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
1841                 return -EINVAL;
1842
1843         off = vma->vm_pgoff << PAGE_SHIFT;
1844         size = vma->vm_end - vma->vm_start;
1845
1846         /* To stop the swapper from even considering these pages. */
1847         vma->vm_flags |= (VM_IO | VM_RESERVED);
1848
1849         if (((vma->vm_pgoff == 0) && (size == info->fix.smem_len)) ||
1850             ((off == info->fix.smem_len) && (size == PAGE_SIZE)))
1851                 off += 0x8000000000000000UL;
1852
1853         vma->vm_pgoff = off >> PAGE_SHIFT;      /* propagate off changes */
1854
1855         /* Each page, see which map applies */
1856         for (page = 0; page < size;) {
1857                 map_size = 0;
1858                 for (i = 0; par->mmap_map[i].size; i++) {
1859                         unsigned long start = par->mmap_map[i].voff;
1860                         unsigned long end = start + par->mmap_map[i].size;
1861                         unsigned long offset = off + page;
1862
1863                         if (start > offset)
1864                                 continue;
1865                         if (offset >= end)
1866                                 continue;
1867
1868                         map_size = par->mmap_map[i].size - (offset - start);
1869                         map_offset =
1870                             par->mmap_map[i].poff + (offset - start);
1871                         break;
1872                 }
1873                 if (!map_size) {
1874                         page += PAGE_SIZE;
1875                         continue;
1876                 }
1877                 if (page + map_size > size)
1878                         map_size = size - page;
1879
1880                 pgprot_val(vma->vm_page_prot) &=
1881                     ~(par->mmap_map[i].prot_mask);
1882                 pgprot_val(vma->vm_page_prot) |= par->mmap_map[i].prot_flag;
1883
1884                 if (remap_pfn_range(vma, vma->vm_start + page,
1885                         map_offset >> PAGE_SHIFT, map_size, vma->vm_page_prot))
1886                         return -EAGAIN;
1887
1888                 page += map_size;
1889         }
1890
1891         if (!map_size)
1892                 return -EINVAL;
1893
1894         if (!par->mmaped)
1895                 par->mmaped = 1;
1896         return 0;
1897 }
1898
1899 static struct {
1900         u32 yoffset;
1901         u8 r[2][256];
1902         u8 g[2][256];
1903         u8 b[2][256];
1904 } atyfb_save;
1905
1906 static void atyfb_save_palette(struct atyfb_par *par, int enter)
1907 {
1908         int i, tmp;
1909
1910         for (i = 0; i < 256; i++) {
1911                 tmp = aty_ld_8(DAC_CNTL, par) & 0xfc;
1912                 if (M64_HAS(EXTRA_BRIGHT))
1913                         tmp |= 0x2;
1914                 aty_st_8(DAC_CNTL, tmp, par);
1915                 aty_st_8(DAC_MASK, 0xff, par);
1916
1917                 writeb(i, &par->aty_cmap_regs->rindex);
1918                 atyfb_save.r[enter][i] = readb(&par->aty_cmap_regs->lut);
1919                 atyfb_save.g[enter][i] = readb(&par->aty_cmap_regs->lut);
1920                 atyfb_save.b[enter][i] = readb(&par->aty_cmap_regs->lut);
1921                 writeb(i, &par->aty_cmap_regs->windex);
1922                 writeb(atyfb_save.r[1 - enter][i],
1923                        &par->aty_cmap_regs->lut);
1924                 writeb(atyfb_save.g[1 - enter][i],
1925                        &par->aty_cmap_regs->lut);
1926                 writeb(atyfb_save.b[1 - enter][i],
1927                        &par->aty_cmap_regs->lut);
1928         }
1929 }
1930
1931 static void atyfb_palette(int enter)
1932 {
1933         struct atyfb_par *par;
1934         struct fb_info *info;
1935         int i;
1936
1937         for (i = 0; i < FB_MAX; i++) {
1938                 info = registered_fb[i];
1939                 if (info && info->fbops == &atyfb_ops) {
1940                         par = (struct atyfb_par *) info->par;
1941
1942                         atyfb_save_palette(par, enter);
1943                         if (enter) {
1944                                 atyfb_save.yoffset = info->var.yoffset;
1945                                 info->var.yoffset = 0;
1946                                 set_off_pitch(par, info);
1947                         } else {
1948                                 info->var.yoffset = atyfb_save.yoffset;
1949                                 set_off_pitch(par, info);
1950                         }
1951                         aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1952                         break;
1953                 }
1954         }
1955 }
1956 #endif /* __sparc__ */
1957
1958
1959
1960 #if defined(CONFIG_PM) && defined(CONFIG_PCI)
1961
1962 /* Power management routines. Those are used for PowerBook sleep.
1963  */
1964 static int aty_power_mgmt(int sleep, struct atyfb_par *par)
1965 {
1966         u32 pm;
1967         int timeout;
1968
1969         pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1970         pm = (pm & ~PWR_MGT_MODE_MASK) | PWR_MGT_MODE_REG;
1971         aty_st_lcd(POWER_MANAGEMENT, pm, par);
1972         pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1973
1974         timeout = 2000;
1975         if (sleep) {
1976                 /* Sleep */
1977                 pm &= ~PWR_MGT_ON;
1978                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1979                 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1980                 udelay(10);
1981                 pm &= ~(PWR_BLON | AUTO_PWR_UP);
1982                 pm |= SUSPEND_NOW;
1983                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1984                 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1985                 udelay(10);
1986                 pm |= PWR_MGT_ON;
1987                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1988                 do {
1989                         pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1990                         mdelay(1);
1991                         if ((--timeout) == 0)
1992                                 break;
1993                 } while ((pm & PWR_MGT_STATUS_MASK) != PWR_MGT_STATUS_SUSPEND);
1994         } else {
1995                 /* Wakeup */
1996                 pm &= ~PWR_MGT_ON;
1997                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1998                 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1999                 udelay(10);
2000                 pm &= ~SUSPEND_NOW;
2001                 pm |= (PWR_BLON | AUTO_PWR_UP);
2002                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2003                 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2004                 udelay(10);
2005                 pm |= PWR_MGT_ON;
2006                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2007                 do {
2008                         pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2009                         mdelay(1);
2010                         if ((--timeout) == 0)
2011                                 break;
2012                 } while ((pm & PWR_MGT_STATUS_MASK) != 0);
2013         }
2014         mdelay(500);
2015
2016         return timeout ? 0 : -EIO;
2017 }
2018
2019 static int atyfb_pci_suspend(struct pci_dev *pdev, u32 state)
2020 {
2021         struct fb_info *info = pci_get_drvdata(pdev);
2022         struct atyfb_par *par = (struct atyfb_par *) info->par;
2023
2024 #ifdef CONFIG_PPC_PMAC
2025         /* HACK ALERT ! Once I find a proper way to say to each driver
2026          * individually what will happen with it's PCI slot, I'll change
2027          * that. On laptops, the AGP slot is just unclocked, so D2 is
2028          * expected, while on desktops, the card is powered off
2029          */
2030         if (state >= 3)
2031                 state = 2;
2032 #endif /* CONFIG_PPC_PMAC */
2033
2034         if (state != 2 || state == pdev->dev.power.power_state)
2035                 return 0;
2036
2037         acquire_console_sem();
2038
2039         fb_set_suspend(info, 1);
2040
2041         /* Idle & reset engine */
2042         wait_for_idle(par);
2043         aty_reset_engine(par);
2044
2045         /* Blank display and LCD */
2046         atyfb_blank(FB_BLANK_POWERDOWN, info);
2047
2048         par->asleep = 1;
2049         par->lock_blank = 1;
2050
2051         /* Set chip to "suspend" mode */
2052         if (aty_power_mgmt(1, par)) {
2053                 par->asleep = 0;
2054                 par->lock_blank = 0;
2055                 atyfb_blank(FB_BLANK_UNBLANK, info);
2056                 fb_set_suspend(info, 0);
2057                 release_console_sem();
2058                 return -EIO;
2059         }
2060
2061         release_console_sem();
2062
2063         pdev->dev.power.power_state = state;
2064
2065         return 0;
2066 }
2067
2068 static int atyfb_pci_resume(struct pci_dev *pdev)
2069 {
2070         struct fb_info *info = pci_get_drvdata(pdev);
2071         struct atyfb_par *par = (struct atyfb_par *) info->par;
2072
2073         if (pdev->dev.power.power_state == 0)
2074                 return 0;
2075
2076         acquire_console_sem();
2077
2078         if (pdev->dev.power.power_state == 2)
2079                 aty_power_mgmt(0, par);
2080         par->asleep = 0;
2081
2082         /* Restore display */
2083         atyfb_set_par(info);
2084
2085         /* Refresh */
2086         fb_set_suspend(info, 0);
2087
2088         /* Unblank */
2089         par->lock_blank = 0;
2090         atyfb_blank(FB_BLANK_UNBLANK, info);
2091
2092         release_console_sem();
2093
2094         pdev->dev.power.power_state = 0;
2095
2096         return 0;
2097 }
2098
2099 #endif /*  defined(CONFIG_PM) && defined(CONFIG_PCI) */
2100
2101 #ifdef CONFIG_PMAC_BACKLIGHT
2102
2103     /*
2104      *   LCD backlight control
2105      */
2106
2107 static int backlight_conv[] = {
2108         0x00, 0x3f, 0x4c, 0x59, 0x66, 0x73, 0x80, 0x8d,
2109         0x9a, 0xa7, 0xb4, 0xc1, 0xcf, 0xdc, 0xe9, 0xff
2110 };
2111
2112 static int aty_set_backlight_enable(int on, int level, void *data)
2113 {
2114         struct fb_info *info = (struct fb_info *) data;
2115         struct atyfb_par *par = (struct atyfb_par *) info->par;
2116         unsigned int reg = aty_ld_lcd(LCD_MISC_CNTL, par);
2117
2118         reg |= (BLMOD_EN | BIASMOD_EN);
2119         if (on && level > BACKLIGHT_OFF) {
2120                 reg &= ~BIAS_MOD_LEVEL_MASK;
2121                 reg |= (backlight_conv[level] << BIAS_MOD_LEVEL_SHIFT);
2122         } else {
2123                 reg &= ~BIAS_MOD_LEVEL_MASK;
2124                 reg |= (backlight_conv[0] << BIAS_MOD_LEVEL_SHIFT);
2125         }
2126         aty_st_lcd(LCD_MISC_CNTL, reg, par);
2127         return 0;
2128 }
2129
2130 static int aty_set_backlight_level(int level, void *data)
2131 {
2132         return aty_set_backlight_enable(1, level, data);
2133 }
2134
2135 static struct backlight_controller aty_backlight_controller = {
2136         aty_set_backlight_enable,
2137         aty_set_backlight_level
2138 };
2139 #endif /* CONFIG_PMAC_BACKLIGHT */
2140
2141 static void __init aty_calc_mem_refresh(struct atyfb_par *par, int xclk)
2142 {
2143         const int ragepro_tbl[] = {
2144                 44, 50, 55, 66, 75, 80, 100
2145         };
2146         const int ragexl_tbl[] = {
2147                 50, 66, 75, 83, 90, 95, 100, 105,
2148                 110, 115, 120, 125, 133, 143, 166
2149         };
2150         const int *refresh_tbl;
2151         int i, size;
2152
2153         if (IS_XL(par->pci_id) || IS_MOBILITY(par->pci_id)) {
2154                 refresh_tbl = ragexl_tbl;
2155                 size = sizeof(ragexl_tbl)/sizeof(int);
2156         } else {
2157                 refresh_tbl = ragepro_tbl;
2158                 size = sizeof(ragepro_tbl)/sizeof(int);
2159         }
2160
2161         for (i=0; i < size; i++) {
2162                 if (xclk < refresh_tbl[i])
2163                 break;
2164         }
2165         par->mem_refresh_rate = i;
2166 }
2167
2168     /*
2169      *  Initialisation
2170      */
2171
2172 static struct fb_info *fb_list = NULL;
2173
2174 static int __init aty_init(struct fb_info *info, const char *name)
2175 {
2176         struct atyfb_par *par = (struct atyfb_par *) info->par;
2177         const char *ramname = NULL, *xtal;
2178         int gtb_memsize;
2179         struct fb_var_screeninfo var;
2180         u8 pll_ref_div;
2181         u32 i;
2182 #if defined(CONFIG_PPC)
2183         int sense;
2184 #endif
2185
2186         init_waitqueue_head(&par->vblank.wait);
2187         spin_lock_init(&par->int_lock);
2188
2189         par->aty_cmap_regs =
2190             (struct aty_cmap_regs __iomem *) (par->ati_regbase + 0xc0);
2191
2192 #ifdef CONFIG_PPC_PMAC
2193         /* The Apple iBook1 uses non-standard memory frequencies. We detect it
2194          * and set the frequency manually. */
2195         if (machine_is_compatible("PowerBook2,1")) {
2196                 par->pll_limits.mclk = 70;
2197                 par->pll_limits.xclk = 53;
2198         }
2199 #endif
2200         if (pll)
2201                 par->pll_limits.pll_max = pll;
2202         if (mclk)
2203                 par->pll_limits.mclk = mclk;
2204         if (xclk)
2205                 par->pll_limits.xclk = xclk;
2206
2207         aty_calc_mem_refresh(par, par->pll_limits.xclk);
2208         par->pll_per = 1000000/par->pll_limits.pll_max;
2209         par->mclk_per = 1000000/par->pll_limits.mclk;
2210         par->xclk_per = 1000000/par->pll_limits.xclk;
2211
2212         par->ref_clk_per = 1000000000000ULL / 14318180;
2213         xtal = "14.31818";
2214
2215 #ifdef CONFIG_FB_ATY_GX
2216         if (!M64_HAS(INTEGRATED)) {
2217                 u32 stat0;
2218                 u8 dac_type, dac_subtype, clk_type;
2219                 stat0 = aty_ld_le32(CONFIG_STAT0, par);
2220                 par->bus_type = (stat0 >> 0) & 0x07;
2221                 par->ram_type = (stat0 >> 3) & 0x07;
2222                 ramname = aty_gx_ram[par->ram_type];
2223                 /* FIXME: clockchip/RAMDAC probing? */
2224                 dac_type = (aty_ld_le32(DAC_CNTL, par) >> 16) & 0x07;
2225 #ifdef CONFIG_ATARI
2226                 clk_type = CLK_ATI18818_1;
2227                 dac_type = (stat0 >> 9) & 0x07;
2228                 if (dac_type == 0x07)
2229                         dac_subtype = DAC_ATT20C408;
2230                 else
2231                         dac_subtype = (aty_ld_8(SCRATCH_REG1 + 1, par) & 0xF0) | dac_type;
2232 #else
2233                 dac_type = DAC_IBMRGB514;
2234                 dac_subtype = DAC_IBMRGB514;
2235                 clk_type = CLK_IBMRGB514;
2236 #endif
2237                 switch (dac_subtype) {
2238                 case DAC_IBMRGB514:
2239                         par->dac_ops = &aty_dac_ibm514;
2240                         break;
2241                 case DAC_ATI68860_B:
2242                 case DAC_ATI68860_C:
2243                         par->dac_ops = &aty_dac_ati68860b;
2244                         break;
2245                 case DAC_ATT20C408:
2246                 case DAC_ATT21C498:
2247                         par->dac_ops = &aty_dac_att21c498;
2248                         break;
2249                 default:
2250                         PRINTKI("aty_init: DAC type not implemented yet!\n");
2251                         par->dac_ops = &aty_dac_unsupported;
2252                         break;
2253                 }
2254                 switch (clk_type) {
2255                 case CLK_ATI18818_1:
2256                         par->pll_ops = &aty_pll_ati18818_1;
2257                         break;
2258                 case CLK_STG1703:
2259                         par->pll_ops = &aty_pll_stg1703;
2260                         break;
2261                 case CLK_CH8398:
2262                         par->pll_ops = &aty_pll_ch8398;
2263                         break;
2264                 case CLK_ATT20C408:
2265                         par->pll_ops = &aty_pll_att20c408;
2266                         break;
2267                 case CLK_IBMRGB514:
2268                         par->pll_ops = &aty_pll_ibm514;
2269                         break;
2270                 default:
2271                         PRINTKI("aty_init: CLK type not implemented yet!");
2272                         par->pll_ops = &aty_pll_unsupported;
2273                         break;
2274                 }
2275         }
2276 #endif /* CONFIG_FB_ATY_GX */
2277 #ifdef CONFIG_FB_ATY_CT
2278         if (M64_HAS(INTEGRATED)) {
2279                 par->dac_ops = &aty_dac_ct;
2280                 par->pll_ops = &aty_pll_ct;
2281                 par->bus_type = PCI;
2282 #ifdef CONFIG_FB_ATY_XL_INIT
2283                 if (IS_XL(par->pci_id))
2284                         atyfb_xl_init(info);
2285 #endif
2286                 par->ram_type = (aty_ld_le32(CONFIG_STAT0, par) & 0x07);
2287                 ramname = aty_ct_ram[par->ram_type];
2288                 /* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */
2289                 if (par->pll_limits.mclk == 67 && par->ram_type < SDRAM)
2290                         par->pll_limits.mclk = 63;
2291         }
2292
2293         if (M64_HAS(GTB_DSP)
2294             && (pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par))) {
2295                 int diff1, diff2;
2296                 diff1 = 510 * 14 / pll_ref_div - par->pll_limits.pll_max;
2297                 diff2 = 510 * 29 / pll_ref_div - par->pll_limits.pll_max;
2298                 if (diff1 < 0)
2299                         diff1 = -diff1;
2300                 if (diff2 < 0)
2301                         diff2 = -diff2;
2302                 if (diff2 < diff1) {
2303                         par->ref_clk_per = 1000000000000ULL / 29498928;
2304                         xtal = "29.498928";
2305                 }
2306         }
2307 #endif /* CONFIG_FB_ATY_CT */
2308
2309         /* save previous video mode */
2310         aty_get_crtc(par, &saved_crtc);
2311         if(par->pll_ops->get_pll)
2312                 par->pll_ops->get_pll(info, &saved_pll);
2313
2314         i = aty_ld_le32(MEM_CNTL, par);
2315         gtb_memsize = M64_HAS(GTB_DSP);
2316         if (gtb_memsize)
2317                 switch (i & 0xF) {      /* 0xF used instead of MEM_SIZE_ALIAS */
2318                 case MEM_SIZE_512K:
2319                         info->fix.smem_len = 0x80000;
2320                         break;
2321                 case MEM_SIZE_1M:
2322                         info->fix.smem_len = 0x100000;
2323                         break;
2324                 case MEM_SIZE_2M_GTB:
2325                         info->fix.smem_len = 0x200000;
2326                         break;
2327                 case MEM_SIZE_4M_GTB:
2328                         info->fix.smem_len = 0x400000;
2329                         break;
2330                 case MEM_SIZE_6M_GTB:
2331                         info->fix.smem_len = 0x600000;
2332                         break;
2333                 case MEM_SIZE_8M_GTB:
2334                         info->fix.smem_len = 0x800000;
2335                         break;
2336                 default:
2337                         info->fix.smem_len = 0x80000;
2338         } else
2339                 switch (i & MEM_SIZE_ALIAS) {
2340                 case MEM_SIZE_512K:
2341                         info->fix.smem_len = 0x80000;
2342                         break;
2343                 case MEM_SIZE_1M:
2344                         info->fix.smem_len = 0x100000;
2345                         break;
2346                 case MEM_SIZE_2M:
2347                         info->fix.smem_len = 0x200000;
2348                         break;
2349                 case MEM_SIZE_4M:
2350                         info->fix.smem_len = 0x400000;
2351                         break;
2352                 case MEM_SIZE_6M:
2353                         info->fix.smem_len = 0x600000;
2354                         break;
2355                 case MEM_SIZE_8M:
2356                         info->fix.smem_len = 0x800000;
2357                         break;
2358                 default:
2359                         info->fix.smem_len = 0x80000;
2360                 }
2361
2362         if (M64_HAS(MAGIC_VRAM_SIZE)) {
2363                 if (aty_ld_le32(CONFIG_STAT1, par) & 0x40000000)
2364                         info->fix.smem_len += 0x400000;
2365         }
2366
2367         if (vram) {
2368                 info->fix.smem_len = vram * 1024;
2369                 i = i & ~(gtb_memsize ? 0xF : MEM_SIZE_ALIAS);
2370                 if (info->fix.smem_len <= 0x80000)
2371                         i |= MEM_SIZE_512K;
2372                 else if (info->fix.smem_len <= 0x100000)
2373                         i |= MEM_SIZE_1M;
2374                 else if (info->fix.smem_len <= 0x200000)
2375                         i |= gtb_memsize ? MEM_SIZE_2M_GTB : MEM_SIZE_2M;
2376                 else if (info->fix.smem_len <= 0x400000)
2377                         i |= gtb_memsize ? MEM_SIZE_4M_GTB : MEM_SIZE_4M;
2378                 else if (info->fix.smem_len <= 0x600000)
2379                         i |= gtb_memsize ? MEM_SIZE_6M_GTB : MEM_SIZE_6M;
2380                 else
2381                         i |= gtb_memsize ? MEM_SIZE_8M_GTB : MEM_SIZE_8M;
2382                 aty_st_le32(MEM_CNTL, i, par);
2383         }
2384
2385         /*
2386          *  Reg Block 0 (CT-compatible block) is at mmio_start
2387          *  Reg Block 1 (multimedia extensions) is at mmio_start - 0x400
2388          */
2389         if (M64_HAS(GX)) {
2390                 info->fix.mmio_len = 0x400;
2391                 info->fix.accel = FB_ACCEL_ATI_MACH64GX;
2392         } else if (M64_HAS(CT)) {
2393                 info->fix.mmio_len = 0x400;
2394                 info->fix.accel = FB_ACCEL_ATI_MACH64CT;
2395         } else if (M64_HAS(VT)) {
2396                 info->fix.mmio_start -= 0x400;
2397                 info->fix.mmio_len = 0x800;
2398                 info->fix.accel = FB_ACCEL_ATI_MACH64VT;
2399         } else {/* GT */
2400                 info->fix.mmio_start -= 0x400;
2401                 info->fix.mmio_len = 0x800;
2402                 info->fix.accel = FB_ACCEL_ATI_MACH64GT;
2403         }
2404
2405         PRINTKI("%d%c %s, %s MHz XTAL, %d MHz PLL, %d Mhz MCLK, %d MHz XCLK\n",
2406                info->fix.smem_len == 0x80000 ? 512 : (info->fix.smem_len >> 20),
2407                info->fix.smem_len == 0x80000 ? 'K' : 'M', ramname, xtal, par->pll_limits.pll_max,
2408                par->pll_limits.mclk, par->pll_limits.xclk);
2409
2410 #if defined(DEBUG) && defined(CONFIG_ATY_CT)
2411         if (M64_HAS(INTEGRATED)) {
2412                 int i;
2413                 printk("debug atyfb: BUS_CNTL DAC_CNTL MEM_CNTL EXT_MEM_CNTL CRTC_GEN_CNTL "
2414                        "DSP_CONFIG DSP_ON_OFF CLOCK_CNTL\n"
2415                        "debug atyfb: %08x %08x %08x %08x     %08x      %08x   %08x   %08x\n"
2416                        "debug atyfb: PLL",
2417                         aty_ld_le32(BUS_CNTL, par), aty_ld_le32(DAC_CNTL, par),
2418                         aty_ld_le32(MEM_CNTL, par), aty_ld_le32(EXT_MEM_CNTL, par),
2419                         aty_ld_le32(CRTC_GEN_CNTL, par), aty_ld_le32(DSP_CONFIG, par),
2420                         aty_ld_le32(DSP_ON_OFF, par), aty_ld_le32(CLOCK_CNTL, par));
2421                 for (i = 0; i < 40; i++)
2422                         printk(" %02x", aty_ld_pll_ct(i, par));
2423                 printk("\n");
2424         }
2425 #endif
2426         if(par->pll_ops->init_pll)
2427                 par->pll_ops->init_pll(info, &par->pll);
2428
2429         /*
2430          *  Last page of 8 MB (4 MB on ISA) aperture is MMIO
2431          *  FIXME: we should use the auxiliary aperture instead so we can access
2432          *  the full 8 MB of video RAM on 8 MB boards
2433          */
2434
2435         if (!par->aux_start &&
2436                 (info->fix.smem_len == 0x800000 || (par->bus_type == ISA && info->fix.smem_len == 0x400000)))
2437                 info->fix.smem_len -= GUI_RESERVE;
2438
2439         /*
2440          *  Disable register access through the linear aperture
2441          *  if the auxiliary aperture is used so we can access
2442          *  the full 8 MB of video RAM on 8 MB boards.
2443          */
2444         if (par->aux_start)
2445                 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL, par) | BUS_APER_REG_DIS, par);
2446
2447 #ifdef CONFIG_MTRR
2448         par->mtrr_aper = -1;
2449         par->mtrr_reg = -1;
2450         if (!nomtrr) {
2451                 /* Cover the whole resource. */
2452                  par->mtrr_aper = mtrr_add(par->res_start, par->res_size, MTRR_TYPE_WRCOMB, 1);
2453                  if (par->mtrr_aper >= 0 && !par->aux_start) {
2454                         /* Make a hole for mmio. */
2455                         par->mtrr_reg = mtrr_add(par->res_start + 0x800000 - GUI_RESERVE,
2456                                 GUI_RESERVE, MTRR_TYPE_UNCACHABLE, 1);
2457                         if (par->mtrr_reg < 0) {
2458                                 mtrr_del(par->mtrr_aper, 0, 0);
2459                                 par->mtrr_aper = -1;
2460                         }
2461                  }
2462         }
2463 #endif
2464
2465         info->fbops = &atyfb_ops;
2466         info->pseudo_palette = pseudo_palette;
2467         info->flags = FBINFO_FLAG_DEFAULT;
2468
2469 #ifdef CONFIG_PMAC_BACKLIGHT
2470         if (M64_HAS(G3_PB_1_1) && machine_is_compatible("PowerBook1,1")) {
2471                 /* these bits let the 101 powerbook wake up from sleep -- paulus */
2472                 aty_st_lcd(POWER_MANAGEMENT, aty_ld_lcd(POWER_MANAGEMENT, par)
2473                            | (USE_F32KHZ | TRISTATE_MEM_EN), par);
2474         } else if (M64_HAS(MOBIL_BUS))
2475                 register_backlight_controller(&aty_backlight_controller, info, "ati");
2476 #endif /* CONFIG_PMAC_BACKLIGHT */
2477
2478         memset(&var, 0, sizeof(var));
2479 #ifdef CONFIG_PPC
2480         if (_machine == _MACH_Pmac) {
2481                 /*
2482                  *  FIXME: The NVRAM stuff should be put in a Mac-specific file, as it
2483                  *         applies to all Mac video cards
2484                  */
2485                 if (mode) {
2486                         if (!mac_find_mode(&var, info, mode, 8))
2487                                 var = default_var;
2488                 } else {
2489                         if (default_vmode == VMODE_CHOOSE) {
2490                                 if (M64_HAS(G3_PB_1024x768))
2491                                         /* G3 PowerBook with 1024x768 LCD */
2492                                         default_vmode = VMODE_1024_768_60;
2493                                 else if (machine_is_compatible("iMac"))
2494                                         default_vmode = VMODE_1024_768_75;
2495                                 else if (machine_is_compatible
2496                                          ("PowerBook2,1"))
2497                                         /* iBook with 800x600 LCD */
2498                                         default_vmode = VMODE_800_600_60;
2499                                 else
2500                                         default_vmode = VMODE_640_480_67;
2501                                 sense = read_aty_sense(par);
2502                                 PRINTKI("monitor sense=%x, mode %d\n",
2503                                         sense,  mac_map_monitor_sense(sense));
2504                         }
2505                         if (default_vmode <= 0 || default_vmode > VMODE_MAX)
2506                                 default_vmode = VMODE_640_480_60;
2507                         if (default_cmode < CMODE_8 || default_cmode > CMODE_32)
2508                                 default_cmode = CMODE_8;
2509                         if (mac_vmode_to_var(default_vmode, default_cmode, &var))
2510                                 var = default_var;
2511                 }
2512         } else
2513 #endif /* !CONFIG_PPC */
2514         if (
2515 #if defined(CONFIG_SPARC32) || defined(CONFIG_SPARC64)
2516            /* On Sparc, unless the user gave a specific mode
2517             * specification, use the PROM probed values in
2518             * default_var.
2519             */
2520             !mode ||
2521 #endif
2522             !fb_find_mode(&var, info, mode, NULL, 0, &defmode, 8))
2523                 var = default_var;
2524
2525         if (noaccel)
2526                 var.accel_flags &= ~FB_ACCELF_TEXT;
2527         else
2528                 var.accel_flags |= FB_ACCELF_TEXT;
2529
2530         if (var.yres == var.yres_virtual) {
2531                 u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
2532                 var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual;
2533                 if (var.yres_virtual < var.yres)
2534                         var.yres_virtual = var.yres;
2535         }
2536
2537         if (atyfb_check_var(&var, info)) {
2538                 PRINTKE("can't set default video mode\n");
2539                 goto aty_init_exit;
2540         }
2541
2542 #ifdef __sparc__
2543         atyfb_save_palette(par, 0);
2544 #endif
2545
2546 #ifdef CONFIG_FB_ATY_CT
2547         if (!noaccel && M64_HAS(INTEGRATED))
2548                 aty_init_cursor(info);
2549 #endif /* CONFIG_FB_ATY_CT */
2550         info->var = var;
2551
2552         fb_alloc_cmap(&info->cmap, 256, 0);
2553
2554         if (register_framebuffer(info) < 0)
2555                 goto aty_init_exit;
2556
2557         fb_list = info;
2558
2559         PRINTKI("fb%d: %s frame buffer device on %s\n",
2560                info->node, info->fix.id, name);
2561         return 0;
2562
2563 aty_init_exit:
2564         /* restore video mode */
2565         aty_set_crtc(par, &saved_crtc);
2566         par->pll_ops->set_pll(info, &saved_pll);
2567
2568 #ifdef CONFIG_MTRR
2569         if (par->mtrr_reg >= 0) {
2570             mtrr_del(par->mtrr_reg, 0, 0);
2571             par->mtrr_reg = -1;
2572         }
2573         if (par->mtrr_aper >= 0) {
2574             mtrr_del(par->mtrr_aper, 0, 0);
2575             par->mtrr_aper = -1;
2576         }
2577 #endif
2578         return -1;
2579 }
2580
2581 #ifdef CONFIG_ATARI
2582 static int __init store_video_par(char *video_str, unsigned char m64_num)
2583 {
2584         char *p;
2585         unsigned long vmembase, size, guiregbase;
2586
2587         PRINTKI("store_video_par() '%s' \n", video_str);
2588
2589         if (!(p = strsep(&video_str, ";")) || !*p)
2590                 goto mach64_invalid;
2591         vmembase = simple_strtoul(p, NULL, 0);
2592         if (!(p = strsep(&video_str, ";")) || !*p)
2593                 goto mach64_invalid;
2594         size = simple_strtoul(p, NULL, 0);
2595         if (!(p = strsep(&video_str, ";")) || !*p)
2596                 goto mach64_invalid;
2597         guiregbase = simple_strtoul(p, NULL, 0);
2598
2599         phys_vmembase[m64_num] = vmembase;
2600         phys_size[m64_num] = size;
2601         phys_guiregbase[m64_num] = guiregbase;
2602         PRINTKI("stored them all: $%08lX $%08lX $%08lX \n", vmembase, size,
2603                guiregbase);
2604         return 0;
2605
2606       mach64_invalid:
2607         phys_vmembase[m64_num] = 0;
2608         return -1;
2609 }
2610 #endif /* CONFIG_ATARI */
2611
2612     /*
2613      *  Blank the display.
2614      */
2615
2616 static int atyfb_blank(int blank, struct fb_info *info)
2617 {
2618         struct atyfb_par *par = (struct atyfb_par *) info->par;
2619         u8 gen_cntl;
2620
2621         if (par->lock_blank || par->asleep)
2622                 return 0;
2623
2624 #ifdef CONFIG_PMAC_BACKLIGHT
2625         if ((_machine == _MACH_Pmac) && blank)
2626                 set_backlight_enable(0);
2627 #elif defined(CONFIG_FB_ATY_GENERIC_LCD)
2628         if (par->lcd_table && blank &&
2629             (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2630                 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2631                 pm &= ~PWR_BLON;
2632                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2633         }
2634 #endif
2635
2636         gen_cntl = aty_ld_8(CRTC_GEN_CNTL, par);
2637         switch (blank) {
2638                 case FB_BLANK_UNBLANK:
2639                         gen_cntl &= ~(0x4c);
2640                         break;
2641                 case FB_BLANK_NORMAL:
2642                         gen_cntl |= 0x40;
2643                         break;
2644                 case FB_BLANK_VSYNC_SUSPEND:
2645                         gen_cntl |= 0x8;
2646                         break;
2647                 case FB_BLANK_HSYNC_SUSPEND:
2648                         gen_cntl |= 0x4;
2649                         break;
2650                 case FB_BLANK_POWERDOWN:
2651                         gen_cntl |= 0x4c;
2652                         break;
2653         }
2654         aty_st_8(CRTC_GEN_CNTL, gen_cntl, par);
2655
2656 #ifdef CONFIG_PMAC_BACKLIGHT
2657         if ((_machine == _MACH_Pmac) && !blank)
2658                 set_backlight_enable(1);
2659 #elif defined(CONFIG_FB_ATY_GENERIC_LCD)
2660         if (par->lcd_table && !blank &&
2661             (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2662                 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2663                 pm |= PWR_BLON;
2664                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2665         }
2666 #endif
2667
2668         return 0;
2669 }
2670
2671 static void aty_st_pal(u_int regno, u_int red, u_int green, u_int blue,
2672                        const struct atyfb_par *par)
2673 {
2674 #ifdef CONFIG_ATARI
2675         out_8(&par->aty_cmap_regs->windex, regno);
2676         out_8(&par->aty_cmap_regs->lut, red);
2677         out_8(&par->aty_cmap_regs->lut, green);
2678         out_8(&par->aty_cmap_regs->lut, blue);
2679 #else
2680         writeb(regno, &par->aty_cmap_regs->windex);
2681         writeb(red, &par->aty_cmap_regs->lut);
2682         writeb(green, &par->aty_cmap_regs->lut);
2683         writeb(blue, &par->aty_cmap_regs->lut);
2684 #endif
2685 }
2686
2687     /*
2688      *  Set a single color register. The values supplied are already
2689      *  rounded down to the hardware's capabilities (according to the
2690      *  entries in the var structure). Return != 0 for invalid regno.
2691      *  !! 4 & 8 =  PSEUDO, > 8 = DIRECTCOLOR
2692      */
2693
2694 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
2695         u_int transp, struct fb_info *info)
2696 {
2697         struct atyfb_par *par = (struct atyfb_par *) info->par;
2698         int i, depth;
2699         u32 *pal = info->pseudo_palette;
2700
2701         depth = info->var.bits_per_pixel;
2702         if (depth == 16)
2703                 depth = (info->var.green.length == 5) ? 15 : 16;
2704
2705         if (par->asleep)
2706                 return 0;
2707
2708         if (regno > 255 ||
2709             (depth == 16 && regno > 63) ||
2710             (depth == 15 && regno > 31))
2711                 return 1;
2712
2713         red >>= 8;
2714         green >>= 8;
2715         blue >>= 8;
2716
2717         par->palette[regno].red = red;
2718         par->palette[regno].green = green;
2719         par->palette[regno].blue = blue;
2720
2721         if (regno < 16) {
2722                 switch (depth) {
2723                 case 15:
2724                         pal[regno] = (regno << 10) | (regno << 5) | regno;
2725                         break;
2726                 case 16:
2727                         pal[regno] = (regno << 11) | (regno << 5) | regno;
2728                         break;
2729                 case 24:
2730                         pal[regno] = (regno << 16) | (regno << 8) | regno;
2731                         break;
2732                 case 32:
2733                         i = (regno << 8) | regno;
2734                         pal[regno] = (i << 16) | i;
2735                         break;
2736                 }
2737         }
2738
2739         i = aty_ld_8(DAC_CNTL, par) & 0xfc;
2740         if (M64_HAS(EXTRA_BRIGHT))
2741                 i |= 0x2; /* DAC_CNTL | 0x2 turns off the extra brightness for gt */
2742         aty_st_8(DAC_CNTL, i, par);
2743         aty_st_8(DAC_MASK, 0xff, par);
2744
2745         if (M64_HAS(INTEGRATED)) {
2746                 if (depth == 16) {
2747                         if (regno < 32)
2748                                 aty_st_pal(regno << 3, red,
2749                                            par->palette[regno<<1].green,
2750                                            blue, par);
2751                         red = par->palette[regno>>1].red;
2752                         blue = par->palette[regno>>1].blue;
2753                         regno <<= 2;
2754                 } else if (depth == 15) {
2755                         regno <<= 3;
2756                         for(i = 0; i < 8; i++) {
2757                             aty_st_pal(regno + i, red, green, blue, par);
2758                         }
2759                 }
2760         }
2761         aty_st_pal(regno, red, green, blue, par);
2762
2763         return 0;
2764 }
2765
2766 #ifdef CONFIG_PCI
2767
2768 #ifdef __sparc__
2769
2770 extern void (*prom_palette) (int);
2771
2772 static int __devinit atyfb_setup_sparc(struct pci_dev *pdev,
2773                         struct fb_info *info, unsigned long addr)
2774 {
2775         extern int con_is_present(void);
2776
2777         struct atyfb_par *par = info->par;
2778         struct pcidev_cookie *pcp;
2779         char prop[128];
2780         int node, len, i, j, ret;
2781         u32 mem, chip_id;
2782
2783         /* Do not attach when we have a serial console. */
2784         if (!con_is_present())
2785                 return -ENXIO;
2786
2787         /*
2788          * Map memory-mapped registers.
2789          */
2790         par->ati_regbase = (void *)addr + 0x7ffc00UL;
2791         info->fix.mmio_start = addr + 0x7ffc00UL;
2792
2793         /*
2794          * Map in big-endian aperture.
2795          */
2796         info->screen_base = (char *) (addr + 0x800000UL);
2797         info->fix.smem_start = addr + 0x800000UL;
2798
2799         /*
2800          * Figure mmap addresses from PCI config space.
2801          * Split Framebuffer in big- and little-endian halfs.
2802          */
2803         for (i = 0; i < 6 && pdev->resource[i].start; i++)
2804                 /* nothing */ ;
2805         j = i + 4;
2806
2807         par->mmap_map = kmalloc(j * sizeof(*par->mmap_map), GFP_ATOMIC);
2808         if (!par->mmap_map) {
2809                 PRINTKE("atyfb_setup_sparc() can't alloc mmap_map\n");
2810                 return -ENOMEM;
2811         }
2812         memset(par->mmap_map, 0, j * sizeof(*par->mmap_map));
2813
2814         for (i = 0, j = 2; i < 6 && pdev->resource[i].start; i++) {
2815                 struct resource *rp = &pdev->resource[i];
2816                 int io, breg = PCI_BASE_ADDRESS_0 + (i << 2);
2817                 unsigned long base;
2818                 u32 size, pbase;
2819
2820                 base = rp->start;
2821
2822                 io = (rp->flags & IORESOURCE_IO);
2823
2824                 size = rp->end - base + 1;
2825
2826                 pci_read_config_dword(pdev, breg, &pbase);
2827
2828                 if (io)
2829                         size &= ~1;
2830
2831                 /*
2832                  * Map the framebuffer a second time, this time without
2833                  * the braindead _PAGE_IE setting. This is used by the
2834                  * fixed Xserver, but we need to maintain the old mapping
2835                  * to stay compatible with older ones...
2836                  */
2837                 if (base == addr) {
2838                         par->mmap_map[j].voff = (pbase + 0x10000000) & PAGE_MASK;
2839                         par->mmap_map[j].poff = base & PAGE_MASK;
2840                         par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
2841                         par->mmap_map[j].prot_mask = _PAGE_CACHE;
2842                         par->mmap_map[j].prot_flag = _PAGE_E;
2843                         j++;
2844                 }
2845
2846                 /*
2847                  * Here comes the old framebuffer mapping with _PAGE_IE
2848                  * set for the big endian half of the framebuffer...
2849                  */
2850                 if (base == addr) {
2851                         par->mmap_map[j].voff = (pbase + 0x800000) & PAGE_MASK;
2852                         par->mmap_map[j].poff = (base + 0x800000) & PAGE_MASK;
2853                         par->mmap_map[j].size = 0x800000;
2854                         par->mmap_map[j].prot_mask = _PAGE_CACHE;
2855                         par->mmap_map[j].prot_flag = _PAGE_E | _PAGE_IE;
2856                         size -= 0x800000;
2857                         j++;
2858                 }
2859
2860                 par->mmap_map[j].voff = pbase & PAGE_MASK;
2861                 par->mmap_map[j].poff = base & PAGE_MASK;
2862                 par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
2863                 par->mmap_map[j].prot_mask = _PAGE_CACHE;
2864                 par->mmap_map[j].prot_flag = _PAGE_E;
2865                 j++;
2866         }
2867
2868         if((ret = correct_chipset(par)))
2869                 return ret;
2870
2871         if (IS_XL(pdev->device)) {
2872                 /*
2873                  * Fix PROMs idea of MEM_CNTL settings...
2874                  */
2875                 mem = aty_ld_le32(MEM_CNTL, par);
2876                 chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
2877                 if (((chip_id & CFG_CHIP_TYPE) == VT_CHIP_ID) && !((chip_id >> 24) & 1)) {
2878                         switch (mem & 0x0f) {
2879                         case 3:
2880                                 mem = (mem & ~(0x0f)) | 2;
2881                                 break;
2882                         case 7:
2883                                 mem = (mem & ~(0x0f)) | 3;
2884                                 break;
2885                         case 9:
2886                                 mem = (mem & ~(0x0f)) | 4;
2887                                 break;
2888                         case 11:
2889                                 mem = (mem & ~(0x0f)) | 5;
2890                                 break;
2891                         default:
2892                                 break;
2893                         }
2894                         if ((aty_ld_le32(CONFIG_STAT0, par) & 7) >= SDRAM)
2895                                 mem &= ~(0x00700000);
2896                 }
2897                 mem &= ~(0xcf80e000);   /* Turn off all undocumented bits. */
2898                 aty_st_le32(MEM_CNTL, mem, par);
2899         }
2900
2901         /*
2902          * If this is the console device, we will set default video
2903          * settings to what the PROM left us with.
2904          */
2905         node = prom_getchild(prom_root_node);
2906         node = prom_searchsiblings(node, "aliases");
2907         if (node) {
2908                 len = prom_getproperty(node, "screen", prop, sizeof(prop));
2909                 if (len > 0) {
2910                         prop[len] = '\0';
2911                         node = prom_finddevice(prop);
2912                 } else
2913                         node = 0;
2914         }
2915
2916         pcp = pdev->sysdata;
2917         if (node == pcp->prom_node) {
2918                 struct fb_var_screeninfo *var = &default_var;
2919                 unsigned int N, P, Q, M, T, R;
2920                 u32 v_total, h_total;
2921                 struct crtc crtc;
2922                 u8 pll_regs[16];
2923                 u8 clock_cntl;
2924
2925                 crtc.vxres = prom_getintdefault(node, "width", 1024);
2926                 crtc.vyres = prom_getintdefault(node, "height", 768);
2927                 var->bits_per_pixel = prom_getintdefault(node, "depth", 8);
2928                 var->xoffset = var->yoffset = 0;
2929                 crtc.h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
2930                 crtc.h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
2931                 crtc.v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
2932                 crtc.v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
2933                 crtc.gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
2934                 aty_crtc_to_var(&crtc, var);
2935
2936                 h_total = var->xres + var->right_margin + var->hsync_len + var->left_margin;
2937                 v_total = var->yres + var->lower_margin + var->vsync_len + var->upper_margin;
2938
2939                 /*
2940                  * Read the PLL to figure actual Refresh Rate.
2941                  */
2942                 clock_cntl = aty_ld_8(CLOCK_CNTL, par);
2943                 /* DPRINTK("CLOCK_CNTL %02x\n", clock_cntl); */
2944                 for (i = 0; i < 16; i++)
2945                         pll_regs[i] = aty_ld_pll_ct(i, par);
2946
2947                 /*
2948                  * PLL Reference Divider M:
2949                  */
2950                 M = pll_regs[2];
2951
2952                 /*
2953                  * PLL Feedback Divider N (Dependant on CLOCK_CNTL):
2954                  */
2955                 N = pll_regs[7 + (clock_cntl & 3)];
2956
2957                 /*
2958                  * PLL Post Divider P (Dependant on CLOCK_CNTL):
2959                  */
2960                 P = 1 << (pll_regs[6] >> ((clock_cntl & 3) << 1));
2961
2962                 /*
2963                  * PLL Divider Q:
2964                  */
2965                 Q = N / P;
2966
2967                 /*
2968                  * Target Frequency:
2969                  *
2970                  *      T * M
2971                  * Q = -------
2972                  *      2 * R
2973                  *
2974                  * where R is XTALIN (= 14318 or 29498 kHz).
2975                  */
2976                 if (IS_XL(pdev->device))
2977                         R = 29498;
2978                 else
2979                         R = 14318;
2980
2981                 T = 2 * Q * R / M;
2982
2983                 default_var.pixclock = 1000000000 / T;
2984         }
2985
2986         return 0;
2987 }
2988
2989 #else /* __sparc__ */
2990
2991 #ifdef __i386__
2992 #ifdef CONFIG_FB_ATY_GENERIC_LCD
2993 void aty_init_lcd(struct atyfb_par *par, u32 bios_base)
2994 {
2995         u32 driv_inf_tab, sig;
2996         u16 lcd_ofs;
2997
2998         /* To support an LCD panel, we should know it's dimensions and
2999          *  it's desired pixel clock.
3000          * There are two ways to do it:
3001          *  - Check the startup video mode and calculate the panel
3002          *    size from it. This is unreliable.
3003          *  - Read it from the driver information table in the video BIOS.
3004         */
3005         /* Address of driver information table is at offset 0x78. */
3006         driv_inf_tab = bios_base + *((u16 *)(bios_base+0x78));
3007
3008         /* Check for the driver information table signature. */
3009         sig = (*(u32 *)driv_inf_tab);
3010         if ((sig == 0x54504c24) || /* Rage LT pro */
3011                 (sig == 0x544d5224) || /* Rage mobility */
3012                 (sig == 0x54435824) || /* Rage XC */
3013                 (sig == 0x544c5824)) { /* Rage XL */
3014                 PRINTKI("BIOS contains driver information table.\n");
3015                 lcd_ofs = (*(u16 *)(driv_inf_tab + 10));
3016                 par->lcd_table = 0;
3017                 if (lcd_ofs != 0) {
3018                         par->lcd_table = bios_base + lcd_ofs;
3019                 }
3020         }
3021
3022         if (par->lcd_table != 0) {
3023                 char model[24];
3024                 char strbuf[16];
3025                 char refresh_rates_buf[100];
3026                 int id, tech, f, i, m, default_refresh_rate;
3027                 char *txtcolour;
3028                 char *txtmonitor;
3029                 char *txtdual;
3030                 char *txtformat;
3031                 u16 width, height, panel_type, refresh_rates;
3032                 u16 *lcdmodeptr;
3033                 u32 format;
3034                 u8 lcd_refresh_rates[16] = {50,56,60,67,70,72,75,76,85,90,100,120,140,150,160,200};
3035                 /* The most important information is the panel size at
3036                  * offset 25 and 27, but there's some other nice information
3037                  * which we print to the screen.
3038                  */
3039                 id = *(u8 *)par->lcd_table;
3040                 strncpy(model,(char *)par->lcd_table+1,24);
3041                 model[23]=0;
3042
3043                 width = par->lcd_width = *(u16 *)(par->lcd_table+25);
3044                 height = par->lcd_height = *(u16 *)(par->lcd_table+27);
3045                 panel_type = *(u16 *)(par->lcd_table+29);
3046                 if (panel_type & 1)
3047                         txtcolour = "colour";
3048                 else
3049                         txtcolour = "monochrome";
3050                 if (panel_type & 2)
3051                         txtdual = "dual (split) ";
3052                 else
3053                         txtdual = "";
3054                 tech = (panel_type>>2) & 63;
3055                 switch (tech) {
3056                 case 0:
3057                         txtmonitor = "passive matrix";
3058                         break;
3059                 case 1:
3060                         txtmonitor = "active matrix";
3061                         break;
3062                 case 2:
3063                         txtmonitor = "active addressed STN";
3064                         break;
3065                 case 3:
3066                         txtmonitor = "EL";
3067                         break;
3068                 case 4:
3069                         txtmonitor = "plasma";
3070                         break;
3071                 default:
3072                         txtmonitor = "unknown";
3073                 }
3074                 format = *(u32 *)(par->lcd_table+57);
3075                 if (tech == 0 || tech == 2) {
3076                         switch (format & 7) {
3077                         case 0:
3078                                 txtformat = "12 bit interface";
3079                                 break;
3080                         case 1:
3081                                 txtformat = "16 bit interface";
3082                                 break;
3083                         case 2:
3084                                 txtformat = "24 bit interface";
3085                                 break;
3086                         default:
3087                                 txtformat = "unkown format";
3088                         }
3089                 } else {
3090                         switch (format & 7) {
3091                         case 0:
3092                                 txtformat = "8 colours";
3093                                 break;
3094                         case 1:
3095                                 txtformat = "512 colours";
3096                                 break;
3097                         case 2:
3098                                 txtformat = "4096 colours";
3099                                 break;
3100                         case 4:
3101                                 txtformat = "262144 colours (LT mode)";
3102                                 break;
3103                         case 5:
3104                                 txtformat = "16777216 colours";
3105                                 break;
3106                         case 6:
3107                                 txtformat = "262144 colours (FDPI-2 mode)";
3108                                 break;
3109                         default:
3110                                 txtformat = "unkown format";
3111                         }
3112                 }
3113                 PRINTKI("%s%s %s monitor detected: %s\n",
3114                         txtdual ,txtcolour, txtmonitor, model);
3115                 PRINTKI("       id=%d, %dx%d pixels, %s\n",
3116                         id, width, height, txtformat);
3117                 refresh_rates_buf[0] = 0;
3118                 refresh_rates = *(u16 *)(par->lcd_table+62);
3119                 m = 1;
3120                 f = 0;
3121                 for (i=0;i<16;i++) {
3122                         if (refresh_rates & m) {
3123                                 if (f == 0) {
3124                                         sprintf(strbuf, "%d", lcd_refresh_rates[i]);
3125                                         f++;
3126                                 } else {
3127                                         sprintf(strbuf, ",%d", lcd_refresh_rates[i]);
3128                                 }
3129                                 strcat(refresh_rates_buf,strbuf);
3130                         }
3131                         m = m << 1;
3132                 }
3133                 default_refresh_rate = (*(u8 *)(par->lcd_table+61) & 0xf0) >> 4;
3134                 PRINTKI("       supports refresh rates [%s], default %d Hz\n",
3135                         refresh_rates_buf, lcd_refresh_rates[default_refresh_rate]);
3136                 par->lcd_refreshrate = lcd_refresh_rates[default_refresh_rate];
3137                 /* We now need to determine the crtc parameters for the
3138                  * lcd monitor. This is tricky, because they are not stored
3139                  * individually in the BIOS. Instead, the BIOS contains a
3140                  * table of display modes that work for this monitor.
3141                  *
3142                  * The idea is that we search for a mode of the same dimensions
3143                  * as the dimensions of the lcd monitor. Say our lcd monitor
3144                  * is 800x600 pixels, we search for a 800x600 monitor.
3145                  * The CRTC parameters we find here are the ones that we need
3146                  * to use to simulate other resolutions on the lcd screen.
3147                  */
3148                 lcdmodeptr = (u16 *)(par->lcd_table + 64);
3149                 while (*lcdmodeptr != 0) {
3150                         u32 modeptr;
3151                         u16 mwidth, mheight, lcd_hsync_start, lcd_vsync_start;
3152                         modeptr = bios_base + *lcdmodeptr;
3153
3154                         mwidth = *((u16 *)(modeptr+0));
3155                         mheight = *((u16 *)(modeptr+2));
3156
3157                         if (mwidth == width && mheight == height) {
3158                                 par->lcd_pixclock = 100000000 / *((u16 *)(modeptr+9));
3159                                 par->lcd_htotal = *((u16 *)(modeptr+17)) & 511;
3160                                 par->lcd_hdisp = *((u16 *)(modeptr+19)) & 511;
3161                                 lcd_hsync_start = *((u16 *)(modeptr+21)) & 511;
3162                                 par->lcd_hsync_dly = (*((u16 *)(modeptr+21)) >> 9) & 7;
3163                                 par->lcd_hsync_len = *((u8 *)(modeptr+23)) & 63;
3164
3165                                 par->lcd_vtotal = *((u16 *)(modeptr+24)) & 2047;
3166                                 par->lcd_vdisp = *((u16 *)(modeptr+26)) & 2047;
3167                                 lcd_vsync_start = *((u16 *)(modeptr+28)) & 2047;
3168                                 par->lcd_vsync_len = (*((u16 *)(modeptr+28)) >> 11) & 31;
3169
3170                                 par->lcd_htotal = (par->lcd_htotal + 1) * 8;
3171                                 par->lcd_hdisp = (par->lcd_hdisp + 1) * 8;
3172                                 lcd_hsync_start = (lcd_hsync_start + 1) * 8;
3173                                 par->lcd_hsync_len = par->lcd_hsync_len * 8;
3174
3175                                 par->lcd_vtotal++;
3176                                 par->lcd_vdisp++;
3177                                 lcd_vsync_start++;
3178
3179                                 par->lcd_right_margin = lcd_hsync_start - par->lcd_hdisp;
3180                                 par->lcd_lower_margin = lcd_vsync_start - par->lcd_vdisp;
3181                                 par->lcd_hblank_len = par->lcd_htotal - par->lcd_hdisp;
3182                                 par->lcd_vblank_len = par->lcd_vtotal - par->lcd_vdisp;
3183                                 break;
3184                         }
3185
3186                         lcdmodeptr++;
3187                 }
3188                 if (*lcdmodeptr == 0) {
3189                         PRINTKE("LCD monitor CRTC parameters not found!!!\n");
3190                         /* To do: Switch to CRT if possible. */
3191                 } else {
3192                         PRINTKI("       LCD CRTC parameters: %d.%d  %d %d %d %d  %d %d %d %d\n",
3193                                 1000000 / par->lcd_pixclock, 1000000 % par->lcd_pixclock,
3194                                 par->lcd_hdisp,
3195                                 par->lcd_hdisp + par->lcd_right_margin,
3196                                 par->lcd_hdisp + par->lcd_right_margin
3197                                         + par->lcd_hsync_dly + par->lcd_hsync_len,
3198                                 par->lcd_htotal,
3199                                 par->lcd_vdisp,
3200                                 par->lcd_vdisp + par->lcd_lower_margin,
3201                                 par->lcd_vdisp + par->lcd_lower_margin + par->lcd_vsync_len,
3202                                 par->lcd_vtotal);
3203                         PRINTKI("                          : %d %d %d %d %d %d %d %d %d\n",
3204                                 par->lcd_pixclock,
3205                                 par->lcd_hblank_len - (par->lcd_right_margin +
3206                                         par->lcd_hsync_dly + par->lcd_hsync_len),
3207                                 par->lcd_hdisp,
3208                                 par->lcd_right_margin,
3209                                 par->lcd_hsync_len,
3210                                 par->lcd_vblank_len - (par->lcd_lower_margin + par->lcd_vsync_len),
3211                                 par->lcd_vdisp,
3212                                 par->lcd_lower_margin,
3213                                 par->lcd_vsync_len);
3214                 }
3215         }
3216 }
3217 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
3218
3219 static int __devinit init_from_bios(struct atyfb_par *par)
3220 {
3221         u32 bios_base, rom_addr;
3222         int ret;
3223
3224         rom_addr = 0xc0000 + ((aty_ld_le32(SCRATCH_REG1, par) & 0x7f) << 11);
3225         bios_base = (unsigned long)ioremap(rom_addr, 0x10000);
3226
3227         /* The BIOS starts with 0xaa55. */
3228         if (*((u16 *)bios_base) == 0xaa55) {
3229
3230                 u8 *bios_ptr;
3231                 u16 rom_table_offset, freq_table_offset;
3232                 PLL_BLOCK_MACH64 pll_block;
3233
3234                 PRINTKI("Mach64 BIOS is located at %x, mapped at %x.\n", rom_addr, bios_base);
3235
3236                 /* check for frequncy table */
3237                 bios_ptr = (u8*)bios_base;
3238                 rom_table_offset = (u16)(bios_ptr[0x48] | (bios_ptr[0x49] << 8));
3239                 freq_table_offset = bios_ptr[rom_table_offset + 16] | (bios_ptr[rom_table_offset + 17] << 8);
3240                 memcpy(&pll_block, bios_ptr + freq_table_offset, sizeof(PLL_BLOCK_MACH64));
3241
3242                 PRINTKI("BIOS frequency table:\n");
3243                 PRINTKI("PCLK_min_freq %d, PCLK_max_freq %d, ref_freq %d, ref_divider %d\n",
3244                         pll_block.PCLK_min_freq, pll_block.PCLK_max_freq,
3245                         pll_block.ref_freq, pll_block.ref_divider);
3246                 PRINTKI("MCLK_pwd %d, MCLK_max_freq %d, XCLK_max_freq %d, SCLK_freq %d\n",
3247                         pll_block.MCLK_pwd, pll_block.MCLK_max_freq,
3248                         pll_block.XCLK_max_freq, pll_block.SCLK_freq);
3249
3250                 par->pll_limits.pll_min = pll_block.PCLK_min_freq/100;
3251                 par->pll_limits.pll_max = pll_block.PCLK_max_freq/100;
3252                 par->pll_limits.ref_clk = pll_block.ref_freq/100;
3253                 par->pll_limits.ref_div = pll_block.ref_divider;
3254                 par->pll_limits.sclk = pll_block.SCLK_freq/100;
3255                 par->pll_limits.mclk = pll_block.MCLK_max_freq/100;
3256                 par->pll_limits.mclk_pm = pll_block.MCLK_pwd/100;
3257                 par->pll_limits.xclk = pll_block.XCLK_max_freq/100;
3258 #ifdef CONFIG_FB_ATY_GENERIC_LCD
3259                 aty_init_lcd(par, bios_base);
3260 #endif
3261                 ret = 0;
3262         } else {
3263                 PRINTKE("no BIOS frequency table found, use parameters\n");
3264                 ret = -ENXIO;
3265         }
3266         iounmap((void* __iomem )bios_base);
3267
3268         return ret;
3269 }
3270 #endif /* __i386__ */
3271
3272 static int __devinit atyfb_setup_generic(struct pci_dev *pdev, struct fb_info *info, unsigned long addr)
3273 {
3274         struct atyfb_par *par = info->par;
3275         u16 tmp;
3276         unsigned long raddr;
3277         struct resource *rrp;
3278         int ret = 0;
3279
3280         raddr = addr + 0x7ff000UL;
3281         rrp = &pdev->resource[2];
3282         if ((rrp->flags & IORESOURCE_MEM) && request_mem_region(rrp->start, rrp->end - rrp->start + 1, "atyfb")) {
3283                 par->aux_start = rrp->start;
3284                 par->aux_size = rrp->end - rrp->start + 1;
3285                 raddr = rrp->start;
3286                 PRINTKI("using auxiliary register aperture\n");
3287         }
3288
3289         info->fix.mmio_start = raddr;
3290         par->ati_regbase = ioremap(info->fix.mmio_start, 0x1000);
3291         if (par->ati_regbase == 0)
3292                 return -ENOMEM;
3293
3294         info->fix.mmio_start += par->aux_start ? 0x400 : 0xc00;
3295         par->ati_regbase += par->aux_start ? 0x400 : 0xc00;
3296
3297         /*
3298          * Enable memory-space accesses using config-space
3299          * command register.
3300          */
3301         pci_read_config_word(pdev, PCI_COMMAND, &tmp);
3302         if (!(tmp & PCI_COMMAND_MEMORY)) {
3303                 tmp |= PCI_COMMAND_MEMORY;
3304                 pci_write_config_word(pdev, PCI_COMMAND, tmp);
3305         }
3306 #ifdef __BIG_ENDIAN
3307         /* Use the big-endian aperture */
3308         addr += 0x800000;
3309 #endif
3310
3311         /* Map in frame buffer */
3312         info->fix.smem_start = addr;
3313         info->screen_base = ioremap(addr, 0x800000);
3314         if (info->screen_base == NULL) {
3315                 ret = -ENOMEM;
3316                 goto atyfb_setup_generic_fail;
3317         }
3318
3319         if((ret = correct_chipset(par)))
3320                 goto atyfb_setup_generic_fail;
3321 #ifdef __i386__
3322         if((ret = init_from_bios(par)))
3323                 goto atyfb_setup_generic_fail;
3324 #endif
3325         if (!(aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_EXT_DISP_EN))
3326                 par->clk_wr_offset = (inb(R_GENMO) & 0x0CU) >> 2;
3327         else
3328                 par->clk_wr_offset = aty_ld_8(CLOCK_CNTL, par) & 0x03U;
3329
3330         /* according to ATI, we should use clock 3 for acelerated mode */
3331         par->clk_wr_offset = 3;
3332
3333         return 0;
3334
3335 atyfb_setup_generic_fail:
3336         iounmap(par->ati_regbase);
3337         par->ati_regbase = NULL;
3338         return ret;
3339 }
3340
3341 #endif /* !__sparc__ */
3342
3343 static int __devinit atyfb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3344 {
3345         unsigned long addr, res_start, res_size;
3346         struct fb_info *info;
3347         struct resource *rp;
3348         struct atyfb_par *par;
3349         int i, rc = -ENOMEM;
3350
3351         for (i = sizeof(aty_chips) / sizeof(*aty_chips) - 1; i >= 0; i--)
3352                 if (pdev->device == aty_chips[i].pci_id)
3353                         break;
3354
3355         if (i < 0)
3356                 return -ENODEV;
3357
3358         /* Enable device in PCI config */
3359         if (pci_enable_device(pdev)) {
3360                 PRINTKE("Cannot enable PCI device\n");
3361                 return -ENXIO;
3362         }
3363
3364         /* Find which resource to use */
3365         rp = &pdev->resource[0];
3366         if (rp->flags & IORESOURCE_IO)
3367                 rp = &pdev->resource[1];
3368         addr = rp->start;
3369         if (!addr)
3370                 return -ENXIO;
3371
3372         /* Reserve space */
3373         res_start = rp->start;
3374         res_size = rp->end - rp->start + 1;
3375         if (!request_mem_region (res_start, res_size, "atyfb"))
3376                 return -EBUSY;
3377
3378         /* Allocate framebuffer */
3379         info = framebuffer_alloc(sizeof(struct atyfb_par), &pdev->dev);
3380         if (!info) {
3381                 PRINTKE("atyfb_pci_probe() can't alloc fb_info\n");
3382                 return -ENOMEM;
3383         }
3384         par = info->par;
3385         info->fix = atyfb_fix;
3386         info->device = &pdev->dev;
3387         par->pci_id = aty_chips[i].pci_id;
3388         par->res_start = res_start;
3389         par->res_size = res_size;
3390         par->irq = pdev->irq;
3391
3392         /* Setup "info" structure */
3393 #ifdef __sparc__
3394         rc = atyfb_setup_sparc(pdev, info, addr);
3395 #else
3396         rc = atyfb_setup_generic(pdev, info, addr);
3397 #endif
3398         if (rc)
3399                 goto err_release_mem;
3400
3401         pci_set_drvdata(pdev, info);
3402
3403         /* Init chip & register framebuffer */
3404         if (aty_init(info, "PCI"))
3405                 goto err_release_io;
3406
3407 #ifdef __sparc__
3408         if (!prom_palette)
3409                 prom_palette = atyfb_palette;
3410
3411         /*
3412          * Add /dev/fb mmap values.
3413          */
3414         par->mmap_map[0].voff = 0x8000000000000000UL;
3415         par->mmap_map[0].poff = (unsigned long) info->screen_base & PAGE_MASK;
3416         par->mmap_map[0].size = info->fix.smem_len;
3417         par->mmap_map[0].prot_mask = _PAGE_CACHE;
3418         par->mmap_map[0].prot_flag = _PAGE_E;
3419         par->mmap_map[1].voff = par->mmap_map[0].voff + info->fix.smem_len;
3420         par->mmap_map[1].poff = (long)par->ati_regbase & PAGE_MASK;
3421         par->mmap_map[1].size = PAGE_SIZE;
3422         par->mmap_map[1].prot_mask = _PAGE_CACHE;
3423         par->mmap_map[1].prot_flag = _PAGE_E;
3424 #endif /* __sparc__ */
3425
3426         return 0;
3427
3428 err_release_io:
3429 #ifdef __sparc__
3430         if (par->mmap_map)
3431                 kfree(par->mmap_map);
3432 #else
3433         if (par->ati_regbase)
3434                 iounmap(par->ati_regbase);
3435         if (info->screen_base)
3436                 iounmap(info->screen_base);
3437 #endif
3438 err_release_mem:
3439         if(par->aux_start)
3440                 release_mem_region(par->aux_start, par->aux_size);
3441
3442         release_mem_region(par->res_start, par->res_size);
3443         framebuffer_release(info);
3444
3445         return rc;
3446 }
3447
3448 #endif /* CONFIG_PCI */
3449
3450 #ifdef CONFIG_ATARI
3451
3452 static int __devinit atyfb_atari_probe(void)
3453 {
3454         struct aty_par *par;
3455         struct fb_info *info;
3456         int m64_num;
3457         u32 clock_r;
3458
3459         for (m64_num = 0; m64_num < mach64_count; m64_num++) {
3460                 if (!phys_vmembase[m64_num] || !phys_size[m64_num] ||
3461                     !phys_guiregbase[m64_num]) {
3462                     PRINTKI("phys_*[%d] parameters not set => returning early. \n", m64_num);
3463                         continue;
3464                 }
3465
3466                 info = framebuffer_alloc(sizeof(struct atyfb_par), NULL);
3467                 if (!info) {
3468                         PRINTKE("atyfb_atari_probe() can't alloc fb_info\n");
3469                         return -ENOMEM;
3470                 }
3471                 par = info->par;
3472
3473                 info->fix = atyfb_fix;
3474
3475                 par->irq = (unsigned int) -1; /* something invalid */
3476
3477                 /*
3478                  *  Map the video memory (physical address given) to somewhere in the
3479                  *  kernel address space.
3480                  */
3481                 info->screen_base = ioremap(phys_vmembase[m64_num], phys_size[m64_num]);
3482                 info->fix.smem_start = (unsigned long)info->screen_base; /* Fake! */
3483                 par->ati_regbase = ioremap(phys_guiregbase[m64_num], 0x10000) +
3484                                                 0xFC00ul;
3485                 info->fix.mmio_start = (unsigned long)par->ati_regbase; /* Fake! */
3486
3487                 aty_st_le32(CLOCK_CNTL, 0x12345678, par);
3488                 clock_r = aty_ld_le32(CLOCK_CNTL, par);
3489
3490                 switch (clock_r & 0x003F) {
3491                 case 0x12:
3492                         par->clk_wr_offset = 3; /*  */
3493                         break;
3494                 case 0x34:
3495                         par->clk_wr_offset = 2; /* Medusa ST-IO ISA Adapter etc. */
3496                         break;
3497                 case 0x16:
3498                         par->clk_wr_offset = 1; /*  */
3499                         break;
3500                 case 0x38:
3501                         par->clk_wr_offset = 0; /* Panther 1 ISA Adapter (Gerald) */
3502                         break;
3503                 }
3504
3505                 if (aty_init(info, "ISA bus")) {
3506                         framebuffer_release(info);
3507                         /* This is insufficient! kernel_map has added two large chunks!! */
3508                         return -ENXIO;
3509                 }
3510         }
3511 }
3512
3513 #endif /* CONFIG_ATARI */
3514
3515 static void __devexit atyfb_remove(struct fb_info *info)
3516 {
3517         struct atyfb_par *par = (struct atyfb_par *) info->par;
3518
3519         /* restore video mode */
3520         aty_set_crtc(par, &saved_crtc);
3521         par->pll_ops->set_pll(info, &saved_pll);
3522
3523         unregister_framebuffer(info);
3524
3525 #ifdef CONFIG_MTRR
3526         if (par->mtrr_reg >= 0) {
3527             mtrr_del(par->mtrr_reg, 0, 0);
3528             par->mtrr_reg = -1;
3529         }
3530         if (par->mtrr_aper >= 0) {
3531             mtrr_del(par->mtrr_aper, 0, 0);
3532             par->mtrr_aper = -1;
3533         }
3534 #endif
3535 #ifndef __sparc__
3536         if (par->ati_regbase)
3537                 iounmap(par->ati_regbase);
3538         if (info->screen_base)
3539                 iounmap(info->screen_base);
3540 #ifdef __BIG_ENDIAN
3541         if (info->sprite.addr)
3542                 iounmap(info->sprite.addr);
3543 #endif
3544 #endif
3545 #ifdef __sparc__
3546         if (par->mmap_map)
3547                 kfree(par->mmap_map);
3548 #endif
3549         if (par->aux_start)
3550                 release_mem_region(par->aux_start, par->aux_size);
3551
3552         if (par->res_start)
3553                 release_mem_region(par->res_start, par->res_size);
3554
3555         framebuffer_release(info);
3556 }
3557
3558 #ifdef CONFIG_PCI
3559
3560 static void __devexit atyfb_pci_remove(struct pci_dev *pdev)
3561 {
3562         struct fb_info *info = pci_get_drvdata(pdev);
3563
3564         atyfb_remove(info);
3565 }
3566
3567 /*
3568  * This driver uses its own matching table. That will be more difficult
3569  * to fix, so for now, we just match against any ATI ID and let the
3570  * probe() function find out what's up. That also mean we don't have
3571  * a module ID table though.
3572  */
3573 static struct pci_device_id atyfb_pci_tbl[] = {
3574         { PCI_VENDOR_ID_ATI, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
3575           PCI_BASE_CLASS_DISPLAY << 16, 0xff0000, 0 },
3576         { 0, }
3577 };
3578
3579 static struct pci_driver atyfb_driver = {
3580         .name           = "atyfb",
3581         .id_table       = atyfb_pci_tbl,
3582         .probe          = atyfb_pci_probe,
3583         .remove         = __devexit_p(atyfb_pci_remove),
3584 #ifdef CONFIG_PM
3585         .suspend        = atyfb_pci_suspend,
3586         .resume         = atyfb_pci_resume,
3587 #endif /* CONFIG_PM */
3588 };
3589
3590 #endif /* CONFIG_PCI */
3591
3592 int __init atyfb_setup(char *options)
3593 {
3594         char *this_opt;
3595
3596         if (!options || !*options)
3597                 return 0;
3598
3599         while ((this_opt = strsep(&options, ",")) != NULL) {
3600                 if (!strncmp(this_opt, "noaccel", 7)) {
3601                         noaccel = 1;
3602 #ifdef CONFIG_MTRR
3603                 } else if (!strncmp(this_opt, "nomtrr", 6)) {
3604                         nomtrr = 1;
3605 #endif
3606                 } else if (!strncmp(this_opt, "vram:", 5))
3607                         vram = simple_strtoul(this_opt + 5, NULL, 0);
3608                 else if (!strncmp(this_opt, "pll:", 4))
3609                         pll = simple_strtoul(this_opt + 4, NULL, 0);
3610                 else if (!strncmp(this_opt, "mclk:", 5))
3611                         mclk = simple_strtoul(this_opt + 5, NULL, 0);
3612                 else if (!strncmp(this_opt, "xclk:", 5))
3613                         xclk = simple_strtoul(this_opt+5, NULL, 0);
3614 #ifdef CONFIG_PPC
3615                 else if (!strncmp(this_opt, "vmode:", 6)) {
3616                         unsigned int vmode =
3617                             simple_strtoul(this_opt + 6, NULL, 0);
3618                         if (vmode > 0 && vmode <= VMODE_MAX)
3619                                 default_vmode = vmode;
3620                 } else if (!strncmp(this_opt, "cmode:", 6)) {
3621                         unsigned int cmode =
3622                             simple_strtoul(this_opt + 6, NULL, 0);
3623                         switch (cmode) {
3624                         case 0:
3625                         case 8:
3626                                 default_cmode = CMODE_8;
3627                                 break;
3628                         case 15:
3629                         case 16:
3630                                 default_cmode = CMODE_16;
3631                                 break;
3632                         case 24:
3633                         case 32:
3634                                 default_cmode = CMODE_32;
3635                                 break;
3636                         }
3637                 }
3638 #endif
3639 #ifdef CONFIG_ATARI
3640                 /*
3641                  * Why do we need this silly Mach64 argument?
3642                  * We are already here because of mach64= so its redundant.
3643                  */
3644                 else if (MACH_IS_ATARI
3645                          && (!strncmp(this_opt, "Mach64:", 7))) {
3646                         static unsigned char m64_num;
3647                         static char mach64_str[80];
3648                         strlcpy(mach64_str, this_opt + 7, sizeof(mach64_str));
3649                         if (!store_video_par(mach64_str, m64_num)) {
3650                                 m64_num++;
3651                                 mach64_count = m64_num;
3652                         }
3653                 }
3654 #endif
3655                 else
3656                         mode = this_opt;
3657         }
3658         return 0;
3659 }
3660
3661 int __init atyfb_init(void)
3662 {
3663 #ifndef MODULE
3664     char *option = NULL;
3665
3666     if (fb_get_options("atyfb", &option))
3667         return -ENODEV;
3668     atyfb_setup(option);
3669 #endif
3670
3671 #ifdef CONFIG_PCI
3672     pci_module_init(&atyfb_driver);
3673 #endif
3674 #ifdef CONFIG_ATARI
3675     atyfb_atari_probe();
3676 #endif
3677     return 0;
3678 }
3679
3680 void __exit atyfb_exit(void)
3681 {
3682 #ifdef CONFIG_PCI
3683         pci_unregister_driver(&atyfb_driver);
3684 #endif
3685 }
3686
3687 module_init(atyfb_init);
3688 #ifdef MODULE
3689 module_exit(atyfb_exit);
3690 #endif
3691
3692 MODULE_DESCRIPTION("FBDev driver for ATI Mach64 cards");
3693 MODULE_LICENSE("GPL");
3694 module_param(noaccel, bool, 0);
3695 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
3696 module_param(vram, int, 0);
3697 MODULE_PARM_DESC(vram, "int: override size of video ram");
3698 module_param(pll, int, 0);
3699 MODULE_PARM_DESC(pll, "int: override video clock");
3700 module_param(mclk, int, 0);
3701 MODULE_PARM_DESC(mclk, "int: override memory clock");
3702 module_param(xclk, int, 0);
3703 MODULE_PARM_DESC(xclk, "int: override accelerated engine clock");
3704 module_param(mode, charp, 0);
3705 MODULE_PARM_DESC(mode, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
3706 #ifdef CONFIG_MTRR
3707 module_param(nomtrr, bool, 0);
3708 MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
3709 #endif