drivers/video/aty/radeon_accel.c

   1 #include "radeonfb.h"
   2
   3 /* the accelerated functions here are patterned after the
   4  * "ACCEL_MMIO" ifdef branches in XFree86
   5  * --dte
   6  */
   7 static void radeonfb_prim_fillrect(struct radeonfb_info *rinfo,
   8                                    const struct fb_fillrect *region)
   9 {
  10         radeon_fifo_wait(4);
  11
  12         OUTREG(DP_GUI_MASTER_CNTL,
  13                 rinfo->dp_gui_master_cntl  /* contains, like GMC_DST_32BPP */
  14                 | GMC_BRUSH_SOLID_COLOR
  15                 | ROP3_P);
  16         if (radeon_get_dstbpp(rinfo->depth) != DST_8BPP)
  17                 OUTREG(DP_BRUSH_FRGD_CLR, rinfo->pseudo_palette[region->color]);
  18         else
  19                 OUTREG(DP_BRUSH_FRGD_CLR, region->color);
  20         OUTREG(DP_WRITE_MSK, 0xffffffff);
  21         OUTREG(DP_CNTL, (DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM));
  22
  23         radeon_fifo_wait(2);
  24         OUTREG(DST_Y_X, (region->dy << 16) | region->dx);
  25         OUTREG(DST_WIDTH_HEIGHT, (region->width << 16) | region->height);
  26 }
  27
  28 void radeonfb_fillrect(struct fb_info *info, const struct fb_fillrect *region)
  29 {
  30         struct radeonfb_info *rinfo = info->par;
  31         struct fb_fillrect modded;
  32         int vxres, vyres;
  33
  34         if (info->state != FBINFO_STATE_RUNNING)
  35                 return;
  36         if (radeon_accel_disabled()) {
  37                 cfb_fillrect(info, region);
  38                 return;
  39         }
  40
  41         vxres = info->var.xres;
  42         vyres = info->var.yres;
  43
  44         memcpy(&modded, region, sizeof(struct fb_fillrect));
  45
  46         if(!modded.width || !modded.height ||
  47            modded.dx >= vxres || modded.dy >= vyres)
  48                 return;
  49
  50         if(modded.dx + modded.width  > vxres) modded.width  = vxres - modded.dx;
  51         if(modded.dy + modded.height > vyres) modded.height = vyres - modded.dy;
  52
  53         radeonfb_prim_fillrect(rinfo, &modded);
  54 }
  55
  56 static void radeonfb_prim_copyarea(struct radeonfb_info *rinfo,
  57                                    const struct fb_copyarea *area)
  58 {
  59         int xdir, ydir;
  60         u32 sx, sy, dx, dy, w, h;
  61
  62         w = area->width; h = area->height;
  63         dx = area->dx; dy = area->dy;
  64         sx = area->sx; sy = area->sy;
  65         xdir = sx - dx;
  66         ydir = sy - dy;
  67
  68         if ( xdir < 0 ) { sx += w-1; dx += w-1; }
  69         if ( ydir < 0 ) { sy += h-1; dy += h-1; }
  70
  71         radeon_fifo_wait(3);
  72         OUTREG(DP_GUI_MASTER_CNTL,
  73                 rinfo->dp_gui_master_cntl /* i.e. GMC_DST_32BPP */
  74                 | GMC_SRC_DSTCOLOR
  75                 | ROP3_S
  76                 | DP_SRC_RECT );
  77         OUTREG(DP_WRITE_MSK, 0xffffffff);
  78         OUTREG(DP_CNTL, (xdir>=0 ? DST_X_LEFT_TO_RIGHT : 0)
  79                         | (ydir>=0 ? DST_Y_TOP_TO_BOTTOM : 0));
  80
  81         radeon_fifo_wait(3);
  82         OUTREG(SRC_Y_X, (sy << 16) | sx);
  83         OUTREG(DST_Y_X, (dy << 16) | dx);
  84         OUTREG(DST_HEIGHT_WIDTH, (h << 16) | w);
  85 }
  86
  87
  88 void radeonfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
  89 {
  90         struct radeonfb_info *rinfo = info->par;
  91         struct fb_copyarea modded;
  92         u32 vxres, vyres;
  93         modded.sx = area->sx;
  94         modded.sy = area->sy;
  95         modded.dx = area->dx;
  96         modded.dy = area->dy;
  97         modded.width  = area->width;
  98         modded.height = area->height;
  99
 100         if (info->state != FBINFO_STATE_RUNNING)
 101                 return;
 102         if (radeon_accel_disabled()) {
 103                 cfb_copyarea(info, area);
 104                 return;
 105         }
 106
 107         vxres = info->var.xres;
 108         vyres = info->var.yres;
 109
 110         if(!modded.width || !modded.height ||
 111            modded.sx >= vxres || modded.sy >= vyres ||
 112            modded.dx >= vxres || modded.dy >= vyres)
 113                 return;
 114
 115         if(modded.sx + modded.width > vxres)  modded.width = vxres - modded.sx;
 116         if(modded.dx + modded.width > vxres)  modded.width = vxres - modded.dx;
 117         if(modded.sy + modded.height > vyres) modded.height = vyres - modded.sy;
 118         if(modded.dy + modded.height > vyres) modded.height = vyres - modded.dy;
 119
 120         radeonfb_prim_copyarea(rinfo, &modded);
 121 }
 122
 123 void radeonfb_imageblit(struct fb_info *info, const struct fb_image *image)
 124 {
 125         struct radeonfb_info *rinfo = info->par;
 126
 127         if (info->state != FBINFO_STATE_RUNNING)
 128                 return;
 129         radeon_engine_idle();
 130
 131         cfb_imageblit(info, image);
 132 }
 133
 134 int radeonfb_sync(struct fb_info *info)
 135 {
 136         struct radeonfb_info *rinfo = info->par;
 137
 138         if (info->state != FBINFO_STATE_RUNNING)
 139                 return 0;
 140         radeon_engine_idle();
 141
 142         return 0;
 143 }
 144
 145 void radeonfb_engine_reset(struct radeonfb_info *rinfo)
 146 {
 147         u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
 148         u32 host_path_cntl;
 149
 150         radeon_engine_flush (rinfo);
 151
 152         /* Some ASICs have bugs with dynamic-on feature, which are
 153          * ASIC-version dependent, so we force all blocks on for now
 154          * -- from XFree86
 155          * We don't do that on macs, things just work here with dynamic
 156          * clocking... --BenH
 157          */
 158 #ifdef CONFIG_ALL_PPC
 159         if (_machine != _MACH_Pmac && rinfo->hasCRTC2)
 160 #else
 161         if (rinfo->has_CRTC2)
 162 #endif
 163         {
 164                 u32 tmp;
 165
 166                 tmp = INPLL(SCLK_CNTL);
 167                 OUTPLL(SCLK_CNTL, ((tmp & ~DYN_STOP_LAT_MASK) |
 168                                    CP_MAX_DYN_STOP_LAT |
 169                                    SCLK_FORCEON_MASK));
 170
 171                 if (rinfo->family == CHIP_FAMILY_RV200)
 172                 {
 173                         tmp = INPLL(SCLK_MORE_CNTL);
 174                         OUTPLL(SCLK_MORE_CNTL, tmp | SCLK_MORE_FORCEON);
 175                 }
 176         }
 177
 178         clock_cntl_index = INREG(CLOCK_CNTL_INDEX);
 179         mclk_cntl = INPLL(MCLK_CNTL);
 180
 181         OUTPLL(MCLK_CNTL, (mclk_cntl |
 182                            FORCEON_MCLKA |
 183                            FORCEON_MCLKB |
 184                            FORCEON_YCLKA |
 185                            FORCEON_YCLKB |
 186                            FORCEON_MC |
 187                            FORCEON_AIC));
 188
 189         host_path_cntl = INREG(HOST_PATH_CNTL);
 190         rbbm_soft_reset = INREG(RBBM_SOFT_RESET);
 191
 192         if (rinfo->family == CHIP_FAMILY_R300 ||
 193             rinfo->family == CHIP_FAMILY_R350 ||
 194             rinfo->family == CHIP_FAMILY_RV350) {
 195                 u32 tmp;
 196
 197                 OUTREG(RBBM_SOFT_RESET, (rbbm_soft_reset |
 198                                          SOFT_RESET_CP |
 199                                          SOFT_RESET_HI |
 200                                          SOFT_RESET_E2));
 201                 INREG(RBBM_SOFT_RESET);
 202                 OUTREG(RBBM_SOFT_RESET, 0);
 203                 tmp = INREG(RB2D_DSTCACHE_MODE);
 204                 OUTREG(RB2D_DSTCACHE_MODE, tmp | (1 << 17)); /* FIXME */
 205         } else {
 206                 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset |
 207                                         SOFT_RESET_CP |
 208                                         SOFT_RESET_HI |
 209                                         SOFT_RESET_SE |
 210                                         SOFT_RESET_RE |
 211                                         SOFT_RESET_PP |
 212                                         SOFT_RESET_E2 |
 213                                         SOFT_RESET_RB);
 214                 INREG(RBBM_SOFT_RESET);
 215                 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset & (u32)
 216                                         ~(SOFT_RESET_CP |
 217                                           SOFT_RESET_HI |
 218                                           SOFT_RESET_SE |
 219                                           SOFT_RESET_RE |
 220                                           SOFT_RESET_PP |
 221                                           SOFT_RESET_E2 |
 222                                           SOFT_RESET_RB));
 223                 INREG(RBBM_SOFT_RESET);
 224         }
 225
 226         OUTREG(HOST_PATH_CNTL, host_path_cntl | HDP_SOFT_RESET);
 227         INREG(HOST_PATH_CNTL);
 228         OUTREG(HOST_PATH_CNTL, host_path_cntl);
 229
 230         if (rinfo->family != CHIP_FAMILY_R300 ||
 231             rinfo->family != CHIP_FAMILY_R350 ||
 232             rinfo->family != CHIP_FAMILY_RV350)
 233                 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset);
 234
 235         OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index);
 236         OUTPLL(MCLK_CNTL, mclk_cntl);
 237         if (rinfo->R300_cg_workaround)
 238                 R300_cg_workardound(rinfo);
 239 }
 240
 241 void radeonfb_engine_init (struct radeonfb_info *rinfo)
 242 {
 243         unsigned long temp;
 244
 245         /* disable 3D engine */
 246         OUTREG(RB3D_CNTL, 0);
 247
 248         radeonfb_engine_reset(rinfo);
 249
 250         radeon_fifo_wait (1);
 251         if ((rinfo->family != CHIP_FAMILY_R300) &&
 252             (rinfo->family != CHIP_FAMILY_R350) &&
 253             (rinfo->family != CHIP_FAMILY_RV350))
 254                 OUTREG(RB2D_DSTCACHE_MODE, 0);
 255
 256         radeon_fifo_wait (3);
 257         /* We re-read MC_FB_LOCATION from card as it can have been
 258          * modified by XFree drivers (ouch !)
 259          */
 260         rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;
 261
 262         OUTREG(DEFAULT_PITCH_OFFSET, (rinfo->pitch << 0x16) |
 263                                      (rinfo->fb_local_base >> 10));
 264         OUTREG(DST_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10));
 265         OUTREG(SRC_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10));
 266
 267         radeon_fifo_wait (1);
 268 #if defined(__BIG_ENDIAN)
 269         OUTREGP(DP_DATATYPE, HOST_BIG_ENDIAN_EN, ~HOST_BIG_ENDIAN_EN);
 270 #else
 271         OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN);
 272 #endif
 273         radeon_fifo_wait (2);
 274         OUTREG(DEFAULT_SC_TOP_LEFT, 0);
 275         OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX |
 276                                          DEFAULT_SC_BOTTOM_MAX));
 277
 278         temp = radeon_get_dstbpp(rinfo->depth);
 279         rinfo->dp_gui_master_cntl = ((temp << 8) | GMC_CLR_CMP_CNTL_DIS);
 280
 281         radeon_fifo_wait (1);
 282         OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl |
 283                                     GMC_BRUSH_SOLID_COLOR |
 284                                     GMC_SRC_DATATYPE_COLOR));
 285
 286         radeon_fifo_wait (7);
 287
 288         /* clear line drawing regs */
 289         OUTREG(DST_LINE_START, 0);
 290         OUTREG(DST_LINE_END, 0);
 291
 292         /* set brush color regs */
 293         OUTREG(DP_BRUSH_FRGD_CLR, 0xffffffff);
 294         OUTREG(DP_BRUSH_BKGD_CLR, 0x00000000);
 295
 296         /* set source color regs */
 297         OUTREG(DP_SRC_FRGD_CLR, 0xffffffff);
 298         OUTREG(DP_SRC_BKGD_CLR, 0x00000000);
 299
 300         /* default write mask */
 301         OUTREG(DP_WRITE_MSK, 0xffffffff);
 302
 303         radeon_engine_idle ();
 304 }