drivers/video/aty/radeon_accel.c

   1 #include "radeonfb.h"
   2
   3 /* the accelerated functions here are patterned after the
   4  * "ACCEL_MMIO" ifdef branches in XFree86
   5  * --dte
   6  */
   7 static void radeonfb_prim_fillrect(struct radeonfb_info *rinfo,
   8                                    const struct fb_fillrect *region)
   9 {
  10         radeon_fifo_wait(4);
  11
  12         OUTREG(DP_GUI_MASTER_CNTL,
  13                 rinfo->dp_gui_master_cntl  /* contains, like GMC_DST_32BPP */
  14                 | GMC_BRUSH_SOLID_COLOR
  15                 | ROP3_P);
  16         OUTREG(DP_BRUSH_FRGD_CLR, region->color);
  17         OUTREG(DP_WRITE_MSK, 0xffffffff);
  18         OUTREG(DP_CNTL, (DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM));
  19
  20         radeon_fifo_wait(2);
  21         OUTREG(DST_Y_X, (region->dy << 16) | region->dx);
  22         OUTREG(DST_WIDTH_HEIGHT, (region->width << 16) | region->height);
  23 }
  24
  25 void radeonfb_fillrect(struct fb_info *info, const struct fb_fillrect *region)
  26 {
  27         struct radeonfb_info *rinfo = info->par;
  28         struct fb_fillrect modded;
  29         int vxres, vyres;
  30
  31         if (info->state != FBINFO_STATE_RUNNING)
  32                 return;
  33         if (radeon_accel_disabled()) {
  34                 cfb_fillrect(info, region);
  35                 return;
  36         }
  37
  38         vxres = info->var.xres;
  39         vyres = info->var.yres;
  40
  41         memcpy(&modded, region, sizeof(struct fb_fillrect));
  42
  43         if(!modded.width || !modded.height ||
  44            modded.dx >= vxres || modded.dy >= vyres)
  45                 return;
  46
  47         if(modded.dx + modded.width  > vxres) modded.width  = vxres - modded.dx;
  48         if(modded.dy + modded.height > vyres) modded.height = vyres - modded.dy;
  49
  50         radeonfb_prim_fillrect(rinfo, &modded);
  51 }
  52
  53 static void radeonfb_prim_copyarea(struct radeonfb_info *rinfo,
  54                                    const struct fb_copyarea *area)
  55 {
  56         radeon_fifo_wait(3);
  57         OUTREG(DP_GUI_MASTER_CNTL,
  58                 rinfo->dp_gui_master_cntl /* i.e. GMC_DST_32BPP */
  59                 | GMC_SRC_DSTCOLOR
  60                 | ROP3_S
  61                 | DP_SRC_RECT );
  62         OUTREG(DP_WRITE_MSK, 0xffffffff);
  63         OUTREG(DP_CNTL, (DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM));
  64
  65         radeon_fifo_wait(3);
  66         OUTREG(SRC_Y_X, (area->sy << 16) | area->sx);
  67         OUTREG(DST_Y_X, (area->dy << 16) | area->dx);
  68         OUTREG(DST_HEIGHT_WIDTH, (area->height << 16) | area->width);
  69 }
  70
  71
  72 void radeonfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
  73 {
  74         struct radeonfb_info *rinfo = info->par;
  75         struct fb_copyarea modded;
  76         u32 vxres, vyres;
  77         modded.sx = area->sx;
  78         modded.sy = area->sy;
  79         modded.dx = area->dx;
  80         modded.dy = area->dy;
  81         modded.width  = area->width;
  82         modded.height = area->height;
  83
  84         if (info->state != FBINFO_STATE_RUNNING)
  85                 return;
  86         if (radeon_accel_disabled()) {
  87                 cfb_copyarea(info, area);
  88                 return;
  89         }
  90
  91         vxres = info->var.xres;
  92         vyres = info->var.yres;
  93
  94         if(!modded.width || !modded.height ||
  95            modded.sx >= vxres || modded.sy >= vyres ||
  96            modded.dx >= vxres || modded.dy >= vyres)
  97                 return;
  98
  99         if(modded.sx + modded.width > vxres)  modded.width = vxres - modded.sx;
 100         if(modded.dx + modded.width > vxres)  modded.width = vxres - modded.dx;
 101         if(modded.sy + modded.height > vyres) modded.height = vyres - modded.sy;
 102         if(modded.dy + modded.height > vyres) modded.height = vyres - modded.dy;
 103
 104         radeonfb_prim_copyarea(rinfo, &modded);
 105 }
 106
 107 void radeonfb_imageblit(struct fb_info *info, const struct fb_image *image)
 108 {
 109         struct radeonfb_info *rinfo = info->par;
 110
 111         if (info->state != FBINFO_STATE_RUNNING)
 112                 return;
 113         radeon_engine_idle();
 114
 115         cfb_imageblit(info, image);
 116 }
 117
 118 int radeonfb_sync(struct fb_info *info)
 119 {
 120         struct radeonfb_info *rinfo = info->par;
 121
 122         if (info->state != FBINFO_STATE_RUNNING)
 123                 return 0;
 124         radeon_engine_idle();
 125
 126         return 0;
 127 }
 128
 129 void radeonfb_engine_reset(struct radeonfb_info *rinfo)
 130 {
 131         u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
 132         u32 host_path_cntl;
 133
 134         radeon_engine_flush (rinfo);
 135
 136         /* Some ASICs have bugs with dynamic-on feature, which are
 137          * ASIC-version dependent, so we force all blocks on for now
 138          * -- from XFree86
 139          * We don't do that on macs, things just work here with dynamic
 140          * clocking... --BenH
 141          */
 142 #ifdef CONFIG_ALL_PPC
 143         if (_machine != _MACH_Pmac && rinfo->hasCRTC2)
 144 #else
 145         if (rinfo->has_CRTC2)
 146 #endif
 147         {
 148                 u32 tmp;
 149
 150                 tmp = INPLL(SCLK_CNTL);
 151                 OUTPLL(SCLK_CNTL, ((tmp & ~DYN_STOP_LAT_MASK) |
 152                                    CP_MAX_DYN_STOP_LAT |
 153                                    SCLK_FORCEON_MASK));
 154
 155                 if (rinfo->family == CHIP_FAMILY_RV200)
 156                 {
 157                         tmp = INPLL(SCLK_MORE_CNTL);
 158                         OUTPLL(SCLK_MORE_CNTL, tmp | SCLK_MORE_FORCEON);
 159                 }
 160         }
 161
 162         clock_cntl_index = INREG(CLOCK_CNTL_INDEX);
 163         mclk_cntl = INPLL(MCLK_CNTL);
 164
 165         OUTPLL(MCLK_CNTL, (mclk_cntl |
 166                            FORCEON_MCLKA |
 167                            FORCEON_MCLKB |
 168                            FORCEON_YCLKA |
 169                            FORCEON_YCLKB |
 170                            FORCEON_MC |
 171                            FORCEON_AIC));
 172
 173         host_path_cntl = INREG(HOST_PATH_CNTL);
 174         rbbm_soft_reset = INREG(RBBM_SOFT_RESET);
 175
 176         if (rinfo->family == CHIP_FAMILY_R300 ||
 177             rinfo->family == CHIP_FAMILY_R350 ||
 178             rinfo->family == CHIP_FAMILY_RV350) {
 179                 u32 tmp;
 180
 181                 OUTREG(RBBM_SOFT_RESET, (rbbm_soft_reset |
 182                                          SOFT_RESET_CP |
 183                                          SOFT_RESET_HI |
 184                                          SOFT_RESET_E2));
 185                 INREG(RBBM_SOFT_RESET);
 186                 OUTREG(RBBM_SOFT_RESET, 0);
 187                 tmp = INREG(RB2D_DSTCACHE_MODE);
 188                 OUTREG(RB2D_DSTCACHE_MODE, tmp | (1 << 17)); /* FIXME */
 189         } else {
 190                 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset |
 191                                         SOFT_RESET_CP |
 192                                         SOFT_RESET_HI |
 193                                         SOFT_RESET_SE |
 194                                         SOFT_RESET_RE |
 195                                         SOFT_RESET_PP |
 196                                         SOFT_RESET_E2 |
 197                                         SOFT_RESET_RB);
 198                 INREG(RBBM_SOFT_RESET);
 199                 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset & (u32)
 200                                         ~(SOFT_RESET_CP |
 201                                           SOFT_RESET_HI |
 202                                           SOFT_RESET_SE |
 203                                           SOFT_RESET_RE |
 204                                           SOFT_RESET_PP |
 205                                           SOFT_RESET_E2 |
 206                                           SOFT_RESET_RB));
 207                 INREG(RBBM_SOFT_RESET);
 208         }
 209
 210         OUTREG(HOST_PATH_CNTL, host_path_cntl | HDP_SOFT_RESET);
 211         INREG(HOST_PATH_CNTL);
 212         OUTREG(HOST_PATH_CNTL, host_path_cntl);
 213
 214         if (rinfo->family != CHIP_FAMILY_R300 ||
 215             rinfo->family != CHIP_FAMILY_R350 ||
 216             rinfo->family != CHIP_FAMILY_RV350)
 217                 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset);
 218
 219         OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index);
 220         OUTPLL(MCLK_CNTL, mclk_cntl);
 221         if (rinfo->R300_cg_workaround)
 222                 R300_cg_workardound(rinfo);
 223 }
 224
 225 void radeonfb_engine_init (struct radeonfb_info *rinfo)
 226 {
 227         unsigned long temp;
 228
 229         /* disable 3D engine */
 230         OUTREG(RB3D_CNTL, 0);
 231
 232         radeonfb_engine_reset(rinfo);
 233
 234         radeon_fifo_wait (1);
 235         if ((rinfo->family != CHIP_FAMILY_R300) &&
 236             (rinfo->family != CHIP_FAMILY_R350) &&
 237             (rinfo->family != CHIP_FAMILY_RV350))
 238                 OUTREG(RB2D_DSTCACHE_MODE, 0);
 239
 240         radeon_fifo_wait (3);
 241         /* We re-read MC_FB_LOCATION from card as it can have been
 242          * modified by XFree drivers (ouch !)
 243          */
 244         rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;
 245
 246         OUTREG(DEFAULT_PITCH_OFFSET, (rinfo->pitch << 0x16) |
 247                                      (rinfo->fb_local_base >> 10));
 248         OUTREG(DST_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10));
 249         OUTREG(SRC_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10));
 250
 251         radeon_fifo_wait (1);
 252 #if defined(__BIG_ENDIAN)
 253         OUTREGP(DP_DATATYPE, HOST_BIG_ENDIAN_EN, ~HOST_BIG_ENDIAN_EN);
 254 #else
 255         OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN);
 256 #endif
 257         radeon_fifo_wait (2);
 258         OUTREG(DEFAULT_SC_TOP_LEFT, 0);
 259         OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX |
 260                                          DEFAULT_SC_BOTTOM_MAX));
 261
 262         temp = radeon_get_dstbpp(rinfo->depth);
 263         rinfo->dp_gui_master_cntl = ((temp << 8) | GMC_CLR_CMP_CNTL_DIS);
 264
 265         radeon_fifo_wait (1);
 266         OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl |
 267                                     GMC_BRUSH_SOLID_COLOR |
 268                                     GMC_SRC_DATATYPE_COLOR));
 269
 270         radeon_fifo_wait (7);
 271
 272         /* clear line drawing regs */
 273         OUTREG(DST_LINE_START, 0);
 274         OUTREG(DST_LINE_END, 0);
 275
 276         /* set brush color regs */
 277         OUTREG(DP_BRUSH_FRGD_CLR, 0xffffffff);
 278         OUTREG(DP_BRUSH_BKGD_CLR, 0x00000000);
 279
 280         /* set source color regs */
 281         OUTREG(DP_SRC_FRGD_CLR, 0xffffffff);
 282         OUTREG(DP_SRC_BKGD_CLR, 0x00000000);
 283
 284         /* default write mask */
 285         OUTREG(DP_WRITE_MSK, 0xffffffff);
 286
 287         radeon_engine_idle ();
 288 }