drivers/video/aty/radeon_accel.c

   1 #include "radeonfb.h"
   2
   3 /* the accelerated functions here are patterned after the
   4  * "ACCEL_MMIO" ifdef branches in XFree86
   5  * --dte
   6  */
   7 static void radeonfb_prim_fillrect(struct radeonfb_info *rinfo,
   8                                    const struct fb_fillrect *region)
   9 {
  10         radeon_fifo_wait(4);
  11
  12         OUTREG(DP_GUI_MASTER_CNTL,
  13                 rinfo->dp_gui_master_cntl  /* contains, like GMC_DST_32BPP */
  14                 | GMC_BRUSH_SOLID_COLOR
  15                 | ROP3_P);
  16         OUTREG(DP_BRUSH_FRGD_CLR, region->color);
  17         OUTREG(DP_WRITE_MSK, 0xffffffff);
  18         OUTREG(DP_CNTL, (DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM));
  19
  20         radeon_fifo_wait(2);
  21         OUTREG(DST_Y_X, (region->dy << 16) | region->dx);
  22         OUTREG(DST_WIDTH_HEIGHT, (region->width << 16) | region->height);
  23 }
  24
  25 void radeonfb_fillrect(struct fb_info *info, const struct fb_fillrect *region)
  26 {
  27         struct radeonfb_info *rinfo = info->par;
  28         struct fb_fillrect modded;
  29         int vxres, vyres;
  30
  31         if (info->state != FBINFO_STATE_RUNNING)
  32                 return;
  33         if (radeon_accel_disabled()) {
  34                 cfb_fillrect(info, region);
  35                 return;
  36         }
  37
  38         vxres = info->var.xres;
  39         vyres = info->var.yres;
  40
  41         memcpy(&modded, region, sizeof(struct fb_fillrect));
  42
  43         if(!modded.width || !modded.height ||
  44            modded.dx >= vxres || modded.dy >= vyres)
  45                 return;
  46
  47         if(modded.dx + modded.width  > vxres) modded.width  = vxres - modded.dx;
  48         if(modded.dy + modded.height > vyres) modded.height = vyres - modded.dy;
  49
  50         radeonfb_prim_fillrect(rinfo, &modded);
  51 }
  52
  53 static void radeonfb_prim_copyarea(struct radeonfb_info *rinfo,
  54                                    const struct fb_copyarea *area)
  55 {
  56         int xdir, ydir;
  57         u32 sx, sy, dx, dy, w, h;
  58
  59         w = area->width; h = area->height;
  60         dx = area->dx; dy = area->dy;
  61         sx = area->sx; sy = area->sy;
  62         xdir = sx - dx;
  63         ydir = sy - dy;
  64
  65         if ( xdir < 0 ) { sx += w-1; dx += w-1; }
  66         if ( ydir < 0 ) { sy += h-1; dy += h-1; }
  67
  68         radeon_fifo_wait(3);
  69         OUTREG(DP_GUI_MASTER_CNTL,
  70                 rinfo->dp_gui_master_cntl /* i.e. GMC_DST_32BPP */
  71                 | GMC_SRC_DSTCOLOR
  72                 | ROP3_S
  73                 | DP_SRC_RECT );
  74         OUTREG(DP_WRITE_MSK, 0xffffffff);
  75         OUTREG(DP_CNTL, (xdir>=0 ? DST_X_LEFT_TO_RIGHT : 0)
  76                         | (ydir>=0 ? DST_Y_TOP_TO_BOTTOM : 0));
  77
  78         radeon_fifo_wait(3);
  79         OUTREG(SRC_Y_X, (sy << 16) | sx);
  80         OUTREG(DST_Y_X, (dy << 16) | dx);
  81         OUTREG(DST_HEIGHT_WIDTH, (h << 16) | w);
  82 }
  83
  84
  85 void radeonfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
  86 {
  87         struct radeonfb_info *rinfo = info->par;
  88         struct fb_copyarea modded;
  89         u32 vxres, vyres;
  90         modded.sx = area->sx;
  91         modded.sy = area->sy;
  92         modded.dx = area->dx;
  93         modded.dy = area->dy;
  94         modded.width  = area->width;
  95         modded.height = area->height;
  96
  97         if (info->state != FBINFO_STATE_RUNNING)
  98                 return;
  99         if (radeon_accel_disabled()) {
 100                 cfb_copyarea(info, area);
 101                 return;
 102         }
 103
 104         vxres = info->var.xres;
 105         vyres = info->var.yres;
 106
 107         if(!modded.width || !modded.height ||
 108            modded.sx >= vxres || modded.sy >= vyres ||
 109            modded.dx >= vxres || modded.dy >= vyres)
 110                 return;
 111
 112         if(modded.sx + modded.width > vxres)  modded.width = vxres - modded.sx;
 113         if(modded.dx + modded.width > vxres)  modded.width = vxres - modded.dx;
 114         if(modded.sy + modded.height > vyres) modded.height = vyres - modded.sy;
 115         if(modded.dy + modded.height > vyres) modded.height = vyres - modded.dy;
 116
 117         radeonfb_prim_copyarea(rinfo, &modded);
 118 }
 119
 120 void radeonfb_imageblit(struct fb_info *info, const struct fb_image *image)
 121 {
 122         struct radeonfb_info *rinfo = info->par;
 123
 124         if (info->state != FBINFO_STATE_RUNNING)
 125                 return;
 126         radeon_engine_idle();
 127
 128         cfb_imageblit(info, image);
 129 }
 130
 131 int radeonfb_sync(struct fb_info *info)
 132 {
 133         struct radeonfb_info *rinfo = info->par;
 134
 135         if (info->state != FBINFO_STATE_RUNNING)
 136                 return 0;
 137         radeon_engine_idle();
 138
 139         return 0;
 140 }
 141
 142 void radeonfb_engine_reset(struct radeonfb_info *rinfo)
 143 {
 144         u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
 145         u32 host_path_cntl;
 146
 147         radeon_engine_flush (rinfo);
 148
 149         /* Some ASICs have bugs with dynamic-on feature, which are
 150          * ASIC-version dependent, so we force all blocks on for now
 151          * -- from XFree86
 152          * We don't do that on macs, things just work here with dynamic
 153          * clocking... --BenH
 154          */
 155 #ifdef CONFIG_ALL_PPC
 156         if (_machine != _MACH_Pmac && rinfo->hasCRTC2)
 157 #else
 158         if (rinfo->has_CRTC2)
 159 #endif
 160         {
 161                 u32 tmp;
 162
 163                 tmp = INPLL(SCLK_CNTL);
 164                 OUTPLL(SCLK_CNTL, ((tmp & ~DYN_STOP_LAT_MASK) |
 165                                    CP_MAX_DYN_STOP_LAT |
 166                                    SCLK_FORCEON_MASK));
 167
 168                 if (rinfo->family == CHIP_FAMILY_RV200)
 169                 {
 170                         tmp = INPLL(SCLK_MORE_CNTL);
 171                         OUTPLL(SCLK_MORE_CNTL, tmp | SCLK_MORE_FORCEON);
 172                 }
 173         }
 174
 175         clock_cntl_index = INREG(CLOCK_CNTL_INDEX);
 176         mclk_cntl = INPLL(MCLK_CNTL);
 177
 178         OUTPLL(MCLK_CNTL, (mclk_cntl |
 179                            FORCEON_MCLKA |
 180                            FORCEON_MCLKB |
 181                            FORCEON_YCLKA |
 182                            FORCEON_YCLKB |
 183                            FORCEON_MC |
 184                            FORCEON_AIC));
 185
 186         host_path_cntl = INREG(HOST_PATH_CNTL);
 187         rbbm_soft_reset = INREG(RBBM_SOFT_RESET);
 188
 189         if (rinfo->family == CHIP_FAMILY_R300 ||
 190             rinfo->family == CHIP_FAMILY_R350 ||
 191             rinfo->family == CHIP_FAMILY_RV350) {
 192                 u32 tmp;
 193
 194                 OUTREG(RBBM_SOFT_RESET, (rbbm_soft_reset |
 195                                          SOFT_RESET_CP |
 196                                          SOFT_RESET_HI |
 197                                          SOFT_RESET_E2));
 198                 INREG(RBBM_SOFT_RESET);
 199                 OUTREG(RBBM_SOFT_RESET, 0);
 200                 tmp = INREG(RB2D_DSTCACHE_MODE);
 201                 OUTREG(RB2D_DSTCACHE_MODE, tmp | (1 << 17)); /* FIXME */
 202         } else {
 203                 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset |
 204                                         SOFT_RESET_CP |
 205                                         SOFT_RESET_HI |
 206                                         SOFT_RESET_SE |
 207                                         SOFT_RESET_RE |
 208                                         SOFT_RESET_PP |
 209                                         SOFT_RESET_E2 |
 210                                         SOFT_RESET_RB);
 211                 INREG(RBBM_SOFT_RESET);
 212                 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset & (u32)
 213                                         ~(SOFT_RESET_CP |
 214                                           SOFT_RESET_HI |
 215                                           SOFT_RESET_SE |
 216                                           SOFT_RESET_RE |
 217                                           SOFT_RESET_PP |
 218                                           SOFT_RESET_E2 |
 219                                           SOFT_RESET_RB));
 220                 INREG(RBBM_SOFT_RESET);
 221         }
 222
 223         OUTREG(HOST_PATH_CNTL, host_path_cntl | HDP_SOFT_RESET);
 224         INREG(HOST_PATH_CNTL);
 225         OUTREG(HOST_PATH_CNTL, host_path_cntl);
 226
 227         if (rinfo->family != CHIP_FAMILY_R300 ||
 228             rinfo->family != CHIP_FAMILY_R350 ||
 229             rinfo->family != CHIP_FAMILY_RV350)
 230                 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset);
 231
 232         OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index);
 233         OUTPLL(MCLK_CNTL, mclk_cntl);
 234         if (rinfo->R300_cg_workaround)
 235                 R300_cg_workardound(rinfo);
 236 }
 237
 238 void radeonfb_engine_init (struct radeonfb_info *rinfo)
 239 {
 240         unsigned long temp;
 241
 242         /* disable 3D engine */
 243         OUTREG(RB3D_CNTL, 0);
 244
 245         radeonfb_engine_reset(rinfo);
 246
 247         radeon_fifo_wait (1);
 248         if ((rinfo->family != CHIP_FAMILY_R300) &&
 249             (rinfo->family != CHIP_FAMILY_R350) &&
 250             (rinfo->family != CHIP_FAMILY_RV350))
 251                 OUTREG(RB2D_DSTCACHE_MODE, 0);
 252
 253         radeon_fifo_wait (3);
 254         /* We re-read MC_FB_LOCATION from card as it can have been
 255          * modified by XFree drivers (ouch !)
 256          */
 257         rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;
 258
 259         OUTREG(DEFAULT_PITCH_OFFSET, (rinfo->pitch << 0x16) |
 260                                      (rinfo->fb_local_base >> 10));
 261         OUTREG(DST_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10));
 262         OUTREG(SRC_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10));
 263
 264         radeon_fifo_wait (1);
 265 #if defined(__BIG_ENDIAN)
 266         OUTREGP(DP_DATATYPE, HOST_BIG_ENDIAN_EN, ~HOST_BIG_ENDIAN_EN);
 267 #else
 268         OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN);
 269 #endif
 270         radeon_fifo_wait (2);
 271         OUTREG(DEFAULT_SC_TOP_LEFT, 0);
 272         OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX |
 273                                          DEFAULT_SC_BOTTOM_MAX));
 274
 275         temp = radeon_get_dstbpp(rinfo->depth);
 276         rinfo->dp_gui_master_cntl = ((temp << 8) | GMC_CLR_CMP_CNTL_DIS);
 277
 278         radeon_fifo_wait (1);
 279         OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl |
 280                                     GMC_BRUSH_SOLID_COLOR |
 281                                     GMC_SRC_DATATYPE_COLOR));
 282
 283         radeon_fifo_wait (7);
 284
 285         /* clear line drawing regs */
 286         OUTREG(DST_LINE_START, 0);
 287         OUTREG(DST_LINE_END, 0);
 288
 289         /* set brush color regs */
 290         OUTREG(DP_BRUSH_FRGD_CLR, 0xffffffff);
 291         OUTREG(DP_BRUSH_BKGD_CLR, 0x00000000);
 292
 293         /* set source color regs */
 294         OUTREG(DP_SRC_FRGD_CLR, 0xffffffff);
 295         OUTREG(DP_SRC_BKGD_CLR, 0x00000000);
 296
 297         /* default write mask */
 298         OUTREG(DP_WRITE_MSK, 0xffffffff);
 299
 300         radeon_engine_idle ();
 301 }