3 /* the accelerated functions here are patterned after the
4 * "ACCEL_MMIO" ifdef branches in XFree86
7 static void radeonfb_prim_fillrect(struct radeonfb_info *rinfo,
8 const struct fb_fillrect *region)
12 OUTREG(DP_GUI_MASTER_CNTL,
13 rinfo->dp_gui_master_cntl /* contains, like GMC_DST_32BPP */
14 | GMC_BRUSH_SOLID_COLOR
16 if (radeon_get_dstbpp(rinfo->depth) != DST_8BPP)
17 OUTREG(DP_BRUSH_FRGD_CLR, rinfo->pseudo_palette[region->color]);
19 OUTREG(DP_BRUSH_FRGD_CLR, region->color);
20 OUTREG(DP_WRITE_MSK, 0xffffffff);
21 OUTREG(DP_CNTL, (DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM));
24 OUTREG(DST_Y_X, (region->dy << 16) | region->dx);
25 OUTREG(DST_WIDTH_HEIGHT, (region->width << 16) | region->height);
28 void radeonfb_fillrect(struct fb_info *info, const struct fb_fillrect *region)
30 struct radeonfb_info *rinfo = info->par;
31 struct fb_fillrect modded;
34 if (info->state != FBINFO_STATE_RUNNING)
36 if (info->flags & FBINFO_HWACCEL_DISABLED) {
37 cfb_fillrect(info, region);
41 vxres = info->var.xres_virtual;
42 vyres = info->var.yres_virtual;
44 memcpy(&modded, region, sizeof(struct fb_fillrect));
46 if(!modded.width || !modded.height ||
47 modded.dx >= vxres || modded.dy >= vyres)
50 if(modded.dx + modded.width > vxres) modded.width = vxres - modded.dx;
51 if(modded.dy + modded.height > vyres) modded.height = vyres - modded.dy;
53 radeonfb_prim_fillrect(rinfo, &modded);
56 static void radeonfb_prim_copyarea(struct radeonfb_info *rinfo,
57 const struct fb_copyarea *area)
60 u32 sx, sy, dx, dy, w, h;
62 w = area->width; h = area->height;
63 dx = area->dx; dy = area->dy;
64 sx = area->sx; sy = area->sy;
68 if ( xdir < 0 ) { sx += w-1; dx += w-1; }
69 if ( ydir < 0 ) { sy += h-1; dy += h-1; }
72 OUTREG(DP_GUI_MASTER_CNTL,
73 rinfo->dp_gui_master_cntl /* i.e. GMC_DST_32BPP */
77 | DP_SRC_SOURCE_MEMORY );
78 OUTREG(DP_WRITE_MSK, 0xffffffff);
79 OUTREG(DP_CNTL, (xdir>=0 ? DST_X_LEFT_TO_RIGHT : 0)
80 | (ydir>=0 ? DST_Y_TOP_TO_BOTTOM : 0));
83 OUTREG(SRC_Y_X, (sy << 16) | sx);
84 OUTREG(DST_Y_X, (dy << 16) | dx);
85 OUTREG(DST_HEIGHT_WIDTH, (h << 16) | w);
89 void radeonfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
91 struct radeonfb_info *rinfo = info->par;
92 struct fb_copyarea modded;
98 modded.width = area->width;
99 modded.height = area->height;
101 if (info->state != FBINFO_STATE_RUNNING)
103 if (info->flags & FBINFO_HWACCEL_DISABLED) {
104 cfb_copyarea(info, area);
108 vxres = info->var.xres_virtual;
109 vyres = info->var.yres_virtual;
111 if(!modded.width || !modded.height ||
112 modded.sx >= vxres || modded.sy >= vyres ||
113 modded.dx >= vxres || modded.dy >= vyres)
116 if(modded.sx + modded.width > vxres) modded.width = vxres - modded.sx;
117 if(modded.dx + modded.width > vxres) modded.width = vxres - modded.dx;
118 if(modded.sy + modded.height > vyres) modded.height = vyres - modded.sy;
119 if(modded.dy + modded.height > vyres) modded.height = vyres - modded.dy;
121 radeonfb_prim_copyarea(rinfo, &modded);
124 void radeonfb_imageblit(struct fb_info *info, const struct fb_image *image)
126 struct radeonfb_info *rinfo = info->par;
128 if (info->state != FBINFO_STATE_RUNNING)
130 radeon_engine_idle();
132 cfb_imageblit(info, image);
135 int radeonfb_sync(struct fb_info *info)
137 struct radeonfb_info *rinfo = info->par;
139 if (info->state != FBINFO_STATE_RUNNING)
141 radeon_engine_idle();
146 void radeonfb_engine_reset(struct radeonfb_info *rinfo)
148 u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
151 radeon_engine_flush (rinfo);
153 /* Some ASICs have bugs with dynamic-on feature, which are
154 * ASIC-version dependent, so we force all blocks on for now
156 * We don't do that on macs, things just work here with dynamic
159 #ifdef CONFIG_ALL_PPC
160 if (_machine != _MACH_Pmac && rinfo->hasCRTC2)
162 if (rinfo->has_CRTC2)
167 tmp = INPLL(SCLK_CNTL);
168 OUTPLL(SCLK_CNTL, ((tmp & ~DYN_STOP_LAT_MASK) |
169 CP_MAX_DYN_STOP_LAT |
172 if (rinfo->family == CHIP_FAMILY_RV200)
174 tmp = INPLL(SCLK_MORE_CNTL);
175 OUTPLL(SCLK_MORE_CNTL, tmp | SCLK_MORE_FORCEON);
179 clock_cntl_index = INREG(CLOCK_CNTL_INDEX);
180 mclk_cntl = INPLL(MCLK_CNTL);
182 OUTPLL(MCLK_CNTL, (mclk_cntl |
190 host_path_cntl = INREG(HOST_PATH_CNTL);
191 rbbm_soft_reset = INREG(RBBM_SOFT_RESET);
193 if (rinfo->family == CHIP_FAMILY_R300 ||
194 rinfo->family == CHIP_FAMILY_R350 ||
195 rinfo->family == CHIP_FAMILY_RV350) {
198 OUTREG(RBBM_SOFT_RESET, (rbbm_soft_reset |
202 INREG(RBBM_SOFT_RESET);
203 OUTREG(RBBM_SOFT_RESET, 0);
204 tmp = INREG(RB2D_DSTCACHE_MODE);
205 OUTREG(RB2D_DSTCACHE_MODE, tmp | (1 << 17)); /* FIXME */
207 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset |
215 INREG(RBBM_SOFT_RESET);
216 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset & (u32)
224 INREG(RBBM_SOFT_RESET);
227 OUTREG(HOST_PATH_CNTL, host_path_cntl | HDP_SOFT_RESET);
228 INREG(HOST_PATH_CNTL);
229 OUTREG(HOST_PATH_CNTL, host_path_cntl);
231 if (rinfo->family != CHIP_FAMILY_R300 ||
232 rinfo->family != CHIP_FAMILY_R350 ||
233 rinfo->family != CHIP_FAMILY_RV350)
234 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset);
236 OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index);
237 OUTPLL(MCLK_CNTL, mclk_cntl);
238 if (rinfo->R300_cg_workaround)
239 R300_cg_workardound(rinfo);
242 void radeonfb_engine_init (struct radeonfb_info *rinfo)
246 /* disable 3D engine */
247 OUTREG(RB3D_CNTL, 0);
249 radeonfb_engine_reset(rinfo);
251 radeon_fifo_wait (1);
252 if ((rinfo->family != CHIP_FAMILY_R300) &&
253 (rinfo->family != CHIP_FAMILY_R350) &&
254 (rinfo->family != CHIP_FAMILY_RV350))
255 OUTREG(RB2D_DSTCACHE_MODE, 0);
257 radeon_fifo_wait (3);
258 /* We re-read MC_FB_LOCATION from card as it can have been
259 * modified by XFree drivers (ouch !)
261 rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;
263 OUTREG(DEFAULT_PITCH_OFFSET, (rinfo->pitch << 0x16) |
264 (rinfo->fb_local_base >> 10));
265 OUTREG(DST_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10));
266 OUTREG(SRC_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10));
268 radeon_fifo_wait (1);
269 #if defined(__BIG_ENDIAN)
270 OUTREGP(DP_DATATYPE, HOST_BIG_ENDIAN_EN, ~HOST_BIG_ENDIAN_EN);
272 OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN);
274 radeon_fifo_wait (2);
275 OUTREG(DEFAULT_SC_TOP_LEFT, 0);
276 OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX |
277 DEFAULT_SC_BOTTOM_MAX));
279 temp = radeon_get_dstbpp(rinfo->depth);
280 rinfo->dp_gui_master_cntl = ((temp << 8) | GMC_CLR_CMP_CNTL_DIS);
282 radeon_fifo_wait (1);
283 OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl |
284 GMC_BRUSH_SOLID_COLOR |
285 GMC_SRC_DATATYPE_COLOR));
287 radeon_fifo_wait (7);
289 /* clear line drawing regs */
290 OUTREG(DST_LINE_START, 0);
291 OUTREG(DST_LINE_END, 0);
293 /* set brush color regs */
294 OUTREG(DP_BRUSH_FRGD_CLR, 0xffffffff);
295 OUTREG(DP_BRUSH_BKGD_CLR, 0x00000000);
297 /* set source color regs */
298 OUTREG(DP_SRC_FRGD_CLR, 0xffffffff);
299 OUTREG(DP_SRC_BKGD_CLR, 0x00000000);
301 /* default write mask */
302 OUTREG(DP_WRITE_MSK, 0xffffffff);
304 radeon_engine_idle ();