drivers/video/aty/radeon_base.c

   1 /*
   2  *      drivers/video/radeonfb.c
   3  *      framebuffer driver for ATI Radeon chipset video boards
   4  *
   5  *      Copyright 2003  Ben. Herrenschmidt <benh@kernel.crashing.org>
   6  *      Copyright 2000  Ani Joshi <ajoshi@kernel.crashing.org>
   7  *
   8  *      i2c bits from Luca Tettamanti <kronos@kronoz.cjb.net>
   9  *
  10  *      Special thanks to ATI DevRel team for their hardware donations.
  11  *
  12  *      ...Insert GPL boilerplate here...
  13  *
  14  *      Significant portions of this driver apdated from XFree86 Radeon
  15  *      driver which has the following copyright notice:
  16  *
  17  *      Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
  18  *                     VA Linux Systems Inc., Fremont, California.
  19  *
  20  *      All Rights Reserved.
  21  *
  22  *      Permission is hereby granted, free of charge, to any person obtaining
  23  *      a copy of this software and associated documentation files (the
  24  *      "Software"), to deal in the Software without restriction, including
  25  *      without limitation on the rights to use, copy, modify, merge,
  26  *      publish, distribute, sublicense, and/or sell copies of the Software,
  27  *      and to permit persons to whom the Software is furnished to do so,
  28  *      subject to the following conditions:
  29  *
  30  *      The above copyright notice and this permission notice (including the
  31  *      next paragraph) shall be included in all copies or substantial
  32  *      portions of the Software.
  33  *
  34  *      THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *      EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  36  *      MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *      NON-INFRINGEMENT.  IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
  38  *      THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *      WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  40  *      OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  41  *      DEALINGS IN THE SOFTWARE.
  42  *
  43  *      XFree86 driver authors:
  44  *
  45  *         Kevin E. Martin <martin@xfree86.org>
  46  *         Rickard E. Faith <faith@valinux.com>
  47  *         Alan Hourihane <alanh@fairlite.demon.co.uk>
  48  *
  49  */
  50
  51
  52 #define RADEON_VERSION  "0.2.0"
  53
  54 #include <linux/config.h>
  55 #include <linux/module.h>
  56 #include <linux/moduleparam.h>
  57 #include <linux/kernel.h>
  58 #include <linux/errno.h>
  59 #include <linux/string.h>
  60 #include <linux/mm.h>
  61 #include <linux/tty.h>
  62 #include <linux/slab.h>
  63 #include <linux/delay.h>
  64 #include <linux/fb.h>
  65 #include <linux/ioport.h>
  66 #include <linux/init.h>
  67 #include <linux/pci.h>
  68 #include <linux/vmalloc.h>
  69 #include <linux/device.h>
  70 #include <linux/i2c.h>
  71
  72 #include <asm/io.h>
  73 #include <asm/uaccess.h>
  74
  75 #ifdef CONFIG_PPC_OF
  76
  77 #include <asm/prom.h>
  78 #include <asm/pci-bridge.h>
  79 #include "../macmodes.h"
  80
  81 #ifdef CONFIG_PMAC_BACKLIGHT
  82 #include <asm/backlight.h>
  83 #endif
  84
  85 #ifdef CONFIG_BOOTX_TEXT
  86 #include <asm/btext.h>
  87 #endif
  88
  89 #endif /* CONFIG_PPC_OF */
  90
  91 #ifdef CONFIG_MTRR
  92 #include <asm/mtrr.h>
  93 #endif
  94
  95 #include <video/radeon.h>
  96 #include <linux/radeonfb.h>
  97
  98 #include "../edid.h" // MOVE THAT TO include/video
  99 #include "ati_ids.h"
 100 #include "radeonfb.h"
 101
 102 #define MAX_MAPPED_VRAM (2048*2048*4)
 103 #define MIN_MAPPED_VRAM (1024*768*1)
 104
 105 #define CHIP_DEF(id, family, flags)                                     \
 106         { PCI_VENDOR_ID_ATI, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (flags) | (CHIP_FAMILY_##family) }
 107
 108 static struct pci_device_id radeonfb_pci_table[] = {
 109         /* Mobility M6 */
 110         CHIP_DEF(PCI_CHIP_RADEON_LY,    RV100,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 111         CHIP_DEF(PCI_CHIP_RADEON_LZ,    RV100,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 112         /* Radeon VE/7000 */
 113         CHIP_DEF(PCI_CHIP_RV100_QY,     RV100,  CHIP_HAS_CRTC2),
 114         CHIP_DEF(PCI_CHIP_RV100_QZ,     RV100,  CHIP_HAS_CRTC2),
 115         /* Radeon IGP320M (U1) */
 116         CHIP_DEF(PCI_CHIP_RS100_4336,   RS100,  CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
 117         /* Radeon IGP320 (A3) */
 118         CHIP_DEF(PCI_CHIP_RS100_4136,   RS100,  CHIP_HAS_CRTC2 | CHIP_IS_IGP),
 119         /* IGP330M/340M/350M (U2) */
 120         CHIP_DEF(PCI_CHIP_RS200_4337,   RS200,  CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
 121         /* IGP330/340/350 (A4) */
 122         CHIP_DEF(PCI_CHIP_RS200_4137,   RS200,  CHIP_HAS_CRTC2 | CHIP_IS_IGP),
 123         /* Mobility 7000 IGP */
 124         CHIP_DEF(PCI_CHIP_RS250_4437,   RS200,  CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
 125         /* 7000 IGP (A4+) */
 126         CHIP_DEF(PCI_CHIP_RS250_4237,   RS200,  CHIP_HAS_CRTC2 | CHIP_IS_IGP),
 127         /* 8500 AIW */
 128         CHIP_DEF(PCI_CHIP_R200_BB,      R200,   CHIP_HAS_CRTC2),
 129         CHIP_DEF(PCI_CHIP_R200_BC,      R200,   CHIP_HAS_CRTC2),
 130         /* 8700/8800 */
 131         CHIP_DEF(PCI_CHIP_R200_QH,      R200,   CHIP_HAS_CRTC2),
 132         /* 8500 */
 133         CHIP_DEF(PCI_CHIP_R200_QL,      R200,   CHIP_HAS_CRTC2),
 134         /* 9100 */
 135         CHIP_DEF(PCI_CHIP_R200_QM,      R200,   CHIP_HAS_CRTC2),
 136         /* Mobility M7 */
 137         CHIP_DEF(PCI_CHIP_RADEON_LW,    RV200,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 138         CHIP_DEF(PCI_CHIP_RADEON_LX,    RV200,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 139         /* 7500 */
 140         CHIP_DEF(PCI_CHIP_RV200_QW,     RV200,  CHIP_HAS_CRTC2),
 141         CHIP_DEF(PCI_CHIP_RV200_QX,     RV200,  CHIP_HAS_CRTC2),
 142         /* Mobility M9 */
 143         CHIP_DEF(PCI_CHIP_RV250_Ld,     RV250,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 144         CHIP_DEF(PCI_CHIP_RV250_Le,     RV250,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 145         CHIP_DEF(PCI_CHIP_RV250_Lf,     RV250,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 146         CHIP_DEF(PCI_CHIP_RV250_Lg,     RV250,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 147         /* 9000/Pro */
 148         CHIP_DEF(PCI_CHIP_RV250_If,     RV250,  CHIP_HAS_CRTC2),
 149         CHIP_DEF(PCI_CHIP_RV250_Ig,     RV250,  CHIP_HAS_CRTC2),
 150         /* Mobility 9100 IGP (U3) */
 151         CHIP_DEF(PCI_CHIP_RS300_5835,   RS300,  CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
 152         /* 9100 IGP (A5) */
 153         CHIP_DEF(PCI_CHIP_RS300_5834,   RS300,  CHIP_HAS_CRTC2 | CHIP_IS_IGP),
 154         /* Mobility 9200 (M9+) */
 155         CHIP_DEF(PCI_CHIP_RV280_5C61,   RV280,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 156         CHIP_DEF(PCI_CHIP_RV280_5C63,   RV280,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 157         /* 9200 */
 158         CHIP_DEF(PCI_CHIP_RV280_5960,   RV280,  CHIP_HAS_CRTC2),
 159         CHIP_DEF(PCI_CHIP_RV280_5961,   RV280,  CHIP_HAS_CRTC2),
 160         CHIP_DEF(PCI_CHIP_RV280_5962,   RV280,  CHIP_HAS_CRTC2),
 161         CHIP_DEF(PCI_CHIP_RV280_5964,   RV280,  CHIP_HAS_CRTC2),
 162         /* 9500 */
 163         CHIP_DEF(PCI_CHIP_R300_AD,      R300,   CHIP_HAS_CRTC2),
 164         CHIP_DEF(PCI_CHIP_R300_AE,      R300,   CHIP_HAS_CRTC2),
 165         /* 9600TX / FireGL Z1 */
 166         CHIP_DEF(PCI_CHIP_R300_AF,      R300,   CHIP_HAS_CRTC2),
 167         CHIP_DEF(PCI_CHIP_R300_AG,      R300,   CHIP_HAS_CRTC2),
 168         /* 9700/9500/Pro/FireGL X1 */
 169         CHIP_DEF(PCI_CHIP_R300_ND,      R300,   CHIP_HAS_CRTC2),
 170         CHIP_DEF(PCI_CHIP_R300_NE,      R300,   CHIP_HAS_CRTC2),
 171         CHIP_DEF(PCI_CHIP_R300_NF,      R300,   CHIP_HAS_CRTC2),
 172         CHIP_DEF(PCI_CHIP_R300_NG,      R300,   CHIP_HAS_CRTC2),
 173         /* Mobility M10/M11 */
 174         CHIP_DEF(PCI_CHIP_RV350_NP,     RV350,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 175         CHIP_DEF(PCI_CHIP_RV350_NQ,     RV350,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 176         CHIP_DEF(PCI_CHIP_RV350_NR,     RV350,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 177         CHIP_DEF(PCI_CHIP_RV350_NS,     RV350,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 178         CHIP_DEF(PCI_CHIP_RV350_NT,     RV350,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 179         CHIP_DEF(PCI_CHIP_RV350_NV,     RV350,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
 180         /* 9600/FireGL T2 */
 181         CHIP_DEF(PCI_CHIP_RV350_AP,     RV350,  CHIP_HAS_CRTC2),
 182         CHIP_DEF(PCI_CHIP_RV350_AQ,     RV350,  CHIP_HAS_CRTC2),
 183         CHIP_DEF(PCI_CHIP_RV360_AR,     RV350,  CHIP_HAS_CRTC2),
 184         CHIP_DEF(PCI_CHIP_RV350_AS,     RV350,  CHIP_HAS_CRTC2),
 185         CHIP_DEF(PCI_CHIP_RV350_AT,     RV350,  CHIP_HAS_CRTC2),
 186         CHIP_DEF(PCI_CHIP_RV350_AV,     RV350,  CHIP_HAS_CRTC2),
 187         /* 9800/Pro/FileGL X2 */
 188         CHIP_DEF(PCI_CHIP_R350_AH,      R350,   CHIP_HAS_CRTC2),
 189         CHIP_DEF(PCI_CHIP_R350_AI,      R350,   CHIP_HAS_CRTC2),
 190         CHIP_DEF(PCI_CHIP_R350_AJ,      R350,   CHIP_HAS_CRTC2),
 191         CHIP_DEF(PCI_CHIP_R350_AK,      R350,   CHIP_HAS_CRTC2),
 192         CHIP_DEF(PCI_CHIP_R350_NH,      R350,   CHIP_HAS_CRTC2),
 193         CHIP_DEF(PCI_CHIP_R350_NI,      R350,   CHIP_HAS_CRTC2),
 194         CHIP_DEF(PCI_CHIP_R360_NJ,      R350,   CHIP_HAS_CRTC2),
 195         CHIP_DEF(PCI_CHIP_R350_NK,      R350,   CHIP_HAS_CRTC2),
 196         /* Original Radeon/7200 */
 197         CHIP_DEF(PCI_CHIP_RADEON_QD,    RADEON, 0),
 198         CHIP_DEF(PCI_CHIP_RADEON_QE,    RADEON, 0),
 199         CHIP_DEF(PCI_CHIP_RADEON_QF,    RADEON, 0),
 200         CHIP_DEF(PCI_CHIP_RADEON_QG,    RADEON, 0),
 201         { 0, }
 202 };
 203 MODULE_DEVICE_TABLE(pci, radeonfb_pci_table);
 204
 205
 206 typedef struct {
 207         u16 reg;
 208         u32 val;
 209 } reg_val;
 210
 211
 212 /* these common regs are cleared before mode setting so they do not
 213  * interfere with anything
 214  */
 215 static reg_val common_regs[] = {
 216         { OVR_CLR, 0 },
 217         { OVR_WID_LEFT_RIGHT, 0 },
 218         { OVR_WID_TOP_BOTTOM, 0 },
 219         { OV0_SCALE_CNTL, 0 },
 220         { SUBPIC_CNTL, 0 },
 221         { VIPH_CONTROL, 0 },
 222         { I2C_CNTL_1, 0 },
 223         { GEN_INT_CNTL, 0 },
 224         { CAP0_TRIG_CNTL, 0 },
 225         { CAP1_TRIG_CNTL, 0 },
 226 };
 227
 228 /*
 229  * globals
 230  */
 231
 232 static char *mode_option;
 233 static char *monitor_layout;
 234 static int noaccel = 0;
 235 static int nomodeset = 0;
 236 static int ignore_edid = 0;
 237 static int mirror = 0;
 238 static int panel_yres = 0;
 239 static int force_dfp = 0;
 240 static int force_measure_pll = 0;
 241 #ifdef CONFIG_MTRR
 242 static int nomtrr = 0;
 243 #endif
 244
 245 /*
 246  * prototypes
 247  */
 248
 249
 250 #ifdef CONFIG_PPC_OF
 251
 252 #ifdef CONFIG_PMAC_BACKLIGHT
 253 static int radeon_set_backlight_enable(int on, int level, void *data);
 254 static int radeon_set_backlight_level(int level, void *data);
 255 static struct backlight_controller radeon_backlight_controller = {
 256         radeon_set_backlight_enable,
 257         radeon_set_backlight_level
 258 };
 259 #endif /* CONFIG_PMAC_BACKLIGHT */
 260
 261 #endif /* CONFIG_PPC_OF */
 262
 263 static void __devexit radeon_unmap_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
 264 {
 265         // leave it disabled and unassigned
 266         struct resource *r = &dev->resource[PCI_ROM_RESOURCE];
 267
 268         if (!rinfo->bios_seg)
 269                 return;
 270         iounmap(rinfo->bios_seg);
 271
 272         /* Release the ROM resource if we used it in the first place */
 273         if (r->parent && r->flags & PCI_ROM_ADDRESS_ENABLE) {
 274                 release_resource(r);
 275                 r->flags &= ~PCI_ROM_ADDRESS_ENABLE;
 276                 r->end -= r->start;
 277                 r->start = 0;
 278         }
 279         /* This will disable and set address to unassigned */
 280         pci_write_config_dword(dev, dev->rom_base_reg, 0);
 281 }
 282
 283 static int __devinit radeon_map_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
 284 {
 285         void *rom;
 286         struct resource *r;
 287         u16 dptr;
 288         u8 rom_type;
 289
 290         /* If this is a primary card, there is a shadow copy of the
 291          * ROM somewhere in the first meg. We will just ignore the copy
 292          * and use the ROM directly.
 293          */
 294
 295         /* Fix from ATI for problem with Radeon hardware not leaving ROM enabled */
 296         unsigned int temp;
 297         temp = INREG(MPP_TB_CONFIG);
 298         temp &= 0x00ffffffu;
 299         temp |= 0x04 << 24;
 300         OUTREG(MPP_TB_CONFIG, temp);
 301         temp = INREG(MPP_TB_CONFIG);
 302
 303         /* no need to search for the ROM, just ask the card where it is. */
 304         r = &dev->resource[PCI_ROM_RESOURCE];
 305
 306         /* assign the ROM an address if it doesn't have one */
 307         if (r->parent == NULL)
 308                 pci_assign_resource(dev, PCI_ROM_RESOURCE);
 309
 310         /* enable if needed */
 311         if (!(r->flags & PCI_ROM_ADDRESS_ENABLE)) {
 312                 pci_write_config_dword(dev, dev->rom_base_reg,
 313                                        r->start | PCI_ROM_ADDRESS_ENABLE);
 314                 r->flags |= PCI_ROM_ADDRESS_ENABLE;
 315         }
 316
 317         rom = ioremap(r->start, r->end - r->start + 1);
 318         if (!rom) {
 319                 printk(KERN_ERR "radeonfb: ROM failed to map\n");
 320                 return -ENOMEM;
 321         }
 322
 323         rinfo->bios_seg = rom;
 324
 325         /* Very simple test to make sure it appeared */
 326         if (BIOS_IN16(0) != 0xaa55) {
 327                 printk(KERN_ERR "radeonfb: Invalid ROM signature %x should be 0xaa55\n",
 328                        BIOS_IN16(0));
 329                 goto failed;
 330         }
 331         /* Look for the PCI data to check the ROM type */
 332         dptr = BIOS_IN16(0x18);
 333
 334         /* Check the PCI data signature. If it's wrong, we still assume a normal x86 ROM
 335          * for now, until I've verified this works everywhere. The goal here is more
 336          * to phase out Open Firmware images.
 337          *
 338          * Currently, we only look at the first PCI data, we could iteratre and deal with
 339          * them all, and we should use fb_bios_start relative to start of image and not
 340          * relative start of ROM, but so far, I never found a dual-image ATI card
 341          *
 342          * typedef struct {
 343          *      u32     signature;      + 0x00
 344          *      u16     vendor;         + 0x04
 345          *      u16     device;         + 0x06
 346          *      u16     reserved_1;     + 0x08
 347          *      u16     dlen;           + 0x0a
 348          *      u8      drevision;      + 0x0c
 349          *      u8      class_hi;       + 0x0d
 350          *      u16     class_lo;       + 0x0e
 351          *      u16     ilen;           + 0x10
 352          *      u16     irevision;      + 0x12
 353          *      u8      type;           + 0x14
 354          *      u8      indicator;      + 0x15
 355          *      u16     reserved_2;     + 0x16
 356          * } pci_data_t;
 357          */
 358         if (BIOS_IN32(dptr) !=  (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {
 359                 printk(KERN_WARNING "radeonfb: PCI DATA signature in ROM incorrect: %08x\n",
 360                        BIOS_IN32(dptr));
 361                 goto anyway;
 362         }
 363         rom_type = BIOS_IN8(dptr + 0x14);
 364         switch(rom_type) {
 365         case 0:
 366                 printk(KERN_INFO "radeonfb: Found Intel x86 BIOS ROM Image\n");
 367                 break;
 368         case 1:
 369                 printk(KERN_INFO "radeonfb: Found Open Firmware ROM Image\n");
 370                 goto failed;
 371         case 2:
 372                 printk(KERN_INFO "radeonfb: Found HP PA-RISC ROM Image\n");
 373                 goto failed;
 374         default:
 375                 printk(KERN_INFO "radeonfb: Found unknown type %d ROM Image\n", rom_type);
 376                 goto failed;
 377         }
 378  anyway:
 379         /* Locate the flat panel infos, do some sanity checking !!! */
 380         rinfo->fp_bios_start = BIOS_IN16(0x48);
 381         return 0;
 382
 383  failed:
 384         rinfo->bios_seg = NULL;
 385         radeon_unmap_ROM(rinfo, dev);
 386         return -ENXIO;
 387 }
 388
 389 #ifdef CONFIG_X86
 390 static int  __devinit radeon_find_mem_vbios(struct radeonfb_info *rinfo)
 391 {
 392         /* I simplified this code as we used to miss the signatures in
 393          * a lot of case. It's now closer to XFree, we just don't check
 394          * for signatures at all... Something better will have to be done
 395          * if we end up having conflicts
 396          */
 397         u32  segstart;
 398         unsigned char *rom_base = NULL;
 399
 400         for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
 401                 rom_base = (char *)ioremap(segstart, 0x10000);
 402                 if (rom_base == NULL)
 403                         return -ENOMEM;
 404                 if ((*rom_base == 0x55) && (((*(rom_base + 1)) & 0xff) == 0xaa))
 405                         break;
 406                 iounmap(rom_base);
 407                 rom_base = NULL;
 408         }
 409         if (rom_base == NULL)
 410                 return -ENXIO;
 411
 412         /* Locate the flat panel infos, do some sanity checking !!! */
 413         rinfo->bios_seg = rom_base;
 414         rinfo->fp_bios_start = BIOS_IN16(0x48);
 415
 416         return 0;
 417 }
 418 #endif
 419
 420 #ifdef CONFIG_PPC_OF
 421 /*
 422  * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device
 423  * tree. Hopefully, ATI OF driver is kind enough to fill these
 424  */
 425 static int __devinit radeon_read_xtal_OF (struct radeonfb_info *rinfo)
 426 {
 427         struct device_node *dp;
 428         u32 *val;
 429
 430         dp = pci_device_to_OF_node(rinfo->pdev);
 431         if (dp == NULL) {
 432                 printk(KERN_WARNING "radeonfb: Cannot match card to OF node !\n");
 433                 return -ENODEV;
 434         }
 435         val = (u32 *) get_property(dp, "ATY,RefCLK", NULL);
 436         if (!val || !*val) {
 437                 printk(KERN_WARNING "radeonfb: No ATY,RefCLK property !\n");
 438                 return -EINVAL;
 439         }
 440
 441         rinfo->pll.ref_clk = (*val) / 10;
 442
 443         val = (u32 *) get_property(dp, "ATY,SCLK", NULL);
 444         if (val && *val)
 445                 rinfo->pll.sclk = (*val) / 10;
 446
 447         val = (u32 *) get_property(dp, "ATY,MCLK", NULL);
 448         if (val && *val)
 449                 rinfo->pll.mclk = (*val) / 10;
 450
 451         return 0;
 452 }
 453 #endif /* CONFIG_PPC_OF */
 454
 455 /*
 456  * Read PLL infos from chip registers
 457  */
 458 static int __devinit radeon_probe_pll_params(struct radeonfb_info *rinfo)
 459 {
 460         unsigned char ppll_div_sel;
 461         unsigned Ns, Nm, M;
 462         unsigned sclk, mclk, tmp, ref_div;
 463         int hTotal, vTotal, num, denom, m, n;
 464         unsigned long long hz, vclk;
 465         long xtal;
 466         struct timeval start_tv, stop_tv;
 467         long total_secs, total_usecs;
 468         int i;
 469
 470         /* Ugh, we cut interrupts, bad bad bad, but we want some precision
 471          * here, so... --BenH
 472          */
 473
 474         /* Flush PCI buffers ? */
 475         tmp = INREG(DEVICE_ID);
 476
 477         local_irq_disable();
 478
 479         for(i=0; i<1000000; i++)
 480                 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
 481                         break;
 482
 483         do_gettimeofday(&start_tv);
 484
 485         for(i=0; i<1000000; i++)
 486                 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) != 0)
 487                         break;
 488
 489         for(i=0; i<1000000; i++)
 490                 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
 491                         break;
 492
 493         do_gettimeofday(&stop_tv);
 494
 495         local_irq_enable();
 496
 497         total_secs = stop_tv.tv_sec - start_tv.tv_sec;
 498         if (total_secs > 10)
 499                 return -1;
 500         total_usecs = stop_tv.tv_usec - start_tv.tv_usec;
 501         total_usecs += total_secs * 1000000;
 502         if (total_usecs < 0)
 503                 total_usecs = -total_usecs;
 504         hz = 1000000/total_usecs;
 505
 506         hTotal = ((INREG(CRTC_H_TOTAL_DISP) & 0x1ff) + 1) * 8;
 507         vTotal = ((INREG(CRTC_V_TOTAL_DISP) & 0x3ff) + 1);
 508         vclk = (long long)hTotal * (long long)vTotal * hz;
 509
 510         switch((INPLL(PPLL_REF_DIV) & 0x30000) >> 16) {
 511         case 0:
 512         default:
 513                 num = 1;
 514                 denom = 1;
 515                 break;
 516         case 1:
 517                 n = ((INPLL(X_MPLL_REF_FB_DIV) >> 16) & 0xff);
 518                 m = (INPLL(X_MPLL_REF_FB_DIV) & 0xff);
 519                 num = 2*n;
 520                 denom = 2*m;
 521                 break;
 522         case 2:
 523                 n = ((INPLL(X_MPLL_REF_FB_DIV) >> 8) & 0xff);
 524                 m = (INPLL(X_MPLL_REF_FB_DIV) & 0xff);
 525                 num = 2*n;
 526                 denom = 2*m;
 527         break;
 528         }
 529
 530         OUTREG8(CLOCK_CNTL_INDEX, 1);
 531         ppll_div_sel = INREG8(CLOCK_CNTL_DATA + 1) & 0x3;
 532
 533         n = (INPLL(PPLL_DIV_0 + ppll_div_sel) & 0x7ff);
 534         m = (INPLL(PPLL_REF_DIV) & 0x3ff);
 535
 536         num *= n;
 537         denom *= m;
 538
 539         switch ((INPLL(PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) {
 540         case 1:
 541                 denom *= 2;
 542                 break;
 543         case 2:
 544                 denom *= 4;
 545                 break;
 546         case 3:
 547                 denom *= 8;
 548                 break;
 549         case 4:
 550                 denom *= 3;
 551                 break;
 552         case 6:
 553                 denom *= 6;
 554                 break;
 555         case 7:
 556                 denom *= 12;
 557                 break;
 558         }
 559
 560         vclk *= denom;
 561         do_div(vclk, 1000 * num);
 562         xtal = vclk;
 563
 564         if ((xtal > 26900) && (xtal < 27100))
 565                 xtal = 2700;
 566         else if ((xtal > 14200) && (xtal < 14400))
 567                 xtal = 1432;
 568         else if ((xtal > 29400) && (xtal < 29600))
 569                 xtal = 2950;
 570         else {
 571                 printk(KERN_WARNING "xtal calculation failed: %ld\n", xtal);
 572                 return -1;
 573         }
 574
 575         tmp = INPLL(X_MPLL_REF_FB_DIV);
 576         ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;
 577
 578         Ns = (tmp & 0xff0000) >> 16;
 579         Nm = (tmp & 0xff00) >> 8;
 580         M = (tmp & 0xff);
 581         sclk = round_div((2 * Ns * xtal), (2 * M));
 582         mclk = round_div((2 * Nm * xtal), (2 * M));
 583
 584         /* we're done, hopefully these are sane values */
 585         rinfo->pll.ref_clk = xtal;
 586         rinfo->pll.ref_div = ref_div;
 587         rinfo->pll.sclk = sclk;
 588         rinfo->pll.mclk = mclk;
 589
 590         return 0;
 591 }
 592
 593 /*
 594  * Retreive PLL infos by different means (BIOS, Open Firmware, register probing...)
 595  */
 596 static void __devinit radeon_get_pllinfo(struct radeonfb_info *rinfo)
 597 {
 598 #ifdef CONFIG_PPC_OF
 599         /*
 600          * Retreive PLL infos from Open Firmware first
 601          */
 602         if (!force_measure_pll && radeon_read_xtal_OF(rinfo) == 0) {
 603                 printk(KERN_INFO "radeonfb: Retreived PLL infos from Open Firmware\n");
 604                 rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;
 605                 /* FIXME: Max clock may be higher on newer chips */
 606                 rinfo->pll.ppll_min = 12000;
 607                 rinfo->pll.ppll_max = 35000;
 608                 goto found;
 609         }
 610 #endif /* CONFIG_PPC_OF */
 611
 612         /*
 613          * Check out if we have an X86 which gave us some PLL informations
 614          * and if yes, retreive them
 615          */
 616         if (!force_measure_pll && rinfo->bios_seg) {
 617                 u16 pll_info_block = BIOS_IN16(rinfo->fp_bios_start + 0x30);
 618
 619                 rinfo->pll.sclk         = BIOS_IN16(pll_info_block + 0x08);
 620                 rinfo->pll.mclk         = BIOS_IN16(pll_info_block + 0x0a);
 621                 rinfo->pll.ref_clk      = BIOS_IN16(pll_info_block + 0x0e);
 622                 rinfo->pll.ref_div      = BIOS_IN16(pll_info_block + 0x10);
 623                 rinfo->pll.ppll_min     = BIOS_IN32(pll_info_block + 0x12);
 624                 rinfo->pll.ppll_max     = BIOS_IN32(pll_info_block + 0x16);
 625
 626                 printk(KERN_INFO "radeonfb: Retreived PLL infos from BIOS\n");
 627                 goto found;
 628         }
 629
 630         /*
 631          * We didn't get PLL parameters from either OF or BIOS, we try to
 632          * probe them
 633          */
 634         if (radeon_probe_pll_params(rinfo) == 0) {
 635                 printk(KERN_INFO "radeonfb: Retreived PLL infos from registers\n");
 636                 /* FIXME: Max clock may be higher on newer chips */
 637                 rinfo->pll.ppll_min = 12000;
 638                 rinfo->pll.ppll_max = 35000;
 639                 goto found;
 640         }
 641
 642         /*
 643          * Neither of the above worked, we have a few default values, though
 644          * that's mostly incomplete
 645          */
 646         switch (rinfo->chipset) {
 647         case PCI_DEVICE_ID_ATI_RADEON_QW:
 648         case PCI_DEVICE_ID_ATI_RADEON_QX:
 649                 rinfo->pll.ppll_max = 35000;
 650                 rinfo->pll.ppll_min = 12000;
 651                 rinfo->pll.mclk = 23000;
 652                 rinfo->pll.sclk = 23000;
 653                 rinfo->pll.ref_clk = 2700;
 654                 break;
 655         case PCI_DEVICE_ID_ATI_RADEON_QL:
 656         case PCI_DEVICE_ID_ATI_RADEON_QN:
 657         case PCI_DEVICE_ID_ATI_RADEON_QO:
 658         case PCI_DEVICE_ID_ATI_RADEON_Ql:
 659         case PCI_DEVICE_ID_ATI_RADEON_BB:
 660                 rinfo->pll.ppll_max = 35000;
 661                 rinfo->pll.ppll_min = 12000;
 662                 rinfo->pll.mclk = 27500;
 663                 rinfo->pll.sclk = 27500;
 664                 rinfo->pll.ref_clk = 2700;
 665                 break;
 666         case PCI_DEVICE_ID_ATI_RADEON_Id:
 667         case PCI_DEVICE_ID_ATI_RADEON_Ie:
 668         case PCI_DEVICE_ID_ATI_RADEON_If:
 669         case PCI_DEVICE_ID_ATI_RADEON_Ig:
 670                 rinfo->pll.ppll_max = 35000;
 671                 rinfo->pll.ppll_min = 12000;
 672                 rinfo->pll.mclk = 25000;
 673                 rinfo->pll.sclk = 25000;
 674                 rinfo->pll.ref_clk = 2700;
 675                 break;
 676         case PCI_DEVICE_ID_ATI_RADEON_ND:
 677         case PCI_DEVICE_ID_ATI_RADEON_NE:
 678         case PCI_DEVICE_ID_ATI_RADEON_NF:
 679         case PCI_DEVICE_ID_ATI_RADEON_NG:
 680                 rinfo->pll.ppll_max = 40000;
 681                 rinfo->pll.ppll_min = 20000;
 682                 rinfo->pll.mclk = 27000;
 683                 rinfo->pll.sclk = 27000;
 684                 rinfo->pll.ref_clk = 2700;
 685                 break;
 686         case PCI_DEVICE_ID_ATI_RADEON_QD:
 687         case PCI_DEVICE_ID_ATI_RADEON_QE:
 688         case PCI_DEVICE_ID_ATI_RADEON_QF:
 689         case PCI_DEVICE_ID_ATI_RADEON_QG:
 690         default:
 691                 rinfo->pll.ppll_max = 35000;
 692                 rinfo->pll.ppll_min = 12000;
 693                 rinfo->pll.mclk = 16600;
 694                 rinfo->pll.sclk = 16600;
 695                 rinfo->pll.ref_clk = 2700;
 696                 break;
 697         }
 698         rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;
 699
 700         printk(KERN_INFO "radeonfb: Used default PLL infos\n");
 701
 702 found:
 703         /*
 704          * Some methods fail to retreive SCLK and MCLK values, we apply default
 705          * settings in this case (200Mhz). If that really happne often, we could
 706          * fetch from registers instead...
 707          */
 708         if (rinfo->pll.mclk == 0)
 709                 rinfo->pll.mclk = 20000;
 710         if (rinfo->pll.sclk == 0)
 711                 rinfo->pll.sclk = 20000;
 712
 713         printk("radeonfb: Reference=%d.%02d MHz (RefDiv=%d) Memory=%d.%02d Mhz, System=%d.%02d MHz\n",
 714                rinfo->pll.ref_clk / 100, rinfo->pll.ref_clk % 100,
 715                rinfo->pll.ref_div,
 716                rinfo->pll.mclk / 100, rinfo->pll.mclk % 100,
 717                rinfo->pll.sclk / 100, rinfo->pll.sclk % 100);
 718 }
 719
 720 static int radeonfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info)
 721 {
 722         struct radeonfb_info *rinfo = info->par;
 723         struct fb_var_screeninfo v;
 724         int nom, den;
 725         unsigned int pitch;
 726
 727         if (radeon_match_mode(rinfo, &v, var))
 728                 return -EINVAL;
 729
 730         switch (v.bits_per_pixel) {
 731                 case 0 ... 8:
 732                         v.bits_per_pixel = 8;
 733                         break;
 734                 case 9 ... 16:
 735                         v.bits_per_pixel = 16;
 736                         break;
 737                 case 17 ... 24:
 738 #if 0 /* Doesn't seem to work */
 739                         v.bits_per_pixel = 24;
 740                         break;
 741 #endif
 742                         return -EINVAL;
 743                 case 25 ... 32:
 744                         v.bits_per_pixel = 32;
 745                         break;
 746                 default:
 747                         return -EINVAL;
 748         }
 749
 750         switch (var_to_depth(&v)) {
 751                 case 8:
 752                         nom = den = 1;
 753                         v.red.offset = v.green.offset = v.blue.offset = 0;
 754                         v.red.length = v.green.length = v.blue.length = 8;
 755                         v.transp.offset = v.transp.length = 0;
 756                         break;
 757                 case 15:
 758                         nom = 2;
 759                         den = 1;
 760                         v.red.offset = 10;
 761                         v.green.offset = 5;
 762                         v.blue.offset = 0;
 763                         v.red.length = v.green.length = v.blue.length = 5;
 764                         v.transp.offset = v.transp.length = 0;
 765                         break;
 766                 case 16:
 767                         nom = 2;
 768                         den = 1;
 769                         v.red.offset = 11;
 770                         v.green.offset = 5;
 771                         v.blue.offset = 0;
 772                         v.red.length = 5;
 773                         v.green.length = 6;
 774                         v.blue.length = 5;
 775                         v.transp.offset = v.transp.length = 0;
 776                         break;
 777                 case 24:
 778                         nom = 4;
 779                         den = 1;
 780                         v.red.offset = 16;
 781                         v.green.offset = 8;
 782                         v.blue.offset = 0;
 783                         v.red.length = v.blue.length = v.green.length = 8;
 784                         v.transp.offset = v.transp.length = 0;
 785                         break;
 786                 case 32:
 787                         nom = 4;
 788                         den = 1;
 789                         v.red.offset = 16;
 790                         v.green.offset = 8;
 791                         v.blue.offset = 0;
 792                         v.red.length = v.blue.length = v.green.length = 8;
 793                         v.transp.offset = 24;
 794                         v.transp.length = 8;
 795                         break;
 796                 default:
 797                         printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n",
 798                                 var->xres, var->yres, var->bits_per_pixel);
 799                         return -EINVAL;
 800         }
 801
 802         if (v.yres_virtual < v.yres)
 803                 v.yres_virtual = v.yres;
 804         if (v.xres_virtual < v.xres)
 805                 v.xres_virtual = v.xres;
 806
 807
 808         /* XXX I'm adjusting xres_virtual to the pitch, that may help XFree
 809          * with some panels, though I don't quite like this solution
 810          */
 811         if (rinfo->info->flags & FBINFO_HWACCEL_DISABLED) {
 812                 v.xres_virtual = v.xres_virtual & ~7ul;
 813         } else {
 814                 pitch = ((v.xres_virtual * ((v.bits_per_pixel + 1) / 8) + 0x3f)
 815                                 & ~(0x3f)) >> 6;
 816                 v.xres_virtual = (pitch << 6) / ((v.bits_per_pixel + 1) / 8);
 817         }
 818
 819         if (((v.xres_virtual * v.yres_virtual * nom) / den) > rinfo->mapped_vram)
 820                 return -EINVAL;
 821
 822         if (v.xres_virtual < v.xres)
 823                 v.xres = v.xres_virtual;
 824
 825         if (v.xoffset < 0)
 826                 v.xoffset = 0;
 827         if (v.yoffset < 0)
 828                 v.yoffset = 0;
 829
 830         if (v.xoffset > v.xres_virtual - v.xres)
 831                 v.xoffset = v.xres_virtual - v.xres - 1;
 832
 833         if (v.yoffset > v.yres_virtual - v.yres)
 834                 v.yoffset = v.yres_virtual - v.yres - 1;
 835
 836         v.red.msb_right = v.green.msb_right = v.blue.msb_right =
 837                           v.transp.offset = v.transp.length =
 838                           v.transp.msb_right = 0;
 839
 840         memcpy(var, &v, sizeof(v));
 841
 842         return 0;
 843 }
 844
 845
 846 static int radeonfb_pan_display (struct fb_var_screeninfo *var,
 847                                  struct fb_info *info)
 848 {
 849         struct radeonfb_info *rinfo = info->par;
 850
 851         if ((var->xoffset + var->xres > var->xres_virtual)
 852             || (var->yoffset + var->yres > var->yres_virtual))
 853                return -EINVAL;
 854
 855         if (rinfo->asleep)
 856                 return 0;
 857
 858         radeon_fifo_wait(2);
 859         OUTREG(CRTC_OFFSET, ((var->yoffset * var->xres_virtual + var->xoffset)
 860                              * var->bits_per_pixel / 8) & ~7);
 861         return 0;
 862 }
 863
 864
 865 static int radeonfb_ioctl (struct inode *inode, struct file *file, unsigned int cmd,
 866                            unsigned long arg, struct fb_info *info)
 867 {
 868         struct radeonfb_info *rinfo = info->par;
 869         unsigned int tmp;
 870         u32 value = 0;
 871         int rc;
 872
 873         switch (cmd) {
 874                 /*
 875                  * TODO:  set mirror accordingly for non-Mobility chipsets with 2 CRTC's
 876                  *        and do something better using 2nd CRTC instead of just hackish
 877                  *        routing to second output
 878                  */
 879                 case FBIO_RADEON_SET_MIRROR:
 880                         if (!rinfo->is_mobility)
 881                                 return -EINVAL;
 882
 883                         rc = get_user(value, (__u32 __user *)arg);
 884
 885                         if (rc)
 886                                 return rc;
 887
 888                         radeon_fifo_wait(2);
 889                         if (value & 0x01) {
 890                                 tmp = INREG(LVDS_GEN_CNTL);
 891
 892                                 tmp |= (LVDS_ON | LVDS_BLON);
 893                         } else {
 894                                 tmp = INREG(LVDS_GEN_CNTL);
 895
 896                                 tmp &= ~(LVDS_ON | LVDS_BLON);
 897                         }
 898
 899                         OUTREG(LVDS_GEN_CNTL, tmp);
 900
 901                         if (value & 0x02) {
 902                                 tmp = INREG(CRTC_EXT_CNTL);
 903                                 tmp |= CRTC_CRT_ON;
 904
 905                                 mirror = 1;
 906                         } else {
 907                                 tmp = INREG(CRTC_EXT_CNTL);
 908                                 tmp &= ~CRTC_CRT_ON;
 909
 910                                 mirror = 0;
 911                         }
 912
 913                         OUTREG(CRTC_EXT_CNTL, tmp);
 914
 915                         break;
 916                 case FBIO_RADEON_GET_MIRROR:
 917                         if (!rinfo->is_mobility)
 918                                 return -EINVAL;
 919
 920                         tmp = INREG(LVDS_GEN_CNTL);
 921                         if ((LVDS_ON | LVDS_BLON) & tmp)
 922                                 value |= 0x01;
 923
 924                         tmp = INREG(CRTC_EXT_CNTL);
 925                         if (CRTC_CRT_ON & tmp)
 926                                 value |= 0x02;
 927
 928                         return put_user(value, (__u32 __user *)arg);
 929                 default:
 930                         return -EINVAL;
 931         }
 932
 933         return -EINVAL;
 934 }
 935
 936
 937 static int radeon_screen_blank (struct radeonfb_info *rinfo, int blank)
 938 {
 939         u32 val = INREG(CRTC_EXT_CNTL);
 940         u32 val2 = 0;
 941
 942         if (rinfo->mon1_type == MT_LCD)
 943                 val2 = INREG(LVDS_GEN_CNTL) & ~LVDS_DISPLAY_DIS;
 944
 945         /* reset it */
 946         val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
 947                  CRTC_VSYNC_DIS);
 948
 949         switch (blank) {
 950                 case VESA_NO_BLANKING:
 951                         break;
 952                 case VESA_VSYNC_SUSPEND:
 953                         val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS);
 954                         break;
 955                 case VESA_HSYNC_SUSPEND:
 956                         val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS);
 957                         break;
 958                 case VESA_POWERDOWN:
 959                         val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS |
 960                                 CRTC_HSYNC_DIS);
 961                         val2 |= (LVDS_DISPLAY_DIS);
 962                         break;
 963         }
 964
 965         radeon_fifo_wait(1);
 966         switch (rinfo->mon1_type) {
 967                 case MT_LCD:
 968                         OUTREG(LVDS_GEN_CNTL, val2);
 969                         break;
 970                 case MT_CRT:
 971                 default:
 972                         OUTREG(CRTC_EXT_CNTL, val);
 973                         break;
 974         }
 975
 976         return 0;
 977 }
 978
 979 int radeonfb_blank (int blank, struct fb_info *info)
 980 {
 981         struct radeonfb_info *rinfo = info->par;
 982
 983         if (rinfo->asleep)
 984                 return 0;
 985
 986 #ifdef CONFIG_PMAC_BACKLIGHT
 987         if (rinfo->mon1_type == MT_LCD && _machine == _MACH_Pmac && blank)
 988                 set_backlight_enable(0);
 989 #endif
 990
 991         radeon_screen_blank(rinfo, blank);
 992
 993 #ifdef CONFIG_PMAC_BACKLIGHT
 994         if (rinfo->mon1_type == MT_LCD && _machine == _MACH_Pmac && !blank)
 995                 set_backlight_enable(1);
 996 #endif
 997
 998         return 0;
 999 }
1000
1001 static int radeonfb_setcolreg (unsigned regno, unsigned red, unsigned green,
1002                              unsigned blue, unsigned transp, struct fb_info *info)
1003 {
1004         struct radeonfb_info *rinfo = info->par;
1005         u32 pindex;
1006         unsigned int i;
1007
1008         if (regno > 255)
1009                 return 1;
1010
1011         red >>= 8;
1012         green >>= 8;
1013         blue >>= 8;
1014         rinfo->palette[regno].red = red;
1015         rinfo->palette[regno].green = green;
1016         rinfo->palette[regno].blue = blue;
1017
1018         /* default */
1019         pindex = regno;
1020
1021         if (!rinfo->asleep) {
1022                 u32 dac_cntl2, vclk_cntl = 0;
1023
1024                 radeon_fifo_wait(9);
1025                 if (rinfo->is_mobility) {
1026                         vclk_cntl = INPLL(VCLK_ECP_CNTL);
1027                         OUTPLL(VCLK_ECP_CNTL, vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1028                 }
1029
1030                 /* Make sure we are on first palette */
1031                 if (rinfo->has_CRTC2) {
1032                         dac_cntl2 = INREG(DAC_CNTL2);
1033                         dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
1034                         OUTREG(DAC_CNTL2, dac_cntl2);
1035                 }
1036
1037                 if (rinfo->bpp == 16) {
1038                         pindex = regno * 8;
1039
1040                         if (rinfo->depth == 16 && regno > 63)
1041                                 return 1;
1042                         if (rinfo->depth == 15 && regno > 31)
1043                                 return 1;
1044
1045                         /* For 565, the green component is mixed one order below */
1046                         if (rinfo->depth == 16) {
1047                                 OUTREG(PALETTE_INDEX, pindex>>1);
1048                                 OUTREG(PALETTE_DATA, (rinfo->palette[regno>>1].red << 16) |
1049                                         (green << 8) | (rinfo->palette[regno>>1].blue));
1050                                 green = rinfo->palette[regno<<1].green;
1051                         }
1052                 }
1053
1054                 if (rinfo->depth != 16 || regno < 32) {
1055                         OUTREG(PALETTE_INDEX, pindex);
1056                         OUTREG(PALETTE_DATA, (red << 16) | (green << 8) | blue);
1057                 }
1058                 if (rinfo->is_mobility)
1059                         OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1060         }
1061         if (regno < 16) {
1062                 u32 *pal = info->pseudo_palette;
1063                 switch (rinfo->depth) {
1064                 case 15:
1065                         pal[regno] = (regno << 10) | (regno << 5) | regno;
1066                         break;
1067                 case 16:
1068                         pal[regno] = (regno << 11) | (regno << 5) | regno;
1069                         break;
1070                 case 24:
1071                         pal[regno] = (regno << 16) | (regno << 8) | regno;
1072                         break;
1073                 case 32:
1074                         i = (regno << 8) | regno;
1075                         pal[regno] = (i << 16) | i;
1076                         break;
1077                 }
1078         }
1079         return 0;
1080 }
1081
1082
1083 static void radeon_save_state (struct radeonfb_info *rinfo, struct radeon_regs *save)
1084 {
1085         /* CRTC regs */
1086         save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1087         save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1088         save->crtc_more_cntl = INREG(CRTC_MORE_CNTL);
1089         save->dac_cntl = INREG(DAC_CNTL);
1090         save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP);
1091         save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID);
1092         save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP);
1093         save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID);
1094         save->crtc_pitch = INREG(CRTC_PITCH);
1095         save->surface_cntl = INREG(SURFACE_CNTL);
1096
1097         /* FP regs */
1098         save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP);
1099         save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP);
1100         save->fp_gen_cntl = INREG(FP_GEN_CNTL);
1101         save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID);
1102         save->fp_horz_stretch = INREG(FP_HORZ_STRETCH);
1103         save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID);
1104         save->fp_vert_stretch = INREG(FP_VERT_STRETCH);
1105         save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
1106         save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL);
1107         save->tmds_crc = INREG(TMDS_CRC);       save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL);
1108         save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL);
1109 }
1110
1111
1112 static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode)
1113 {
1114         int i;
1115
1116         radeon_fifo_wait(20);
1117
1118         /* Workaround from XFree */
1119         if (rinfo->is_mobility) {
1120                 /* A temporal workaround for the occational blanking on certain laptop panels.
1121                    This appears to related to the PLL divider registers (fail to lock?).
1122                    It occurs even when all dividers are the same with their old settings.
1123                    In this case we really don't need to fiddle with PLL registers.
1124                    By doing this we can avoid the blanking problem with some panels.
1125                 */
1126                 if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) &&
1127                     (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) &
1128                                           (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) {
1129                         /* We still have to force a switch to PPLL div 3 thanks to
1130                          * an XFree86 driver bug which will switch it away in some cases
1131                          * even when using UseFDev */
1132                         OUTREGP(CLOCK_CNTL_INDEX, PPLL_DIV_SEL_MASK, ~PPLL_DIV_SEL_MASK);
1133                         return;
1134                 }
1135         }
1136
1137         /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/
1138         OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK);
1139
1140         /* Reset PPLL & enable atomic update */
1141         OUTPLLP(PPLL_CNTL,
1142                 PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN,
1143                 ~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1144
1145         /* Switch to PPLL div 3 */
1146         OUTREGP(CLOCK_CNTL_INDEX, PPLL_DIV_SEL_MASK, ~PPLL_DIV_SEL_MASK);
1147
1148         /* Set PPLL ref. div */
1149         if (rinfo->family == CHIP_FAMILY_R300 ||
1150             rinfo->family == CHIP_FAMILY_RS300 ||
1151             rinfo->family == CHIP_FAMILY_R350 ||
1152             rinfo->family == CHIP_FAMILY_RV350) {
1153                 if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
1154                         /* When restoring console mode, use saved PPLL_REF_DIV
1155                          * setting.
1156                          */
1157                         OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0);
1158                 } else {
1159                         /* R300 uses ref_div_acc field as real ref divider */
1160                         OUTPLLP(PPLL_REF_DIV,
1161                                 (mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
1162                                 ~R300_PPLL_REF_DIV_ACC_MASK);
1163                 }
1164         } else
1165                 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK);
1166
1167         /* Set PPLL divider 3 & post divider*/
1168         OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK);
1169         OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK);
1170
1171         /* Write update */
1172         while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R)
1173                 ;
1174         OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W);
1175
1176         /* Wait read update complete */
1177         /* FIXME: Certain revisions of R300 can't recover here.  Not sure of
1178            the cause yet, but this workaround will mask the problem for now.
1179            Other chips usually will pass at the very first test, so the
1180            workaround shouldn't have any effect on them. */
1181         for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++)
1182                 ;
1183
1184         OUTPLL(HTOTAL_CNTL, 0);
1185
1186         /* Clear reset & atomic update */
1187         OUTPLLP(PPLL_CNTL, 0,
1188                 ~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1189
1190         /* We may want some locking ... oh well */
1191         msleep(5);
1192
1193         /* Switch back VCLK source to PPLL */
1194         OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK);
1195 }
1196
1197 /*
1198  * Timer function for delayed LVDS panel power up/down
1199  */
1200 static void radeon_lvds_timer_func(unsigned long data)
1201 {
1202         struct radeonfb_info *rinfo = (struct radeonfb_info *)data;
1203
1204         radeon_fifo_wait(3);
1205
1206         OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl);
1207         if (rinfo->pending_pixclks_cntl) {
1208                 OUTPLL(PIXCLKS_CNTL, rinfo->pending_pixclks_cntl);
1209                 rinfo->pending_pixclks_cntl = 0;
1210         }
1211 }
1212
1213 /*
1214  * Apply a video mode. This will apply the whole register set, including
1215  * the PLL registers, to the card
1216  */
1217 static void radeon_write_mode (struct radeonfb_info *rinfo,
1218                                struct radeon_regs *mode)
1219 {
1220         int i;
1221         int primary_mon = PRIMARY_MONITOR(rinfo);
1222
1223         if (nomodeset)
1224                 return;
1225
1226         del_timer_sync(&rinfo->lvds_timer);
1227
1228         radeon_screen_blank(rinfo, VESA_POWERDOWN);
1229
1230         radeon_fifo_wait(31);
1231         for (i=0; i<10; i++)
1232                 OUTREG(common_regs[i].reg, common_regs[i].val);
1233
1234         /* Apply surface registers */
1235         for (i=0; i<8; i++) {
1236                 OUTREG(SURFACE0_LOWER_BOUND + 0x10*i, mode->surf_lower_bound[i]);
1237                 OUTREG(SURFACE0_UPPER_BOUND + 0x10*i, mode->surf_upper_bound[i]);
1238                 OUTREG(SURFACE0_INFO + 0x10*i, mode->surf_info[i]);
1239         }
1240
1241         OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
1242         OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
1243                 ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));
1244         OUTREG(CRTC_MORE_CNTL, mode->crtc_more_cntl);
1245         OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
1246         OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
1247         OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
1248         OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
1249         OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
1250         OUTREG(CRTC_OFFSET, 0);
1251         OUTREG(CRTC_OFFSET_CNTL, 0);
1252         OUTREG(CRTC_PITCH, mode->crtc_pitch);
1253         OUTREG(SURFACE_CNTL, mode->surface_cntl);
1254
1255         radeon_write_pll_regs(rinfo, mode);
1256
1257         if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1258                 radeon_fifo_wait(10);
1259                 OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);
1260                 OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);
1261                 OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);
1262                 OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid);
1263                 OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch);
1264                 OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch);
1265                 OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl);
1266                 OUTREG(TMDS_CRC, mode->tmds_crc);
1267                 OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl);
1268
1269                 if (primary_mon == MT_LCD) {
1270                         unsigned int tmp = INREG(LVDS_GEN_CNTL);
1271
1272                         /* HACK: The backlight control code may have modified init_state.lvds_gen_cntl,
1273                          * so we update ourselves
1274                          */
1275                         mode->lvds_gen_cntl &= ~LVDS_STATE_MASK;
1276                         mode->lvds_gen_cntl |= (rinfo->init_state.lvds_gen_cntl & LVDS_STATE_MASK);
1277
1278                         if ((tmp & (LVDS_ON | LVDS_BLON)) ==
1279                             (mode->lvds_gen_cntl & (LVDS_ON | LVDS_BLON))) {
1280                                 OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl);
1281                         } else {
1282                                 rinfo->pending_pixclks_cntl = INPLL(PIXCLKS_CNTL);
1283                                 if (rinfo->is_mobility || rinfo->is_IGP)
1284                                         OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb);
1285                                 if (!(tmp & (LVDS_ON | LVDS_BLON)))
1286                                         OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl | LVDS_BLON);
1287                                 rinfo->pending_lvds_gen_cntl = mode->lvds_gen_cntl;
1288                                 mod_timer(&rinfo->lvds_timer,
1289                                           jiffies + MS_TO_HZ(rinfo->panel_info.pwr_delay));
1290                         }
1291                 }
1292         }
1293
1294         RTRACE("lvds_gen_cntl: %08x\n", INREG(LVDS_GEN_CNTL));
1295
1296         radeon_screen_blank(rinfo, VESA_NO_BLANKING);
1297
1298         radeon_fifo_wait(2);
1299         OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl);
1300
1301         return;
1302 }
1303
1304 /*
1305  * Calculate the PLL values for a given mode
1306  */
1307 static void radeon_calc_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *regs,
1308                                  unsigned long freq)
1309 {
1310         const struct {
1311                 int divider;
1312                 int bitvalue;
1313         } *post_div,
1314           post_divs[] = {
1315                 { 1,  0 },
1316                 { 2,  1 },
1317                 { 4,  2 },
1318                 { 8,  3 },
1319                 { 3,  4 },
1320                 { 16, 5 },
1321                 { 6,  6 },
1322                 { 12, 7 },
1323                 { 0,  0 },
1324         };
1325         int fb_div, pll_output_freq = 0;
1326         int uses_dvo = 0;
1327
1328         /* Check if the DVO port is enabled and sourced from the primary CRTC. I'm
1329          * not sure which model starts having FP2_GEN_CNTL, I assume anything more
1330          * recent than an r(v)100...
1331          */
1332 #if 0
1333         /* XXX I had reports of flicker happening with the cinema display
1334          * on TMDS1 that seem to be fixed if I also forbit odd dividers in
1335          * this case. This could just be a bandwidth calculation issue, I
1336          * haven't implemented the bandwidth code yet, but in the meantime,
1337          * forcing uses_dvo to 1 fixes it and shouln't have bad side effects,
1338          * I haven't seen a case were were absolutely needed an odd PLL
1339          * divider. I'll find a better fix once I have more infos on the
1340          * real cause of the problem.
1341          */
1342         while (rinfo->has_CRTC2) {
1343                 u32 fp2_gen_cntl = INREG(FP2_GEN_CNTL);
1344                 u32 disp_output_cntl;
1345                 int source;
1346
1347                 /* FP2 path not enabled */
1348                 if ((fp2_gen_cntl & FP2_ON) == 0)
1349                         break;
1350                 /* Not all chip revs have the same format for this register,
1351                  * extract the source selection
1352                  */
1353                 if (rinfo->family == CHIP_FAMILY_R200 ||
1354                     rinfo->family == CHIP_FAMILY_R300 ||
1355                     rinfo->family == CHIP_FAMILY_R350 ||
1356                     rinfo->family == CHIP_FAMILY_RV350) {
1357                         source = (fp2_gen_cntl >> 10) & 0x3;
1358                         /* sourced from transform unit, check for transform unit
1359                          * own source
1360                          */
1361                         if (source == 3) {
1362                                 disp_output_cntl = INREG(DISP_OUTPUT_CNTL);
1363                                 source = (disp_output_cntl >> 12) & 0x3;
1364                         }
1365                 } else
1366                         source = (fp2_gen_cntl >> 13) & 0x1;
1367                 /* sourced from CRTC2 -> exit */
1368                 if (source == 1)
1369                         break;
1370
1371                 /* so we end up on CRTC1, let's set uses_dvo to 1 now */
1372                 uses_dvo = 1;
1373                 break;
1374         }
1375 #else
1376         uses_dvo = 1;
1377 #endif
1378         if (freq > rinfo->pll.ppll_max)
1379                 freq = rinfo->pll.ppll_max;
1380         if (freq*12 < rinfo->pll.ppll_min)
1381                 freq = rinfo->pll.ppll_min / 12;
1382
1383         for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
1384                 pll_output_freq = post_div->divider * freq;
1385                 /* If we output to the DVO port (external TMDS), we don't allow an
1386                  * odd PLL divider as those aren't supported on this path
1387                  */
1388                 if (uses_dvo && (post_div->divider & 1))
1389                         continue;
1390                 if (pll_output_freq >= rinfo->pll.ppll_min  &&
1391                     pll_output_freq <= rinfo->pll.ppll_max)
1392                         break;
1393         }
1394
1395         fb_div = round_div(rinfo->pll.ref_div*pll_output_freq,
1396                                   rinfo->pll.ref_clk);
1397         regs->ppll_ref_div = rinfo->pll.ref_div;
1398         regs->ppll_div_3 = fb_div | (post_div->bitvalue << 16);
1399
1400         RTRACE("post div = 0x%x\n", post_div->bitvalue);
1401         RTRACE("fb_div = 0x%x\n", fb_div);
1402         RTRACE("ppll_div_3 = 0x%x\n", regs->ppll_div_3);
1403 }
1404
1405 int radeonfb_set_par(struct fb_info *info)
1406 {
1407         struct radeonfb_info *rinfo = info->par;
1408         struct fb_var_screeninfo *mode = &info->var;
1409         struct radeon_regs *newmode;
1410         int hTotal, vTotal, hSyncStart, hSyncEnd,
1411             hSyncPol, vSyncStart, vSyncEnd, vSyncPol, cSync;
1412         u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5};
1413         u8 hsync_fudge_fp[] = {2, 2, 0, 0, 5, 5};
1414         u32 sync, h_sync_pol, v_sync_pol, dotClock, pixClock;
1415         int i, freq;
1416         int format = 0;
1417         int nopllcalc = 0;
1418         int hsync_start, hsync_fudge, bytpp, hsync_wid, vsync_wid;
1419         int primary_mon = PRIMARY_MONITOR(rinfo);
1420         int depth = var_to_depth(mode);
1421
1422         newmode = kmalloc(sizeof(struct radeon_regs), GFP_KERNEL);
1423         if (!newmode)
1424                 return -ENOMEM;
1425
1426         /* We always want engine to be idle on a mode switch, even
1427          * if we won't actually change the mode
1428          */
1429         radeon_engine_idle();
1430
1431         hSyncStart = mode->xres + mode->right_margin;
1432         hSyncEnd = hSyncStart + mode->hsync_len;
1433         hTotal = hSyncEnd + mode->left_margin;
1434
1435         vSyncStart = mode->yres + mode->lower_margin;
1436         vSyncEnd = vSyncStart + mode->vsync_len;
1437         vTotal = vSyncEnd + mode->upper_margin;
1438         pixClock = mode->pixclock;
1439
1440         sync = mode->sync;
1441         h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1442         v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1443
1444         if (primary_mon == MT_DFP || primary_mon == MT_LCD) {
1445                 if (rinfo->panel_info.xres < mode->xres)
1446                         mode->xres = rinfo->panel_info.xres;
1447                 if (rinfo->panel_info.yres < mode->yres)
1448                         mode->yres = rinfo->panel_info.yres;
1449
1450                 hTotal = mode->xres + rinfo->panel_info.hblank;
1451                 hSyncStart = mode->xres + rinfo->panel_info.hOver_plus;
1452                 hSyncEnd = hSyncStart + rinfo->panel_info.hSync_width;
1453
1454                 vTotal = mode->yres + rinfo->panel_info.vblank;
1455                 vSyncStart = mode->yres + rinfo->panel_info.vOver_plus;
1456                 vSyncEnd = vSyncStart + rinfo->panel_info.vSync_width;
1457
1458                 h_sync_pol = !rinfo->panel_info.hAct_high;
1459                 v_sync_pol = !rinfo->panel_info.vAct_high;
1460
1461                 pixClock = 100000000 / rinfo->panel_info.clock;
1462
1463                 if (rinfo->panel_info.use_bios_dividers) {
1464                         nopllcalc = 1;
1465                         newmode->ppll_div_3 = rinfo->panel_info.fbk_divider |
1466                                 (rinfo->panel_info.post_divider << 16);
1467                         newmode->ppll_ref_div = rinfo->panel_info.ref_divider;
1468                 }
1469         }
1470         dotClock = 1000000000 / pixClock;
1471         freq = dotClock / 10; /* x100 */
1472
1473         RTRACE("hStart = %d, hEnd = %d, hTotal = %d\n",
1474                 hSyncStart, hSyncEnd, hTotal);
1475         RTRACE("vStart = %d, vEnd = %d, vTotal = %d\n",
1476                 vSyncStart, vSyncEnd, vTotal);
1477
1478         hsync_wid = (hSyncEnd - hSyncStart) / 8;
1479         vsync_wid = vSyncEnd - vSyncStart;
1480         if (hsync_wid == 0)
1481                 hsync_wid = 1;
1482         else if (hsync_wid > 0x3f)      /* max */
1483                 hsync_wid = 0x3f;
1484
1485         if (vsync_wid == 0)
1486                 vsync_wid = 1;
1487         else if (vsync_wid > 0x1f)      /* max */
1488                 vsync_wid = 0x1f;
1489
1490         hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1491         vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1492
1493         cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
1494
1495         format = radeon_get_dstbpp(depth);
1496         bytpp = mode->bits_per_pixel >> 3;
1497
1498         if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD))
1499                 hsync_fudge = hsync_fudge_fp[format-1];
1500         else
1501                 hsync_fudge = hsync_adj_tab[format-1];
1502
1503         hsync_start = hSyncStart - 8 + hsync_fudge;
1504
1505         newmode->crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN |
1506                                 (format << 8);
1507
1508         /* Clear auto-center etc... */
1509         newmode->crtc_more_cntl = rinfo->init_state.crtc_more_cntl;
1510         newmode->crtc_more_cntl &= 0xfffffff0;
1511
1512         if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1513                 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN;
1514                 if (mirror)
1515                         newmode->crtc_ext_cntl |= CRTC_CRT_ON;
1516
1517                 newmode->crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN |
1518                                            CRTC_INTERLACE_EN);
1519         } else {
1520                 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN |
1521                                         CRTC_CRT_ON;
1522         }
1523
1524         newmode->dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN |
1525                            DAC_8BIT_EN;
1526
1527         newmode->crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) |
1528                                      (((mode->xres / 8) - 1) << 16));
1529
1530         newmode->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
1531                                         (hsync_wid << 16) | (h_sync_pol << 23));
1532
1533         newmode->crtc_v_total_disp = ((vTotal - 1) & 0xffff) |
1534                                     ((mode->yres - 1) << 16);
1535
1536         newmode->crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) |
1537                                          (vsync_wid << 16) | (v_sync_pol  << 23));
1538
1539         if (!(info->flags & FBINFO_HWACCEL_DISABLED)) {
1540                 /* We first calculate the engine pitch */
1541                 rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
1542                                 & ~(0x3f)) >> 6;
1543
1544                 /* Then, re-multiply it to get the CRTC pitch */
1545                 newmode->crtc_pitch = (rinfo->pitch << 3) / ((mode->bits_per_pixel + 1) / 8);
1546         } else
1547                 newmode->crtc_pitch = (mode->xres_virtual >> 3);
1548
1549         newmode->crtc_pitch |= (newmode->crtc_pitch << 16);
1550
1551         /*
1552          * It looks like recent chips have a problem with SURFACE_CNTL,
1553          * setting SURF_TRANSLATION_DIS completely disables the
1554          * swapper as well, so we leave it unset now.
1555          */
1556         newmode->surface_cntl = 0;
1557
1558 #if defined(__BIG_ENDIAN)
1559
1560         /* Setup swapping on both apertures, though we currently
1561          * only use aperture 0, enabling swapper on aperture 1
1562          * won't harm
1563          */
1564         switch (mode->bits_per_pixel) {
1565                 case 16:
1566                         newmode->surface_cntl |= NONSURF_AP0_SWP_16BPP;
1567                         newmode->surface_cntl |= NONSURF_AP1_SWP_16BPP;
1568                         break;
1569                 case 24:
1570                 case 32:
1571                         newmode->surface_cntl |= NONSURF_AP0_SWP_32BPP;
1572                         newmode->surface_cntl |= NONSURF_AP1_SWP_32BPP;
1573                         break;
1574         }
1575 #endif
1576
1577         /* Clear surface registers */
1578         for (i=0; i<8; i++) {
1579                 newmode->surf_lower_bound[i] = 0;
1580                 newmode->surf_upper_bound[i] = 0x1f;
1581                 newmode->surf_info[i] = 0;
1582         }
1583
1584         RTRACE("h_total_disp = 0x%x\t   hsync_strt_wid = 0x%x\n",
1585                 newmode->crtc_h_total_disp, newmode->crtc_h_sync_strt_wid);
1586         RTRACE("v_total_disp = 0x%x\t   vsync_strt_wid = 0x%x\n",
1587                 newmode->crtc_v_total_disp, newmode->crtc_v_sync_strt_wid);
1588
1589         rinfo->bpp = mode->bits_per_pixel;
1590         rinfo->depth = depth;
1591
1592         RTRACE("pixclock = %lu\n", (unsigned long)pixClock);
1593         RTRACE("freq = %lu\n", (unsigned long)freq);
1594
1595         if (!nopllcalc)
1596                 radeon_calc_pll_regs(rinfo, newmode, freq);
1597
1598         newmode->vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl;
1599
1600         if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1601                 unsigned int hRatio, vRatio;
1602
1603                 if (mode->xres > rinfo->panel_info.xres)
1604                         mode->xres = rinfo->panel_info.xres;
1605                 if (mode->yres > rinfo->panel_info.yres)
1606                         mode->yres = rinfo->panel_info.yres;
1607
1608                 newmode->fp_horz_stretch = (((rinfo->panel_info.xres / 8) - 1)
1609                                            << HORZ_PANEL_SHIFT);
1610                 newmode->fp_vert_stretch = ((rinfo->panel_info.yres - 1)
1611                                            << VERT_PANEL_SHIFT);
1612
1613                 if (mode->xres != rinfo->panel_info.xres) {
1614                         hRatio = round_div(mode->xres * HORZ_STRETCH_RATIO_MAX,
1615                                            rinfo->panel_info.xres);
1616                         newmode->fp_horz_stretch = (((((unsigned long)hRatio) & HORZ_STRETCH_RATIO_MASK)) |
1617                                                    (newmode->fp_horz_stretch &
1618                                                     (HORZ_PANEL_SIZE | HORZ_FP_LOOP_STRETCH |
1619                                                      HORZ_AUTO_RATIO_INC)));
1620                         newmode->fp_horz_stretch |= (HORZ_STRETCH_BLEND |
1621                                                     HORZ_STRETCH_ENABLE);
1622                 }
1623                 newmode->fp_horz_stretch &= ~HORZ_AUTO_RATIO;
1624
1625                 if (mode->yres != rinfo->panel_info.yres) {
1626                         vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX,
1627                                            rinfo->panel_info.yres);
1628                         newmode->fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) |
1629                                                    (newmode->fp_vert_stretch &
1630                                                    (VERT_PANEL_SIZE | VERT_STRETCH_RESERVED)));
1631                         newmode->fp_vert_stretch |= (VERT_STRETCH_BLEND |
1632                                                     VERT_STRETCH_ENABLE);
1633                 }
1634                 newmode->fp_vert_stretch &= ~VERT_AUTO_RATIO_EN;
1635
1636                 newmode->fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32)
1637                                        ~(FP_SEL_CRTC2 |
1638                                          FP_RMX_HVSYNC_CONTROL_EN |
1639                                          FP_DFP_SYNC_SEL |
1640                                          FP_CRT_SYNC_SEL |
1641                                          FP_CRTC_LOCK_8DOT |
1642                                          FP_USE_SHADOW_EN |
1643                                          FP_CRTC_USE_SHADOW_VEND |
1644                                          FP_CRT_SYNC_ALT));
1645
1646                 newmode->fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR |
1647                                         FP_CRTC_DONT_SHADOW_HEND);
1648
1649                 newmode->lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl;
1650                 newmode->lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl;
1651                 newmode->tmds_crc = rinfo->init_state.tmds_crc;
1652                 newmode->tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl;
1653
1654                 if (primary_mon == MT_LCD) {
1655                         newmode->lvds_gen_cntl |= (LVDS_ON | LVDS_BLON);
1656                         newmode->fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN);
1657                 } else {
1658                         /* DFP */
1659                         newmode->fp_gen_cntl |= (FP_FPON | FP_TMDS_EN);
1660                         newmode->tmds_transmitter_cntl = (TMDS_RAN_PAT_RST | TMDS_ICHCSEL) &
1661                                                          ~(TMDS_PLLRST);
1662                         /* TMDS_PLL_EN bit is reversed on RV (and mobility) chips */
1663                         if ((rinfo->family == CHIP_FAMILY_R300) ||
1664                             (rinfo->family == CHIP_FAMILY_R350) ||
1665                             (rinfo->family == CHIP_FAMILY_RV350) ||
1666                             (rinfo->family == CHIP_FAMILY_R200) || !rinfo->has_CRTC2)
1667                                 newmode->tmds_transmitter_cntl &= ~TMDS_PLL_EN;
1668                         else
1669                                 newmode->tmds_transmitter_cntl |= TMDS_PLL_EN;
1670                         newmode->crtc_ext_cntl &= ~CRTC_CRT_ON;
1671                 }
1672
1673                 newmode->fp_crtc_h_total_disp = (((rinfo->panel_info.hblank / 8) & 0x3ff) |
1674                                 (((mode->xres / 8) - 1) << 16));
1675                 newmode->fp_crtc_v_total_disp = (rinfo->panel_info.vblank & 0xffff) |
1676                                 ((mode->yres - 1) << 16);
1677                 newmode->fp_h_sync_strt_wid = ((rinfo->panel_info.hOver_plus & 0x1fff) |
1678                                 (hsync_wid << 16) | (h_sync_pol << 23));
1679                 newmode->fp_v_sync_strt_wid = ((rinfo->panel_info.vOver_plus & 0xfff) |
1680                                 (vsync_wid << 16) | (v_sync_pol  << 23));
1681         }
1682
1683         /* do it! */
1684         if (!rinfo->asleep) {
1685                 radeon_write_mode (rinfo, newmode);
1686                 /* (re)initialize the engine */
1687                 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1688                         radeonfb_engine_init (rinfo);
1689         }
1690         /* Update fix */
1691         if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1692                 info->fix.line_length = rinfo->pitch*64;
1693         else
1694                 info->fix.line_length = mode->xres_virtual
1695                         * ((mode->bits_per_pixel + 1) / 8);
1696         info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR
1697                 : FB_VISUAL_DIRECTCOLOR;
1698
1699 #ifdef CONFIG_BOOTX_TEXT
1700         /* Update debug text engine */
1701         btext_update_display(rinfo->fb_base_phys, mode->xres, mode->yres,
1702                              rinfo->depth, info->fix.line_length);
1703 #endif
1704
1705         kfree(newmode);
1706         return 0;
1707 }
1708
1709
1710
1711 static ssize_t radeonfb_read(struct file *file, char __user *buf, size_t count, loff_t *ppos)
1712 {
1713         unsigned long p = *ppos;
1714         struct inode *inode = file->f_dentry->d_inode;
1715         int fbidx = iminor(inode);
1716         struct fb_info *info = registered_fb[fbidx];
1717         struct radeonfb_info *rinfo = info->par;
1718
1719         if (p >= rinfo->mapped_vram)
1720             return 0;
1721         if (count >= rinfo->mapped_vram)
1722             count = rinfo->mapped_vram;
1723         if (count + p > rinfo->mapped_vram)
1724                 count = rinfo->mapped_vram - p;
1725         radeonfb_sync(info);
1726         if (count) {
1727             char *base_addr;
1728
1729             base_addr = info->screen_base;
1730             count -= copy_to_user(buf, base_addr+p, count);
1731             if (!count)
1732                 return -EFAULT;
1733             *ppos += count;
1734         }
1735         return count;
1736 }
1737
1738 static ssize_t radeonfb_write(struct file *file, const char __user *buf, size_t count,
1739                               loff_t *ppos)
1740 {
1741         unsigned long p = *ppos;
1742         struct inode *inode = file->f_dentry->d_inode;
1743         int fbidx = iminor(inode);
1744         struct fb_info *info = registered_fb[fbidx];
1745         struct radeonfb_info *rinfo = info->par;
1746         int err;
1747
1748         if (p > rinfo->mapped_vram)
1749             return -ENOSPC;
1750         if (count >= rinfo->mapped_vram)
1751             count = rinfo->mapped_vram;
1752         err = 0;
1753         if (count + p > rinfo->mapped_vram) {
1754             count = rinfo->mapped_vram - p;
1755             err = -ENOSPC;
1756         }
1757         radeonfb_sync(info);
1758         if (count) {
1759             char *base_addr;
1760
1761             base_addr = info->screen_base;
1762             count -= copy_from_user(base_addr+p, buf, count);
1763             *ppos += count;
1764             err = -EFAULT;
1765         }
1766         if (count)
1767                 return count;
1768         return err;
1769 }
1770
1771
1772 static struct fb_ops radeonfb_ops = {
1773         .owner                  = THIS_MODULE,
1774         .fb_check_var           = radeonfb_check_var,
1775         .fb_set_par             = radeonfb_set_par,
1776         .fb_setcolreg           = radeonfb_setcolreg,
1777         .fb_pan_display         = radeonfb_pan_display,
1778         .fb_blank               = radeonfb_blank,
1779         .fb_ioctl               = radeonfb_ioctl,
1780         .fb_sync                = radeonfb_sync,
1781         .fb_fillrect            = radeonfb_fillrect,
1782         .fb_copyarea            = radeonfb_copyarea,
1783         .fb_imageblit           = radeonfb_imageblit,
1784         .fb_read                = radeonfb_read,
1785         .fb_write               = radeonfb_write,
1786         .fb_cursor              = soft_cursor,
1787 };
1788
1789
1790 static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
1791 {
1792         struct fb_info *info = rinfo->info;
1793
1794         info->currcon = -1;
1795         info->par = rinfo;
1796         info->pseudo_palette = rinfo->pseudo_palette;
1797         info->flags = FBINFO_DEFAULT
1798                     | FBINFO_HWACCEL_COPYAREA
1799                     | FBINFO_HWACCEL_FILLRECT
1800                     | FBINFO_HWACCEL_XPAN
1801                     | FBINFO_HWACCEL_YPAN;
1802         info->fbops = &radeonfb_ops;
1803         info->screen_base = (char *)rinfo->fb_base;
1804
1805         /* Fill fix common fields */
1806         strlcpy(info->fix.id, rinfo->name, sizeof(info->fix.id));
1807         info->fix.smem_start = rinfo->fb_base_phys;
1808         info->fix.smem_len = rinfo->video_ram;
1809         info->fix.type = FB_TYPE_PACKED_PIXELS;
1810         info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
1811         info->fix.xpanstep = 8;
1812         info->fix.ypanstep = 1;
1813         info->fix.ywrapstep = 0;
1814         info->fix.type_aux = 0;
1815         info->fix.mmio_start = rinfo->mmio_base_phys;
1816         info->fix.mmio_len = RADEON_REGSIZE;
1817
1818         fb_alloc_cmap(&info->cmap, 256, 0);
1819
1820         if (noaccel)
1821                 info->flags |= FBINFO_HWACCEL_DISABLED;
1822
1823         return 0;
1824 }
1825
1826
1827 #ifdef CONFIG_PMAC_BACKLIGHT
1828
1829 /* TODO: Dbl check these tables, we don't go up to full ON backlight
1830  * in these, possibly because we noticed MacOS doesn't, but I'd prefer
1831  * having some more official numbers from ATI
1832  */
1833 static int backlight_conv_m6[] = {
1834         0xff, 0xc0, 0xb5, 0xaa, 0x9f, 0x94, 0x89, 0x7e,
1835         0x73, 0x68, 0x5d, 0x52, 0x47, 0x3c, 0x31, 0x24
1836 };
1837 static int backlight_conv_m7[] = {
1838         0x00, 0x3f, 0x4a, 0x55, 0x60, 0x6b, 0x76, 0x81,
1839         0x8c, 0x97, 0xa2, 0xad, 0xb8, 0xc3, 0xce, 0xd9
1840 };
1841
1842 #define BACKLIGHT_LVDS_OFF
1843 #undef BACKLIGHT_DAC_OFF
1844
1845 /* We turn off the LCD completely instead of just dimming the backlight.
1846  * This provides some greater power saving and the display is useless
1847  * without backlight anyway.
1848  */
1849 static int radeon_set_backlight_enable(int on, int level, void *data)
1850 {
1851         struct radeonfb_info *rinfo = (struct radeonfb_info *)data;
1852         unsigned int lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
1853         unsigned long tmpPixclksCntl = INPLL(PIXCLKS_CNTL);
1854         int* conv_table;
1855
1856         if (rinfo->mon1_type != MT_LCD)
1857                 return 0;
1858
1859         /* Pardon me for that hack... maybe some day we can figure
1860          * out in what direction backlight should work on a given
1861          * panel ?
1862          */
1863         if ((rinfo->family == CHIP_FAMILY_RV200 ||
1864              rinfo->family == CHIP_FAMILY_RV250 ||
1865              rinfo->family == CHIP_FAMILY_RV280 ||
1866              rinfo->family == CHIP_FAMILY_RV350) &&
1867             !machine_is_compatible("PowerBook4,3") &&
1868             !machine_is_compatible("PowerBook6,3") &&
1869             !machine_is_compatible("PowerBook6,5"))
1870                 conv_table = backlight_conv_m7;
1871         else
1872                 conv_table = backlight_conv_m6;
1873
1874         del_timer_sync(&rinfo->lvds_timer);
1875
1876         lvds_gen_cntl |= (LVDS_BL_MOD_EN | LVDS_BLON);
1877         radeon_fifo_wait(3);
1878         if (on && (level > BACKLIGHT_OFF)) {
1879                 lvds_gen_cntl |= LVDS_DIGON;
1880                 if (!(lvds_gen_cntl & LVDS_ON)) {
1881                         lvds_gen_cntl &= ~LVDS_BLON;
1882                         OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
1883                         (void)INREG(LVDS_GEN_CNTL);
1884                         mdelay(rinfo->panel_info.pwr_delay);/* OUCH !!! FIXME */
1885                         lvds_gen_cntl |= LVDS_BLON;
1886                         OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
1887                 }
1888                 lvds_gen_cntl &= ~LVDS_BL_MOD_LEVEL_MASK;
1889                 lvds_gen_cntl |= (conv_table[level] <<
1890                                   LVDS_BL_MOD_LEVEL_SHIFT);
1891                 lvds_gen_cntl |= (LVDS_ON | LVDS_EN);
1892                 lvds_gen_cntl &= ~LVDS_DISPLAY_DIS;
1893         } else {
1894                 /* Asic bug, when turning off LVDS_ON, we have to make sure
1895                    RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
1896                 */
1897                 if (rinfo->is_mobility || rinfo->is_IGP)
1898                         OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb);
1899                 lvds_gen_cntl &= ~LVDS_BL_MOD_LEVEL_MASK;
1900                 lvds_gen_cntl |= (conv_table[0] <<
1901                                   LVDS_BL_MOD_LEVEL_SHIFT);
1902                 lvds_gen_cntl |= LVDS_DISPLAY_DIS | LVDS_BLON;
1903                 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
1904                 mdelay(rinfo->panel_info.pwr_delay);/* OUCH !!! FIXME */
1905                 lvds_gen_cntl &= ~(LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGON);
1906         }
1907
1908         OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
1909         if (rinfo->is_mobility || rinfo->is_IGP)
1910                 OUTPLL(PIXCLKS_CNTL, tmpPixclksCntl);
1911         rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
1912         rinfo->init_state.lvds_gen_cntl |= (lvds_gen_cntl & LVDS_STATE_MASK);
1913
1914         return 0;
1915 }
1916
1917
1918 static int radeon_set_backlight_level(int level, void *data)
1919 {
1920         return radeon_set_backlight_enable(1, level, data);
1921 }
1922 #endif /* CONFIG_PMAC_BACKLIGHT */
1923
1924
1925 /*
1926  * This reconfigure the card's internal memory map. In theory, we'd like
1927  * to setup the card's memory at the same address as it's PCI bus address,
1928  * and the AGP aperture right after that so that system RAM on 32 bits
1929  * machines at least, is directly accessible. However, doing so would
1930  * conflict with the current XFree drivers...
1931  * Ultimately, I hope XFree, GATOS and ATI binary drivers will all agree
1932  * on the proper way to set this up and duplicate this here. In the meantime,
1933  * I put the card's memory at 0 in card space and AGP at some random high
1934  * local (0xe0000000 for now) that will be changed by XFree/DRI anyway
1935  */
1936 #ifdef CONFIG_PPC_OF
1937 #undef SET_MC_FB_FROM_APERTURE
1938 static void fixup_memory_mappings(struct radeonfb_info *rinfo)
1939 {
1940         u32 save_crtc_gen_cntl, save_crtc2_gen_cntl;
1941         u32 save_crtc_ext_cntl;
1942         u32 aper_base, aper_size;
1943         u32 agp_base;
1944
1945         /* First, we disable display to avoid interfering */
1946         if (rinfo->has_CRTC2) {
1947                 save_crtc2_gen_cntl = INREG(CRTC2_GEN_CNTL);
1948                 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl | CRTC2_DISP_REQ_EN_B);
1949         }
1950         save_crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1951         save_crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1952
1953         OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl | CRTC_DISPLAY_DIS);
1954         OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl | CRTC_DISP_REQ_EN_B);
1955         mdelay(100);
1956
1957         aper_base = INREG(CONFIG_APER_0_BASE);
1958         aper_size = INREG(CONFIG_APER_SIZE);
1959
1960 #ifdef SET_MC_FB_FROM_APERTURE
1961         /* Set framebuffer to be at the same address as set in PCI BAR */
1962         OUTREG(MC_FB_LOCATION,
1963                 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16));
1964         rinfo->fb_local_base = aper_base;
1965 #else
1966         OUTREG(MC_FB_LOCATION, 0x7fff0000);
1967         rinfo->fb_local_base = 0;
1968 #endif
1969         agp_base = aper_base + aper_size;
1970         if (agp_base & 0xf0000000)
1971                 agp_base = (aper_base | 0x0fffffff) + 1;
1972
1973         /* Set AGP to be just after the framebuffer on a 256Mb boundary. This
1974          * assumes the FB isn't mapped to 0xf0000000 or above, but this is
1975          * always the case on PPCs afaik.
1976          */
1977 #ifdef SET_MC_FB_FROM_APERTURE
1978         OUTREG(MC_AGP_LOCATION, 0xffff0000 | (agp_base >> 16));
1979 #else
1980         OUTREG(MC_AGP_LOCATION, 0xffffe000);
1981 #endif
1982
1983         /* Fixup the display base addresses & engine offsets while we
1984          * are at it as well
1985          */
1986 #ifdef SET_MC_FB_FROM_APERTURE
1987         OUTREG(DISPLAY_BASE_ADDR, aper_base);
1988         if (rinfo->has_CRTC2)
1989                 OUTREG(CRTC2_DISPLAY_BASE_ADDR, aper_base);
1990 #else
1991         OUTREG(DISPLAY_BASE_ADDR, 0);
1992         if (rinfo->has_CRTC2)
1993                 OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0);
1994 #endif
1995         mdelay(100);
1996
1997         /* Restore display settings */
1998         OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl);
1999         OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl);
2000         if (rinfo->has_CRTC2)
2001                 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl);
2002
2003         RTRACE("aper_base: %08x MC_FB_LOC to: %08x, MC_AGP_LOC to: %08x\n",
2004                 aper_base,
2005                 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16),
2006                 0xffff0000 | (agp_base >> 16));
2007 }
2008 #endif /* CONFIG_PPC_OF */
2009
2010
2011 /*
2012  * Sysfs
2013  */
2014
2015 static ssize_t radeon_show_one_edid(char *buf, loff_t off, size_t count, const u8 *edid)
2016 {
2017         if (off > EDID_LENGTH)
2018                 return 0;
2019
2020         if (off + count > EDID_LENGTH)
2021                 count = EDID_LENGTH - off;
2022
2023         memcpy(buf, edid + off, count);
2024
2025         return count;
2026 }
2027
2028
2029 static ssize_t radeon_show_edid1(struct kobject *kobj, char *buf, loff_t off, size_t count)
2030 {
2031         struct device *dev = container_of(kobj, struct device, kobj);
2032         struct pci_dev *pdev = to_pci_dev(dev);
2033         struct fb_info *info = pci_get_drvdata(pdev);
2034         struct radeonfb_info *rinfo = info->par;
2035
2036         return radeon_show_one_edid(buf, off, count, rinfo->mon1_EDID);
2037 }
2038
2039
2040 static ssize_t radeon_show_edid2(struct kobject *kobj, char *buf, loff_t off, size_t count)
2041 {
2042         struct device *dev = container_of(kobj, struct device, kobj);
2043         struct pci_dev *pdev = to_pci_dev(dev);
2044         struct fb_info *info = pci_get_drvdata(pdev);
2045         struct radeonfb_info *rinfo = info->par;
2046
2047         return radeon_show_one_edid(buf, off, count, rinfo->mon2_EDID);
2048 }
2049
2050 static struct bin_attribute edid1_attr = {
2051         .attr   = {
2052                 .name   = "edid1",
2053                 .owner  = THIS_MODULE,
2054                 .mode   = 0444,
2055         },
2056         .size   = EDID_LENGTH,
2057         .read   = radeon_show_edid1,
2058 };
2059
2060 static struct bin_attribute edid2_attr = {
2061         .attr   = {
2062                 .name   = "edid2",
2063                 .owner  = THIS_MODULE,
2064                 .mode   = 0444,
2065         },
2066         .size   = EDID_LENGTH,
2067         .read   = radeon_show_edid2,
2068 };
2069
2070
2071 static int radeonfb_pci_register (struct pci_dev *pdev,
2072                                   const struct pci_device_id *ent)
2073 {
2074         struct fb_info *info;
2075         struct radeonfb_info *rinfo;
2076         u32 tmp;
2077
2078         RTRACE("radeonfb_pci_register BEGIN\n");
2079
2080         /* Enable device in PCI config */
2081         if (pci_enable_device(pdev) != 0) {
2082                 printk(KERN_ERR "radeonfb: Cannot enable PCI device\n");
2083                 return -ENODEV;
2084         }
2085
2086         info = framebuffer_alloc(sizeof(struct radeonfb_info), &pdev->dev);
2087         if (!info) {
2088                 printk (KERN_ERR "radeonfb: could not allocate memory\n");
2089                 return -ENODEV;
2090         }
2091         rinfo = info->par;
2092         rinfo->info = info;
2093         rinfo->pdev = pdev;
2094
2095         spin_lock_init(&rinfo->reg_lock);
2096         init_timer(&rinfo->lvds_timer);
2097         rinfo->lvds_timer.function = radeon_lvds_timer_func;
2098         rinfo->lvds_timer.data = (unsigned long)rinfo;
2099
2100         strcpy(rinfo->name, "ATI Radeon XX ");
2101         rinfo->name[11] = ent->device >> 8;
2102         rinfo->name[12] = ent->device & 0xFF;
2103         rinfo->family = ent->driver_data & CHIP_FAMILY_MASK;
2104         rinfo->chipset = pdev->device;
2105         rinfo->has_CRTC2 = (ent->driver_data & CHIP_HAS_CRTC2) != 0;
2106         rinfo->is_mobility = (ent->driver_data & CHIP_IS_MOBILITY) != 0;
2107         rinfo->is_IGP = (ent->driver_data & CHIP_IS_IGP) != 0;
2108
2109         /* Set base addrs */
2110         rinfo->fb_base_phys = pci_resource_start (pdev, 0);
2111         rinfo->mmio_base_phys = pci_resource_start (pdev, 2);
2112
2113         /* request the mem regions */
2114         if (!request_mem_region (rinfo->fb_base_phys,
2115                                  pci_resource_len(pdev, 0), "radeonfb")) {
2116                 printk (KERN_ERR "radeonfb: cannot reserve FB region\n");
2117                 goto free_rinfo;
2118         }
2119
2120         if (!request_mem_region (rinfo->mmio_base_phys,
2121                                  pci_resource_len(pdev, 2), "radeonfb")) {
2122                 printk (KERN_ERR "radeonfb: cannot reserve MMIO region\n");
2123                 goto release_fb;
2124         }
2125
2126         /* map the regions */
2127         rinfo->mmio_base = (unsigned long) ioremap (rinfo->mmio_base_phys, RADEON_REGSIZE);
2128         if (!rinfo->mmio_base) {
2129                 printk (KERN_ERR "radeonfb: cannot map MMIO\n");
2130                 goto release_mmio;
2131         }
2132
2133         /* On PPC, the firmware sets up a memory mapping that tends
2134          * to cause lockups when enabling the engine. We reconfigure
2135          * the card internal memory mappings properly
2136          */
2137 #ifdef CONFIG_PPC_OF
2138         fixup_memory_mappings(rinfo);
2139 #else
2140         rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;
2141 #endif /* CONFIG_PPC_OF */
2142
2143         /* framebuffer size */
2144         if ((rinfo->family == CHIP_FAMILY_RS100) ||
2145             (rinfo->family == CHIP_FAMILY_RS200) ||
2146             (rinfo->family == CHIP_FAMILY_RS300)) {
2147           u32 tom = INREG(NB_TOM);
2148           tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024);
2149
2150                 radeon_fifo_wait(6);
2151           OUTREG(MC_FB_LOCATION, tom);
2152           OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2153           OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2154           OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16);
2155
2156           /* This is supposed to fix the crtc2 noise problem. */
2157           OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000);
2158
2159           if ((rinfo->family == CHIP_FAMILY_RS100) ||
2160               (rinfo->family == CHIP_FAMILY_RS200)) {
2161              /* This is to workaround the asic bug for RMX, some versions
2162                 of BIOS dosen't have this register initialized correctly.
2163              */
2164              OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN,
2165                      ~CRTC_H_CUTOFF_ACTIVE_EN);
2166           }
2167         } else {
2168           tmp = INREG(CONFIG_MEMSIZE);
2169         }
2170
2171         /* mem size is bits [28:0], mask off the rest */
2172         rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK;
2173
2174         /* ram type */
2175         tmp = INREG(MEM_SDRAM_MODE_REG);
2176         switch ((MEM_CFG_TYPE & tmp) >> 30) {
2177         case 0:
2178                 /* SDR SGRAM (2:1) */
2179                 strcpy(rinfo->ram_type, "SDR SGRAM");
2180                 rinfo->ram.ml = 4;
2181                 rinfo->ram.mb = 4;
2182                 rinfo->ram.trcd = 1;
2183                 rinfo->ram.trp = 2;
2184                 rinfo->ram.twr = 1;
2185                 rinfo->ram.cl = 2;
2186                 rinfo->ram.loop_latency = 16;
2187                 rinfo->ram.rloop = 16;
2188                 break;
2189         case 1:
2190                 /* DDR SGRAM */
2191                 strcpy(rinfo->ram_type, "DDR SGRAM");
2192                 rinfo->ram.ml = 4;
2193                 rinfo->ram.mb = 4;
2194                 rinfo->ram.trcd = 3;
2195                 rinfo->ram.trp = 3;
2196                 rinfo->ram.twr = 2;
2197                 rinfo->ram.cl = 3;
2198                 rinfo->ram.tr2w = 1;
2199                 rinfo->ram.loop_latency = 16;
2200                 rinfo->ram.rloop = 16;
2201                 break;
2202         default:
2203                 /* 64-bit SDR SGRAM */
2204                 strcpy(rinfo->ram_type, "SDR SGRAM 64");
2205                 rinfo->ram.ml = 4;
2206                 rinfo->ram.mb = 8;
2207                 rinfo->ram.trcd = 3;
2208                 rinfo->ram.trp = 3;
2209                 rinfo->ram.twr = 1;
2210                 rinfo->ram.cl = 3;
2211                 rinfo->ram.tr2w = 1;
2212                 rinfo->ram.loop_latency = 17;
2213                 rinfo->ram.rloop = 17;
2214                 break;
2215         }
2216
2217         /*
2218          * Hack to get around some busted production M6's
2219          * reporting no ram
2220          */
2221         if (rinfo->video_ram == 0) {
2222                 switch (pdev->device) {
2223                 case PCI_CHIP_RADEON_LY:
2224                 case PCI_CHIP_RADEON_LZ:
2225                         rinfo->video_ram = 8192 * 1024;
2226                         break;
2227                 default:
2228                         break;
2229                 }
2230         }
2231
2232         RTRACE("radeonfb: probed %s %ldk videoram\n", (rinfo->ram_type), (rinfo->video_ram/1024));
2233
2234         rinfo->mapped_vram = MAX_MAPPED_VRAM;
2235         if (rinfo->video_ram < rinfo->mapped_vram)
2236                 rinfo->mapped_vram = rinfo->video_ram;
2237         for (;;) {
2238                 rinfo->fb_base = (unsigned long) ioremap (rinfo->fb_base_phys,
2239                                                           rinfo->mapped_vram);
2240                 if (rinfo->fb_base == 0 && rinfo->mapped_vram > MIN_MAPPED_VRAM) {
2241                         rinfo->mapped_vram /= 2;
2242                         continue;
2243                 }
2244                 memset_io(rinfo->fb_base, 0, rinfo->mapped_vram);
2245                 break;
2246         }
2247
2248         if (!rinfo->fb_base) {
2249                 printk (KERN_ERR "radeonfb: cannot map FB\n");
2250                 goto unmap_rom;
2251         }
2252
2253         RTRACE("radeonfb: mapped %ldk videoram\n", rinfo->mapped_vram/1024);
2254
2255
2256         /* Argh. Scary arch !!! */
2257 #ifdef CONFIG_PPC64
2258         rinfo->fb_base = IO_TOKEN_TO_ADDR(rinfo->fb_base);
2259 #endif
2260
2261         /*
2262          * Check for required workaround for PLL accesses
2263          */
2264         rinfo->R300_cg_workaround = (rinfo->family == CHIP_FAMILY_R300 &&
2265                                      (INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK)
2266                                      == CFG_ATI_REV_A11);
2267
2268         /*
2269          * Map the BIOS ROM if any and retreive PLL parameters from
2270          * the BIOS. We skip that on mobility chips as the real panel
2271          * values we need aren't in the ROM but in the BIOS image in
2272          * memory. This is definitely not the best meacnism though,
2273          * we really need the arch code to tell us which is the "primary"
2274          * video adapter to use the memory image (or better, the arch
2275          * should provide us a copy of the BIOS image to shield us from
2276          * archs who would store that elsewhere and/or could initialize
2277          * more than one adapter during boot).
2278          */
2279         if (!rinfo->is_mobility)
2280                 radeon_map_ROM(rinfo, pdev);
2281
2282         /*
2283          * On x86, the primary display on laptop may have it's BIOS
2284          * ROM elsewhere, try to locate it at the legacy memory hole.
2285          * We probably need to make sure this is the primary display,
2286          * but that is difficult without some arch support.
2287          */
2288 #ifdef CONFIG_X86
2289         if (rinfo->bios_seg == NULL)
2290                 radeon_find_mem_vbios(rinfo);
2291 #endif
2292
2293         /* If both above failed, try the BIOS ROM again for mobility
2294          * chips
2295          */
2296         if (rinfo->bios_seg == NULL && rinfo->is_mobility)
2297                 radeon_map_ROM(rinfo, pdev);
2298
2299         /* Get informations about the board's PLL */
2300         radeon_get_pllinfo(rinfo);
2301
2302 #ifdef CONFIG_FB_RADEON_I2C
2303         /* Register I2C bus */
2304         radeon_create_i2c_busses(rinfo);
2305 #endif
2306
2307         /* set all the vital stuff */
2308         radeon_set_fbinfo (rinfo);
2309
2310         /* Probe screen types */
2311         radeon_probe_screens(rinfo, monitor_layout, ignore_edid);
2312
2313         /* Build mode list, check out panel native model */
2314         radeon_check_modes(rinfo, mode_option);
2315
2316         /* Register some sysfs stuff (should be done better) */
2317         if (rinfo->mon1_EDID)
2318                 sysfs_create_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr);
2319         if (rinfo->mon2_EDID)
2320                 sysfs_create_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr);
2321
2322         /* save current mode regs before we switch into the new one
2323          * so we can restore this upon __exit
2324          */
2325         radeon_save_state (rinfo, &rinfo->init_state);
2326
2327         pci_set_drvdata(pdev, info);
2328
2329         /* Enable PM on mobility chips */
2330         if (rinfo->is_mobility) {
2331                 /* Find PM registers in config space */
2332                 rinfo->pm_reg = pci_find_capability(pdev, PCI_CAP_ID_PM);
2333                 /* Enable dynamic PM of chip clocks */
2334                 radeon_pm_enable_dynamic_mode(rinfo);
2335                 printk("radeonfb: Power Management enabled for Mobility chipsets\n");
2336         }
2337
2338         if (register_framebuffer(info) < 0) {
2339                 printk (KERN_ERR "radeonfb: could not register framebuffer\n");
2340                 goto unmap_fb;
2341         }
2342
2343 #ifdef CONFIG_MTRR
2344         rinfo->mtrr_hdl = nomtrr ? -1 : mtrr_add(rinfo->fb_base_phys,
2345                                                  rinfo->video_ram,
2346                                                  MTRR_TYPE_WRCOMB, 1);
2347 #endif
2348
2349 #ifdef CONFIG_PMAC_BACKLIGHT
2350         if (rinfo->mon1_type == MT_LCD) {
2351                 register_backlight_controller(&radeon_backlight_controller,
2352                                               rinfo, "ati");
2353                 register_backlight_controller(&radeon_backlight_controller,
2354                                               rinfo, "mnca");
2355         }
2356 #endif
2357
2358         printk ("radeonfb: %s %s %ld MB\n", rinfo->name, rinfo->ram_type,
2359                 (rinfo->video_ram/(1024*1024)));
2360
2361         if (rinfo->bios_seg)
2362                 radeon_unmap_ROM(rinfo, pdev);
2363         RTRACE("radeonfb_pci_register END\n");
2364
2365         return 0;
2366 unmap_fb:
2367         iounmap ((void*)rinfo->fb_base);
2368 unmap_rom:
2369         if (rinfo->mon1_EDID)
2370             kfree(rinfo->mon1_EDID);
2371         if (rinfo->mon2_EDID)
2372             kfree(rinfo->mon2_EDID);
2373         if (rinfo->mon1_modedb)
2374                 fb_destroy_modedb(rinfo->mon1_modedb);
2375 #ifdef CONFIG_FB_RADEON_I2C
2376         radeon_delete_i2c_busses(rinfo);
2377 #endif
2378         if (rinfo->bios_seg)
2379                 radeon_unmap_ROM(rinfo, pdev);
2380         iounmap ((void*)rinfo->mmio_base);
2381 release_mmio:
2382         release_mem_region (rinfo->mmio_base_phys,
2383                             pci_resource_len(pdev, 2));
2384 release_fb:
2385         release_mem_region (rinfo->fb_base_phys,
2386                             pci_resource_len(pdev, 0));
2387 free_rinfo:
2388         framebuffer_release(info);
2389         return -ENODEV;
2390 }
2391
2392
2393
2394 static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev)
2395 {
2396         struct fb_info *info = pci_get_drvdata(pdev);
2397         struct radeonfb_info *rinfo = info->par;
2398
2399         if (!rinfo)
2400                 return;
2401
2402         /* restore original state
2403          *
2404          * Doesn't quite work yet, possibly because of the PPC hacking
2405          * I do on startup, disable for now. --BenH
2406          */
2407         radeon_write_mode (rinfo, &rinfo->init_state);
2408
2409         del_timer_sync(&rinfo->lvds_timer);
2410
2411 #ifdef CONFIG_MTRR
2412         if (rinfo->mtrr_hdl >= 0)
2413                 mtrr_del(rinfo->mtrr_hdl, 0, 0);
2414 #endif
2415
2416         unregister_framebuffer(info);
2417
2418         iounmap ((void*)rinfo->mmio_base);
2419         iounmap ((void*)rinfo->fb_base);
2420
2421         release_mem_region (rinfo->mmio_base_phys,
2422                             pci_resource_len(pdev, 2));
2423         release_mem_region (rinfo->fb_base_phys,
2424                             pci_resource_len(pdev, 0));
2425
2426         if (rinfo->mon1_EDID)
2427                 kfree(rinfo->mon1_EDID);
2428         if (rinfo->mon2_EDID)
2429                 kfree(rinfo->mon2_EDID);
2430         if (rinfo->mon1_modedb)
2431                 fb_destroy_modedb(rinfo->mon1_modedb);
2432 #ifdef CONFIG_FB_RADEON_I2C
2433         radeon_delete_i2c_busses(rinfo);
2434 #endif
2435         framebuffer_release(info);
2436 }
2437
2438
2439 static struct pci_driver radeonfb_driver = {
2440         .name           = "radeonfb",
2441         .id_table       = radeonfb_pci_table,
2442         .probe          = radeonfb_pci_register,
2443         .remove         = __devexit_p(radeonfb_pci_unregister),
2444 #ifdef CONFIG_PM
2445         .suspend        = radeonfb_pci_suspend,
2446         .resume         = radeonfb_pci_resume,
2447 #endif /* CONFIG_PM */
2448 };
2449
2450
2451 int __init radeonfb_init (void)
2452 {
2453         return pci_module_init (&radeonfb_driver);
2454 }
2455
2456
2457 void __exit radeonfb_exit (void)
2458 {
2459         pci_unregister_driver (&radeonfb_driver);
2460 }
2461
2462 int __init radeonfb_setup (char *options)
2463 {
2464         char *this_opt;
2465
2466         if (!options || !*options)
2467                 return 0;
2468
2469         while ((this_opt = strsep (&options, ",")) != NULL) {
2470                 if (!*this_opt)
2471                         continue;
2472
2473                 if (!strncmp(this_opt, "noaccel", 7)) {
2474                         noaccel = 1;
2475                 } else if (!strncmp(this_opt, "mirror", 6)) {
2476                         mirror = 1;
2477                 } else if (!strncmp(this_opt, "force_dfp", 9)) {
2478                         force_dfp = 1;
2479                 } else if (!strncmp(this_opt, "panel_yres:", 11)) {
2480                         panel_yres = simple_strtoul((this_opt+11), NULL, 0);
2481 #ifdef CONFIG_MTRR
2482                 } else if (!strncmp(this_opt, "nomtrr", 6)) {
2483                         nomtrr = 1;
2484 #endif
2485                 } else if (!strncmp(this_opt, "nomodeset", 9)) {
2486                         nomodeset = 1;
2487                 } else if (!strncmp(this_opt, "force_measure_pll", 17)) {
2488                         force_measure_pll = 1;
2489                 } else if (!strncmp(this_opt, "ignore_edid", 11)) {
2490                         ignore_edid = 1;
2491                 } else
2492                         mode_option = this_opt;
2493         }
2494         return 0;
2495 }
2496
2497
2498 #ifdef MODULE
2499 module_init(radeonfb_init);
2500 module_exit(radeonfb_exit);
2501 #endif
2502
2503 MODULE_AUTHOR("Ani Joshi");
2504 MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset");
2505 MODULE_LICENSE("GPL");
2506 module_param(noaccel, bool, 0);
2507 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
2508 module_param(nomodeset, bool, 0);
2509 MODULE_PARM_DESC(nomodeset, "bool: disable actual setting of video mode");
2510 module_param(mirror, bool, 0);
2511 MODULE_PARM_DESC(mirror, "bool: mirror the display to both monitors");
2512 module_param(force_dfp, bool, 0);
2513 MODULE_PARM_DESC(force_dfp, "bool: force display to dfp");
2514 module_param(ignore_edid, bool, 0);
2515 MODULE_PARM_DESC(ignore_edid, "bool: Ignore EDID data when doing DDC probe");
2516 module_param(monitor_layout, charp, 0);
2517 MODULE_PARM_DESC(monitor_layout, "Specify monitor mapping (like XFree86)");
2518 module_param(force_measure_pll, bool, 0);
2519 MODULE_PARM_DESC(force_measure_pll, "Force measurement of PLL (debug)");
2520 #ifdef CONFIG_MTRR
2521 module_param(nomtrr, bool, 0);
2522 MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
2523 #endif
2524 module_param(panel_yres, int, 0);
2525 MODULE_PARM_DESC(panel_yres, "int: set panel yres");
2526 module_param(mode_option, charp, 0);
2527 MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");