drivers/video/aty/radeon_pm.c

   1 /*
   2  *      drivers/video/aty/radeon_pm.c
   3  *
   4  *      Copyright 2003,2004 Ben. Herrenschmidt <benh@kernel.crashing.org>
   5  *      Copyright 2004 Paul Mackerras <paulus@samba.org>
   6  *
   7  *      This is the power management code for ATI radeon chipsets. It contains
   8  *      some dynamic clock PM enable/disable code similar to what X.org does,
   9  *      some D2-state (APM-style) sleep/wakeup code for use on some PowerMacs,
  10  *      and the necessary bits to re-initialize from scratch a few chips found
  11  *      on PowerMacs as well. The later could be extended to more platforms
  12  *      provided the memory controller configuration code be made more generic,
  13  *      and you can get the proper mode register commands for your RAMs.
  14  *      Those things may be found in the BIOS image...
  15  */
  16
  17 #include "radeonfb.h"
  18
  19 #include <linux/console.h>
  20 #include <linux/agp_backend.h>
  21
  22 #ifdef CONFIG_PPC_PMAC
  23 #include <asm/machdep.h>
  24 #include <asm/prom.h>
  25 #include <asm/pmac_feature.h>
  26 #endif
  27
  28 /* For detecting supported PC laptops */
  29 #ifdef CONFIG_X86
  30 #include <linux/dmi.h>
  31 #endif
  32
  33 #include "ati_ids.h"
  34
  35 #ifdef CONFIG_X86
  36 /* This array holds a list of supported PC laptops.
  37  * Currently only few IBM models are tested.
  38  * If you want to experiment, use dmidecode to find out
  39  * vendor and product codes for Your laptop.
  40  */
  41 static struct dmi_system_id __devinitdata radeonfb_dmi_table[] = {
  42 #include "radeon_pm_whitelist.h"
  43 };
  44
  45 extern int radeon_force_sleep;
  46 #endif
  47
  48 static void radeon_pm_disable_dynamic_mode(struct radeonfb_info *rinfo)
  49 {
  50         u32 tmp;
  51
  52         /* RV100 */
  53         if ((rinfo->family == CHIP_FAMILY_RV100) && (!rinfo->is_mobility)) {
  54                 if (rinfo->has_CRTC2) {
  55                         tmp = INPLL(pllSCLK_CNTL);
  56                         tmp &= ~SCLK_CNTL__DYN_STOP_LAT_MASK;
  57                         tmp |= SCLK_CNTL__CP_MAX_DYN_STOP_LAT | SCLK_CNTL__FORCEON_MASK;
  58                         OUTPLL(pllSCLK_CNTL, tmp);
  59                 }
  60                 tmp = INPLL(pllMCLK_CNTL);
  61                 tmp |= (MCLK_CNTL__FORCE_MCLKA |
  62                         MCLK_CNTL__FORCE_MCLKB |
  63                         MCLK_CNTL__FORCE_YCLKA |
  64                         MCLK_CNTL__FORCE_YCLKB |
  65                         MCLK_CNTL__FORCE_AIC |
  66                         MCLK_CNTL__FORCE_MC);
  67                 OUTPLL(pllMCLK_CNTL, tmp);
  68                 return;
  69         }
  70         /* R100 */
  71         if (!rinfo->has_CRTC2) {
  72                 tmp = INPLL(pllSCLK_CNTL);
  73                 tmp |= (SCLK_CNTL__FORCE_CP     | SCLK_CNTL__FORCE_HDP  |
  74                         SCLK_CNTL__FORCE_DISP1  | SCLK_CNTL__FORCE_TOP  |
  75                         SCLK_CNTL__FORCE_E2     | SCLK_CNTL__FORCE_SE   |
  76                         SCLK_CNTL__FORCE_IDCT   | SCLK_CNTL__FORCE_VIP  |
  77                         SCLK_CNTL__FORCE_RE     | SCLK_CNTL__FORCE_PB   |
  78                         SCLK_CNTL__FORCE_TAM    | SCLK_CNTL__FORCE_TDM  |
  79                         SCLK_CNTL__FORCE_RB);
  80                 OUTPLL(pllSCLK_CNTL, tmp);
  81                 return;
  82         }
  83         /* RV350 (M10/M11) */
  84         if (rinfo->family == CHIP_FAMILY_RV350) {
  85                 /* for RV350/M10/M11, no delays are required. */
  86                 tmp = INPLL(pllSCLK_CNTL2);
  87                 tmp |= (SCLK_CNTL2__R300_FORCE_TCL |
  88                         SCLK_CNTL2__R300_FORCE_GA  |
  89                         SCLK_CNTL2__R300_FORCE_CBA);
  90                 OUTPLL(pllSCLK_CNTL2, tmp);
  91
  92                 tmp = INPLL(pllSCLK_CNTL);
  93                 tmp |= (SCLK_CNTL__FORCE_DISP2          | SCLK_CNTL__FORCE_CP           |
  94                         SCLK_CNTL__FORCE_HDP            | SCLK_CNTL__FORCE_DISP1        |
  95                         SCLK_CNTL__FORCE_TOP            | SCLK_CNTL__FORCE_E2           |
  96                         SCLK_CNTL__R300_FORCE_VAP       | SCLK_CNTL__FORCE_IDCT         |
  97                         SCLK_CNTL__FORCE_VIP            | SCLK_CNTL__R300_FORCE_SR      |
  98                         SCLK_CNTL__R300_FORCE_PX        | SCLK_CNTL__R300_FORCE_TX      |
  99                         SCLK_CNTL__R300_FORCE_US        | SCLK_CNTL__FORCE_TV_SCLK      |
 100                         SCLK_CNTL__R300_FORCE_SU        | SCLK_CNTL__FORCE_OV0);
 101                 OUTPLL(pllSCLK_CNTL, tmp);
 102
 103                 tmp = INPLL(pllSCLK_MORE_CNTL);
 104                 tmp |= (SCLK_MORE_CNTL__FORCE_DISPREGS  | SCLK_MORE_CNTL__FORCE_MC_GUI  |
 105                         SCLK_MORE_CNTL__FORCE_MC_HOST);
 106                 OUTPLL(pllSCLK_MORE_CNTL, tmp);
 107
 108                 tmp = INPLL(pllMCLK_CNTL);
 109                 tmp |= (MCLK_CNTL__FORCE_MCLKA |
 110                         MCLK_CNTL__FORCE_MCLKB |
 111                         MCLK_CNTL__FORCE_YCLKA |
 112                         MCLK_CNTL__FORCE_YCLKB |
 113                         MCLK_CNTL__FORCE_MC);
 114                 OUTPLL(pllMCLK_CNTL, tmp);
 115
 116                 tmp = INPLL(pllVCLK_ECP_CNTL);
 117                 tmp &= ~(VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb  |
 118                          VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb |
 119                          VCLK_ECP_CNTL__R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF);
 120                 OUTPLL(pllVCLK_ECP_CNTL, tmp);
 121
 122                 tmp = INPLL(pllPIXCLKS_CNTL);
 123                 tmp &= ~(PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb               |
 124                          PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb           |
 125                          PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb  |
 126                          PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb           |
 127                          PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb          |
 128                          PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb             |
 129                          PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb       |
 130                          PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb           |
 131                          PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb           |
 132                          PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb     |
 133                          PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb       |
 134                          PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb          |
 135                          PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb          |
 136                          PIXCLKS_CNTL__R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF);
 137                 OUTPLL(pllPIXCLKS_CNTL, tmp);
 138
 139                 return;
 140         }
 141
 142         /* Default */
 143
 144         /* Force Core Clocks */
 145         tmp = INPLL(pllSCLK_CNTL);
 146         tmp |= (SCLK_CNTL__FORCE_CP | SCLK_CNTL__FORCE_E2);
 147
 148         /* XFree doesn't do that case, but we had this code from Apple and it
 149          * seem necessary for proper suspend/resume operations
 150          */
 151         if (rinfo->is_mobility) {
 152                 tmp |=  SCLK_CNTL__FORCE_HDP|
 153                         SCLK_CNTL__FORCE_DISP1|
 154                         SCLK_CNTL__FORCE_DISP2|
 155                         SCLK_CNTL__FORCE_TOP|
 156                         SCLK_CNTL__FORCE_SE|
 157                         SCLK_CNTL__FORCE_IDCT|
 158                         SCLK_CNTL__FORCE_VIP|
 159                         SCLK_CNTL__FORCE_PB|
 160                         SCLK_CNTL__FORCE_RE|
 161                         SCLK_CNTL__FORCE_TAM|
 162                         SCLK_CNTL__FORCE_TDM|
 163                         SCLK_CNTL__FORCE_RB|
 164                         SCLK_CNTL__FORCE_TV_SCLK|
 165                         SCLK_CNTL__FORCE_SUBPIC|
 166                         SCLK_CNTL__FORCE_OV0;
 167         }
 168         else if (rinfo->family == CHIP_FAMILY_R300 ||
 169                    rinfo->family == CHIP_FAMILY_R350) {
 170                 tmp |=  SCLK_CNTL__FORCE_HDP   |
 171                         SCLK_CNTL__FORCE_DISP1 |
 172                         SCLK_CNTL__FORCE_DISP2 |
 173                         SCLK_CNTL__FORCE_TOP   |
 174                         SCLK_CNTL__FORCE_IDCT  |
 175                         SCLK_CNTL__FORCE_VIP;
 176         }
 177         OUTPLL(pllSCLK_CNTL, tmp);
 178         radeon_msleep(16);
 179
 180         if (rinfo->family == CHIP_FAMILY_R300 || rinfo->family == CHIP_FAMILY_R350) {
 181                 tmp = INPLL(pllSCLK_CNTL2);
 182                 tmp |=  SCLK_CNTL2__R300_FORCE_TCL |
 183                         SCLK_CNTL2__R300_FORCE_GA  |
 184                         SCLK_CNTL2__R300_FORCE_CBA;
 185                 OUTPLL(pllSCLK_CNTL2, tmp);
 186                 radeon_msleep(16);
 187         }
 188
 189         tmp = INPLL(pllCLK_PIN_CNTL);
 190         tmp &= ~CLK_PIN_CNTL__SCLK_DYN_START_CNTL;
 191         OUTPLL(pllCLK_PIN_CNTL, tmp);
 192         radeon_msleep(15);
 193
 194         if (rinfo->is_IGP) {
 195                 /* Weird  ... X is _un_ forcing clocks here, I think it's
 196                  * doing backward. Imitate it for now...
 197                  */
 198                 tmp = INPLL(pllMCLK_CNTL);
 199                 tmp &= ~(MCLK_CNTL__FORCE_MCLKA |
 200                          MCLK_CNTL__FORCE_YCLKA);
 201                 OUTPLL(pllMCLK_CNTL, tmp);
 202                 radeon_msleep(16);
 203         }
 204         /* Hrm... same shit, X doesn't do that but I have to */
 205         else if (rinfo->is_mobility) {
 206                 tmp = INPLL(pllMCLK_CNTL);
 207                 tmp |= (MCLK_CNTL__FORCE_MCLKA |
 208                         MCLK_CNTL__FORCE_MCLKB |
 209                         MCLK_CNTL__FORCE_YCLKA |
 210                         MCLK_CNTL__FORCE_YCLKB);
 211                 OUTPLL(pllMCLK_CNTL, tmp);
 212                 radeon_msleep(16);
 213
 214                 tmp = INPLL(pllMCLK_MISC);
 215                 tmp &=  ~(MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT|
 216                           MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT|
 217                           MCLK_MISC__MC_MCLK_DYN_ENABLE|
 218                           MCLK_MISC__IO_MCLK_DYN_ENABLE);
 219                 OUTPLL(pllMCLK_MISC, tmp);
 220                 radeon_msleep(15);
 221         }
 222
 223         if (rinfo->is_mobility) {
 224                 tmp = INPLL(pllSCLK_MORE_CNTL);
 225                 tmp |=  SCLK_MORE_CNTL__FORCE_DISPREGS|
 226                         SCLK_MORE_CNTL__FORCE_MC_GUI|
 227                         SCLK_MORE_CNTL__FORCE_MC_HOST;
 228                 OUTPLL(pllSCLK_MORE_CNTL, tmp);
 229                 radeon_msleep(16);
 230         }
 231
 232         tmp = INPLL(pllPIXCLKS_CNTL);
 233         tmp &= ~(PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb |
 234                  PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb|
 235                  PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb |
 236                  PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb|
 237                  PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb|
 238                  PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb|
 239                  PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb);
 240         OUTPLL(pllPIXCLKS_CNTL, tmp);
 241         radeon_msleep(16);
 242
 243         tmp = INPLL( pllVCLK_ECP_CNTL);
 244         tmp &= ~(VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb |
 245                  VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb);
 246         OUTPLL( pllVCLK_ECP_CNTL, tmp);
 247         radeon_msleep(16);
 248 }
 249
 250 static void radeon_pm_enable_dynamic_mode(struct radeonfb_info *rinfo)
 251 {
 252         u32 tmp;
 253
 254         /* R100 */
 255         if (!rinfo->has_CRTC2) {
 256                 tmp = INPLL(pllSCLK_CNTL);
 257
 258                 if ((INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK) > CFG_ATI_REV_A13)
 259                     tmp &= ~(SCLK_CNTL__FORCE_CP        | SCLK_CNTL__FORCE_RB);
 260                 tmp &= ~(SCLK_CNTL__FORCE_HDP           | SCLK_CNTL__FORCE_DISP1 |
 261                          SCLK_CNTL__FORCE_TOP           | SCLK_CNTL__FORCE_SE   |
 262                          SCLK_CNTL__FORCE_IDCT          | SCLK_CNTL__FORCE_RE   |
 263                          SCLK_CNTL__FORCE_PB            | SCLK_CNTL__FORCE_TAM  |
 264                          SCLK_CNTL__FORCE_TDM);
 265                 OUTPLL(pllSCLK_CNTL, tmp);
 266                 return;
 267         }
 268
 269         /* M10/M11 */
 270         if (rinfo->family == CHIP_FAMILY_RV350) {
 271                 tmp = INPLL(pllSCLK_CNTL2);
 272                 tmp &= ~(SCLK_CNTL2__R300_FORCE_TCL |
 273                          SCLK_CNTL2__R300_FORCE_GA  |
 274                          SCLK_CNTL2__R300_FORCE_CBA);
 275                 tmp |=  (SCLK_CNTL2__R300_TCL_MAX_DYN_STOP_LAT |
 276                          SCLK_CNTL2__R300_GA_MAX_DYN_STOP_LAT  |
 277                          SCLK_CNTL2__R300_CBA_MAX_DYN_STOP_LAT);
 278                 OUTPLL(pllSCLK_CNTL2, tmp);
 279
 280                 tmp = INPLL(pllSCLK_CNTL);
 281                 tmp &= ~(SCLK_CNTL__FORCE_DISP2 | SCLK_CNTL__FORCE_CP      |
 282                          SCLK_CNTL__FORCE_HDP   | SCLK_CNTL__FORCE_DISP1   |
 283                          SCLK_CNTL__FORCE_TOP   | SCLK_CNTL__FORCE_E2      |
 284                          SCLK_CNTL__R300_FORCE_VAP | SCLK_CNTL__FORCE_IDCT |
 285                          SCLK_CNTL__FORCE_VIP   | SCLK_CNTL__R300_FORCE_SR |
 286                          SCLK_CNTL__R300_FORCE_PX | SCLK_CNTL__R300_FORCE_TX |
 287                          SCLK_CNTL__R300_FORCE_US | SCLK_CNTL__FORCE_TV_SCLK |
 288                          SCLK_CNTL__R300_FORCE_SU | SCLK_CNTL__FORCE_OV0);
 289                 tmp |= SCLK_CNTL__DYN_STOP_LAT_MASK;
 290                 OUTPLL(pllSCLK_CNTL, tmp);
 291
 292                 tmp = INPLL(pllSCLK_MORE_CNTL);
 293                 tmp &= ~SCLK_MORE_CNTL__FORCEON;
 294                 tmp |=  SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT |
 295                         SCLK_MORE_CNTL__MC_GUI_MAX_DYN_STOP_LAT |
 296                         SCLK_MORE_CNTL__MC_HOST_MAX_DYN_STOP_LAT;
 297                 OUTPLL(pllSCLK_MORE_CNTL, tmp);
 298
 299                 tmp = INPLL(pllVCLK_ECP_CNTL);
 300                 tmp |= (VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb |
 301                         VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb);
 302                 OUTPLL(pllVCLK_ECP_CNTL, tmp);
 303
 304                 tmp = INPLL(pllPIXCLKS_CNTL);
 305                 tmp |= (PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb         |
 306                         PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb     |
 307                         PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
 308                         PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb            |
 309                         PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb    |
 310                         PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb       |
 311                         PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb        |
 312                         PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb     |
 313                         PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb     |
 314                         PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb      |
 315                         PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb        |
 316                         PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb           |
 317                         PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb);
 318                 OUTPLL(pllPIXCLKS_CNTL, tmp);
 319
 320                 tmp = INPLL(pllMCLK_MISC);
 321                 tmp |= (MCLK_MISC__MC_MCLK_DYN_ENABLE |
 322                         MCLK_MISC__IO_MCLK_DYN_ENABLE);
 323                 OUTPLL(pllMCLK_MISC, tmp);
 324
 325                 tmp = INPLL(pllMCLK_CNTL);
 326                 tmp |= (MCLK_CNTL__FORCE_MCLKA | MCLK_CNTL__FORCE_MCLKB);
 327                 tmp &= ~(MCLK_CNTL__FORCE_YCLKA  |
 328                          MCLK_CNTL__FORCE_YCLKB  |
 329                          MCLK_CNTL__FORCE_MC);
 330
 331                 /* Some releases of vbios have set DISABLE_MC_MCLKA
 332                  * and DISABLE_MC_MCLKB bits in the vbios table.  Setting these
 333                  * bits will cause H/W hang when reading video memory with dynamic
 334                  * clocking enabled.
 335                  */
 336                 if ((tmp & MCLK_CNTL__R300_DISABLE_MC_MCLKA) &&
 337                     (tmp & MCLK_CNTL__R300_DISABLE_MC_MCLKB)) {
 338                         /* If both bits are set, then check the active channels */
 339                         tmp = INPLL(pllMCLK_CNTL);
 340                         if (rinfo->vram_width == 64) {
 341                             if (INREG(MEM_CNTL) & R300_MEM_USE_CD_CH_ONLY)
 342                                 tmp &= ~MCLK_CNTL__R300_DISABLE_MC_MCLKB;
 343                             else
 344                                 tmp &= ~MCLK_CNTL__R300_DISABLE_MC_MCLKA;
 345                         } else {
 346                             tmp &= ~(MCLK_CNTL__R300_DISABLE_MC_MCLKA |
 347                                      MCLK_CNTL__R300_DISABLE_MC_MCLKB);
 348                         }
 349                 }
 350                 OUTPLL(pllMCLK_CNTL, tmp);
 351                 return;
 352         }
 353
 354         /* R300 */
 355         if (rinfo->family == CHIP_FAMILY_R300 || rinfo->family == CHIP_FAMILY_R350) {
 356                 tmp = INPLL(pllSCLK_CNTL);
 357                 tmp &= ~(SCLK_CNTL__R300_FORCE_VAP);
 358                 tmp |= SCLK_CNTL__FORCE_CP;
 359                 OUTPLL(pllSCLK_CNTL, tmp);
 360                 radeon_msleep(15);
 361
 362                 tmp = INPLL(pllSCLK_CNTL2);
 363                 tmp &= ~(SCLK_CNTL2__R300_FORCE_TCL |
 364                          SCLK_CNTL2__R300_FORCE_GA  |
 365                          SCLK_CNTL2__R300_FORCE_CBA);
 366                 OUTPLL(pllSCLK_CNTL2, tmp);
 367         }
 368
 369         /* Others */
 370
 371         tmp = INPLL( pllCLK_PWRMGT_CNTL);
 372         tmp &= ~(CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK|
 373                  CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT_MASK|
 374                  CLK_PWRMGT_CNTL__DYN_STOP_MODE_MASK);
 375         tmp |= CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE_MASK |
 376                (0x01 << CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT__SHIFT);
 377         OUTPLL( pllCLK_PWRMGT_CNTL, tmp);
 378         radeon_msleep(15);
 379
 380         tmp = INPLL(pllCLK_PIN_CNTL);
 381         tmp |= CLK_PIN_CNTL__SCLK_DYN_START_CNTL;
 382         OUTPLL(pllCLK_PIN_CNTL, tmp);
 383         radeon_msleep(15);
 384
 385         /* When DRI is enabled, setting DYN_STOP_LAT to zero can cause some R200
 386          * to lockup randomly, leave them as set by BIOS.
 387          */
 388         tmp = INPLL(pllSCLK_CNTL);
 389         tmp &= ~SCLK_CNTL__FORCEON_MASK;
 390
 391         /*RAGE_6::A11 A12 A12N1 A13, RV250::A11 A12, R300*/
 392         if ((rinfo->family == CHIP_FAMILY_RV250 &&
 393              ((INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13)) ||
 394             ((rinfo->family == CHIP_FAMILY_RV100) &&
 395              ((INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK) <= CFG_ATI_REV_A13))) {
 396                 tmp |= SCLK_CNTL__FORCE_CP;
 397                 tmp |= SCLK_CNTL__FORCE_VIP;
 398         }
 399         OUTPLL(pllSCLK_CNTL, tmp);
 400         radeon_msleep(15);
 401
 402         if ((rinfo->family == CHIP_FAMILY_RV200) ||
 403             (rinfo->family == CHIP_FAMILY_RV250) ||
 404             (rinfo->family == CHIP_FAMILY_RV280)) {
 405                 tmp = INPLL(pllSCLK_MORE_CNTL);
 406                 tmp &= ~SCLK_MORE_CNTL__FORCEON;
 407
 408                 /* RV200::A11 A12 RV250::A11 A12 */
 409                 if (((rinfo->family == CHIP_FAMILY_RV200) ||
 410                      (rinfo->family == CHIP_FAMILY_RV250)) &&
 411                     ((INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13))
 412                         tmp |= SCLK_MORE_CNTL__FORCEON;
 413
 414                 OUTPLL(pllSCLK_MORE_CNTL, tmp);
 415                 radeon_msleep(15);
 416         }
 417
 418
 419         /* RV200::A11 A12, RV250::A11 A12 */
 420         if (((rinfo->family == CHIP_FAMILY_RV200) ||
 421              (rinfo->family == CHIP_FAMILY_RV250)) &&
 422             ((INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13)) {
 423                 tmp = INPLL(pllPLL_PWRMGT_CNTL);
 424                 tmp |= PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE;
 425                 OUTPLL(pllPLL_PWRMGT_CNTL, tmp);
 426                 radeon_msleep(15);
 427         }
 428
 429         tmp = INPLL(pllPIXCLKS_CNTL);
 430         tmp |=  PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb |
 431                 PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb|
 432                 PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb|
 433                 PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb|
 434                 PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb|
 435                 PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb|
 436                 PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb;
 437         OUTPLL(pllPIXCLKS_CNTL, tmp);
 438         radeon_msleep(15);
 439
 440         tmp = INPLL(pllVCLK_ECP_CNTL);
 441         tmp |=  VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb |
 442                 VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb;
 443         OUTPLL(pllVCLK_ECP_CNTL, tmp);
 444
 445         /* X doesn't do that ... hrm, we do on mobility && Macs */
 446 #ifdef CONFIG_PPC_OF
 447         if (rinfo->is_mobility) {
 448                 tmp  = INPLL(pllMCLK_CNTL);
 449                 tmp &= ~(MCLK_CNTL__FORCE_MCLKA |
 450                          MCLK_CNTL__FORCE_MCLKB |
 451                          MCLK_CNTL__FORCE_YCLKA |
 452                          MCLK_CNTL__FORCE_YCLKB);
 453                 OUTPLL(pllMCLK_CNTL, tmp);
 454                 radeon_msleep(15);
 455
 456                 tmp = INPLL(pllMCLK_MISC);
 457                 tmp |=  MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT|
 458                         MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT|
 459                         MCLK_MISC__MC_MCLK_DYN_ENABLE|
 460                         MCLK_MISC__IO_MCLK_DYN_ENABLE;
 461                 OUTPLL(pllMCLK_MISC, tmp);
 462                 radeon_msleep(15);
 463         }
 464 #endif /* CONFIG_PPC_OF */
 465 }
 466
 467 #ifdef CONFIG_PM
 468
 469 static void OUTMC( struct radeonfb_info *rinfo, u8 indx, u32 value)
 470 {
 471         OUTREG( MC_IND_INDEX, indx | MC_IND_INDEX__MC_IND_WR_EN);
 472         OUTREG( MC_IND_DATA, value);
 473 }
 474
 475 static u32 INMC(struct radeonfb_info *rinfo, u8 indx)
 476 {
 477         OUTREG( MC_IND_INDEX, indx);
 478         return INREG( MC_IND_DATA);
 479 }
 480
 481 static void radeon_pm_save_regs(struct radeonfb_info *rinfo, int saving_for_d3)
 482 {
 483         rinfo->save_regs[0] = INPLL(PLL_PWRMGT_CNTL);
 484         rinfo->save_regs[1] = INPLL(CLK_PWRMGT_CNTL);
 485         rinfo->save_regs[2] = INPLL(MCLK_CNTL);
 486         rinfo->save_regs[3] = INPLL(SCLK_CNTL);
 487         rinfo->save_regs[4] = INPLL(CLK_PIN_CNTL);
 488         rinfo->save_regs[5] = INPLL(VCLK_ECP_CNTL);
 489         rinfo->save_regs[6] = INPLL(PIXCLKS_CNTL);
 490         rinfo->save_regs[7] = INPLL(MCLK_MISC);
 491         rinfo->save_regs[8] = INPLL(P2PLL_CNTL);
 492
 493         rinfo->save_regs[9] = INREG(DISP_MISC_CNTL);
 494         rinfo->save_regs[10] = INREG(DISP_PWR_MAN);
 495         rinfo->save_regs[11] = INREG(LVDS_GEN_CNTL);
 496         rinfo->save_regs[13] = INREG(TV_DAC_CNTL);
 497         rinfo->save_regs[14] = INREG(BUS_CNTL1);
 498         rinfo->save_regs[15] = INREG(CRTC_OFFSET_CNTL);
 499         rinfo->save_regs[16] = INREG(AGP_CNTL);
 500         rinfo->save_regs[17] = (INREG(CRTC_GEN_CNTL) & 0xfdffffff) | 0x04000000;
 501         rinfo->save_regs[18] = (INREG(CRTC2_GEN_CNTL) & 0xfdffffff) | 0x04000000;
 502         rinfo->save_regs[19] = INREG(GPIOPAD_A);
 503         rinfo->save_regs[20] = INREG(GPIOPAD_EN);
 504         rinfo->save_regs[21] = INREG(GPIOPAD_MASK);
 505         rinfo->save_regs[22] = INREG(ZV_LCDPAD_A);
 506         rinfo->save_regs[23] = INREG(ZV_LCDPAD_EN);
 507         rinfo->save_regs[24] = INREG(ZV_LCDPAD_MASK);
 508         rinfo->save_regs[25] = INREG(GPIO_VGA_DDC);
 509         rinfo->save_regs[26] = INREG(GPIO_DVI_DDC);
 510         rinfo->save_regs[27] = INREG(GPIO_MONID);
 511         rinfo->save_regs[28] = INREG(GPIO_CRT2_DDC);
 512
 513         rinfo->save_regs[29] = INREG(SURFACE_CNTL);
 514         rinfo->save_regs[30] = INREG(MC_FB_LOCATION);
 515         rinfo->save_regs[31] = INREG(DISPLAY_BASE_ADDR);
 516         rinfo->save_regs[32] = INREG(MC_AGP_LOCATION);
 517         rinfo->save_regs[33] = INREG(CRTC2_DISPLAY_BASE_ADDR);
 518
 519         rinfo->save_regs[34] = INPLL(SCLK_MORE_CNTL);
 520         rinfo->save_regs[35] = INREG(MEM_SDRAM_MODE_REG);
 521         rinfo->save_regs[36] = INREG(BUS_CNTL);
 522         rinfo->save_regs[39] = INREG(RBBM_CNTL);
 523         rinfo->save_regs[40] = INREG(DAC_CNTL);
 524         rinfo->save_regs[41] = INREG(HOST_PATH_CNTL);
 525         rinfo->save_regs[37] = INREG(MPP_TB_CONFIG);
 526         rinfo->save_regs[38] = INREG(FCP_CNTL);
 527
 528         if (rinfo->is_mobility) {
 529                 rinfo->save_regs[12] = INREG(LVDS_PLL_CNTL);
 530                 rinfo->save_regs[43] = INPLL(pllSSPLL_CNTL);
 531                 rinfo->save_regs[44] = INPLL(pllSSPLL_REF_DIV);
 532                 rinfo->save_regs[45] = INPLL(pllSSPLL_DIV_0);
 533                 rinfo->save_regs[90] = INPLL(pllSS_INT_CNTL);
 534                 rinfo->save_regs[91] = INPLL(pllSS_TST_CNTL);
 535                 rinfo->save_regs[81] = INREG(LVDS_GEN_CNTL);
 536         }
 537
 538         if (rinfo->family >= CHIP_FAMILY_RV200) {
 539                 rinfo->save_regs[42] = INREG(MEM_REFRESH_CNTL);
 540                 rinfo->save_regs[46] = INREG(MC_CNTL);
 541                 rinfo->save_regs[47] = INREG(MC_INIT_GFX_LAT_TIMER);
 542                 rinfo->save_regs[48] = INREG(MC_INIT_MISC_LAT_TIMER);
 543                 rinfo->save_regs[49] = INREG(MC_TIMING_CNTL);
 544                 rinfo->save_regs[50] = INREG(MC_READ_CNTL_AB);
 545                 rinfo->save_regs[51] = INREG(MC_IOPAD_CNTL);
 546                 rinfo->save_regs[52] = INREG(MC_CHIP_IO_OE_CNTL_AB);
 547                 rinfo->save_regs[53] = INREG(MC_DEBUG);
 548         }
 549         rinfo->save_regs[54] = INREG(PAMAC0_DLY_CNTL);
 550         rinfo->save_regs[55] = INREG(PAMAC1_DLY_CNTL);
 551         rinfo->save_regs[56] = INREG(PAD_CTLR_MISC);
 552         rinfo->save_regs[57] = INREG(FW_CNTL);
 553
 554         if (rinfo->family >= CHIP_FAMILY_R300) {
 555                 rinfo->save_regs[58] = INMC(rinfo, ixR300_MC_MC_INIT_WR_LAT_TIMER);
 556                 rinfo->save_regs[59] = INMC(rinfo, ixR300_MC_IMP_CNTL);
 557                 rinfo->save_regs[60] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_C0);
 558                 rinfo->save_regs[61] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_C1);
 559                 rinfo->save_regs[62] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_D0);
 560                 rinfo->save_regs[63] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_D1);
 561                 rinfo->save_regs[64] = INMC(rinfo, ixR300_MC_BIST_CNTL_3);
 562                 rinfo->save_regs[65] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_A0);
 563                 rinfo->save_regs[66] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_A1);
 564                 rinfo->save_regs[67] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_B0);
 565                 rinfo->save_regs[68] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_B1);
 566                 rinfo->save_regs[69] = INMC(rinfo, ixR300_MC_DEBUG_CNTL);
 567                 rinfo->save_regs[70] = INMC(rinfo, ixR300_MC_DLL_CNTL);
 568                 rinfo->save_regs[71] = INMC(rinfo, ixR300_MC_IMP_CNTL_0);
 569                 rinfo->save_regs[72] = INMC(rinfo, ixR300_MC_ELPIDA_CNTL);
 570                 rinfo->save_regs[96] = INMC(rinfo, ixR300_MC_READ_CNTL_CD);
 571         } else {
 572                 rinfo->save_regs[59] = INMC(rinfo, ixMC_IMP_CNTL);
 573                 rinfo->save_regs[65] = INMC(rinfo, ixMC_CHP_IO_CNTL_A0);
 574                 rinfo->save_regs[66] = INMC(rinfo, ixMC_CHP_IO_CNTL_A1);
 575                 rinfo->save_regs[67] = INMC(rinfo, ixMC_CHP_IO_CNTL_B0);
 576                 rinfo->save_regs[68] = INMC(rinfo, ixMC_CHP_IO_CNTL_B1);
 577                 rinfo->save_regs[71] = INMC(rinfo, ixMC_IMP_CNTL_0);
 578         }
 579
 580         rinfo->save_regs[73] = INPLL(pllMPLL_CNTL);
 581         rinfo->save_regs[74] = INPLL(pllSPLL_CNTL);
 582         rinfo->save_regs[75] = INPLL(pllMPLL_AUX_CNTL);
 583         rinfo->save_regs[76] = INPLL(pllSPLL_AUX_CNTL);
 584         rinfo->save_regs[77] = INPLL(pllM_SPLL_REF_FB_DIV);
 585         rinfo->save_regs[78] = INPLL(pllAGP_PLL_CNTL);
 586         rinfo->save_regs[79] = INREG(PAMAC2_DLY_CNTL);
 587
 588         rinfo->save_regs[80] = INREG(OV0_BASE_ADDR);
 589         rinfo->save_regs[82] = INREG(FP_GEN_CNTL);
 590         rinfo->save_regs[83] = INREG(FP2_GEN_CNTL);
 591         rinfo->save_regs[84] = INREG(TMDS_CNTL);
 592         rinfo->save_regs[85] = INREG(TMDS_TRANSMITTER_CNTL);
 593         rinfo->save_regs[86] = INREG(DISP_OUTPUT_CNTL);
 594         rinfo->save_regs[87] = INREG(DISP_HW_DEBUG);
 595         rinfo->save_regs[88] = INREG(TV_MASTER_CNTL);
 596         rinfo->save_regs[89] = INPLL(pllP2PLL_REF_DIV);
 597         rinfo->save_regs[92] = INPLL(pllPPLL_DIV_0);
 598         rinfo->save_regs[93] = INPLL(pllPPLL_CNTL);
 599         rinfo->save_regs[94] = INREG(GRPH_BUFFER_CNTL);
 600         rinfo->save_regs[95] = INREG(GRPH2_BUFFER_CNTL);
 601         rinfo->save_regs[96] = INREG(HDP_DEBUG);
 602         rinfo->save_regs[97] = INPLL(pllMDLL_CKO);
 603         rinfo->save_regs[98] = INPLL(pllMDLL_RDCKA);
 604         rinfo->save_regs[99] = INPLL(pllMDLL_RDCKB);
 605 }
 606
 607 static void radeon_pm_restore_regs(struct radeonfb_info *rinfo)
 608 {
 609         OUTPLL(P2PLL_CNTL, rinfo->save_regs[8] & 0xFFFFFFFE); /* First */
 610
 611         OUTPLL(PLL_PWRMGT_CNTL, rinfo->save_regs[0]);
 612         OUTPLL(CLK_PWRMGT_CNTL, rinfo->save_regs[1]);
 613         OUTPLL(MCLK_CNTL, rinfo->save_regs[2]);
 614         OUTPLL(SCLK_CNTL, rinfo->save_regs[3]);
 615         OUTPLL(CLK_PIN_CNTL, rinfo->save_regs[4]);
 616         OUTPLL(VCLK_ECP_CNTL, rinfo->save_regs[5]);
 617         OUTPLL(PIXCLKS_CNTL, rinfo->save_regs[6]);
 618         OUTPLL(MCLK_MISC, rinfo->save_regs[7]);
 619         if (rinfo->family == CHIP_FAMILY_RV350)
 620                 OUTPLL(SCLK_MORE_CNTL, rinfo->save_regs[34]);
 621
 622         OUTREG(SURFACE_CNTL, rinfo->save_regs[29]);
 623         OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
 624         OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
 625         OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
 626         OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
 627         OUTREG(CONFIG_MEMSIZE, rinfo->video_ram);
 628
 629         OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
 630         OUTREG(DISP_PWR_MAN, rinfo->save_regs[10]);
 631         OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11]);
 632         OUTREG(LVDS_PLL_CNTL,rinfo->save_regs[12]);
 633         OUTREG(TV_DAC_CNTL, rinfo->save_regs[13]);
 634         OUTREG(BUS_CNTL1, rinfo->save_regs[14]);
 635         OUTREG(CRTC_OFFSET_CNTL, rinfo->save_regs[15]);
 636         OUTREG(AGP_CNTL, rinfo->save_regs[16]);
 637         OUTREG(CRTC_GEN_CNTL, rinfo->save_regs[17]);
 638         OUTREG(CRTC2_GEN_CNTL, rinfo->save_regs[18]);
 639         OUTPLL(P2PLL_CNTL, rinfo->save_regs[8]);
 640
 641         OUTREG(GPIOPAD_A, rinfo->save_regs[19]);
 642         OUTREG(GPIOPAD_EN, rinfo->save_regs[20]);
 643         OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]);
 644         OUTREG(ZV_LCDPAD_A, rinfo->save_regs[22]);
 645         OUTREG(ZV_LCDPAD_EN, rinfo->save_regs[23]);
 646         OUTREG(ZV_LCDPAD_MASK, rinfo->save_regs[24]);
 647         OUTREG(GPIO_VGA_DDC, rinfo->save_regs[25]);
 648         OUTREG(GPIO_DVI_DDC, rinfo->save_regs[26]);
 649         OUTREG(GPIO_MONID, rinfo->save_regs[27]);
 650         OUTREG(GPIO_CRT2_DDC, rinfo->save_regs[28]);
 651 }
 652
 653 static void radeon_pm_disable_iopad(struct radeonfb_info *rinfo)
 654 {
 655         OUTREG(GPIOPAD_MASK, 0x0001ffff);
 656         OUTREG(GPIOPAD_EN, 0x00000400);
 657         OUTREG(GPIOPAD_A, 0x00000000);
 658         OUTREG(ZV_LCDPAD_MASK, 0x00000000);
 659         OUTREG(ZV_LCDPAD_EN, 0x00000000);
 660         OUTREG(ZV_LCDPAD_A, 0x00000000);
 661         OUTREG(GPIO_VGA_DDC, 0x00030000);
 662         OUTREG(GPIO_DVI_DDC, 0x00000000);
 663         OUTREG(GPIO_MONID, 0x00030000);
 664         OUTREG(GPIO_CRT2_DDC, 0x00000000);
 665 }
 666
 667 static void radeon_pm_program_v2clk(struct radeonfb_info *rinfo)
 668 {
 669         /* Set v2clk to 65MHz */
 670         if (rinfo->family <= CHIP_FAMILY_RV280) {
 671                 OUTPLL(pllPIXCLKS_CNTL,
 672                          __INPLL(rinfo, pllPIXCLKS_CNTL)
 673                          & ~PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK);
 674
 675                 OUTPLL(pllP2PLL_REF_DIV, 0x0000000c);
 676                 OUTPLL(pllP2PLL_CNTL, 0x0000bf00);
 677         } else {
 678                 OUTPLL(pllP2PLL_REF_DIV, 0x0000000c);
 679                 INPLL(pllP2PLL_REF_DIV);
 680                 OUTPLL(pllP2PLL_CNTL, 0x0000a700);
 681         }
 682
 683         OUTPLL(pllP2PLL_DIV_0, 0x00020074 | P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W);
 684
 685         OUTPLL(pllP2PLL_CNTL, INPLL(pllP2PLL_CNTL) & ~P2PLL_CNTL__P2PLL_SLEEP);
 686         mdelay(1);
 687
 688         OUTPLL(pllP2PLL_CNTL, INPLL(pllP2PLL_CNTL) & ~P2PLL_CNTL__P2PLL_RESET);
 689         mdelay( 1);
 690
 691         OUTPLL(pllPIXCLKS_CNTL,
 692                 (INPLL(pllPIXCLKS_CNTL) & ~PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK)
 693                 | (0x03 << PIXCLKS_CNTL__PIX2CLK_SRC_SEL__SHIFT));
 694         mdelay( 1);
 695 }
 696
 697 static void radeon_pm_low_current(struct radeonfb_info *rinfo)
 698 {
 699         u32 reg;
 700
 701         reg  = INREG(BUS_CNTL1);
 702         if (rinfo->family <= CHIP_FAMILY_RV280) {
 703                 reg &= ~BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK;
 704                 reg |= BUS_CNTL1_AGPCLK_VALID | (1<<BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT);
 705         } else {
 706                 reg |= 0x4080;
 707         }
 708         OUTREG(BUS_CNTL1, reg);
 709
 710         reg  = INPLL(PLL_PWRMGT_CNTL);
 711         reg |= PLL_PWRMGT_CNTL_SPLL_TURNOFF | PLL_PWRMGT_CNTL_PPLL_TURNOFF |
 712                 PLL_PWRMGT_CNTL_P2PLL_TURNOFF | PLL_PWRMGT_CNTL_TVPLL_TURNOFF;
 713         reg &= ~PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK;
 714         reg &= ~PLL_PWRMGT_CNTL_MOBILE_SU;
 715         OUTPLL(PLL_PWRMGT_CNTL, reg);
 716
 717         reg  = INREG(TV_DAC_CNTL);
 718         reg &= ~(TV_DAC_CNTL_BGADJ_MASK |TV_DAC_CNTL_DACADJ_MASK);
 719         reg |=TV_DAC_CNTL_BGSLEEP | TV_DAC_CNTL_RDACPD | TV_DAC_CNTL_GDACPD |
 720                 TV_DAC_CNTL_BDACPD |
 721                 (8<<TV_DAC_CNTL_BGADJ__SHIFT) | (8<<TV_DAC_CNTL_DACADJ__SHIFT);
 722         OUTREG(TV_DAC_CNTL, reg);
 723
 724         reg  = INREG(TMDS_TRANSMITTER_CNTL);
 725         reg &= ~(TMDS_PLL_EN | TMDS_PLLRST);
 726         OUTREG(TMDS_TRANSMITTER_CNTL, reg);
 727
 728         reg = INREG(DAC_CNTL);
 729         reg &= ~DAC_CMP_EN;
 730         OUTREG(DAC_CNTL, reg);
 731
 732         reg = INREG(DAC_CNTL2);
 733         reg &= ~DAC2_CMP_EN;
 734         OUTREG(DAC_CNTL2, reg);
 735
 736         reg  = INREG(TV_DAC_CNTL);
 737         reg &= ~TV_DAC_CNTL_DETECT;
 738         OUTREG(TV_DAC_CNTL, reg);
 739 }
 740
 741 static void radeon_pm_setup_for_suspend(struct radeonfb_info *rinfo)
 742 {
 743
 744         u32 sclk_cntl, mclk_cntl, sclk_more_cntl;
 745
 746         u32 pll_pwrmgt_cntl;
 747         u32 clk_pwrmgt_cntl;
 748         u32 clk_pin_cntl;
 749         u32 vclk_ecp_cntl;
 750         u32 pixclks_cntl;
 751         u32 disp_mis_cntl;
 752         u32 disp_pwr_man;
 753         u32 tmp;
 754
 755         /* Force Core Clocks */
 756         sclk_cntl = INPLL( pllSCLK_CNTL);
 757         sclk_cntl |=    SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT|
 758                         SCLK_CNTL__VIP_MAX_DYN_STOP_LAT|
 759                         SCLK_CNTL__RE_MAX_DYN_STOP_LAT|
 760                         SCLK_CNTL__PB_MAX_DYN_STOP_LAT|
 761                         SCLK_CNTL__TAM_MAX_DYN_STOP_LAT|
 762                         SCLK_CNTL__TDM_MAX_DYN_STOP_LAT|
 763                         SCLK_CNTL__RB_MAX_DYN_STOP_LAT|
 764
 765                         SCLK_CNTL__FORCE_DISP2|
 766                         SCLK_CNTL__FORCE_CP|
 767                         SCLK_CNTL__FORCE_HDP|
 768                         SCLK_CNTL__FORCE_DISP1|
 769                         SCLK_CNTL__FORCE_TOP|
 770                         SCLK_CNTL__FORCE_E2|
 771                         SCLK_CNTL__FORCE_SE|
 772                         SCLK_CNTL__FORCE_IDCT|
 773                         SCLK_CNTL__FORCE_VIP|
 774
 775                         SCLK_CNTL__FORCE_PB|
 776                         SCLK_CNTL__FORCE_TAM|
 777                         SCLK_CNTL__FORCE_TDM|
 778                         SCLK_CNTL__FORCE_RB|
 779                         SCLK_CNTL__FORCE_TV_SCLK|
 780                         SCLK_CNTL__FORCE_SUBPIC|
 781                         SCLK_CNTL__FORCE_OV0;
 782         if (rinfo->family <= CHIP_FAMILY_RV280)
 783                 sclk_cntl |= SCLK_CNTL__FORCE_RE;
 784         else
 785                 sclk_cntl |= SCLK_CNTL__SE_MAX_DYN_STOP_LAT |
 786                         SCLK_CNTL__E2_MAX_DYN_STOP_LAT |
 787                         SCLK_CNTL__TV_MAX_DYN_STOP_LAT |
 788                         SCLK_CNTL__HDP_MAX_DYN_STOP_LAT |
 789                         SCLK_CNTL__CP_MAX_DYN_STOP_LAT;
 790
 791         OUTPLL( pllSCLK_CNTL, sclk_cntl);
 792
 793         sclk_more_cntl = INPLL(pllSCLK_MORE_CNTL);
 794         sclk_more_cntl |=       SCLK_MORE_CNTL__FORCE_DISPREGS |
 795                                 SCLK_MORE_CNTL__FORCE_MC_GUI |
 796                                 SCLK_MORE_CNTL__FORCE_MC_HOST;
 797
 798         OUTPLL(pllSCLK_MORE_CNTL, sclk_more_cntl);
 799
 800
 801         mclk_cntl = INPLL( pllMCLK_CNTL);
 802         mclk_cntl &= ~( MCLK_CNTL__FORCE_MCLKA |
 803                         MCLK_CNTL__FORCE_MCLKB |
 804                         MCLK_CNTL__FORCE_YCLKA |
 805                         MCLK_CNTL__FORCE_YCLKB |
 806                         MCLK_CNTL__FORCE_MC
 807                       );
 808         OUTPLL( pllMCLK_CNTL, mclk_cntl);
 809
 810         /* Force Display clocks */
 811         vclk_ecp_cntl = INPLL( pllVCLK_ECP_CNTL);
 812         vclk_ecp_cntl &= ~(VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb
 813                            | VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb);
 814         vclk_ecp_cntl |= VCLK_ECP_CNTL__ECP_FORCE_ON;
 815         OUTPLL( pllVCLK_ECP_CNTL, vclk_ecp_cntl);
 816
 817
 818         pixclks_cntl = INPLL( pllPIXCLKS_CNTL);
 819         pixclks_cntl &= ~(      PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb |
 820                                 PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb|
 821                                 PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb |
 822                                 PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb|
 823                                 PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb|
 824                                 PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb|
 825                                 PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb);
 826
 827         OUTPLL( pllPIXCLKS_CNTL, pixclks_cntl);
 828
 829         /* Switch off LVDS interface */
 830         OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) &
 831                ~(LVDS_BLON | LVDS_EN | LVDS_ON | LVDS_DIGON));
 832
 833         /* Enable System power management */
 834         pll_pwrmgt_cntl = INPLL( pllPLL_PWRMGT_CNTL);
 835
 836         pll_pwrmgt_cntl |=      PLL_PWRMGT_CNTL__SPLL_TURNOFF |
 837                                 PLL_PWRMGT_CNTL__MPLL_TURNOFF|
 838                                 PLL_PWRMGT_CNTL__PPLL_TURNOFF|
 839                                 PLL_PWRMGT_CNTL__P2PLL_TURNOFF|
 840                                 PLL_PWRMGT_CNTL__TVPLL_TURNOFF;
 841
 842         OUTPLL( pllPLL_PWRMGT_CNTL, pll_pwrmgt_cntl);
 843
 844         clk_pwrmgt_cntl  = INPLL( pllCLK_PWRMGT_CNTL);
 845
 846         clk_pwrmgt_cntl &= ~(   CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF|
 847                                 CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF|
 848                                 CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF|
 849                                 CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF|
 850                                 CLK_PWRMGT_CNTL__MCLK_TURNOFF|
 851                                 CLK_PWRMGT_CNTL__SCLK_TURNOFF|
 852                                 CLK_PWRMGT_CNTL__PCLK_TURNOFF|
 853                                 CLK_PWRMGT_CNTL__P2CLK_TURNOFF|
 854                                 CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF|
 855                                 CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN|
 856                                 CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE|
 857                                 CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK|
 858                                 CLK_PWRMGT_CNTL__CG_NO1_DEBUG_MASK
 859                         );
 860
 861         clk_pwrmgt_cntl |= CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN
 862                 | CLK_PWRMGT_CNTL__DISP_PM;
 863
 864         OUTPLL( pllCLK_PWRMGT_CNTL, clk_pwrmgt_cntl);
 865
 866         clk_pin_cntl = INPLL( pllCLK_PIN_CNTL);
 867
 868         clk_pin_cntl &= ~CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND;
 869
 870         /* because both INPLL and OUTPLL take the same lock, that's why. */
 871         tmp = INPLL( pllMCLK_MISC) | MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND;
 872         OUTPLL( pllMCLK_MISC, tmp);
 873
 874         /* BUS_CNTL1__MOBILE_PLATORM_SEL setting is northbridge chipset
 875          * and radeon chip dependent. Thus we only enable it on Mac for
 876          * now (until we get more info on how to compute the correct
 877          * value for various X86 bridges).
 878          */
 879
 880 #ifdef CONFIG_PPC_PMAC
 881         /* AGP PLL control */
 882         if (rinfo->family <= CHIP_FAMILY_RV280) {
 883                 OUTREG(BUS_CNTL1, INREG(BUS_CNTL1) |  BUS_CNTL1__AGPCLK_VALID);
 884
 885                 OUTREG(BUS_CNTL1,
 886                        (INREG(BUS_CNTL1) & ~BUS_CNTL1__MOBILE_PLATFORM_SEL_MASK)
 887                        | (2<<BUS_CNTL1__MOBILE_PLATFORM_SEL__SHIFT));   // 440BX
 888         } else {
 889                 OUTREG(BUS_CNTL1, INREG(BUS_CNTL1));
 890                 OUTREG(BUS_CNTL1, (INREG(BUS_CNTL1) & ~0x4000) | 0x8000);
 891         }
 892 #endif
 893
 894         OUTREG(CRTC_OFFSET_CNTL, (INREG(CRTC_OFFSET_CNTL)
 895                                   & ~CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN));
 896
 897         clk_pin_cntl &= ~CLK_PIN_CNTL__CG_CLK_TO_OUTPIN;
 898         clk_pin_cntl |= CLK_PIN_CNTL__XTALIN_ALWAYS_ONb;
 899         OUTPLL( pllCLK_PIN_CNTL, clk_pin_cntl);
 900
 901         /* Solano2M */
 902         OUTREG(AGP_CNTL,
 903                 (INREG(AGP_CNTL) & ~(AGP_CNTL__MAX_IDLE_CLK_MASK))
 904                 | (0x20<<AGP_CNTL__MAX_IDLE_CLK__SHIFT));
 905
 906         /* ACPI mode */
 907         /* because both INPLL and OUTPLL take the same lock, that's why. */
 908         tmp = INPLL( pllPLL_PWRMGT_CNTL) & ~PLL_PWRMGT_CNTL__PM_MODE_SEL;
 909         OUTPLL( pllPLL_PWRMGT_CNTL, tmp);
 910
 911
 912         disp_mis_cntl = INREG(DISP_MISC_CNTL);
 913
 914         disp_mis_cntl &= ~(     DISP_MISC_CNTL__SOFT_RESET_GRPH_PP |
 915                                 DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP |
 916                                 DISP_MISC_CNTL__SOFT_RESET_OV0_PP |
 917                                 DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK|
 918                                 DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK|
 919                                 DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK|
 920                                 DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP|
 921                                 DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK|
 922                                 DISP_MISC_CNTL__SOFT_RESET_LVDS|
 923                                 DISP_MISC_CNTL__SOFT_RESET_TMDS|
 924                                 DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS|
 925                                 DISP_MISC_CNTL__SOFT_RESET_TV);
 926
 927         OUTREG(DISP_MISC_CNTL, disp_mis_cntl);
 928
 929         disp_pwr_man = INREG(DISP_PWR_MAN);
 930
 931         disp_pwr_man &= ~(      DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN   |
 932                                 DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN |
 933                                 DISP_PWR_MAN__DISP_PWR_MAN_DPMS_MASK|
 934                                 DISP_PWR_MAN__DISP_D3_RST|
 935                                 DISP_PWR_MAN__DISP_D3_REG_RST
 936                                 );
 937
 938         disp_pwr_man |= DISP_PWR_MAN__DISP_D3_GRPH_RST|
 939                                         DISP_PWR_MAN__DISP_D3_SUBPIC_RST|
 940                                         DISP_PWR_MAN__DISP_D3_OV0_RST|
 941                                         DISP_PWR_MAN__DISP_D1D2_GRPH_RST|
 942                                         DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST|
 943                                         DISP_PWR_MAN__DISP_D1D2_OV0_RST|
 944                                         DISP_PWR_MAN__DIG_TMDS_ENABLE_RST|
 945                                         DISP_PWR_MAN__TV_ENABLE_RST|
 946 //                                      DISP_PWR_MAN__AUTO_PWRUP_EN|
 947                                         0;
 948
 949         OUTREG(DISP_PWR_MAN, disp_pwr_man);
 950
 951         clk_pwrmgt_cntl = INPLL( pllCLK_PWRMGT_CNTL);
 952         pll_pwrmgt_cntl = INPLL( pllPLL_PWRMGT_CNTL) ;
 953         clk_pin_cntl    = INPLL( pllCLK_PIN_CNTL);
 954         disp_pwr_man    = INREG(DISP_PWR_MAN);
 955
 956
 957         /* D2 */
 958         clk_pwrmgt_cntl |= CLK_PWRMGT_CNTL__DISP_PM;
 959         pll_pwrmgt_cntl |= PLL_PWRMGT_CNTL__MOBILE_SU | PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK;
 960         clk_pin_cntl    |= CLK_PIN_CNTL__XTALIN_ALWAYS_ONb;
 961         disp_pwr_man    &= ~(DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN_MASK
 962                              | DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN_MASK);
 963
 964         OUTPLL( pllCLK_PWRMGT_CNTL, clk_pwrmgt_cntl);
 965         OUTPLL( pllPLL_PWRMGT_CNTL, pll_pwrmgt_cntl);
 966         OUTPLL( pllCLK_PIN_CNTL, clk_pin_cntl);
 967         OUTREG(DISP_PWR_MAN, disp_pwr_man);
 968
 969         /* disable display request & disable display */
 970         OUTREG( CRTC_GEN_CNTL, (INREG( CRTC_GEN_CNTL) & ~CRTC_GEN_CNTL__CRTC_EN)
 971                 | CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B);
 972         OUTREG( CRTC2_GEN_CNTL, (INREG( CRTC2_GEN_CNTL) & ~CRTC2_GEN_CNTL__CRTC2_EN)
 973                 | CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B);
 974
 975         mdelay(17);
 976
 977 }
 978
 979 static void radeon_pm_yclk_mclk_sync(struct radeonfb_info *rinfo)
 980 {
 981         u32 mc_chp_io_cntl_a1, mc_chp_io_cntl_b1;
 982
 983         mc_chp_io_cntl_a1 = INMC( rinfo, ixMC_CHP_IO_CNTL_A1)
 984                 & ~MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK;
 985         mc_chp_io_cntl_b1 = INMC( rinfo, ixMC_CHP_IO_CNTL_B1)
 986                 & ~MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK;
 987
 988         OUTMC( rinfo, ixMC_CHP_IO_CNTL_A1, mc_chp_io_cntl_a1
 989                | (1<<MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT));
 990         OUTMC( rinfo, ixMC_CHP_IO_CNTL_B1, mc_chp_io_cntl_b1
 991                | (1<<MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT));
 992
 993         OUTMC( rinfo, ixMC_CHP_IO_CNTL_A1, mc_chp_io_cntl_a1);
 994         OUTMC( rinfo, ixMC_CHP_IO_CNTL_B1, mc_chp_io_cntl_b1);
 995
 996         mdelay( 1);
 997 }
 998
 999 static void radeon_pm_yclk_mclk_sync_m10(struct radeonfb_info *rinfo)
1000 {
1001         u32 mc_chp_io_cntl_a1, mc_chp_io_cntl_b1;
1002
1003         mc_chp_io_cntl_a1 = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_A1)
1004                 & ~MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK;
1005         mc_chp_io_cntl_b1 = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_B1)
1006                 & ~MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK;
1007
1008         OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_A1,
1009                mc_chp_io_cntl_a1 | (1<<MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT));
1010         OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_B1,
1011                mc_chp_io_cntl_b1 | (1<<MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT));
1012
1013         OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_A1, mc_chp_io_cntl_a1);
1014         OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_B1, mc_chp_io_cntl_b1);
1015
1016         mdelay( 1);
1017 }
1018
1019 static void radeon_pm_program_mode_reg(struct radeonfb_info *rinfo, u16 value,
1020                                        u8 delay_required)
1021 {
1022         u32 mem_sdram_mode;
1023
1024         mem_sdram_mode  = INREG( MEM_SDRAM_MODE_REG);
1025
1026         mem_sdram_mode &= ~MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK;
1027         mem_sdram_mode |= (value<<MEM_SDRAM_MODE_REG__MEM_MODE_REG__SHIFT)
1028                 | MEM_SDRAM_MODE_REG__MEM_CFG_TYPE;
1029         OUTREG( MEM_SDRAM_MODE_REG, mem_sdram_mode);
1030         if (delay_required >= 2)
1031                 mdelay(1);
1032
1033         mem_sdram_mode |=  MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET;
1034         OUTREG( MEM_SDRAM_MODE_REG, mem_sdram_mode);
1035         if (delay_required >= 2)
1036                 mdelay(1);
1037
1038         mem_sdram_mode &= ~MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET;
1039         OUTREG( MEM_SDRAM_MODE_REG, mem_sdram_mode);
1040         if (delay_required >= 2)
1041                 mdelay(1);
1042
1043         if (delay_required) {
1044                 do {
1045                         if (delay_required >= 2)
1046                                 mdelay(1);
1047                 } while ((INREG(MC_STATUS)
1048                           & (MC_STATUS__MEM_PWRUP_COMPL_A |
1049                              MC_STATUS__MEM_PWRUP_COMPL_B)) == 0);
1050         }
1051 }
1052
1053 static void radeon_pm_m10_program_mode_wait(struct radeonfb_info *rinfo)
1054 {
1055         int cnt;
1056
1057         for (cnt = 0; cnt < 100; ++cnt) {
1058                 mdelay(1);
1059                 if (INREG(MC_STATUS) & (MC_STATUS__MEM_PWRUP_COMPL_A
1060                                         | MC_STATUS__MEM_PWRUP_COMPL_B))
1061                         break;
1062         }
1063 }
1064
1065
1066 static void radeon_pm_enable_dll(struct radeonfb_info *rinfo)
1067 {
1068 #define DLL_RESET_DELAY         5
1069 #define DLL_SLEEP_DELAY         1
1070
1071         u32 cko = INPLL(pllMDLL_CKO)   | MDLL_CKO__MCKOA_SLEEP
1072                 | MDLL_CKO__MCKOA_RESET;
1073         u32 cka = INPLL(pllMDLL_RDCKA) | MDLL_RDCKA__MRDCKA0_SLEEP
1074                 | MDLL_RDCKA__MRDCKA1_SLEEP | MDLL_RDCKA__MRDCKA0_RESET
1075                 | MDLL_RDCKA__MRDCKA1_RESET;
1076         u32 ckb = INPLL(pllMDLL_RDCKB) | MDLL_RDCKB__MRDCKB0_SLEEP
1077                 | MDLL_RDCKB__MRDCKB1_SLEEP | MDLL_RDCKB__MRDCKB0_RESET
1078                 | MDLL_RDCKB__MRDCKB1_RESET;
1079
1080         /* Setting up the DLL range for write */
1081         OUTPLL(pllMDLL_CKO,     cko);
1082         OUTPLL(pllMDLL_RDCKA,   cka);
1083         OUTPLL(pllMDLL_RDCKB,   ckb);
1084
1085         mdelay(DLL_RESET_DELAY*2);
1086
1087         cko &= ~(MDLL_CKO__MCKOA_SLEEP | MDLL_CKO__MCKOB_SLEEP);
1088         OUTPLL(pllMDLL_CKO, cko);
1089         mdelay(DLL_SLEEP_DELAY);
1090         cko &= ~(MDLL_CKO__MCKOA_RESET | MDLL_CKO__MCKOB_RESET);
1091         OUTPLL(pllMDLL_CKO, cko);
1092         mdelay(DLL_RESET_DELAY);
1093
1094         cka &= ~(MDLL_RDCKA__MRDCKA0_SLEEP | MDLL_RDCKA__MRDCKA1_SLEEP);
1095         OUTPLL(pllMDLL_RDCKA, cka);
1096         mdelay(DLL_SLEEP_DELAY);
1097         cka &= ~(MDLL_RDCKA__MRDCKA0_RESET | MDLL_RDCKA__MRDCKA1_RESET);
1098         OUTPLL(pllMDLL_RDCKA, cka);
1099         mdelay(DLL_RESET_DELAY);
1100
1101         ckb &= ~(MDLL_RDCKB__MRDCKB0_SLEEP | MDLL_RDCKB__MRDCKB1_SLEEP);
1102         OUTPLL(pllMDLL_RDCKB, ckb);
1103         mdelay(DLL_SLEEP_DELAY);
1104         ckb &= ~(MDLL_RDCKB__MRDCKB0_RESET | MDLL_RDCKB__MRDCKB1_RESET);
1105         OUTPLL(pllMDLL_RDCKB, ckb);
1106         mdelay(DLL_RESET_DELAY);
1107
1108
1109 #undef DLL_RESET_DELAY
1110 #undef DLL_SLEEP_DELAY
1111 }
1112
1113 static void radeon_pm_enable_dll_m10(struct radeonfb_info *rinfo)
1114 {
1115         u32 dll_value;
1116         u32 dll_sleep_mask = 0;
1117         u32 dll_reset_mask = 0;
1118         u32 mc;
1119
1120 #define DLL_RESET_DELAY         5
1121 #define DLL_SLEEP_DELAY         1
1122
1123         OUTMC(rinfo, ixR300_MC_DLL_CNTL, rinfo->save_regs[70]);
1124         mc = INREG(MC_CNTL);
1125         /* Check which channels are enabled */
1126         switch (mc & 0x3) {
1127         case 1:
1128                 if (mc & 0x4)
1129                         break;
1130         case 2:
1131                 dll_sleep_mask |= MDLL_R300_RDCK__MRDCKB_SLEEP;
1132                 dll_reset_mask |= MDLL_R300_RDCK__MRDCKB_RESET;
1133         case 0:
1134                 dll_sleep_mask |= MDLL_R300_RDCK__MRDCKA_SLEEP;
1135                 dll_reset_mask |= MDLL_R300_RDCK__MRDCKA_RESET;
1136         }
1137         switch (mc & 0x3) {
1138         case 1:
1139                 if (!(mc & 0x4))
1140                         break;
1141         case 2:
1142                 dll_sleep_mask |= MDLL_R300_RDCK__MRDCKD_SLEEP;
1143                 dll_reset_mask |= MDLL_R300_RDCK__MRDCKD_RESET;
1144                 dll_sleep_mask |= MDLL_R300_RDCK__MRDCKC_SLEEP;
1145                 dll_reset_mask |= MDLL_R300_RDCK__MRDCKC_RESET;
1146         }
1147
1148         dll_value = INPLL(pllMDLL_RDCKA);
1149
1150         /* Power Up */
1151         dll_value &= ~(dll_sleep_mask);
1152         OUTPLL(pllMDLL_RDCKA, dll_value);
1153         mdelay( DLL_SLEEP_DELAY);
1154
1155         dll_value &= ~(dll_reset_mask);
1156         OUTPLL(pllMDLL_RDCKA, dll_value);
1157         mdelay( DLL_RESET_DELAY);
1158
1159 #undef DLL_RESET_DELAY
1160 #undef DLL_SLEEP_DELAY
1161 }
1162
1163
1164 static void radeon_pm_full_reset_sdram(struct radeonfb_info *rinfo)
1165 {
1166         u32 crtcGenCntl, crtcGenCntl2, memRefreshCntl, crtc_more_cntl,
1167                 fp_gen_cntl, fp2_gen_cntl;
1168
1169         crtcGenCntl  = INREG( CRTC_GEN_CNTL);
1170         crtcGenCntl2 = INREG( CRTC2_GEN_CNTL);
1171
1172         crtc_more_cntl  = INREG( CRTC_MORE_CNTL);
1173         fp_gen_cntl     = INREG( FP_GEN_CNTL);
1174         fp2_gen_cntl    = INREG( FP2_GEN_CNTL);
1175
1176
1177         OUTREG( CRTC_MORE_CNTL, 0);
1178         OUTREG( FP_GEN_CNTL, 0);
1179         OUTREG( FP2_GEN_CNTL,0);
1180
1181         OUTREG( CRTC_GEN_CNTL,  (crtcGenCntl | CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B) );
1182         OUTREG( CRTC2_GEN_CNTL, (crtcGenCntl2 | CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B) );
1183
1184         /* This is the code for the Aluminium PowerBooks M10 / iBooks M11 */
1185         if (rinfo->family == CHIP_FAMILY_RV350) {
1186                 u32 sdram_mode_reg = rinfo->save_regs[35];
1187                 static u32 default_mrtable[] =
1188                         { 0x21320032,
1189                           0x21321000, 0xa1321000, 0x21321000, 0xffffffff,
1190                           0x21320032, 0xa1320032, 0x21320032, 0xffffffff,
1191                           0x21321002, 0xa1321002, 0x21321002, 0xffffffff,
1192                           0x21320132, 0xa1320132, 0x21320132, 0xffffffff,
1193                           0x21320032, 0xa1320032, 0x21320032, 0xffffffff,
1194                           0x31320032 };
1195
1196                 u32 *mrtable = default_mrtable;
1197                 int i, mrtable_size = ARRAY_SIZE(default_mrtable);
1198
1199                 mdelay(30);
1200
1201                 /* Disable refresh */
1202                 memRefreshCntl  = INREG( MEM_REFRESH_CNTL)
1203                         & ~MEM_REFRESH_CNTL__MEM_REFRESH_DIS;
1204                 OUTREG( MEM_REFRESH_CNTL, memRefreshCntl
1205                         | MEM_REFRESH_CNTL__MEM_REFRESH_DIS);
1206
1207                 /* Configure and enable M & SPLLs */
1208                 radeon_pm_enable_dll_m10(rinfo);
1209                 radeon_pm_yclk_mclk_sync_m10(rinfo);
1210
1211 #ifdef CONFIG_PPC_OF
1212                 if (rinfo->of_node != NULL) {
1213                         int size;
1214
1215                         mrtable = (u32 *)get_property(rinfo->of_node, "ATY,MRT", &size);
1216                         if (mrtable)
1217                                 mrtable_size = size >> 2;
1218                         else
1219                                 mrtable = default_mrtable;
1220                 }
1221 #endif /* CONFIG_PPC_OF */
1222
1223                 /* Program the SDRAM */
1224                 sdram_mode_reg = mrtable[0];
1225                 OUTREG(MEM_SDRAM_MODE_REG, sdram_mode_reg);
1226                 for (i = 0; i < mrtable_size; i++) {
1227                         if (mrtable[i] == 0xffffffffu)
1228                                 radeon_pm_m10_program_mode_wait(rinfo);
1229                         else {
1230                                 sdram_mode_reg &= ~(MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK
1231                                                     | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE
1232                                                     | MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET);
1233                                 sdram_mode_reg |= mrtable[i];
1234
1235                                 OUTREG(MEM_SDRAM_MODE_REG, sdram_mode_reg);
1236                                 mdelay(1);
1237                         }
1238                 }
1239
1240                 /* Restore memory refresh */
1241                 OUTREG(MEM_REFRESH_CNTL, memRefreshCntl);
1242                 mdelay(30);
1243
1244         }
1245         /* Here come the desktop RV200 "QW" card */
1246         else if (!rinfo->is_mobility && rinfo->family == CHIP_FAMILY_RV200) {
1247                 /* Disable refresh */
1248                 memRefreshCntl  = INREG( MEM_REFRESH_CNTL)
1249                         & ~MEM_REFRESH_CNTL__MEM_REFRESH_DIS;
1250                 OUTREG(MEM_REFRESH_CNTL, memRefreshCntl
1251                        | MEM_REFRESH_CNTL__MEM_REFRESH_DIS);
1252                 mdelay(30);
1253
1254                 /* Reset memory */
1255                 OUTREG(MEM_SDRAM_MODE_REG,
1256                        INREG( MEM_SDRAM_MODE_REG) & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1257
1258                 radeon_pm_program_mode_reg(rinfo, 0x2002, 2);
1259                 radeon_pm_program_mode_reg(rinfo, 0x0132, 2);
1260                 radeon_pm_program_mode_reg(rinfo, 0x0032, 2);
1261
1262                 OUTREG(MEM_SDRAM_MODE_REG,
1263                        INREG(MEM_SDRAM_MODE_REG) | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1264
1265                 OUTREG( MEM_REFRESH_CNTL,       memRefreshCntl);
1266
1267         }
1268         /* The M6 */
1269         else if (rinfo->is_mobility && rinfo->family == CHIP_FAMILY_RV100) {
1270                 /* Disable refresh */
1271                 memRefreshCntl = INREG(EXT_MEM_CNTL) & ~(1 << 20);
1272                 OUTREG( EXT_MEM_CNTL, memRefreshCntl | (1 << 20));
1273
1274                 /* Reset memory */
1275                 OUTREG( MEM_SDRAM_MODE_REG,
1276                         INREG( MEM_SDRAM_MODE_REG)
1277                         & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1278
1279                 /* DLL */
1280                 radeon_pm_enable_dll(rinfo);
1281
1282                 /* MLCK / YCLK sync */
1283                 radeon_pm_yclk_mclk_sync(rinfo);
1284
1285                 /* Program Mode Register */
1286                 radeon_pm_program_mode_reg(rinfo, 0x2000, 1);
1287                 radeon_pm_program_mode_reg(rinfo, 0x2001, 1);
1288                 radeon_pm_program_mode_reg(rinfo, 0x2002, 1);
1289                 radeon_pm_program_mode_reg(rinfo, 0x0132, 1);
1290                 radeon_pm_program_mode_reg(rinfo, 0x0032, 1);
1291
1292                 /* Complete & re-enable refresh */
1293                 OUTREG( MEM_SDRAM_MODE_REG,
1294                         INREG( MEM_SDRAM_MODE_REG) | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1295
1296                 OUTREG(EXT_MEM_CNTL, memRefreshCntl);
1297         }
1298         /* And finally, the M7..M9 models, including M9+ (RV280) */
1299         else if (rinfo->is_mobility) {
1300
1301                 /* Disable refresh */
1302                 memRefreshCntl  = INREG( MEM_REFRESH_CNTL)
1303                         & ~MEM_REFRESH_CNTL__MEM_REFRESH_DIS;
1304                 OUTREG( MEM_REFRESH_CNTL, memRefreshCntl
1305                         | MEM_REFRESH_CNTL__MEM_REFRESH_DIS);
1306
1307                 /* Reset memory */
1308                 OUTREG( MEM_SDRAM_MODE_REG,
1309                         INREG( MEM_SDRAM_MODE_REG)
1310                         & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1311
1312                 /* DLL */
1313                 radeon_pm_enable_dll(rinfo);
1314
1315                 /* MLCK / YCLK sync */
1316                 radeon_pm_yclk_mclk_sync(rinfo);
1317
1318                 /* M6, M7 and M9 so far ... */
1319                 if (rinfo->family <= CHIP_FAMILY_RV250) {
1320                         radeon_pm_program_mode_reg(rinfo, 0x2000, 1);
1321                         radeon_pm_program_mode_reg(rinfo, 0x2001, 1);
1322                         radeon_pm_program_mode_reg(rinfo, 0x2002, 1);
1323                         radeon_pm_program_mode_reg(rinfo, 0x0132, 1);
1324                         radeon_pm_program_mode_reg(rinfo, 0x0032, 1);
1325                 }
1326                 /* M9+ (iBook G4) */
1327                 else if (rinfo->family == CHIP_FAMILY_RV280) {
1328                         radeon_pm_program_mode_reg(rinfo, 0x2000, 1);
1329                         radeon_pm_program_mode_reg(rinfo, 0x0132, 1);
1330                         radeon_pm_program_mode_reg(rinfo, 0x0032, 1);
1331                 }
1332
1333                 /* Complete & re-enable refresh */
1334                 OUTREG( MEM_SDRAM_MODE_REG,
1335                         INREG( MEM_SDRAM_MODE_REG) | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1336
1337                 OUTREG( MEM_REFRESH_CNTL,       memRefreshCntl);
1338         }
1339
1340         OUTREG( CRTC_GEN_CNTL,          crtcGenCntl);
1341         OUTREG( CRTC2_GEN_CNTL,         crtcGenCntl2);
1342         OUTREG( FP_GEN_CNTL,            fp_gen_cntl);
1343         OUTREG( FP2_GEN_CNTL,           fp2_gen_cntl);
1344
1345         OUTREG( CRTC_MORE_CNTL,         crtc_more_cntl);
1346
1347         mdelay( 15);
1348 }
1349
1350 static void radeon_pm_reset_pad_ctlr_strength(struct radeonfb_info *rinfo)
1351 {
1352         u32 tmp, tmp2;
1353         int i,j;
1354
1355         /* Reset the PAD_CTLR_STRENGTH & wait for it to be stable */
1356         INREG(PAD_CTLR_STRENGTH);
1357         OUTREG(PAD_CTLR_STRENGTH, INREG(PAD_CTLR_STRENGTH) & ~PAD_MANUAL_OVERRIDE);
1358         tmp = INREG(PAD_CTLR_STRENGTH);
1359         for (i = j = 0; i < 65; ++i) {
1360                 mdelay(1);
1361                 tmp2 = INREG(PAD_CTLR_STRENGTH);
1362                 if (tmp != tmp2) {
1363                         tmp = tmp2;
1364                         i = 0;
1365                         j++;
1366                         if (j > 10) {
1367                                 printk(KERN_WARNING "radeon: PAD_CTLR_STRENGTH doesn't "
1368                                        "stabilize !\n");
1369                                 break;
1370                         }
1371                 }
1372         }
1373 }
1374
1375 static void radeon_pm_all_ppls_off(struct radeonfb_info *rinfo)
1376 {
1377         u32 tmp;
1378
1379         tmp = INPLL(pllPPLL_CNTL);
1380         OUTPLL(pllPPLL_CNTL, tmp | 0x3);
1381         tmp = INPLL(pllP2PLL_CNTL);
1382         OUTPLL(pllP2PLL_CNTL, tmp | 0x3);
1383         tmp = INPLL(pllSPLL_CNTL);
1384         OUTPLL(pllSPLL_CNTL, tmp | 0x3);
1385         tmp = INPLL(pllMPLL_CNTL);
1386         OUTPLL(pllMPLL_CNTL, tmp | 0x3);
1387 }
1388
1389 static void radeon_pm_start_mclk_sclk(struct radeonfb_info *rinfo)
1390 {
1391         u32 tmp;
1392
1393         /* Switch SPLL to PCI source */
1394         tmp = INPLL(pllSCLK_CNTL);
1395         OUTPLL(pllSCLK_CNTL, tmp & ~SCLK_CNTL__SCLK_SRC_SEL_MASK);
1396
1397         /* Reconfigure SPLL charge pump, VCO gain, duty cycle */
1398         tmp = INPLL(pllSPLL_CNTL);
1399         OUTREG8(CLOCK_CNTL_INDEX, pllSPLL_CNTL + PLL_WR_EN);
1400         radeon_pll_errata_after_index(rinfo);
1401         OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
1402         radeon_pll_errata_after_data(rinfo);
1403
1404         /* Set SPLL feedback divider */
1405         tmp = INPLL(pllM_SPLL_REF_FB_DIV);
1406         tmp = (tmp & 0xff00fffful) | (rinfo->save_regs[77] & 0x00ff0000ul);
1407         OUTPLL(pllM_SPLL_REF_FB_DIV, tmp);
1408
1409         /* Power up SPLL */
1410         tmp = INPLL(pllSPLL_CNTL);
1411         OUTPLL(pllSPLL_CNTL, tmp & ~1);
1412         (void)INPLL(pllSPLL_CNTL);
1413
1414         mdelay(10);
1415
1416         /* Release SPLL reset */
1417         tmp = INPLL(pllSPLL_CNTL);
1418         OUTPLL(pllSPLL_CNTL, tmp & ~0x2);
1419         (void)INPLL(pllSPLL_CNTL);
1420
1421         mdelay(10);
1422
1423         /* Select SCLK source  */
1424         tmp = INPLL(pllSCLK_CNTL);
1425         tmp &= ~SCLK_CNTL__SCLK_SRC_SEL_MASK;
1426         tmp |= rinfo->save_regs[3] & SCLK_CNTL__SCLK_SRC_SEL_MASK;
1427         OUTPLL(pllSCLK_CNTL, tmp);
1428         (void)INPLL(pllSCLK_CNTL);
1429
1430         mdelay(10);
1431
1432         /* Reconfigure MPLL charge pump, VCO gain, duty cycle */
1433         tmp = INPLL(pllMPLL_CNTL);
1434         OUTREG8(CLOCK_CNTL_INDEX, pllMPLL_CNTL + PLL_WR_EN);
1435         radeon_pll_errata_after_index(rinfo);
1436         OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
1437         radeon_pll_errata_after_data(rinfo);
1438
1439         /* Set MPLL feedback divider */
1440         tmp = INPLL(pllM_SPLL_REF_FB_DIV);
1441         tmp = (tmp & 0xffff00fful) | (rinfo->save_regs[77] & 0x0000ff00ul);
1442
1443         OUTPLL(pllM_SPLL_REF_FB_DIV, tmp);
1444         /* Power up MPLL */
1445         tmp = INPLL(pllMPLL_CNTL);
1446         OUTPLL(pllMPLL_CNTL, tmp & ~0x2);
1447         (void)INPLL(pllMPLL_CNTL);
1448
1449         mdelay(10);
1450
1451         /* Un-reset MPLL */
1452         tmp = INPLL(pllMPLL_CNTL);
1453         OUTPLL(pllMPLL_CNTL, tmp & ~0x1);
1454         (void)INPLL(pllMPLL_CNTL);
1455
1456         mdelay(10);
1457
1458         /* Select source for MCLK */
1459         tmp = INPLL(pllMCLK_CNTL);
1460         tmp |= rinfo->save_regs[2] & 0xffff;
1461         OUTPLL(pllMCLK_CNTL, tmp);
1462         (void)INPLL(pllMCLK_CNTL);
1463
1464         mdelay(10);
1465 }
1466
1467 static void radeon_pm_m10_disable_spread_spectrum(struct radeonfb_info *rinfo)
1468 {
1469         u32 r2ec;
1470
1471         /* GACK ! I though we didn't have a DDA on Radeon's anymore
1472          * here we rewrite with the same value, ... I suppose we clear
1473          * some bits that are already clear ? Or maybe this 0x2ec
1474          * register is something new ?
1475          */
1476         mdelay(20);
1477         r2ec = INREG(VGA_DDA_ON_OFF);
1478         OUTREG(VGA_DDA_ON_OFF, r2ec);
1479         mdelay(1);
1480
1481         /* Spread spectrum PLLL off */
1482         OUTPLL(pllSSPLL_CNTL, 0xbf03);
1483
1484         /* Spread spectrum disabled */
1485         OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90] & ~3);
1486
1487         /* The trace shows read & rewrite of LVDS_PLL_CNTL here with same
1488          * value, not sure what for...
1489          */
1490
1491         r2ec |= 0x3f0;
1492         OUTREG(VGA_DDA_ON_OFF, r2ec);
1493         mdelay(1);
1494 }
1495
1496 static void radeon_pm_m10_enable_lvds_spread_spectrum(struct radeonfb_info *rinfo)
1497 {
1498         u32 r2ec, tmp;
1499
1500         /* GACK (bis) ! I though we didn't have a DDA on Radeon's anymore
1501          * here we rewrite with the same value, ... I suppose we clear/set
1502          * some bits that are already clear/set ?
1503          */
1504         r2ec = INREG(VGA_DDA_ON_OFF);
1505         OUTREG(VGA_DDA_ON_OFF, r2ec);
1506         mdelay(1);
1507
1508         /* Enable spread spectrum */
1509         OUTPLL(pllSSPLL_CNTL, rinfo->save_regs[43] | 3);
1510         mdelay(3);
1511
1512         OUTPLL(pllSSPLL_REF_DIV, rinfo->save_regs[44]);
1513         OUTPLL(pllSSPLL_DIV_0, rinfo->save_regs[45]);
1514         tmp = INPLL(pllSSPLL_CNTL);
1515         OUTPLL(pllSSPLL_CNTL, tmp & ~0x2);
1516         mdelay(6);
1517         tmp = INPLL(pllSSPLL_CNTL);
1518         OUTPLL(pllSSPLL_CNTL, tmp & ~0x1);
1519         mdelay(5);
1520
1521         OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90]);
1522
1523         r2ec |= 8;
1524         OUTREG(VGA_DDA_ON_OFF, r2ec);
1525         mdelay(20);
1526
1527         /* Enable LVDS interface */
1528         tmp = INREG(LVDS_GEN_CNTL);
1529         OUTREG(LVDS_GEN_CNTL, tmp | LVDS_EN);
1530
1531         /* Enable LVDS_PLL */
1532         tmp = INREG(LVDS_PLL_CNTL);
1533         tmp &= ~0x30000;
1534         tmp |= 0x10000;
1535         OUTREG(LVDS_PLL_CNTL, tmp);
1536
1537         OUTPLL(pllSCLK_MORE_CNTL, rinfo->save_regs[34]);
1538         OUTPLL(pllSS_TST_CNTL, rinfo->save_regs[91]);
1539
1540         /* The trace reads that one here, waiting for something to settle down ? */
1541         INREG(RBBM_STATUS);
1542
1543         /* Ugh ? SS_TST_DEC is supposed to be a read register in the
1544          * R300 register spec at least...
1545          */
1546         tmp = INPLL(pllSS_TST_CNTL);
1547         tmp |= 0x00400000;
1548         OUTPLL(pllSS_TST_CNTL, tmp);
1549 }
1550
1551 static void radeon_pm_restore_pixel_pll(struct radeonfb_info *rinfo)
1552 {
1553         u32 tmp;
1554
1555         OUTREG8(CLOCK_CNTL_INDEX, pllHTOTAL_CNTL + PLL_WR_EN);
1556         radeon_pll_errata_after_index(rinfo);
1557         OUTREG8(CLOCK_CNTL_DATA, 0);
1558         radeon_pll_errata_after_data(rinfo);
1559
1560         tmp = INPLL(pllVCLK_ECP_CNTL);
1561         OUTPLL(pllVCLK_ECP_CNTL, tmp | 0x80);
1562         mdelay(5);
1563
1564         tmp = INPLL(pllPPLL_REF_DIV);
1565         tmp = (tmp & ~PPLL_REF_DIV_MASK) | rinfo->pll.ref_div;
1566         OUTPLL(pllPPLL_REF_DIV, tmp);
1567         INPLL(pllPPLL_REF_DIV);
1568
1569         /* Reconfigure SPLL charge pump, VCO gain, duty cycle,
1570          * probably useless since we already did it ...
1571          */
1572         tmp = INPLL(pllPPLL_CNTL);
1573         OUTREG8(CLOCK_CNTL_INDEX, pllSPLL_CNTL + PLL_WR_EN);
1574         radeon_pll_errata_after_index(rinfo);
1575         OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
1576         radeon_pll_errata_after_data(rinfo);
1577
1578         /* Restore our "reference" PPLL divider set by firmware
1579          * according to proper spread spectrum calculations
1580          */
1581         OUTPLL(pllPPLL_DIV_0, rinfo->save_regs[92]);
1582
1583         tmp = INPLL(pllPPLL_CNTL);
1584         OUTPLL(pllPPLL_CNTL, tmp & ~0x2);
1585         mdelay(5);
1586
1587         tmp = INPLL(pllPPLL_CNTL);
1588         OUTPLL(pllPPLL_CNTL, tmp & ~0x1);
1589         mdelay(5);
1590
1591         tmp = INPLL(pllVCLK_ECP_CNTL);
1592         OUTPLL(pllVCLK_ECP_CNTL, tmp | 3);
1593         mdelay(5);
1594
1595         tmp = INPLL(pllVCLK_ECP_CNTL);
1596         OUTPLL(pllVCLK_ECP_CNTL, tmp | 3);
1597         mdelay(5);
1598
1599         /* Switch pixel clock to firmware default div 0 */
1600         OUTREG8(CLOCK_CNTL_INDEX+1, 0);
1601         radeon_pll_errata_after_index(rinfo);
1602         radeon_pll_errata_after_data(rinfo);
1603 }
1604
1605 static void radeon_pm_m10_reconfigure_mc(struct radeonfb_info *rinfo)
1606 {
1607         OUTREG(MC_CNTL, rinfo->save_regs[46]);
1608         OUTREG(MC_INIT_GFX_LAT_TIMER, rinfo->save_regs[47]);
1609         OUTREG(MC_INIT_MISC_LAT_TIMER, rinfo->save_regs[48]);
1610         OUTREG(MEM_SDRAM_MODE_REG,
1611                rinfo->save_regs[35] & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1612         OUTREG(MC_TIMING_CNTL, rinfo->save_regs[49]);
1613         OUTREG(MEM_REFRESH_CNTL, rinfo->save_regs[42]);
1614         OUTREG(MC_READ_CNTL_AB, rinfo->save_regs[50]);
1615         OUTREG(MC_CHIP_IO_OE_CNTL_AB, rinfo->save_regs[52]);
1616         OUTREG(MC_IOPAD_CNTL, rinfo->save_regs[51]);
1617         OUTREG(MC_DEBUG, rinfo->save_regs[53]);
1618
1619         OUTMC(rinfo, ixR300_MC_MC_INIT_WR_LAT_TIMER, rinfo->save_regs[58]);
1620         OUTMC(rinfo, ixR300_MC_IMP_CNTL, rinfo->save_regs[59]);
1621         OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_C0, rinfo->save_regs[60]);
1622         OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_C1, rinfo->save_regs[61]);
1623         OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_D0, rinfo->save_regs[62]);
1624         OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_D1, rinfo->save_regs[63]);
1625         OUTMC(rinfo, ixR300_MC_BIST_CNTL_3, rinfo->save_regs[64]);
1626         OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_A0, rinfo->save_regs[65]);
1627         OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_A1, rinfo->save_regs[66]);
1628         OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_B0, rinfo->save_regs[67]);
1629         OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_B1, rinfo->save_regs[68]);
1630         OUTMC(rinfo, ixR300_MC_DEBUG_CNTL, rinfo->save_regs[69]);
1631         OUTMC(rinfo, ixR300_MC_DLL_CNTL, rinfo->save_regs[70]);
1632         OUTMC(rinfo, ixR300_MC_IMP_CNTL_0, rinfo->save_regs[71]);
1633         OUTMC(rinfo, ixR300_MC_ELPIDA_CNTL, rinfo->save_regs[72]);
1634         OUTMC(rinfo, ixR300_MC_READ_CNTL_CD, rinfo->save_regs[96]);
1635         OUTREG(MC_IND_INDEX, 0);
1636 }
1637
1638 static void radeon_reinitialize_M10(struct radeonfb_info *rinfo)
1639 {
1640         u32 tmp, i;
1641
1642         /* Restore a bunch of registers first */
1643         OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
1644         OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
1645         OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
1646         OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
1647         OUTREG(OV0_BASE_ADDR, rinfo->save_regs[80]);
1648         OUTREG(CONFIG_MEMSIZE, rinfo->video_ram);
1649         OUTREG(BUS_CNTL, rinfo->save_regs[36]);
1650         OUTREG(BUS_CNTL1, rinfo->save_regs[14]);
1651         OUTREG(MPP_TB_CONFIG, rinfo->save_regs[37]);
1652         OUTREG(FCP_CNTL, rinfo->save_regs[38]);
1653         OUTREG(RBBM_CNTL, rinfo->save_regs[39]);
1654         OUTREG(DAC_CNTL, rinfo->save_regs[40]);
1655         OUTREG(DAC_MACRO_CNTL, (INREG(DAC_MACRO_CNTL) & ~0x6) | 8);
1656         OUTREG(DAC_MACRO_CNTL, (INREG(DAC_MACRO_CNTL) & ~0x6) | 8);
1657
1658         /* Hrm... */
1659         OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | DAC2_EXPAND_MODE);
1660
1661         /* Reset the PAD CTLR */
1662         radeon_pm_reset_pad_ctlr_strength(rinfo);
1663
1664         /* Some PLLs are Read & written identically in the trace here...
1665          * I suppose it's actually to switch them all off & reset,
1666          * let's assume off is what we want. I'm just doing that for all major PLLs now.
1667          */
1668         radeon_pm_all_ppls_off(rinfo);
1669
1670         /* Clear tiling, reset swappers */
1671         INREG(SURFACE_CNTL);
1672         OUTREG(SURFACE_CNTL, 0);
1673
1674         /* Some black magic with TV_DAC_CNTL, we should restore those from backups
1675          * rather than hard coding...
1676          */
1677         tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_BGADJ_MASK;
1678         tmp |= 8 << TV_DAC_CNTL_BGADJ__SHIFT;
1679         OUTREG(TV_DAC_CNTL, tmp);
1680
1681         tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_DACADJ_MASK;
1682         tmp |= 7 << TV_DAC_CNTL_DACADJ__SHIFT;
1683         OUTREG(TV_DAC_CNTL, tmp);
1684
1685         /* More registers restored */
1686         OUTREG(AGP_CNTL, rinfo->save_regs[16]);
1687         OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]);
1688         OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
1689
1690         /* Hrmmm ... What is that ? */
1691         tmp = rinfo->save_regs[1]
1692                 & ~(CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK |
1693                     CLK_PWRMGT_CNTL__MC_BUSY);
1694         OUTPLL(pllCLK_PWRMGT_CNTL, tmp);
1695
1696         OUTREG(PAD_CTLR_MISC, rinfo->save_regs[56]);
1697         OUTREG(FW_CNTL, rinfo->save_regs[57]);
1698         OUTREG(HDP_DEBUG, rinfo->save_regs[96]);
1699         OUTREG(PAMAC0_DLY_CNTL, rinfo->save_regs[54]);
1700         OUTREG(PAMAC1_DLY_CNTL, rinfo->save_regs[55]);
1701         OUTREG(PAMAC2_DLY_CNTL, rinfo->save_regs[79]);
1702
1703         /* Restore Memory Controller configuration */
1704         radeon_pm_m10_reconfigure_mc(rinfo);
1705
1706         /* Make sure CRTC's dont touch memory */
1707         OUTREG(CRTC_GEN_CNTL, INREG(CRTC_GEN_CNTL)
1708                | CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B);
1709         OUTREG(CRTC2_GEN_CNTL, INREG(CRTC2_GEN_CNTL)
1710                | CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B);
1711         mdelay(30);
1712
1713         /* Disable SDRAM refresh */
1714         OUTREG(MEM_REFRESH_CNTL, INREG(MEM_REFRESH_CNTL)
1715                | MEM_REFRESH_CNTL__MEM_REFRESH_DIS);
1716
1717         /* Restore XTALIN routing (CLK_PIN_CNTL) */
1718         OUTPLL(pllCLK_PIN_CNTL, rinfo->save_regs[4]);
1719
1720         /* Switch MCLK, YCLK and SCLK PLLs to PCI source & force them ON */
1721         tmp = rinfo->save_regs[2] & 0xff000000;
1722         tmp |=  MCLK_CNTL__FORCE_MCLKA |
1723                 MCLK_CNTL__FORCE_MCLKB |
1724                 MCLK_CNTL__FORCE_YCLKA |
1725                 MCLK_CNTL__FORCE_YCLKB |
1726                 MCLK_CNTL__FORCE_MC;
1727         OUTPLL(pllMCLK_CNTL, tmp);
1728
1729         /* Force all clocks on in SCLK */
1730         tmp = INPLL(pllSCLK_CNTL);
1731         tmp |=  SCLK_CNTL__FORCE_DISP2|
1732                 SCLK_CNTL__FORCE_CP|
1733                 SCLK_CNTL__FORCE_HDP|
1734                 SCLK_CNTL__FORCE_DISP1|
1735                 SCLK_CNTL__FORCE_TOP|
1736                 SCLK_CNTL__FORCE_E2|
1737                 SCLK_CNTL__FORCE_SE|
1738                 SCLK_CNTL__FORCE_IDCT|
1739                 SCLK_CNTL__FORCE_VIP|
1740                 SCLK_CNTL__FORCE_PB|
1741                 SCLK_CNTL__FORCE_TAM|
1742                 SCLK_CNTL__FORCE_TDM|
1743                 SCLK_CNTL__FORCE_RB|
1744                 SCLK_CNTL__FORCE_TV_SCLK|
1745                 SCLK_CNTL__FORCE_SUBPIC|
1746                 SCLK_CNTL__FORCE_OV0;
1747         tmp |=  SCLK_CNTL__CP_MAX_DYN_STOP_LAT  |
1748                 SCLK_CNTL__HDP_MAX_DYN_STOP_LAT |
1749                 SCLK_CNTL__TV_MAX_DYN_STOP_LAT  |
1750                 SCLK_CNTL__E2_MAX_DYN_STOP_LAT  |
1751                 SCLK_CNTL__SE_MAX_DYN_STOP_LAT  |
1752                 SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT|
1753                 SCLK_CNTL__VIP_MAX_DYN_STOP_LAT |
1754                 SCLK_CNTL__RE_MAX_DYN_STOP_LAT  |
1755                 SCLK_CNTL__PB_MAX_DYN_STOP_LAT  |
1756                 SCLK_CNTL__TAM_MAX_DYN_STOP_LAT |
1757                 SCLK_CNTL__TDM_MAX_DYN_STOP_LAT |
1758                 SCLK_CNTL__RB_MAX_DYN_STOP_LAT;
1759         OUTPLL(pllSCLK_CNTL, tmp);
1760
1761         OUTPLL(pllVCLK_ECP_CNTL, 0);
1762         OUTPLL(pllPIXCLKS_CNTL, 0);
1763         OUTPLL(pllMCLK_MISC,
1764                MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT |
1765                MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT);
1766
1767         mdelay(5);
1768
1769         /* Restore the M_SPLL_REF_FB_DIV, MPLL_AUX_CNTL and SPLL_AUX_CNTL values */
1770         OUTPLL(pllM_SPLL_REF_FB_DIV, rinfo->save_regs[77]);
1771         OUTPLL(pllMPLL_AUX_CNTL, rinfo->save_regs[75]);
1772         OUTPLL(pllSPLL_AUX_CNTL, rinfo->save_regs[76]);
1773
1774         /* Now restore the major PLLs settings, keeping them off & reset though */
1775         OUTPLL(pllPPLL_CNTL, rinfo->save_regs[93] | 0x3);
1776         OUTPLL(pllP2PLL_CNTL, rinfo->save_regs[8] | 0x3);
1777         OUTPLL(pllMPLL_CNTL, rinfo->save_regs[73] | 0x03);
1778         OUTPLL(pllSPLL_CNTL, rinfo->save_regs[74] | 0x03);
1779
1780         /* Restore MC DLL state and switch it off/reset too  */
1781         OUTMC(rinfo, ixR300_MC_DLL_CNTL, rinfo->save_regs[70]);
1782
1783         /* Switch MDLL off & reset */
1784         OUTPLL(pllMDLL_RDCKA, rinfo->save_regs[98] | 0xff);
1785         mdelay(5);
1786
1787         /* Setup some black magic bits in PLL_PWRMGT_CNTL. Hrm... we saved
1788          * 0xa1100007... and MacOS writes 0xa1000007 ..
1789          */
1790         OUTPLL(pllPLL_PWRMGT_CNTL, rinfo->save_regs[0]);
1791
1792         /* Restore more stuffs */
1793         OUTPLL(pllHTOTAL_CNTL, 0);
1794         OUTPLL(pllHTOTAL2_CNTL, 0);
1795
1796         /* More PLL initial configuration */
1797         tmp = INPLL(pllSCLK_CNTL2); /* What for ? */
1798         OUTPLL(pllSCLK_CNTL2, tmp);
1799
1800         tmp = INPLL(pllSCLK_MORE_CNTL);
1801         tmp |=  SCLK_MORE_CNTL__FORCE_DISPREGS |        /* a guess */
1802                 SCLK_MORE_CNTL__FORCE_MC_GUI |
1803                 SCLK_MORE_CNTL__FORCE_MC_HOST;
1804         OUTPLL(pllSCLK_MORE_CNTL, tmp);
1805
1806         /* Now we actually start MCLK and SCLK */
1807         radeon_pm_start_mclk_sclk(rinfo);
1808
1809         /* Full reset sdrams, this also re-inits the MDLL */
1810         radeon_pm_full_reset_sdram(rinfo);
1811
1812         /* Fill palettes */
1813         OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | 0x20);
1814         for (i=0; i<256; i++)
1815                 OUTREG(PALETTE_30_DATA, 0x15555555);
1816         OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~20);
1817         udelay(20);
1818         for (i=0; i<256; i++)
1819                 OUTREG(PALETTE_30_DATA, 0x15555555);
1820
1821         OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~0x20);
1822         mdelay(3);
1823
1824         /* Restore TMDS */
1825         OUTREG(FP_GEN_CNTL, rinfo->save_regs[82]);
1826         OUTREG(FP2_GEN_CNTL, rinfo->save_regs[83]);
1827
1828         /* Set LVDS registers but keep interface & pll down */
1829         OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11] &
1830                ~(LVDS_EN | LVDS_ON | LVDS_DIGON | LVDS_BLON | LVDS_BL_MOD_EN));
1831         OUTREG(LVDS_PLL_CNTL, (rinfo->save_regs[12] & ~0xf0000) | 0x20000);
1832
1833         OUTREG(DISP_OUTPUT_CNTL, rinfo->save_regs[86]);
1834
1835         /* Restore GPIOPAD state */
1836         OUTREG(GPIOPAD_A, rinfo->save_regs[19]);
1837         OUTREG(GPIOPAD_EN, rinfo->save_regs[20]);
1838         OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]);
1839
1840         /* write some stuff to the framebuffer... */
1841         for (i = 0; i < 0x8000; ++i)
1842                 writeb(0, rinfo->fb_base + i);
1843
1844         mdelay(40);
1845         OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) | LVDS_DIGON | LVDS_ON);
1846         mdelay(40);
1847
1848         /* Restore a few more things */
1849         OUTREG(GRPH_BUFFER_CNTL, rinfo->save_regs[94]);
1850         OUTREG(GRPH2_BUFFER_CNTL, rinfo->save_regs[95]);
1851
1852         /* Take care of spread spectrum & PPLLs now */
1853         radeon_pm_m10_disable_spread_spectrum(rinfo);
1854         radeon_pm_restore_pixel_pll(rinfo);
1855
1856         /* GRRRR... I can't figure out the proper LVDS power sequence, and the
1857          * code I have for blank/unblank doesn't quite work on some laptop models
1858          * it seems ... Hrm. What I have here works most of the time ...
1859          */
1860         radeon_pm_m10_enable_lvds_spread_spectrum(rinfo);
1861 }
1862
1863 #ifdef CONFIG_PPC_OF
1864
1865 static void radeon_pm_m9p_reconfigure_mc(struct radeonfb_info *rinfo)
1866 {
1867         OUTREG(MC_CNTL, rinfo->save_regs[46]);
1868         OUTREG(MC_INIT_GFX_LAT_TIMER, rinfo->save_regs[47]);
1869         OUTREG(MC_INIT_MISC_LAT_TIMER, rinfo->save_regs[48]);
1870         OUTREG(MEM_SDRAM_MODE_REG,
1871                rinfo->save_regs[35] & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1872         OUTREG(MC_TIMING_CNTL, rinfo->save_regs[49]);
1873         OUTREG(MC_READ_CNTL_AB, rinfo->save_regs[50]);
1874         OUTREG(MEM_REFRESH_CNTL, rinfo->save_regs[42]);
1875         OUTREG(MC_IOPAD_CNTL, rinfo->save_regs[51]);
1876         OUTREG(MC_DEBUG, rinfo->save_regs[53]);
1877         OUTREG(MC_CHIP_IO_OE_CNTL_AB, rinfo->save_regs[52]);
1878
1879         OUTMC(rinfo, ixMC_IMP_CNTL, rinfo->save_regs[59] /*0x00f460d6*/);
1880         OUTMC(rinfo, ixMC_CHP_IO_CNTL_A0, rinfo->save_regs[65] /*0xfecfa666*/);
1881         OUTMC(rinfo, ixMC_CHP_IO_CNTL_A1, rinfo->save_regs[66] /*0x141555ff*/);
1882         OUTMC(rinfo, ixMC_CHP_IO_CNTL_B0, rinfo->save_regs[67] /*0xfecfa666*/);
1883         OUTMC(rinfo, ixMC_CHP_IO_CNTL_B1, rinfo->save_regs[68] /*0x141555ff*/);
1884         OUTMC(rinfo, ixMC_IMP_CNTL_0, rinfo->save_regs[71] /*0x00009249*/);
1885         OUTREG(MC_IND_INDEX, 0);
1886         OUTREG(CONFIG_MEMSIZE, rinfo->video_ram);
1887
1888         mdelay(20);
1889 }
1890
1891 static void radeon_reinitialize_M9P(struct radeonfb_info *rinfo)
1892 {
1893         u32 tmp, i;
1894
1895         /* Restore a bunch of registers first */
1896         OUTREG(SURFACE_CNTL, rinfo->save_regs[29]);
1897         OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
1898         OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
1899         OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
1900         OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
1901         OUTREG(OV0_BASE_ADDR, rinfo->save_regs[80]);
1902         OUTREG(BUS_CNTL, rinfo->save_regs[36]);
1903         OUTREG(BUS_CNTL1, rinfo->save_regs[14]);
1904         OUTREG(MPP_TB_CONFIG, rinfo->save_regs[37]);
1905         OUTREG(FCP_CNTL, rinfo->save_regs[38]);
1906         OUTREG(RBBM_CNTL, rinfo->save_regs[39]);
1907
1908         OUTREG(DAC_CNTL, rinfo->save_regs[40]);
1909         OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | DAC2_EXPAND_MODE);
1910
1911         /* Reset the PAD CTLR */
1912         radeon_pm_reset_pad_ctlr_strength(rinfo);
1913
1914         /* Some PLLs are Read & written identically in the trace here...
1915          * I suppose it's actually to switch them all off & reset,
1916          * let's assume off is what we want. I'm just doing that for all major PLLs now.
1917          */
1918         radeon_pm_all_ppls_off(rinfo);
1919
1920         /* Clear tiling, reset swappers */
1921         INREG(SURFACE_CNTL);
1922         OUTREG(SURFACE_CNTL, 0);
1923
1924         /* Some black magic with TV_DAC_CNTL, we should restore those from backups
1925          * rather than hard coding...
1926          */
1927         tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_BGADJ_MASK;
1928         tmp |= 6 << TV_DAC_CNTL_BGADJ__SHIFT;
1929         OUTREG(TV_DAC_CNTL, tmp);
1930
1931         tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_DACADJ_MASK;
1932         tmp |= 6 << TV_DAC_CNTL_DACADJ__SHIFT;
1933         OUTREG(TV_DAC_CNTL, tmp);
1934
1935         OUTPLL(pllAGP_PLL_CNTL, rinfo->save_regs[78]);
1936
1937         OUTREG(PAMAC0_DLY_CNTL, rinfo->save_regs[54]);
1938         OUTREG(PAMAC1_DLY_CNTL, rinfo->save_regs[55]);
1939         OUTREG(PAMAC2_DLY_CNTL, rinfo->save_regs[79]);
1940
1941         OUTREG(AGP_CNTL, rinfo->save_regs[16]);
1942         OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]); /* MacOS sets that to 0 !!! */
1943         OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
1944
1945         tmp  = rinfo->save_regs[1]
1946                 & ~(CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK |
1947                     CLK_PWRMGT_CNTL__MC_BUSY);
1948         OUTPLL(pllCLK_PWRMGT_CNTL, tmp);
1949
1950         OUTREG(FW_CNTL, rinfo->save_regs[57]);
1951
1952         /* Disable SDRAM refresh */
1953         OUTREG(MEM_REFRESH_CNTL, INREG(MEM_REFRESH_CNTL)
1954                | MEM_REFRESH_CNTL__MEM_REFRESH_DIS);
1955
1956         /* Restore XTALIN routing (CLK_PIN_CNTL) */
1957         OUTPLL(pllCLK_PIN_CNTL, rinfo->save_regs[4]);
1958
1959         /* Force MCLK to be PCI sourced and forced ON */
1960         tmp = rinfo->save_regs[2] & 0xff000000;
1961         tmp |=  MCLK_CNTL__FORCE_MCLKA |
1962                 MCLK_CNTL__FORCE_MCLKB |
1963                 MCLK_CNTL__FORCE_YCLKA |
1964                 MCLK_CNTL__FORCE_YCLKB |
1965                 MCLK_CNTL__FORCE_MC    |
1966                 MCLK_CNTL__FORCE_AIC;
1967         OUTPLL(pllMCLK_CNTL, tmp);
1968
1969         /* Force SCLK to be PCI sourced with a bunch forced */
1970         tmp =   0 |
1971                 SCLK_CNTL__FORCE_DISP2|
1972                 SCLK_CNTL__FORCE_CP|
1973                 SCLK_CNTL__FORCE_HDP|
1974                 SCLK_CNTL__FORCE_DISP1|
1975                 SCLK_CNTL__FORCE_TOP|
1976                 SCLK_CNTL__FORCE_E2|
1977                 SCLK_CNTL__FORCE_SE|
1978                 SCLK_CNTL__FORCE_IDCT|
1979                 SCLK_CNTL__FORCE_VIP|
1980                 SCLK_CNTL__FORCE_RE|
1981                 SCLK_CNTL__FORCE_PB|
1982                 SCLK_CNTL__FORCE_TAM|
1983                 SCLK_CNTL__FORCE_TDM|
1984                 SCLK_CNTL__FORCE_RB;
1985         OUTPLL(pllSCLK_CNTL, tmp);
1986
1987         /* Clear VCLK_ECP_CNTL & PIXCLKS_CNTL  */
1988         OUTPLL(pllVCLK_ECP_CNTL, 0);
1989         OUTPLL(pllPIXCLKS_CNTL, 0);
1990
1991         /* Setup MCLK_MISC, non dynamic mode */
1992         OUTPLL(pllMCLK_MISC,
1993                MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT |
1994                MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT);
1995
1996         mdelay(5);
1997
1998         /* Set back the default clock dividers */
1999         OUTPLL(pllM_SPLL_REF_FB_DIV, rinfo->save_regs[77]);
2000         OUTPLL(pllMPLL_AUX_CNTL, rinfo->save_regs[75]);
2001         OUTPLL(pllSPLL_AUX_CNTL, rinfo->save_regs[76]);
2002
2003         /* PPLL and P2PLL default values & off */
2004         OUTPLL(pllPPLL_CNTL, rinfo->save_regs[93] | 0x3);
2005         OUTPLL(pllP2PLL_CNTL, rinfo->save_regs[8] | 0x3);
2006
2007         /* S and M PLLs are reset & off, configure them */
2008         OUTPLL(pllMPLL_CNTL, rinfo->save_regs[73] | 0x03);
2009         OUTPLL(pllSPLL_CNTL, rinfo->save_regs[74] | 0x03);
2010
2011         /* Default values for MDLL ... fixme */
2012         OUTPLL(pllMDLL_CKO, 0x9c009c);
2013         OUTPLL(pllMDLL_RDCKA, 0x08830883);
2014         OUTPLL(pllMDLL_RDCKB, 0x08830883);
2015         mdelay(5);
2016
2017         /* Restore PLL_PWRMGT_CNTL */ // XXXX
2018         tmp = rinfo->save_regs[0];
2019         tmp &= ~PLL_PWRMGT_CNTL_SU_SCLK_USE_BCLK;
2020         tmp |= PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK;
2021         OUTPLL(PLL_PWRMGT_CNTL,  tmp);
2022
2023         /* Clear HTOTAL_CNTL & HTOTAL2_CNTL */
2024         OUTPLL(pllHTOTAL_CNTL, 0);
2025         OUTPLL(pllHTOTAL2_CNTL, 0);
2026
2027         /* All outputs off */
2028         OUTREG(CRTC_GEN_CNTL, 0x04000000);
2029         OUTREG(CRTC2_GEN_CNTL, 0x04000000);
2030         OUTREG(FP_GEN_CNTL, 0x00004008);
2031         OUTREG(FP2_GEN_CNTL, 0x00000008);
2032         OUTREG(LVDS_GEN_CNTL, 0x08000008);
2033
2034         /* Restore Memory Controller configuration */
2035         radeon_pm_m9p_reconfigure_mc(rinfo);
2036
2037         /* Now we actually start MCLK and SCLK */
2038         radeon_pm_start_mclk_sclk(rinfo);
2039
2040         /* Full reset sdrams, this also re-inits the MDLL */
2041         radeon_pm_full_reset_sdram(rinfo);
2042
2043         /* Fill palettes */
2044         OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | 0x20);
2045         for (i=0; i<256; i++)
2046                 OUTREG(PALETTE_30_DATA, 0x15555555);
2047         OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~20);
2048         udelay(20);
2049         for (i=0; i<256; i++)
2050                 OUTREG(PALETTE_30_DATA, 0x15555555);
2051
2052         OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~0x20);
2053         mdelay(3);
2054
2055         /* Restore TV stuff, make sure TV DAC is down */
2056         OUTREG(TV_MASTER_CNTL, rinfo->save_regs[88]);
2057         OUTREG(TV_DAC_CNTL, rinfo->save_regs[13] | 0x07000000);
2058
2059         /* Restore GPIOS. MacOS does some magic here with one of the GPIO bits,
2060          * possibly related to the weird PLL related workarounds and to the
2061          * fact that CLK_PIN_CNTL is tweaked in ways I don't fully understand,
2062          * but we keep things the simple way here
2063          */
2064         OUTREG(GPIOPAD_A, rinfo->save_regs[19]);
2065         OUTREG(GPIOPAD_EN, rinfo->save_regs[20]);
2066         OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]);
2067
2068         /* Now do things with SCLK_MORE_CNTL. Force bits are already set, copy
2069          * high bits from backup
2070          */
2071         tmp = INPLL(pllSCLK_MORE_CNTL) & 0x0000ffff;
2072         tmp |= rinfo->save_regs[34] & 0xffff0000;
2073         tmp |= SCLK_MORE_CNTL__FORCE_DISPREGS;
2074         OUTPLL(pllSCLK_MORE_CNTL, tmp);
2075
2076         tmp = INPLL(pllSCLK_MORE_CNTL) & 0x0000ffff;
2077         tmp |= rinfo->save_regs[34] & 0xffff0000;
2078         tmp |= SCLK_MORE_CNTL__FORCE_DISPREGS;
2079         OUTPLL(pllSCLK_MORE_CNTL, tmp);
2080
2081         OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11] &
2082                ~(LVDS_EN | LVDS_ON | LVDS_DIGON | LVDS_BLON | LVDS_BL_MOD_EN));
2083         OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) | LVDS_BLON);
2084         OUTREG(LVDS_PLL_CNTL, (rinfo->save_regs[12] & ~0xf0000) | 0x20000);
2085         mdelay(20);
2086
2087         /* write some stuff to the framebuffer... */
2088         for (i = 0; i < 0x8000; ++i)
2089                 writeb(0, rinfo->fb_base + i);
2090
2091         OUTREG(0x2ec, 0x6332a020);
2092         OUTPLL(pllSSPLL_REF_DIV, rinfo->save_regs[44] /*0x3f */);
2093         OUTPLL(pllSSPLL_DIV_0, rinfo->save_regs[45] /*0x000081bb */);
2094         tmp = INPLL(pllSSPLL_CNTL);
2095         tmp &= ~2;
2096         OUTPLL(pllSSPLL_CNTL, tmp);
2097         mdelay(6);
2098         tmp &= ~1;
2099         OUTPLL(pllSSPLL_CNTL, tmp);
2100         mdelay(5);
2101         tmp |= 3;
2102         OUTPLL(pllSSPLL_CNTL, tmp);
2103         mdelay(5);
2104
2105         OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90] & ~3);/*0x0020300c*/
2106         OUTREG(0x2ec, 0x6332a3f0);
2107         mdelay(17);
2108
2109         OUTPLL(pllPPLL_REF_DIV, rinfo->pll.ref_div);
2110         OUTPLL(pllPPLL_DIV_0, rinfo->save_regs[92]);
2111
2112         mdelay(40);
2113         OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) | LVDS_DIGON | LVDS_ON);
2114         mdelay(40);
2115
2116         /* Restore a few more things */
2117         OUTREG(GRPH_BUFFER_CNTL, rinfo->save_regs[94]);
2118         OUTREG(GRPH2_BUFFER_CNTL, rinfo->save_regs[95]);
2119
2120         /* Restore PPLL, spread spectrum & LVDS */
2121         radeon_pm_m10_disable_spread_spectrum(rinfo);
2122         radeon_pm_restore_pixel_pll(rinfo);
2123         radeon_pm_m10_enable_lvds_spread_spectrum(rinfo);
2124 }
2125
2126 #if 0 /* Not ready yet */
2127 static void radeon_reinitialize_QW(struct radeonfb_info *rinfo)
2128 {
2129         int i;
2130         u32 tmp, tmp2;
2131         u32 cko, cka, ckb;
2132         u32 cgc, cec, c2gc;
2133
2134         OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
2135         OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
2136         OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
2137         OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
2138         OUTREG(BUS_CNTL, rinfo->save_regs[36]);
2139         OUTREG(RBBM_CNTL, rinfo->save_regs[39]);
2140
2141         INREG(PAD_CTLR_STRENGTH);
2142         OUTREG(PAD_CTLR_STRENGTH, INREG(PAD_CTLR_STRENGTH) & ~0x10000);
2143         for (i = 0; i < 65; ++i) {
2144                 mdelay(1);
2145                 INREG(PAD_CTLR_STRENGTH);
2146         }
2147
2148         OUTREG(DISP_TEST_DEBUG_CNTL, INREG(DISP_TEST_DEBUG_CNTL) | 0x10000000);
2149         OUTREG(OV0_FLAG_CNTRL, INREG(OV0_FLAG_CNTRL) | 0x100);
2150         OUTREG(CRTC_GEN_CNTL, INREG(CRTC_GEN_CNTL));
2151         OUTREG(DAC_CNTL, 0xff00410a);
2152         OUTREG(CRTC2_GEN_CNTL, INREG(CRTC2_GEN_CNTL));
2153         OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | 0x4000);
2154
2155         OUTREG(SURFACE_CNTL, rinfo->save_regs[29]);
2156         OUTREG(AGP_CNTL, rinfo->save_regs[16]);
2157         OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]);
2158         OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
2159
2160         OUTMC(rinfo, ixMC_CHP_IO_CNTL_A0, 0xf7bb4433);
2161         OUTREG(MC_IND_INDEX, 0);
2162         OUTMC(rinfo, ixMC_CHP_IO_CNTL_B0, 0xf7bb4433);
2163         OUTREG(MC_IND_INDEX, 0);
2164
2165         OUTREG(CRTC_MORE_CNTL, INREG(CRTC_MORE_CNTL));
2166
2167         tmp = INPLL(pllVCLK_ECP_CNTL);
2168         OUTPLL(pllVCLK_ECP_CNTL, tmp);
2169         tmp = INPLL(pllPIXCLKS_CNTL);
2170         OUTPLL(pllPIXCLKS_CNTL, tmp);
2171
2172         OUTPLL(MCLK_CNTL, 0xaa3f0000);
2173         OUTPLL(SCLK_CNTL, 0xffff0000);
2174         OUTPLL(pllMPLL_AUX_CNTL, 6);
2175         OUTPLL(pllSPLL_AUX_CNTL, 1);
2176         OUTPLL(MDLL_CKO, 0x9f009f);
2177         OUTPLL(MDLL_RDCKA, 0x830083);
2178         OUTPLL(pllMDLL_RDCKB, 0x830083);
2179         OUTPLL(PPLL_CNTL, 0xa433);
2180         OUTPLL(P2PLL_CNTL, 0xa433);
2181         OUTPLL(MPLL_CNTL, 0x0400a403);
2182         OUTPLL(SPLL_CNTL, 0x0400a433);
2183
2184         tmp = INPLL(M_SPLL_REF_FB_DIV);
2185         OUTPLL(M_SPLL_REF_FB_DIV, tmp);
2186         tmp = INPLL(M_SPLL_REF_FB_DIV);
2187         OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0xc);
2188         INPLL(M_SPLL_REF_FB_DIV);
2189
2190         tmp = INPLL(MPLL_CNTL);
2191         OUTREG8(CLOCK_CNTL_INDEX, MPLL_CNTL + PLL_WR_EN);
2192         radeon_pll_errata_after_index(rinfo);
2193         OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
2194         radeon_pll_errata_after_data(rinfo);
2195
2196         tmp = INPLL(M_SPLL_REF_FB_DIV);
2197         OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0x5900);
2198
2199         tmp = INPLL(MPLL_CNTL);
2200         OUTPLL(MPLL_CNTL, tmp & ~0x2);
2201         mdelay(1);
2202         tmp = INPLL(MPLL_CNTL);
2203         OUTPLL(MPLL_CNTL, tmp & ~0x1);
2204         mdelay(10);
2205
2206         OUTPLL(MCLK_CNTL, 0xaa3f1212);
2207         mdelay(1);
2208
2209         INPLL(M_SPLL_REF_FB_DIV);
2210         INPLL(MCLK_CNTL);
2211         INPLL(M_SPLL_REF_FB_DIV);
2212
2213         tmp = INPLL(SPLL_CNTL);
2214         OUTREG8(CLOCK_CNTL_INDEX, SPLL_CNTL + PLL_WR_EN);
2215         radeon_pll_errata_after_index(rinfo);
2216         OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
2217         radeon_pll_errata_after_data(rinfo);
2218
2219         tmp = INPLL(M_SPLL_REF_FB_DIV);
2220         OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0x780000);
2221
2222         tmp = INPLL(SPLL_CNTL);
2223         OUTPLL(SPLL_CNTL, tmp & ~0x1);
2224         mdelay(1);
2225         tmp = INPLL(SPLL_CNTL);
2226         OUTPLL(SPLL_CNTL, tmp & ~0x2);
2227         mdelay(10);
2228
2229         tmp = INPLL(SCLK_CNTL);
2230         OUTPLL(SCLK_CNTL, tmp | 2);
2231         mdelay(1);
2232
2233         cko = INPLL(pllMDLL_CKO);
2234         cka = INPLL(pllMDLL_RDCKA);
2235         ckb = INPLL(pllMDLL_RDCKB);
2236
2237         cko &= ~(MDLL_CKO__MCKOA_SLEEP | MDLL_CKO__MCKOB_SLEEP);
2238         OUTPLL(pllMDLL_CKO, cko);
2239         mdelay(1);
2240         cko &= ~(MDLL_CKO__MCKOA_RESET | MDLL_CKO__MCKOB_RESET);
2241         OUTPLL(pllMDLL_CKO, cko);
2242         mdelay(5);
2243
2244         cka &= ~(MDLL_RDCKA__MRDCKA0_SLEEP | MDLL_RDCKA__MRDCKA1_SLEEP);
2245         OUTPLL(pllMDLL_RDCKA, cka);
2246         mdelay(1);
2247         cka &= ~(MDLL_RDCKA__MRDCKA0_RESET | MDLL_RDCKA__MRDCKA1_RESET);
2248         OUTPLL(pllMDLL_RDCKA, cka);
2249         mdelay(5);
2250
2251         ckb &= ~(MDLL_RDCKB__MRDCKB0_SLEEP | MDLL_RDCKB__MRDCKB1_SLEEP);
2252         OUTPLL(pllMDLL_RDCKB, ckb);
2253         mdelay(1);
2254         ckb &= ~(MDLL_RDCKB__MRDCKB0_RESET | MDLL_RDCKB__MRDCKB1_RESET);
2255         OUTPLL(pllMDLL_RDCKB, ckb);
2256         mdelay(5);
2257
2258         OUTMC(rinfo, ixMC_CHP_IO_CNTL_A1, 0x151550ff);
2259         OUTREG(MC_IND_INDEX, 0);
2260         OUTMC(rinfo, ixMC_CHP_IO_CNTL_B1, 0x151550ff);
2261         OUTREG(MC_IND_INDEX, 0);
2262         mdelay(1);
2263         OUTMC(rinfo, ixMC_CHP_IO_CNTL_A1, 0x141550ff);
2264         OUTREG(MC_IND_INDEX, 0);
2265         OUTMC(rinfo, ixMC_CHP_IO_CNTL_B1, 0x141550ff);
2266         OUTREG(MC_IND_INDEX, 0);
2267         mdelay(1);
2268
2269         OUTPLL(pllHTOTAL_CNTL, 0);
2270         OUTPLL(pllHTOTAL2_CNTL, 0);
2271
2272         OUTREG(MEM_CNTL, 0x29002901);
2273         OUTREG(MEM_SDRAM_MODE_REG, 0x45320032); /* XXX use save_regs[35]? */
2274         OUTREG(EXT_MEM_CNTL, 0x1a394333);
2275         OUTREG(MEM_IO_CNTL_A1, 0x0aac0aac);
2276         OUTREG(MEM_INIT_LATENCY_TIMER, 0x34444444);
2277         OUTREG(MEM_REFRESH_CNTL, 0x1f1f7218);   /* XXX or save_regs[42]? */
2278         OUTREG(MC_DEBUG, 0);
2279         OUTREG(MEM_IO_OE_CNTL, 0x04300430);
2280
2281         OUTMC(rinfo, ixMC_IMP_CNTL, 0x00f460d6);
2282         OUTREG(MC_IND_INDEX, 0);
2283         OUTMC(rinfo, ixMC_IMP_CNTL_0, 0x00009249);
2284         OUTREG(MC_IND_INDEX, 0);
2285
2286         OUTREG(CONFIG_MEMSIZE, rinfo->video_ram);
2287
2288         radeon_pm_full_reset_sdram(rinfo);
2289
2290         INREG(FP_GEN_CNTL);
2291         OUTREG(TMDS_CNTL, 0x01000000);  /* XXX ? */
2292         tmp = INREG(FP_GEN_CNTL);
2293         tmp |= FP_CRTC_DONT_SHADOW_HEND | FP_CRTC_DONT_SHADOW_VPAR | 0x200;
2294         OUTREG(FP_GEN_CNTL, tmp);
2295
2296         tmp = INREG(DISP_OUTPUT_CNTL);
2297         tmp &= ~0x400;
2298         OUTREG(DISP_OUTPUT_CNTL, tmp);
2299
2300         OUTPLL(CLK_PIN_CNTL, rinfo->save_regs[4]);
2301         OUTPLL(CLK_PWRMGT_CNTL, rinfo->save_regs[1]);
2302         OUTPLL(PLL_PWRMGT_CNTL, rinfo->save_regs[0]);
2303
2304         tmp = INPLL(MCLK_MISC);
2305         tmp |= MCLK_MISC__MC_MCLK_DYN_ENABLE | MCLK_MISC__IO_MCLK_DYN_ENABLE;
2306         OUTPLL(MCLK_MISC, tmp);
2307
2308         tmp = INPLL(SCLK_CNTL);
2309         OUTPLL(SCLK_CNTL, tmp);
2310
2311         OUTREG(CRTC_MORE_CNTL, 0);
2312         OUTREG8(CRTC_GEN_CNTL+1, 6);
2313         OUTREG8(CRTC_GEN_CNTL+3, 1);
2314         OUTREG(CRTC_PITCH, 32);
2315
2316         tmp = INPLL(VCLK_ECP_CNTL);
2317         OUTPLL(VCLK_ECP_CNTL, tmp);
2318
2319         tmp = INPLL(PPLL_CNTL);
2320         OUTPLL(PPLL_CNTL, tmp);
2321
2322         /* palette stuff and BIOS_1_SCRATCH... */
2323
2324         tmp = INREG(FP_GEN_CNTL);
2325         tmp2 = INREG(TMDS_TRANSMITTER_CNTL);
2326         tmp |= 2;
2327         OUTREG(FP_GEN_CNTL, tmp);
2328         mdelay(5);
2329         OUTREG(FP_GEN_CNTL, tmp);
2330         mdelay(5);
2331         OUTREG(TMDS_TRANSMITTER_CNTL, tmp2);
2332         OUTREG(CRTC_MORE_CNTL, 0);
2333         mdelay(20);
2334
2335         tmp = INREG(CRTC_MORE_CNTL);
2336         OUTREG(CRTC_MORE_CNTL, tmp);
2337
2338         cgc = INREG(CRTC_GEN_CNTL);
2339         cec = INREG(CRTC_EXT_CNTL);
2340         c2gc = INREG(CRTC2_GEN_CNTL);
2341
2342         OUTREG(CRTC_H_SYNC_STRT_WID, 0x008e0580);
2343         OUTREG(CRTC_H_TOTAL_DISP, 0x009f00d2);
2344         OUTREG8(CLOCK_CNTL_INDEX, HTOTAL_CNTL + PLL_WR_EN);
2345         radeon_pll_errata_after_index(rinfo);
2346         OUTREG8(CLOCK_CNTL_DATA, 0);
2347         radeon_pll_errata_after_data(rinfo);
2348         OUTREG(CRTC_V_SYNC_STRT_WID, 0x00830403);
2349         OUTREG(CRTC_V_TOTAL_DISP, 0x03ff0429);
2350         OUTREG(FP_CRTC_H_TOTAL_DISP, 0x009f0033);
2351         OUTREG(FP_H_SYNC_STRT_WID, 0x008e0080);
2352         OUTREG(CRT_CRTC_H_SYNC_STRT_WID, 0x008e0080);
2353         OUTREG(FP_CRTC_V_TOTAL_DISP, 0x03ff002a);
2354         OUTREG(FP_V_SYNC_STRT_WID, 0x00830004);
2355         OUTREG(CRT_CRTC_V_SYNC_STRT_WID, 0x00830004);
2356         OUTREG(FP_HORZ_VERT_ACTIVE, 0x009f03ff);
2357         OUTREG(FP_HORZ_STRETCH, 0);
2358         OUTREG(FP_VERT_STRETCH, 0);
2359         OUTREG(OVR_CLR, 0);
2360         OUTREG(OVR_WID_LEFT_RIGHT, 0);
2361         OUTREG(OVR_WID_TOP_BOTTOM, 0);
2362
2363         tmp = INPLL(PPLL_REF_DIV);
2364         tmp = (tmp & ~PPLL_REF_DIV_MASK) | rinfo->pll.ref_div;
2365         OUTPLL(PPLL_REF_DIV, tmp);
2366         INPLL(PPLL_REF_DIV);
2367
2368         OUTREG8(CLOCK_CNTL_INDEX, PPLL_CNTL + PLL_WR_EN);
2369         radeon_pll_errata_after_index(rinfo);
2370         OUTREG8(CLOCK_CNTL_DATA + 1, 0xbc);
2371         radeon_pll_errata_after_data(rinfo);
2372
2373         tmp = INREG(CLOCK_CNTL_INDEX);
2374         radeon_pll_errata_after_index(rinfo);
2375         OUTREG(CLOCK_CNTL_INDEX, tmp & 0xff);
2376         radeon_pll_errata_after_index(rinfo);
2377         radeon_pll_errata_after_data(rinfo);
2378
2379         OUTPLL(PPLL_DIV_0, 0x48090);
2380
2381         tmp = INPLL(PPLL_CNTL);
2382         OUTPLL(PPLL_CNTL, tmp & ~0x2);
2383         mdelay(1);
2384         tmp = INPLL(PPLL_CNTL);
2385         OUTPLL(PPLL_CNTL, tmp & ~0x1);
2386         mdelay(10);
2387
2388         tmp = INPLL(VCLK_ECP_CNTL);
2389         OUTPLL(VCLK_ECP_CNTL, tmp | 3);
2390         mdelay(1);
2391
2392         tmp = INPLL(VCLK_ECP_CNTL);
2393         OUTPLL(VCLK_ECP_CNTL, tmp);
2394
2395         c2gc |= CRTC2_DISP_REQ_EN_B;
2396         OUTREG(CRTC2_GEN_CNTL, c2gc);
2397         cgc |= CRTC_EN;
2398         OUTREG(CRTC_GEN_CNTL, cgc);
2399         OUTREG(CRTC_EXT_CNTL, cec);
2400         OUTREG(CRTC_PITCH, 0xa0);
2401         OUTREG(CRTC_OFFSET, 0);
2402         OUTREG(CRTC_OFFSET_CNTL, 0);
2403
2404         OUTREG(GRPH_BUFFER_CNTL, 0x20117c7c);
2405         OUTREG(GRPH2_BUFFER_CNTL, 0x00205c5c);
2406
2407         tmp2 = INREG(FP_GEN_CNTL);
2408         tmp = INREG(TMDS_TRANSMITTER_CNTL);
2409         OUTREG(0x2a8, 0x0000061b);
2410         tmp |= TMDS_PLL_EN;
2411         OUTREG(TMDS_TRANSMITTER_CNTL, tmp);
2412         mdelay(1);
2413         tmp &= ~TMDS_PLLRST;
2414         OUTREG(TMDS_TRANSMITTER_CNTL, tmp);
2415         tmp2 &= ~2;
2416         tmp2 |= FP_TMDS_EN;
2417         OUTREG(FP_GEN_CNTL, tmp2);
2418         mdelay(5);
2419         tmp2 |= FP_FPON;
2420         OUTREG(FP_GEN_CNTL, tmp2);
2421
2422         OUTREG(CUR_HORZ_VERT_OFF, CUR_LOCK | 1);
2423         cgc = INREG(CRTC_GEN_CNTL);
2424         OUTREG(CUR_HORZ_VERT_POSN, 0xbfff0fff);
2425         cgc |= 0x10000;
2426         OUTREG(CUR_OFFSET, 0);
2427 }
2428 #endif /* 0 */
2429
2430 #endif /* CONFIG_PPC_OF */
2431
2432 static void radeon_set_suspend(struct radeonfb_info *rinfo, int suspend)
2433 {
2434         u16 pwr_cmd;
2435         u32 tmp;
2436         int i;
2437
2438         if (!rinfo->pm_reg)
2439                 return;
2440
2441         /* Set the chip into appropriate suspend mode (we use D2,
2442          * D3 would require a compete re-initialization of the chip,
2443          * including PCI config registers, clocks, AGP conf, ...)
2444          */
2445         if (suspend) {
2446                 printk(KERN_DEBUG "radeonfb (%s): switching to D2 state...\n",
2447                        pci_name(rinfo->pdev));
2448
2449                 /* Disable dynamic power management of clocks for the
2450                  * duration of the suspend/resume process
2451                  */
2452                 radeon_pm_disable_dynamic_mode(rinfo);
2453
2454                 /* Save some registers */
2455                 radeon_pm_save_regs(rinfo, 0);
2456
2457                 /* Prepare mobility chips for suspend.
2458                  */
2459                 if (rinfo->is_mobility) {
2460                         /* Program V2CLK */
2461                         radeon_pm_program_v2clk(rinfo);
2462
2463                         /* Disable IO PADs */
2464                         radeon_pm_disable_iopad(rinfo);
2465
2466                         /* Set low current */
2467                         radeon_pm_low_current(rinfo);
2468
2469                         /* Prepare chip for power management */
2470                         radeon_pm_setup_for_suspend(rinfo);
2471
2472                         if (rinfo->family <= CHIP_FAMILY_RV280) {
2473                                 /* Reset the MDLL */
2474                                 /* because both INPLL and OUTPLL take the same
2475                                  * lock, that's why. */
2476                                 tmp = INPLL( pllMDLL_CKO) | MDLL_CKO__MCKOA_RESET
2477                                         | MDLL_CKO__MCKOB_RESET;
2478                                 OUTPLL( pllMDLL_CKO, tmp );
2479                         }
2480                 }
2481
2482                 for (i = 0; i < 64; ++i)
2483                         pci_read_config_dword(rinfo->pdev, i * 4,
2484                                               &rinfo->cfg_save[i]);
2485
2486                 /* Switch PCI power managment to D2. */
2487                 pci_disable_device(rinfo->pdev);
2488                 for (;;) {
2489                         pci_read_config_word(
2490                                 rinfo->pdev, rinfo->pm_reg+PCI_PM_CTRL,
2491                                 &pwr_cmd);
2492                         if (pwr_cmd & 2)
2493                                 break;
2494                         pci_write_config_word(
2495                                 rinfo->pdev, rinfo->pm_reg+PCI_PM_CTRL,
2496                                 (pwr_cmd & ~PCI_PM_CTRL_STATE_MASK) | 2);
2497                         mdelay(500);
2498                 }
2499         } else {
2500                 printk(KERN_DEBUG "radeonfb (%s): switching to D0 state...\n",
2501                        pci_name(rinfo->pdev));
2502
2503                 /* Switch back PCI powermanagment to D0 */
2504                 mdelay(200);
2505                 pci_write_config_word(rinfo->pdev, rinfo->pm_reg+PCI_PM_CTRL, 0);
2506                 mdelay(500);
2507
2508                 if (rinfo->family <= CHIP_FAMILY_RV250) {
2509                         /* Reset the SDRAM controller  */
2510                         radeon_pm_full_reset_sdram(rinfo);
2511
2512                         /* Restore some registers */
2513                         radeon_pm_restore_regs(rinfo);
2514                 } else {
2515                         /* Restore registers first */
2516                         radeon_pm_restore_regs(rinfo);
2517                         /* init sdram controller */
2518                         radeon_pm_full_reset_sdram(rinfo);
2519                 }
2520         }
2521 }
2522
2523 static int radeon_restore_pci_cfg(struct radeonfb_info *rinfo)
2524 {
2525         int i;
2526         static u32 radeon_cfg_after_resume[64];
2527
2528         for (i = 0; i < 64; ++i)
2529                 pci_read_config_dword(rinfo->pdev, i * 4,
2530                                       &radeon_cfg_after_resume[i]);
2531
2532         if (radeon_cfg_after_resume[PCI_BASE_ADDRESS_0/4]
2533             == rinfo->cfg_save[PCI_BASE_ADDRESS_0/4])
2534                 return 0;       /* assume everything is ok */
2535
2536         for (i = PCI_BASE_ADDRESS_0/4; i < 64; ++i) {
2537                 if (radeon_cfg_after_resume[i] != rinfo->cfg_save[i])
2538                         pci_write_config_dword(rinfo->pdev, i * 4,
2539                                                rinfo->cfg_save[i]);
2540         }
2541         pci_write_config_word(rinfo->pdev, PCI_CACHE_LINE_SIZE,
2542                               rinfo->cfg_save[PCI_CACHE_LINE_SIZE/4]);
2543         pci_write_config_word(rinfo->pdev, PCI_COMMAND,
2544                               rinfo->cfg_save[PCI_COMMAND/4]);
2545         return 1;
2546 }
2547
2548
2549 int radeonfb_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2550 {
2551         struct fb_info *info = pci_get_drvdata(pdev);
2552         struct radeonfb_info *rinfo = info->par;
2553         int i;
2554
2555         if (state.event == pdev->dev.power.power_state.event)
2556                 return 0;
2557
2558         printk(KERN_DEBUG "radeonfb (%s): suspending to state: %d...\n",
2559                pci_name(pdev), state.event);
2560
2561         /* For suspend-to-disk, we cheat here. We don't suspend anything and
2562          * let fbcon continue drawing until we are all set. That shouldn't
2563          * really cause any problem at this point, provided that the wakeup
2564          * code knows that any state in memory may not match the HW
2565          */
2566         if (state.event == PM_EVENT_FREEZE)
2567                 goto done;
2568
2569         acquire_console_sem();
2570
2571         fb_set_suspend(info, 1);
2572
2573         if (!(info->flags & FBINFO_HWACCEL_DISABLED)) {
2574                 /* Make sure engine is reset */
2575                 radeon_engine_idle();
2576                 radeonfb_engine_reset(rinfo);
2577                 radeon_engine_idle();
2578         }
2579
2580         /* Blank display and LCD */
2581         radeon_screen_blank(rinfo, FB_BLANK_POWERDOWN, 1);
2582
2583         /* Sleep */
2584         rinfo->asleep = 1;
2585         rinfo->lock_blank = 1;
2586         del_timer_sync(&rinfo->lvds_timer);
2587
2588 #ifdef CONFIG_PPC_PMAC
2589         /* On powermac, we have hooks to properly suspend/resume AGP now,
2590          * use them here. We'll ultimately need some generic support here,
2591          * but the generic code isn't quite ready for that yet
2592          */
2593         pmac_suspend_agp_for_card(pdev);
2594 #endif /* CONFIG_PPC_PMAC */
2595
2596         /* If we support wakeup from poweroff, we save all regs we can including cfg
2597          * space
2598          */
2599         if (rinfo->pm_mode & radeon_pm_off) {
2600                 /* Always disable dynamic clocks or weird things are happening when
2601                  * the chip goes off (basically the panel doesn't shut down properly
2602                  * and we crash on wakeup),
2603                  * also, we want the saved regs context to have no dynamic clocks in
2604                  * it, we'll restore the dynamic clocks state on wakeup
2605                  */
2606                 radeon_pm_disable_dynamic_mode(rinfo);
2607                 mdelay(50);
2608                 radeon_pm_save_regs(rinfo, 1);
2609
2610                 if (rinfo->is_mobility && !(rinfo->pm_mode & radeon_pm_d2)) {
2611                         /* Switch off LVDS interface */
2612                         mdelay(1);
2613                         OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & ~(LVDS_BL_MOD_EN));
2614                         mdelay(1);
2615                         OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & ~(LVDS_EN | LVDS_ON));
2616                         OUTREG(LVDS_PLL_CNTL, (INREG(LVDS_PLL_CNTL) & ~30000) | 0x20000);
2617                         mdelay(20);
2618                         OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & ~(LVDS_DIGON));
2619                 }
2620                 // FIXME: Use PCI layer
2621                 for (i = 0; i < 64; ++i)
2622                         pci_read_config_dword(pdev, i * 4, &rinfo->cfg_save[i]);
2623                 pci_disable_device(pdev);
2624         }
2625         /* If we support D2, we go to it (should be fixed later with a flag forcing
2626          * D3 only for some laptops)
2627          */
2628         if (rinfo->pm_mode & radeon_pm_d2)
2629                 radeon_set_suspend(rinfo, 1);
2630
2631         release_console_sem();
2632
2633  done:
2634         pdev->dev.power.power_state = state;
2635
2636         return 0;
2637 }
2638
2639 int radeonfb_pci_resume(struct pci_dev *pdev)
2640 {
2641         struct fb_info *info = pci_get_drvdata(pdev);
2642         struct radeonfb_info *rinfo = info->par;
2643         int rc = 0;
2644
2645         if (pdev->dev.power.power_state.event == PM_EVENT_ON)
2646                 return 0;
2647
2648         if (rinfo->no_schedule) {
2649                 if (try_acquire_console_sem())
2650                         return 0;
2651         } else
2652                 acquire_console_sem();
2653
2654         printk(KERN_DEBUG "radeonfb (%s): resuming from state: %d...\n",
2655                pci_name(pdev), pdev->dev.power.power_state.event);
2656
2657
2658         if (pci_enable_device(pdev)) {
2659                 rc = -ENODEV;
2660                 printk(KERN_ERR "radeonfb (%s): can't enable PCI device !\n",
2661                        pci_name(pdev));
2662                 goto bail;
2663         }
2664         pci_set_master(pdev);
2665
2666         if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
2667                 /* Wakeup chip. Check from config space if we were powered off
2668                  * (todo: additionally, check CLK_PIN_CNTL too)
2669                  */
2670                 if ((rinfo->pm_mode & radeon_pm_off) && radeon_restore_pci_cfg(rinfo)) {
2671                         if (rinfo->reinit_func != NULL)
2672                                 rinfo->reinit_func(rinfo);
2673                         else {
2674                                 printk(KERN_ERR "radeonfb (%s): can't resume radeon from"
2675                                        " D3 cold, need softboot !", pci_name(pdev));
2676                                 rc = -EIO;
2677                                 goto bail;
2678                         }
2679                 }
2680                 /* If we support D2, try to resume... we should check what was our
2681                  * state though... (were we really in D2 state ?). Right now, this code
2682                  * is only enable on Macs so it's fine.
2683                  */
2684                 else if (rinfo->pm_mode & radeon_pm_d2)
2685                         radeon_set_suspend(rinfo, 0);
2686
2687                 rinfo->asleep = 0;
2688         } else
2689                 radeon_engine_idle();
2690
2691         /* Restore display & engine */
2692         radeon_write_mode (rinfo, &rinfo->state, 1);
2693         if (!(info->flags & FBINFO_HWACCEL_DISABLED))
2694                 radeonfb_engine_init (rinfo);
2695
2696         fb_pan_display(info, &info->var);
2697         fb_set_cmap(&info->cmap, info);
2698
2699         /* Refresh */
2700         fb_set_suspend(info, 0);
2701
2702         /* Unblank */
2703         rinfo->lock_blank = 0;
2704         radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 1);
2705
2706 #ifdef CONFIG_PPC_PMAC
2707         /* On powermac, we have hooks to properly suspend/resume AGP now,
2708          * use them here. We'll ultimately need some generic support here,
2709          * but the generic code isn't quite ready for that yet
2710          */
2711         pmac_resume_agp_for_card(pdev);
2712 #endif /* CONFIG_PPC_PMAC */
2713
2714
2715         /* Check status of dynclk */
2716         if (rinfo->dynclk == 1)
2717                 radeon_pm_enable_dynamic_mode(rinfo);
2718         else if (rinfo->dynclk == 0)
2719                 radeon_pm_disable_dynamic_mode(rinfo);
2720
2721         pdev->dev.power.power_state = PMSG_ON;
2722
2723  bail:
2724         release_console_sem();
2725
2726         return rc;
2727 }
2728
2729 #ifdef CONFIG_PPC_OF
2730 static void radeonfb_early_resume(void *data)
2731 {
2732         struct radeonfb_info *rinfo = data;
2733
2734         rinfo->no_schedule = 1;
2735         radeonfb_pci_resume(rinfo->pdev);
2736         rinfo->no_schedule = 0;
2737 }
2738 #endif /* CONFIG_PPC_OF */
2739
2740 #endif /* CONFIG_PM */
2741
2742 void radeonfb_pm_init(struct radeonfb_info *rinfo, int dynclk)
2743 {
2744         /* Find PM registers in config space if any*/
2745         rinfo->pm_reg = pci_find_capability(rinfo->pdev, PCI_CAP_ID_PM);
2746
2747         /* Enable/Disable dynamic clocks: TODO add sysfs access */
2748         rinfo->dynclk = dynclk;
2749         if (dynclk == 1) {
2750                 radeon_pm_enable_dynamic_mode(rinfo);
2751                 printk("radeonfb: Dynamic Clock Power Management enabled\n");
2752         } else if (dynclk == 0) {
2753                 radeon_pm_disable_dynamic_mode(rinfo);
2754                 printk("radeonfb: Dynamic Clock Power Management disabled\n");
2755         }
2756
2757 #if defined(CONFIG_PM)
2758         /* Check if we can power manage on suspend/resume. We can do
2759          * D2 on M6, M7 and M9, and we can resume from D3 cold a few other
2760          * "Mac" cards, but that's all. We need more infos about what the
2761          * BIOS does tho. Right now, all this PM stuff is pmac-only for that
2762          * reason. --BenH
2763          */
2764         /* Special case for Samsung P35 laptops
2765          */
2766         if ((rinfo->pdev->vendor == PCI_VENDOR_ID_ATI) &&
2767             (rinfo->pdev->device == PCI_CHIP_RV350_NP) &&
2768             (rinfo->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG) &&
2769             (rinfo->pdev->subsystem_device == 0xc00c)) {
2770                 rinfo->reinit_func = radeon_reinitialize_M10;
2771                 rinfo->pm_mode |= radeon_pm_off;
2772         }
2773 #if defined(CONFIG_PPC_PMAC)
2774         if (machine_is(powermac) && rinfo->of_node) {
2775                 if (rinfo->is_mobility && rinfo->pm_reg &&
2776                     rinfo->family <= CHIP_FAMILY_RV250)
2777                         rinfo->pm_mode |= radeon_pm_d2;
2778
2779                 /* We can restart Jasper (M10 chip in albooks), BlueStone (7500 chip
2780                  * in some desktop G4s), Via (M9+ chip on iBook G4) and
2781                  * Snowy (M11 chip on iBook G4 manufactured after July 2005)
2782                  */
2783                 if (!strcmp(rinfo->of_node->name, "ATY,JasperParent") ||
2784                     !strcmp(rinfo->of_node->name, "ATY,SnowyParent")) {
2785                         rinfo->reinit_func = radeon_reinitialize_M10;
2786                         rinfo->pm_mode |= radeon_pm_off;
2787                 }
2788 #if 0 /* Not ready yet */
2789                 if (!strcmp(rinfo->of_node->name, "ATY,BlueStoneParent")) {
2790                         rinfo->reinit_func = radeon_reinitialize_QW;
2791                         rinfo->pm_mode |= radeon_pm_off;
2792                 }
2793 #endif
2794                 if (!strcmp(rinfo->of_node->name, "ATY,ViaParent")) {
2795                         rinfo->reinit_func = radeon_reinitialize_M9P;
2796                         rinfo->pm_mode |= radeon_pm_off;
2797                 }
2798
2799                 /* If any of the above is set, we assume the machine can sleep/resume.
2800                  * It's a bit of a "shortcut" but will work fine. Ideally, we need infos
2801                  * from the platform about what happens to the chip...
2802                  * Now we tell the platform about our capability
2803                  */
2804                 if (rinfo->pm_mode != radeon_pm_none) {
2805                         pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE, rinfo->of_node, 0, 1);
2806                         pmac_set_early_video_resume(radeonfb_early_resume, rinfo);
2807                 }
2808
2809 #if 0
2810                 /* Power down TV DAC, taht saves a significant amount of power,
2811                  * we'll have something better once we actually have some TVOut
2812                  * support
2813                  */
2814                 OUTREG(TV_DAC_CNTL, INREG(TV_DAC_CNTL) | 0x07000000);
2815 #endif
2816         }
2817 #endif /* defined(CONFIG_PPC_PMAC) */
2818 #endif /* defined(CONFIG_PM) */
2819
2820 /* The PM code also works on some PC laptops.
2821  * Only a few models are actually tested so Your mileage may vary.
2822  * We can do D2 on at least M7 and M9 on some IBM ThinkPad T41 models.
2823  */
2824 #if defined(CONFIG_PM) && defined(CONFIG_X86)
2825         if (radeon_force_sleep || dmi_check_system(radeonfb_dmi_table)) {
2826                 if (radeon_force_sleep)
2827                         printk("radeonfb: forcefully enabling sleep mode\n");
2828                 else
2829                         printk("radeonfb: enabling sleep mode\n");
2830
2831                 if (rinfo->is_mobility && rinfo->pm_reg &&
2832                     rinfo->family <= CHIP_FAMILY_RV250)
2833                         rinfo->pm_mode |= radeon_pm_d2;
2834
2835                 /* Power down TV DAC, that saves a significant amount of power,
2836                  * we'll have something better once we actually have some TVOut
2837                  * support
2838                  */
2839                 OUTREG(TV_DAC_CNTL, INREG(TV_DAC_CNTL) | 0x07000000);
2840         }
2841 #endif /* defined(CONFIG_PM) && defined(CONFIG_X86) */
2842 }
2843
2844 void radeonfb_pm_exit(struct radeonfb_info *rinfo)
2845 {
2846 #if defined(CONFIG_PM) && defined(CONFIG_PPC_PMAC)
2847         if (rinfo->pm_mode != radeon_pm_none)
2848                 pmac_set_early_video_resume(NULL, NULL);
2849 #endif
2850 }