drivers/video/aty/radeonfb.h

   1 #ifndef __RADEONFB_H__
   2 #define __RADEONFB_H__
   3
   4 #include <linux/config.h>
   5 #include <linux/module.h>
   6 #include <linux/kernel.h>
   7 #include <linux/sched.h>
   8 #include <linux/delay.h>
   9 #include <linux/pci.h>
  10 #include <linux/fb.h>
  11
  12
  13 #include <linux/i2c.h>
  14 #include <linux/i2c-id.h>
  15 #include <linux/i2c-algo-bit.h>
  16
  17 #include <asm/io.h>
  18
  19 #ifdef CONFIG_PPC_OF
  20 #include <asm/prom.h>
  21 #endif
  22
  23 #include <video/radeon.h>
  24
  25 /* Some weird black magic use by Apple driver that we don't use for
  26  * now --BenH
  27  */
  28 #undef HAS_PLL_M9_GPIO_MAGIC
  29
  30 /***************************************************************
  31  * Most of the definitions here are adapted right from XFree86 *
  32  ***************************************************************/
  33
  34
  35 /*
  36  * Chip families. Must fit in the low 16 bits of a long word
  37  */
  38 enum radeon_family {
  39         CHIP_FAMILY_UNKNOW,
  40         CHIP_FAMILY_LEGACY,
  41         CHIP_FAMILY_RADEON,
  42         CHIP_FAMILY_RV100,
  43         CHIP_FAMILY_RS100,    /* U1 (IGP320M) or A3 (IGP320)*/
  44         CHIP_FAMILY_RV200,
  45         CHIP_FAMILY_RS200,    /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350),
  46                                  RS250 (IGP 7000) */
  47         CHIP_FAMILY_R200,
  48         CHIP_FAMILY_RV250,
  49         CHIP_FAMILY_RS300,    /* Radeon 9000 IGP */
  50         CHIP_FAMILY_RV280,
  51         CHIP_FAMILY_R300,
  52         CHIP_FAMILY_R350,
  53         CHIP_FAMILY_RV350,
  54         CHIP_FAMILY_RV380,    /* RV370/RV380/M22/M24 */
  55         CHIP_FAMILY_R420,     /* R420/R423/M18 */
  56         CHIP_FAMILY_LAST,
  57 };
  58
  59 #define IS_RV100_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_RV100)  || \
  60                                  ((rinfo)->family == CHIP_FAMILY_RV200)  || \
  61                                  ((rinfo)->family == CHIP_FAMILY_RS100)  || \
  62                                  ((rinfo)->family == CHIP_FAMILY_RS200)  || \
  63                                  ((rinfo)->family == CHIP_FAMILY_RV250)  || \
  64                                  ((rinfo)->family == CHIP_FAMILY_RV280)  || \
  65                                  ((rinfo)->family == CHIP_FAMILY_RS300))
  66
  67
  68 #define IS_R300_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_R300)  || \
  69                                 ((rinfo)->family == CHIP_FAMILY_RV350) || \
  70                                 ((rinfo)->family == CHIP_FAMILY_R350)  || \
  71                                 ((rinfo)->family == CHIP_FAMILY_RV380) || \
  72                                 ((rinfo)->family == CHIP_FAMILY_R420))
  73
  74 /*
  75  * Chip flags
  76  */
  77 enum radeon_chip_flags {
  78         CHIP_FAMILY_MASK        = 0x0000ffffUL,
  79         CHIP_FLAGS_MASK         = 0xffff0000UL,
  80         CHIP_IS_MOBILITY        = 0x00010000UL,
  81         CHIP_IS_IGP             = 0x00020000UL,
  82         CHIP_HAS_CRTC2          = 0x00040000UL,
  83 };
  84
  85
  86 /*
  87  * Monitor types
  88  */
  89 enum radeon_montype {
  90         MT_NONE = 0,
  91         MT_CRT,         /* CRT */
  92         MT_LCD,         /* LCD */
  93         MT_DFP,         /* DVI */
  94         MT_CTV,         /* composite TV */
  95         MT_STV          /* S-Video out */
  96 };
  97
  98 /*
  99  * DDC i2c ports
 100  */
 101 enum ddc_type {
 102         ddc_none,
 103         ddc_monid,
 104         ddc_dvi,
 105         ddc_vga,
 106         ddc_crt2,
 107 };
 108
 109 /*
 110  * Connector types
 111  */
 112 enum conn_type {
 113         conn_none,
 114         conn_proprietary,
 115         conn_crt,
 116         conn_DVI_I,
 117         conn_DVI_D,
 118 };
 119
 120
 121 /*
 122  * PLL infos
 123  */
 124 struct pll_info {
 125         int ppll_max;
 126         int ppll_min;
 127         int sclk, mclk;
 128         int ref_div;
 129         int ref_clk;
 130 };
 131
 132
 133 /*
 134  * This structure contains the various registers manipulated by this
 135  * driver for setting or restoring a mode. It's mostly copied from
 136  * XFree's RADEONSaveRec structure. A few chip settings might still be
 137  * tweaked without beeing reflected or saved in these registers though
 138  */
 139 struct radeon_regs {
 140         /* Common registers */
 141         u32             ovr_clr;
 142         u32             ovr_wid_left_right;
 143         u32             ovr_wid_top_bottom;
 144         u32             ov0_scale_cntl;
 145         u32             mpp_tb_config;
 146         u32             mpp_gp_config;
 147         u32             subpic_cntl;
 148         u32             viph_control;
 149         u32             i2c_cntl_1;
 150         u32             gen_int_cntl;
 151         u32             cap0_trig_cntl;
 152         u32             cap1_trig_cntl;
 153         u32             bus_cntl;
 154         u32             surface_cntl;
 155         u32             bios_5_scratch;
 156
 157         /* Other registers to save for VT switches or driver load/unload */
 158         u32             dp_datatype;
 159         u32             rbbm_soft_reset;
 160         u32             clock_cntl_index;
 161         u32             amcgpio_en_reg;
 162         u32             amcgpio_mask;
 163
 164         /* Surface/tiling registers */
 165         u32             surf_lower_bound[8];
 166         u32             surf_upper_bound[8];
 167         u32             surf_info[8];
 168
 169         /* CRTC registers */
 170         u32             crtc_gen_cntl;
 171         u32             crtc_ext_cntl;
 172         u32             dac_cntl;
 173         u32             crtc_h_total_disp;
 174         u32             crtc_h_sync_strt_wid;
 175         u32             crtc_v_total_disp;
 176         u32             crtc_v_sync_strt_wid;
 177         u32             crtc_offset;
 178         u32             crtc_offset_cntl;
 179         u32             crtc_pitch;
 180         u32             disp_merge_cntl;
 181         u32             grph_buffer_cntl;
 182         u32             crtc_more_cntl;
 183
 184         /* CRTC2 registers */
 185         u32             crtc2_gen_cntl;
 186         u32             dac2_cntl;
 187         u32             disp_output_cntl;
 188         u32             disp_hw_debug;
 189         u32             disp2_merge_cntl;
 190         u32             grph2_buffer_cntl;
 191         u32             crtc2_h_total_disp;
 192         u32             crtc2_h_sync_strt_wid;
 193         u32             crtc2_v_total_disp;
 194         u32             crtc2_v_sync_strt_wid;
 195         u32             crtc2_offset;
 196         u32             crtc2_offset_cntl;
 197         u32             crtc2_pitch;
 198
 199         /* Flat panel regs */
 200         u32             fp_crtc_h_total_disp;
 201         u32             fp_crtc_v_total_disp;
 202         u32             fp_gen_cntl;
 203         u32             fp2_gen_cntl;
 204         u32             fp_h_sync_strt_wid;
 205         u32             fp2_h_sync_strt_wid;
 206         u32             fp_horz_stretch;
 207         u32             fp_panel_cntl;
 208         u32             fp_v_sync_strt_wid;
 209         u32             fp2_v_sync_strt_wid;
 210         u32             fp_vert_stretch;
 211         u32             lvds_gen_cntl;
 212         u32             lvds_pll_cntl;
 213         u32             tmds_crc;
 214         u32             tmds_transmitter_cntl;
 215
 216         /* Computed values for PLL */
 217         u32             dot_clock_freq;
 218         int             feedback_div;
 219         int             post_div;
 220
 221         /* PLL registers */
 222         u32             ppll_div_3;
 223         u32             ppll_ref_div;
 224         u32             vclk_ecp_cntl;
 225         u32             clk_cntl_index;
 226
 227         /* Computed values for PLL2 */
 228         u32             dot_clock_freq_2;
 229         int             feedback_div_2;
 230         int             post_div_2;
 231
 232         /* PLL2 registers */
 233         u32             p2pll_ref_div;
 234         u32             p2pll_div_0;
 235         u32             htotal_cntl2;
 236
 237         /* Palette */
 238         int             palette_valid;
 239 };
 240
 241 struct panel_info {
 242         int xres, yres;
 243         int valid;
 244         int clock;
 245         int hOver_plus, hSync_width, hblank;
 246         int vOver_plus, vSync_width, vblank;
 247         int hAct_high, vAct_high, interlaced;
 248         int pwr_delay;
 249         int use_bios_dividers;
 250         int ref_divider;
 251         int post_divider;
 252         int fbk_divider;
 253 };
 254
 255 struct radeonfb_info;
 256
 257 #ifdef CONFIG_FB_RADEON_I2C
 258 struct radeon_i2c_chan {
 259         struct radeonfb_info            *rinfo;
 260         u32                             ddc_reg;
 261         struct i2c_adapter              adapter;
 262         struct i2c_algo_bit_data        algo;
 263 };
 264 #endif
 265
 266 enum radeon_pm_mode {
 267         radeon_pm_none  = 0,            /* Nothing supported */
 268         radeon_pm_d2    = 0x00000001,   /* Can do D2 state */
 269         radeon_pm_off   = 0x00000002,   /* Can resume from D3 cold */
 270 };
 271
 272 struct radeonfb_info {
 273         struct fb_info          *info;
 274
 275         struct radeon_regs      state;
 276         struct radeon_regs      init_state;
 277
 278         char                    name[DEVICE_NAME_SIZE];
 279
 280         unsigned long           mmio_base_phys;
 281         unsigned long           fb_base_phys;
 282
 283         void __iomem            *mmio_base;
 284         void __iomem            *fb_base;
 285
 286         unsigned long           fb_local_base;
 287
 288         struct pci_dev          *pdev;
 289 #ifdef CONFIG_PPC_OF
 290         struct device_node      *of_node;
 291 #endif
 292
 293         void __iomem            *bios_seg;
 294         int                     fp_bios_start;
 295
 296         u32                     pseudo_palette[17];
 297         struct { u8 red, green, blue, pad; }
 298                                 palette[256];
 299
 300         int                     chipset;
 301         u8                      family;
 302         u8                      rev;
 303         unsigned long           video_ram;
 304         unsigned long           mapped_vram;
 305         int                     vram_width;
 306         int                     vram_ddr;
 307
 308         int                     pitch, bpp, depth;
 309
 310         int                     has_CRTC2;
 311         int                     is_mobility;
 312         int                     is_IGP;
 313         int                     R300_cg_workaround;
 314         int                     m9p_workaround;
 315         int                     reversed_DAC;
 316         int                     reversed_TMDS;
 317         struct panel_info       panel_info;
 318         int                     mon1_type;
 319         u8                      *mon1_EDID;
 320         struct fb_videomode     *mon1_modedb;
 321         int                     mon1_dbsize;
 322         int                     mon2_type;
 323         u8                      *mon2_EDID;
 324
 325         u32                     dp_gui_master_cntl;
 326
 327         struct pll_info         pll;
 328
 329         int                     mtrr_hdl;
 330
 331         int                     pm_reg;
 332         u32                     save_regs[100];
 333         int                     asleep;
 334         int                     lock_blank;
 335         int                     dynclk;
 336         int                     no_schedule;
 337         enum radeon_pm_mode     pm_mode;
 338         void                    (*reinit_func)(struct radeonfb_info *rinfo);
 339
 340         /* Lock on register access */
 341         spinlock_t              reg_lock;
 342
 343         /* Timer used for delayed LVDS operations */
 344         struct timer_list       lvds_timer;
 345         u32                     pending_lvds_gen_cntl;
 346
 347 #ifdef CONFIG_FB_RADEON_I2C
 348         struct radeon_i2c_chan  i2c[4];
 349 #endif
 350
 351         u32                     cfg_save[64];
 352 };
 353
 354
 355 #define PRIMARY_MONITOR(rinfo)  (rinfo->mon1_type)
 356
 357
 358 /*
 359  * Debugging stuffs
 360  */
 361 #ifdef CONFIG_FB_RADEON_DEBUG
 362 #define DEBUG           1
 363 #else
 364 #define DEBUG           0
 365 #endif
 366
 367 #if DEBUG
 368 #define RTRACE          printk
 369 #else
 370 #define RTRACE          if(0) printk
 371 #endif
 372
 373
 374 /*
 375  * IO macros
 376  */
 377
 378 #define INREG8(addr)            readb((rinfo->mmio_base)+addr)
 379 #define OUTREG8(addr,val)       writeb(val, (rinfo->mmio_base)+addr)
 380 #define INREG(addr)             readl((rinfo->mmio_base)+addr)
 381 #define OUTREG(addr,val)        writel(val, (rinfo->mmio_base)+addr)
 382
 383 static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr,
 384                        u32 val, u32 mask)
 385 {
 386         unsigned long flags;
 387         unsigned int tmp;
 388
 389         spin_lock_irqsave(&rinfo->reg_lock, flags);
 390         tmp = INREG(addr);
 391         tmp &= (mask);
 392         tmp |= (val);
 393         OUTREG(addr, tmp);
 394         spin_unlock_irqrestore(&rinfo->reg_lock, flags);
 395 }
 396
 397 #define OUTREGP(addr,val,mask)  _OUTREGP(rinfo, addr, val,mask)
 398
 399 static inline void R300_cg_workardound(struct radeonfb_info *rinfo)
 400 {
 401         u32 save, tmp;
 402         save = INREG(CLOCK_CNTL_INDEX);
 403         tmp = save & ~(0x3f | PLL_WR_EN);
 404         OUTREG(CLOCK_CNTL_INDEX, tmp);
 405         tmp = INREG(CLOCK_CNTL_DATA);
 406         OUTREG(CLOCK_CNTL_INDEX, save);
 407 }
 408
 409
 410 static inline u32 __INPLL(struct radeonfb_info *rinfo, u32 addr)
 411 {
 412         u32 data;
 413 #ifdef HAS_PLL_M9_GPIO_MAGIC
 414         u32 sv[3];
 415
 416         if (rinfo->m9p_workaround) {
 417                 sv[0] = INREG(0x19c);
 418                 sv[1] = INREG(0x1a0);
 419                 sv[2] = INREG(0x198);
 420                 OUTREG(0x198, 0);
 421                 OUTREG(0x1a0, 0);
 422                 OUTREG(0x19c, 0);
 423         }
 424 #endif /* HAS_PLL_M9_GPIO_MAGIC */
 425
 426         OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f);
 427         data = (INREG(CLOCK_CNTL_DATA));
 428
 429 #ifdef HAS_PLL_M9_GPIO_MAGIC
 430         if (rinfo->m9p_workaround) {
 431                 (void)INREG(CRTC_GEN_CNTL);
 432                 data = INREG(CLOCK_CNTL_DATA);
 433                 OUTREG(0x19c, sv[0]);
 434                 OUTREG(0x1a0, sv[1]);
 435                 OUTREG(0x198, sv[2]);
 436         }
 437 #endif /* HAS_PLL_M9_GPIO_MAGIC */
 438         if (rinfo->R300_cg_workaround)
 439                 R300_cg_workardound(rinfo);
 440         return data;
 441 }
 442
 443 static inline u32 _INPLL(struct radeonfb_info *rinfo, u32 addr)
 444 {
 445         unsigned long flags;
 446         u32 data;
 447
 448         spin_lock_irqsave(&rinfo->reg_lock, flags);
 449         data = __INPLL(rinfo, addr);
 450         spin_unlock_irqrestore(&rinfo->reg_lock, flags);
 451         return data;
 452 }
 453
 454 #define INPLL(addr)             _INPLL(rinfo, addr)
 455
 456
 457 static inline void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index, u32 val)
 458 {
 459 #ifdef HAS_PLL_M9_GPIO_MAGIC
 460         u32 sv[3];
 461
 462         if (rinfo->m9p_workaround) {
 463                 sv[0] = INREG(0x19c);
 464                 sv[1] = INREG(0x1a0);
 465                 sv[2] = INREG(0x198);
 466                 OUTREG(0x198, 0);
 467                 OUTREG(0x1a0, 0);
 468                 OUTREG(0x19c, 0);
 469                 mdelay(1);
 470         }
 471 #endif /* HAS_PLL_M9_GPIO_MAGIC */
 472
 473         OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) | 0x00000080);
 474         OUTREG(CLOCK_CNTL_DATA, val);
 475
 476 #ifdef HAS_PLL_M9_GPIO_MAGIC
 477         if (rinfo->m9p_workaround) {
 478                 OUTREG(0x19c, sv[0]);
 479                 OUTREG(0x1a0, sv[1]);
 480                 OUTREG(0x198, sv[2]);
 481         }
 482 #endif /* HAS_PLL_M9_GPIO_MAGIC */
 483 }
 484
 485 static inline void _OUTPLL(struct radeonfb_info *rinfo, unsigned int index, u32 val)
 486 {
 487         unsigned long flags;
 488         spin_lock_irqsave(&rinfo->reg_lock, flags);
 489         __OUTPLL(rinfo, index, val);
 490         spin_unlock_irqrestore(&rinfo->reg_lock, flags);
 491 }
 492
 493 static inline void _OUTPLLP(struct radeonfb_info *rinfo, unsigned int index,
 494                             u32 val, u32 mask)
 495 {
 496         unsigned long flags;
 497         unsigned int tmp;
 498
 499         spin_lock_irqsave(&rinfo->reg_lock, flags);
 500         tmp  = __INPLL(rinfo, index);
 501         tmp &= (mask);
 502         tmp |= (val);
 503         __OUTPLL(rinfo, index, tmp);
 504         spin_unlock_irqrestore(&rinfo->reg_lock, flags);
 505 }
 506
 507
 508 #define OUTPLL(index, val)              _OUTPLL(rinfo, index, val)
 509 #define OUTPLLP(index, val, mask)       _OUTPLLP(rinfo, index, val, mask)
 510
 511
 512 #define BIOS_IN8(v)     (readb(rinfo->bios_seg + (v)))
 513 #define BIOS_IN16(v)    (readb(rinfo->bios_seg + (v)) | \
 514                           (readb(rinfo->bios_seg + (v) + 1) << 8))
 515 #define BIOS_IN32(v)    (readb(rinfo->bios_seg + (v)) | \
 516                           (readb(rinfo->bios_seg + (v) + 1) << 8) | \
 517                           (readb(rinfo->bios_seg + (v) + 2) << 16) | \
 518                           (readb(rinfo->bios_seg + (v) + 3) << 24))
 519
 520 /*
 521  * Inline utilities
 522  */
 523 static inline int round_div(int num, int den)
 524 {
 525         return (num + (den / 2)) / den;
 526 }
 527
 528 static inline int var_to_depth(const struct fb_var_screeninfo *var)
 529 {
 530         if (var->bits_per_pixel != 16)
 531                 return var->bits_per_pixel;
 532         return (var->green.length == 5) ? 15 : 16;
 533 }
 534
 535 static inline u32 radeon_get_dstbpp(u16 depth)
 536 {
 537         switch (depth) {
 538         case 8:
 539                 return DST_8BPP;
 540         case 15:
 541                 return DST_15BPP;
 542         case 16:
 543                 return DST_16BPP;
 544         case 32:
 545                 return DST_32BPP;
 546         default:
 547                 return 0;
 548         }
 549 }
 550
 551 /*
 552  * 2D Engine helper routines
 553  */
 554 static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
 555 {
 556         int i;
 557
 558         /* initiate flush */
 559         OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
 560                 ~RB2D_DC_FLUSH_ALL);
 561
 562         for (i=0; i < 2000000; i++) {
 563                 if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
 564                         return;
 565                 udelay(1);
 566         }
 567         printk(KERN_ERR "radeonfb: Flush Timeout !\n");
 568 }
 569
 570
 571 static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries)
 572 {
 573         int i;
 574
 575         for (i=0; i<2000000; i++) {
 576                 if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
 577                         return;
 578                 udelay(1);
 579         }
 580         printk(KERN_ERR "radeonfb: FIFO Timeout !\n");
 581 }
 582
 583
 584 static inline void _radeon_engine_idle(struct radeonfb_info *rinfo)
 585 {
 586         int i;
 587
 588         /* ensure FIFO is empty before waiting for idle */
 589         _radeon_fifo_wait (rinfo, 64);
 590
 591         for (i=0; i<2000000; i++) {
 592                 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
 593                         radeon_engine_flush (rinfo);
 594                         return;
 595                 }
 596                 udelay(1);
 597         }
 598         printk(KERN_ERR "radeonfb: Idle Timeout !\n");
 599 }
 600
 601 /* Note about this function: we have some rare cases where we must not schedule,
 602  * this typically happen with our special "wake up early" hook which allows us to
 603  * wake up the graphic chip (and thus get the console back) before everything else
 604  * on some machines that support that mecanism. At this point, interrupts are off
 605  * and scheduling is not permitted
 606  */
 607 static inline void _radeon_msleep(struct radeonfb_info *rinfo, unsigned long ms)
 608 {
 609         if (rinfo->no_schedule)
 610                 mdelay(ms);
 611         else
 612                 msleep(ms);
 613 }
 614
 615
 616 #define radeon_engine_idle()            _radeon_engine_idle(rinfo)
 617 #define radeon_fifo_wait(entries)       _radeon_fifo_wait(rinfo,entries)
 618 #define radeon_msleep(ms)               _radeon_msleep(rinfo,ms)
 619
 620
 621 /* I2C Functions */
 622 extern void radeon_create_i2c_busses(struct radeonfb_info *rinfo);
 623 extern void radeon_delete_i2c_busses(struct radeonfb_info *rinfo);
 624 extern int radeon_probe_i2c_connector(struct radeonfb_info *rinfo, int conn, u8 **out_edid);
 625
 626 /* PM Functions */
 627 extern int radeonfb_pci_suspend(struct pci_dev *pdev, u32 state);
 628 extern int radeonfb_pci_resume(struct pci_dev *pdev);
 629 extern void radeonfb_pm_init(struct radeonfb_info *rinfo, int dynclk);
 630 extern void radeonfb_pm_exit(struct radeonfb_info *rinfo);
 631
 632 /* Monitor probe functions */
 633 extern void radeon_probe_screens(struct radeonfb_info *rinfo,
 634                                  const char *monitor_layout, int ignore_edid);
 635 extern void radeon_check_modes(struct radeonfb_info *rinfo, const char *mode_option);
 636 extern int radeon_match_mode(struct radeonfb_info *rinfo,
 637                              struct fb_var_screeninfo *dest,
 638                              const struct fb_var_screeninfo *src);
 639
 640 /* Accel functions */
 641 extern void radeonfb_fillrect(struct fb_info *info, const struct fb_fillrect *region);
 642 extern void radeonfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
 643 extern void radeonfb_imageblit(struct fb_info *p, const struct fb_image *image);
 644 extern int radeonfb_sync(struct fb_info *info);
 645 extern void radeonfb_engine_init (struct radeonfb_info *rinfo);
 646 extern void radeonfb_engine_reset(struct radeonfb_info *rinfo);
 647
 648 /* Other functions */
 649 extern int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch);
 650 extern void radeon_save_state (struct radeonfb_info *rinfo, struct radeon_regs *save);
 651 extern void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
 652                                int reg_only);
 653
 654 #endif /* __RADEONFB_H__ */