drivers/video/aty/radeonfb.h

   1 #ifndef __RADEONFB_H__
   2 #define __RADEONFB_H__
   3
   4 #include <linux/config.h>
   5 #include <linux/module.h>
   6 #include <linux/kernel.h>
   7 #include <linux/sched.h>
   8 #include <linux/delay.h>
   9 #include <linux/pci.h>
  10 #include <linux/fb.h>
  11
  12
  13 #include <linux/i2c.h>
  14 #include <linux/i2c-id.h>
  15 #include <linux/i2c-algo-bit.h>
  16
  17 #include <asm/io.h>
  18
  19 #include <video/radeon.h>
  20
  21 /***************************************************************
  22  * Most of the definitions here are adapted right from XFree86 *
  23  ***************************************************************/
  24
  25
  26 /*
  27  * Chip families. Must fit in the low 16 bits of a long word
  28  */
  29 enum radeon_family {
  30         CHIP_FAMILY_UNKNOW,
  31         CHIP_FAMILY_LEGACY,
  32         CHIP_FAMILY_RADEON,
  33         CHIP_FAMILY_RV100,
  34         CHIP_FAMILY_RS100,    /* U1 (IGP320M) or A3 (IGP320)*/
  35         CHIP_FAMILY_RV200,
  36         CHIP_FAMILY_RS200,    /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350), RS250 (IGP 7000) */
  37         CHIP_FAMILY_R200,
  38         CHIP_FAMILY_RV250,
  39         CHIP_FAMILY_RS300,    /* Radeon 9000 IGP */
  40         CHIP_FAMILY_RV280,
  41         CHIP_FAMILY_R300,
  42         CHIP_FAMILY_R350,
  43         CHIP_FAMILY_RV350,
  44         CHIP_FAMILY_LAST,
  45 };
  46
  47 /*
  48  * Chip flags
  49  */
  50 enum radeon_chip_flags {
  51         CHIP_FAMILY_MASK        = 0x0000ffffUL,
  52         CHIP_FLAGS_MASK         = 0xffff0000UL,
  53         CHIP_IS_MOBILITY        = 0x00010000UL,
  54         CHIP_IS_IGP             = 0x00020000UL,
  55         CHIP_HAS_CRTC2          = 0x00040000UL,
  56 };
  57
  58
  59 /*
  60  * Monitor types
  61  */
  62 enum radeon_montype {
  63         MT_NONE = 0,
  64         MT_CRT,         /* CRT */
  65         MT_LCD,         /* LCD */
  66         MT_DFP,         /* DVI */
  67         MT_CTV,         /* composite TV */
  68         MT_STV          /* S-Video out */
  69 };
  70
  71 /*
  72  * DDC i2c ports
  73  */
  74 enum ddc_type {
  75         ddc_none,
  76         ddc_monid,
  77         ddc_dvi,
  78         ddc_vga,
  79         ddc_crt2,
  80 };
  81
  82 /*
  83  * Connector types
  84  */
  85 enum conn_type {
  86         conn_none,
  87         conn_proprietary,
  88         conn_crt,
  89         conn_DVI_I,
  90         conn_DVI_D,
  91 };
  92
  93
  94 /*
  95  * PLL infos
  96  */
  97 struct pll_info {
  98         int ppll_max;
  99         int ppll_min;
 100         int sclk, mclk;
 101         int ref_div;
 102         int ref_clk;
 103 };
 104
 105 /*
 106  * VRAM infos
 107  */
 108 struct ram_info {
 109         int ml;
 110         int mb;
 111         int trcd;
 112         int trp;
 113         int twr;
 114         int cl;
 115         int tr2w;
 116         int loop_latency;
 117         int rloop;
 118 };
 119
 120
 121 /*
 122  * This structure contains the various registers manipulated by this
 123  * driver for setting or restoring a mode. It's mostly copied from
 124  * XFree's RADEONSaveRec structure. A few chip settings might still be
 125  * tweaked without beeing reflected or saved in these registers though
 126  */
 127 struct radeon_regs {
 128         /* Common registers */
 129         u32             ovr_clr;
 130         u32             ovr_wid_left_right;
 131         u32             ovr_wid_top_bottom;
 132         u32             ov0_scale_cntl;
 133         u32             mpp_tb_config;
 134         u32             mpp_gp_config;
 135         u32             subpic_cntl;
 136         u32             viph_control;
 137         u32             i2c_cntl_1;
 138         u32             gen_int_cntl;
 139         u32             cap0_trig_cntl;
 140         u32             cap1_trig_cntl;
 141         u32             bus_cntl;
 142         u32             surface_cntl;
 143         u32             bios_5_scratch;
 144
 145         /* Other registers to save for VT switches or driver load/unload */
 146         u32             dp_datatype;
 147         u32             rbbm_soft_reset;
 148         u32             clock_cntl_index;
 149         u32             amcgpio_en_reg;
 150         u32             amcgpio_mask;
 151
 152         /* Surface/tiling registers */
 153         u32             surf_lower_bound[8];
 154         u32             surf_upper_bound[8];
 155         u32             surf_info[8];
 156
 157         /* CRTC registers */
 158         u32             crtc_gen_cntl;
 159         u32             crtc_ext_cntl;
 160         u32             dac_cntl;
 161         u32             crtc_h_total_disp;
 162         u32             crtc_h_sync_strt_wid;
 163         u32             crtc_v_total_disp;
 164         u32             crtc_v_sync_strt_wid;
 165         u32             crtc_offset;
 166         u32             crtc_offset_cntl;
 167         u32             crtc_pitch;
 168         u32             disp_merge_cntl;
 169         u32             grph_buffer_cntl;
 170         u32             crtc_more_cntl;
 171
 172         /* CRTC2 registers */
 173         u32             crtc2_gen_cntl;
 174         u32             dac2_cntl;
 175         u32             disp_output_cntl;
 176         u32             disp_hw_debug;
 177         u32             disp2_merge_cntl;
 178         u32             grph2_buffer_cntl;
 179         u32             crtc2_h_total_disp;
 180         u32             crtc2_h_sync_strt_wid;
 181         u32             crtc2_v_total_disp;
 182         u32             crtc2_v_sync_strt_wid;
 183         u32             crtc2_offset;
 184         u32             crtc2_offset_cntl;
 185         u32             crtc2_pitch;
 186
 187         /* Flat panel regs */
 188         u32             fp_crtc_h_total_disp;
 189         u32             fp_crtc_v_total_disp;
 190         u32             fp_gen_cntl;
 191         u32             fp2_gen_cntl;
 192         u32             fp_h_sync_strt_wid;
 193         u32             fp2_h_sync_strt_wid;
 194         u32             fp_horz_stretch;
 195         u32             fp_panel_cntl;
 196         u32             fp_v_sync_strt_wid;
 197         u32             fp2_v_sync_strt_wid;
 198         u32             fp_vert_stretch;
 199         u32             lvds_gen_cntl;
 200         u32             lvds_pll_cntl;
 201         u32             tmds_crc;
 202         u32             tmds_transmitter_cntl;
 203
 204         /* Computed values for PLL */
 205         u32             dot_clock_freq;
 206         int             feedback_div;
 207         int             post_div;
 208
 209         /* PLL registers */
 210         u32             ppll_div_3;
 211         u32             ppll_ref_div;
 212         u32             vclk_ecp_cntl;
 213
 214         /* Computed values for PLL2 */
 215         u32             dot_clock_freq_2;
 216         int             feedback_div_2;
 217         int             post_div_2;
 218
 219         /* PLL2 registers */
 220         u32             p2pll_ref_div;
 221         u32             p2pll_div_0;
 222         u32             htotal_cntl2;
 223
 224         /* Palette */
 225         int             palette_valid;
 226         u32             palette[256];
 227         u32             palette2[256];
 228 };
 229
 230 struct panel_info {
 231         int xres, yres;
 232         int valid;
 233         int clock;
 234         int hOver_plus, hSync_width, hblank;
 235         int vOver_plus, vSync_width, vblank;
 236         int hAct_high, vAct_high, interlaced;
 237         int pwr_delay;
 238         int use_bios_dividers;
 239         int ref_divider;
 240         int post_divider;
 241         int fbk_divider;
 242 };
 243
 244 struct radeonfb_info;
 245
 246 #ifdef CONFIG_FB_RADEON_I2C
 247 struct radeon_i2c_chan {
 248         struct radeonfb_info            *rinfo;
 249         u32                             ddc_reg;
 250         struct i2c_adapter              adapter;
 251         struct i2c_algo_bit_data        algo;
 252 };
 253 #endif
 254
 255 struct radeonfb_info {
 256         struct fb_info          *info;
 257
 258         struct radeon_regs      state;
 259         struct radeon_regs      init_state;
 260
 261         char                    name[DEVICE_NAME_SIZE];
 262         char                    ram_type[12];
 263
 264         unsigned long           mmio_base_phys;
 265         unsigned long           fb_base_phys;
 266
 267         unsigned long           mmio_base;
 268         unsigned long           fb_base;
 269
 270         unsigned long           fb_local_base;
 271
 272         struct pci_dev          *pdev;
 273
 274         u8                      *bios_seg;
 275         int                     fp_bios_start;
 276
 277         u32                     pseudo_palette[17];
 278         struct { u8 red, green, blue, pad; }
 279                                 palette[256];
 280
 281         int                     chipset;
 282         u8                      family;
 283         u8                      rev;
 284         unsigned long           video_ram;
 285         unsigned long           mapped_vram;
 286
 287         int                     pitch, bpp, depth;
 288
 289         int                     has_CRTC2;
 290         int                     is_mobility;
 291         int                     is_IGP;
 292         int                     R300_cg_workaround;
 293         int                     reversed_DAC;
 294         int                     reversed_TMDS;
 295         struct panel_info       panel_info;
 296         int                     mon1_type;
 297         u8                      *mon1_EDID;
 298         struct fb_videomode     *mon1_modedb;
 299         int                     mon1_dbsize;
 300         int                     mon2_type;
 301         u8                      *mon2_EDID;
 302
 303         u32                     dp_gui_master_cntl;
 304
 305         struct pll_info         pll;
 306
 307         struct ram_info         ram;
 308
 309         int                     mtrr_hdl;
 310
 311         int                     pm_reg;
 312         u32                     save_regs[64];
 313         int                     asleep;
 314         int                     lock_blank;
 315
 316         /* Lock on register access */
 317         spinlock_t              reg_lock;
 318
 319         /* Timer used for delayed LVDS operations */
 320         struct timer_list       lvds_timer;
 321         u32                     pending_lvds_gen_cntl;
 322         u32                     pending_pixclks_cntl;
 323
 324 #ifdef CONFIG_FB_RADEON_I2C
 325         struct radeon_i2c_chan  i2c[4];
 326 #endif
 327 };
 328
 329
 330 #define PRIMARY_MONITOR(rinfo)  (rinfo->mon1_type)
 331
 332
 333 /*
 334  * Debugging stuffs
 335  */
 336 #ifdef CONFIG_FB_RADEON_DEBUG
 337 #define DEBUG           1
 338 #else
 339 #define DEBUG           0
 340 #endif
 341
 342 #if DEBUG
 343 #define RTRACE          printk
 344 #else
 345 #define RTRACE          if(0) printk
 346 #endif
 347
 348
 349 /*
 350  * IO macros
 351  */
 352
 353 #define INREG8(addr)            readb((rinfo->mmio_base)+addr)
 354 #define OUTREG8(addr,val)       writeb(val, (rinfo->mmio_base)+addr)
 355 #define INREG(addr)             readl((rinfo->mmio_base)+addr)
 356 #define OUTREG(addr,val)        writel(val, (rinfo->mmio_base)+addr)
 357
 358 static inline void R300_cg_workardound(struct radeonfb_info *rinfo)
 359 {
 360         u32 save, tmp;
 361         save = INREG(CLOCK_CNTL_INDEX);
 362         tmp = save & ~(0x3f | PLL_WR_EN);
 363         OUTREG(CLOCK_CNTL_INDEX, tmp);
 364         tmp = INREG(CLOCK_CNTL_DATA);
 365         OUTREG(CLOCK_CNTL_INDEX, save);
 366 }
 367
 368 #define __OUTPLL(addr,val)      \
 369         do {    \
 370                 OUTREG8(CLOCK_CNTL_INDEX, (addr & 0x0000003f) | 0x00000080); \
 371                 OUTREG(CLOCK_CNTL_DATA, val); \
 372 } while(0)
 373
 374
 375 static inline u32 __INPLL(struct radeonfb_info *rinfo, u32 addr)
 376 {
 377         u32 data;
 378         OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f);
 379         data = (INREG(CLOCK_CNTL_DATA));
 380         if (rinfo->R300_cg_workaround)
 381                 R300_cg_workardound(rinfo);
 382         return data;
 383 }
 384
 385 static inline u32 _INPLL(struct radeonfb_info *rinfo, u32 addr)
 386 {
 387         unsigned long flags;
 388         u32 data;
 389
 390         spin_lock_irqsave(&rinfo->reg_lock, flags);
 391         data = __INPLL(rinfo, addr);
 392         spin_unlock_irqrestore(&rinfo->reg_lock, flags);
 393         return data;
 394 }
 395
 396 #define INPLL(addr)             _INPLL(rinfo, addr)
 397
 398 #define OUTPLL(addr,val)        \
 399         do {    \
 400                 unsigned long flags;\
 401                 spin_lock_irqsave(&rinfo->reg_lock, flags); \
 402                 __OUTPLL(addr, val); \
 403                 spin_unlock_irqrestore(&rinfo->reg_lock, flags); \
 404         } while(0)
 405
 406 #define OUTPLLP(addr,val,mask)                                          \
 407         do {                                                            \
 408                 unsigned long flags;                                    \
 409                 unsigned int _tmp;                                      \
 410                 spin_lock_irqsave(&rinfo->reg_lock, flags);             \
 411                 _tmp  = __INPLL(rinfo,addr);                            \
 412                 _tmp &= (mask);                                         \
 413                 _tmp |= (val);                                          \
 414                 __OUTPLL(addr, _tmp);                                   \
 415                 spin_unlock_irqrestore(&rinfo->reg_lock, flags);        \
 416         } while (0)
 417
 418 #define OUTREGP(addr,val,mask)                                          \
 419         do {                                                            \
 420                 unsigned long flags;                                    \
 421                 unsigned int _tmp;                                      \
 422                 spin_lock_irqsave(&rinfo->reg_lock, flags);             \
 423                 _tmp = INREG(addr);                                     \
 424                 _tmp &= (mask);                                         \
 425                 _tmp |= (val);                                          \
 426                 OUTREG(addr, _tmp);                                     \
 427                 spin_unlock_irqrestore(&rinfo->reg_lock, flags);        \
 428         } while (0)
 429
 430 #define MS_TO_HZ(ms)       ((ms * HZ + 999) / 1000)
 431
 432 #define BIOS_IN8(v)     (readb(rinfo->bios_seg + (v)))
 433 #define BIOS_IN16(v)    (readb(rinfo->bios_seg + (v)) | \
 434                           (readb(rinfo->bios_seg + (v) + 1) << 8))
 435 #define BIOS_IN32(v)    (readb(rinfo->bios_seg + (v)) | \
 436                           (readb(rinfo->bios_seg + (v) + 1) << 8) | \
 437                           (readb(rinfo->bios_seg + (v) + 2) << 16) | \
 438                           (readb(rinfo->bios_seg + (v) + 3) << 24))
 439
 440 /*
 441  * Inline utilities
 442  */
 443
 444 static inline void wait_ms(unsigned long ms)
 445 {
 446         set_current_state(TASK_UNINTERRUPTIBLE);
 447         schedule_timeout((ms * HZ + 999) / 1000);
 448 }
 449
 450
 451
 452 static inline int round_div(int num, int den)
 453 {
 454         return (num + (den / 2)) / den;
 455 }
 456
 457 static inline int var_to_depth(const struct fb_var_screeninfo *var)
 458 {
 459         if (var->bits_per_pixel != 16)
 460                 return var->bits_per_pixel;
 461         return (var->green.length == 5) ? 15 : 16;
 462 }
 463
 464 static inline u32 radeon_get_dstbpp(u16 depth)
 465 {
 466         switch (depth) {
 467         case 8:
 468                 return DST_8BPP;
 469         case 15:
 470                 return DST_15BPP;
 471         case 16:
 472                 return DST_16BPP;
 473         case 32:
 474                 return DST_32BPP;
 475         default:
 476                 return 0;
 477         }
 478 }
 479
 480 /*
 481  * 2D Engine helper routines
 482  */
 483 static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
 484 {
 485         int i;
 486
 487         /* initiate flush */
 488         OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
 489                 ~RB2D_DC_FLUSH_ALL);
 490
 491         for (i=0; i < 2000000; i++) {
 492                 if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
 493                         return;
 494                 udelay(1);
 495         }
 496         printk(KERN_ERR "radeonfb: Flush Timeout !\n");
 497 }
 498
 499
 500 static inline void _radeon_fifo_wait (struct radeonfb_info *rinfo, int entries)
 501 {
 502         int i;
 503
 504         for (i=0; i<2000000; i++) {
 505                 if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
 506                         return;
 507                 udelay(1);
 508         }
 509         printk(KERN_ERR "radeonfb: FIFO Timeout !\n");
 510 }
 511
 512
 513 static inline void _radeon_engine_idle (struct radeonfb_info *rinfo)
 514 {
 515         int i;
 516
 517         /* ensure FIFO is empty before waiting for idle */
 518         _radeon_fifo_wait (rinfo, 64);
 519
 520         for (i=0; i<2000000; i++) {
 521                 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
 522                         radeon_engine_flush (rinfo);
 523                         return;
 524                 }
 525                 udelay(1);
 526         }
 527         printk(KERN_ERR "radeonfb: Idle Timeout !\n");
 528 }
 529
 530 static inline int radeon_accel_disabled(void)
 531 {
 532         extern int radeonfb_noaccel;
 533         return radeonfb_noaccel;
 534 }
 535
 536 #define radeon_engine_idle()            _radeon_engine_idle(rinfo)
 537 #define radeon_fifo_wait(entries)       _radeon_fifo_wait(rinfo,entries)
 538
 539
 540 /* I2C Functions */
 541 extern void radeon_create_i2c_busses(struct radeonfb_info *rinfo);
 542 extern void radeon_delete_i2c_busses(struct radeonfb_info *rinfo);
 543 extern int radeon_probe_i2c_connector(struct radeonfb_info *rinfo, int conn, u8 **out_edid);
 544
 545 /* PM Functions */
 546 extern void radeon_pm_disable_dynamic_mode(struct radeonfb_info *rinfo);
 547 extern void radeon_pm_enable_dynamic_mode(struct radeonfb_info *rinfo);
 548 extern int radeonfb_pci_suspend(struct pci_dev *pdev, u32 state);
 549 extern int radeonfb_pci_resume(struct pci_dev *pdev);
 550
 551 /* Monitor probe functions */
 552 extern void radeon_probe_screens(struct radeonfb_info *rinfo,
 553                                  const char *monitor_layout, int ignore_edid);
 554 extern void radeon_check_modes(struct radeonfb_info *rinfo, const char *mode_option);
 555 extern int radeon_match_mode(struct radeonfb_info *rinfo,
 556                              struct fb_var_screeninfo *dest,
 557                              const struct fb_var_screeninfo *src);
 558
 559 /* Accel functions */
 560 extern void radeonfb_fillrect(struct fb_info *info, const struct fb_fillrect *region);
 561 extern void radeonfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
 562 extern void radeonfb_imageblit(struct fb_info *p, const struct fb_image *image);
 563 extern int radeonfb_sync(struct fb_info *info);
 564 extern void radeonfb_engine_init (struct radeonfb_info *rinfo);
 565 extern void radeonfb_engine_reset(struct radeonfb_info *rinfo);
 566
 567 /* Other functions */
 568 extern int radeonfb_blank(int blank, struct fb_info *info);
 569 extern int radeonfb_set_par(struct fb_info *info);
 570
 571 #endif /* __RADEONFB_H__ */