drivers/video/aty/radeonfb.h

   1 #ifndef __RADEONFB_H__
   2 #define __RADEONFB_H__
   3
   4 #include <linux/config.h>
   5 #include <linux/module.h>
   6 #include <linux/kernel.h>
   7 #include <linux/sched.h>
   8 #include <linux/delay.h>
   9 #include <linux/pci.h>
  10 #include <linux/fb.h>
  11
  12
  13 #include <linux/i2c.h>
  14 #include <linux/i2c-id.h>
  15 #include <linux/i2c-algo-bit.h>
  16
  17 #include <asm/io.h>
  18
  19 #include <video/radeon.h>
  20
  21 /***************************************************************
  22  * Most of the definitions here are adapted right from XFree86 *
  23  ***************************************************************/
  24
  25
  26 /*
  27  * Chip families. Must fit in the low 16 bits of a long word
  28  */
  29 enum radeon_family {
  30         CHIP_FAMILY_UNKNOW,
  31         CHIP_FAMILY_LEGACY,
  32         CHIP_FAMILY_RADEON,
  33         CHIP_FAMILY_RV100,
  34         CHIP_FAMILY_RS100,    /* U1 (IGP320M) or A3 (IGP320)*/
  35         CHIP_FAMILY_RV200,
  36         CHIP_FAMILY_RS200,    /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350), RS250 (IGP 7000) */
  37         CHIP_FAMILY_R200,
  38         CHIP_FAMILY_RV250,
  39         CHIP_FAMILY_RS300,    /* Radeon 9000 IGP */
  40         CHIP_FAMILY_RV280,
  41         CHIP_FAMILY_R300,
  42         CHIP_FAMILY_R350,
  43         CHIP_FAMILY_RV350,
  44         CHIP_FAMILY_LAST,
  45 };
  46
  47 /*
  48  * Chip flags
  49  */
  50 enum radeon_chip_flags {
  51         CHIP_FAMILY_MASK        = 0x0000ffffUL,
  52         CHIP_FLAGS_MASK         = 0xffff0000UL,
  53         CHIP_IS_MOBILITY        = 0x00010000UL,
  54         CHIP_IS_IGP             = 0x00020000UL,
  55         CHIP_HAS_CRTC2          = 0x00040000UL,
  56 };
  57
  58
  59 /*
  60  * Monitor types
  61  */
  62 enum radeon_montype {
  63         MT_NONE = 0,
  64         MT_CRT,         /* CRT */
  65         MT_LCD,         /* LCD */
  66         MT_DFP,         /* DVI */
  67         MT_CTV,         /* composite TV */
  68         MT_STV          /* S-Video out */
  69 };
  70
  71 /*
  72  * DDC i2c ports
  73  */
  74 enum ddc_type {
  75         ddc_none,
  76         ddc_monid,
  77         ddc_dvi,
  78         ddc_vga,
  79         ddc_crt2,
  80 };
  81
  82 /*
  83  * Connector types
  84  */
  85 enum conn_type {
  86         conn_none,
  87         conn_proprietary,
  88         conn_crt,
  89         conn_DVI_I,
  90         conn_DVI_D,
  91 };
  92
  93
  94 /*
  95  * PLL infos
  96  */
  97 struct pll_info {
  98         int ppll_max;
  99         int ppll_min;
 100         int sclk, mclk;
 101         int ref_div;
 102         int ref_clk;
 103 };
 104
 105 /*
 106  * VRAM infos
 107  */
 108 struct ram_info {
 109         int ml;
 110         int mb;
 111         int trcd;
 112         int trp;
 113         int twr;
 114         int cl;
 115         int tr2w;
 116         int loop_latency;
 117         int rloop;
 118 };
 119
 120
 121 /*
 122  * This structure contains the various registers manipulated by this
 123  * driver for setting or restoring a mode. It's mostly copied from
 124  * XFree's RADEONSaveRec structure. A few chip settings might still be
 125  * tweaked without beeing reflected or saved in these registers though
 126  */
 127 struct radeon_regs {
 128         /* Common registers */
 129         u32             ovr_clr;
 130         u32             ovr_wid_left_right;
 131         u32             ovr_wid_top_bottom;
 132         u32             ov0_scale_cntl;
 133         u32             mpp_tb_config;
 134         u32             mpp_gp_config;
 135         u32             subpic_cntl;
 136         u32             viph_control;
 137         u32             i2c_cntl_1;
 138         u32             gen_int_cntl;
 139         u32             cap0_trig_cntl;
 140         u32             cap1_trig_cntl;
 141         u32             bus_cntl;
 142         u32             surface_cntl;
 143         u32             bios_5_scratch;
 144
 145         /* Other registers to save for VT switches or driver load/unload */
 146         u32             dp_datatype;
 147         u32             rbbm_soft_reset;
 148         u32             clock_cntl_index;
 149         u32             amcgpio_en_reg;
 150         u32             amcgpio_mask;
 151
 152         /* Surface/tiling registers */
 153         u32             surf_lower_bound[8];
 154         u32             surf_upper_bound[8];
 155         u32             surf_info[8];
 156
 157         /* CRTC registers */
 158         u32             crtc_gen_cntl;
 159         u32             crtc_ext_cntl;
 160         u32             dac_cntl;
 161         u32             crtc_h_total_disp;
 162         u32             crtc_h_sync_strt_wid;
 163         u32             crtc_v_total_disp;
 164         u32             crtc_v_sync_strt_wid;
 165         u32             crtc_offset;
 166         u32             crtc_offset_cntl;
 167         u32             crtc_pitch;
 168         u32             disp_merge_cntl;
 169         u32             grph_buffer_cntl;
 170         u32             crtc_more_cntl;
 171
 172         /* CRTC2 registers */
 173         u32             crtc2_gen_cntl;
 174         u32             dac2_cntl;
 175         u32             disp_output_cntl;
 176         u32             disp_hw_debug;
 177         u32             disp2_merge_cntl;
 178         u32             grph2_buffer_cntl;
 179         u32             crtc2_h_total_disp;
 180         u32             crtc2_h_sync_strt_wid;
 181         u32             crtc2_v_total_disp;
 182         u32             crtc2_v_sync_strt_wid;
 183         u32             crtc2_offset;
 184         u32             crtc2_offset_cntl;
 185         u32             crtc2_pitch;
 186
 187         /* Flat panel regs */
 188         u32             fp_crtc_h_total_disp;
 189         u32             fp_crtc_v_total_disp;
 190         u32             fp_gen_cntl;
 191         u32             fp2_gen_cntl;
 192         u32             fp_h_sync_strt_wid;
 193         u32             fp2_h_sync_strt_wid;
 194         u32             fp_horz_stretch;
 195         u32             fp_panel_cntl;
 196         u32             fp_v_sync_strt_wid;
 197         u32             fp2_v_sync_strt_wid;
 198         u32             fp_vert_stretch;
 199         u32             lvds_gen_cntl;
 200         u32             lvds_pll_cntl;
 201         u32             tmds_crc;
 202         u32             tmds_transmitter_cntl;
 203
 204         /* Computed values for PLL */
 205         u32             dot_clock_freq;
 206         int             feedback_div;
 207         int             post_div;
 208
 209         /* PLL registers */
 210         u32             ppll_div_3;
 211         u32             ppll_ref_div;
 212         u32             vclk_ecp_cntl;
 213
 214         /* Computed values for PLL2 */
 215         u32             dot_clock_freq_2;
 216         int             feedback_div_2;
 217         int             post_div_2;
 218
 219         /* PLL2 registers */
 220         u32             p2pll_ref_div;
 221         u32             p2pll_div_0;
 222         u32             htotal_cntl2;
 223
 224         /* Palette */
 225         int             palette_valid;
 226 };
 227
 228 struct panel_info {
 229         int xres, yres;
 230         int valid;
 231         int clock;
 232         int hOver_plus, hSync_width, hblank;
 233         int vOver_plus, vSync_width, vblank;
 234         int hAct_high, vAct_high, interlaced;
 235         int pwr_delay;
 236         int use_bios_dividers;
 237         int ref_divider;
 238         int post_divider;
 239         int fbk_divider;
 240 };
 241
 242 struct radeonfb_info;
 243
 244 #ifdef CONFIG_FB_RADEON_I2C
 245 struct radeon_i2c_chan {
 246         struct radeonfb_info            *rinfo;
 247         u32                             ddc_reg;
 248         struct i2c_adapter              adapter;
 249         struct i2c_algo_bit_data        algo;
 250 };
 251 #endif
 252
 253 struct radeonfb_info {
 254         struct fb_info          *info;
 255
 256         struct radeon_regs      state;
 257         struct radeon_regs      init_state;
 258
 259         char                    name[DEVICE_NAME_SIZE];
 260         char                    ram_type[12];
 261
 262         unsigned long           mmio_base_phys;
 263         unsigned long           fb_base_phys;
 264
 265         unsigned long           mmio_base;
 266         unsigned long           fb_base;
 267
 268         unsigned long           fb_local_base;
 269
 270         struct pci_dev          *pdev;
 271
 272         u8                      *bios_seg;
 273         int                     fp_bios_start;
 274
 275         u32                     pseudo_palette[17];
 276         struct { u8 red, green, blue, pad; }
 277                                 palette[256];
 278
 279         int                     chipset;
 280         u8                      family;
 281         u8                      rev;
 282         unsigned long           video_ram;
 283         unsigned long           mapped_vram;
 284
 285         int                     pitch, bpp, depth;
 286
 287         int                     has_CRTC2;
 288         int                     is_mobility;
 289         int                     is_IGP;
 290         int                     R300_cg_workaround;
 291         int                     reversed_DAC;
 292         int                     reversed_TMDS;
 293         struct panel_info       panel_info;
 294         int                     mon1_type;
 295         u8                      *mon1_EDID;
 296         struct fb_videomode     *mon1_modedb;
 297         int                     mon1_dbsize;
 298         int                     mon2_type;
 299         u8                      *mon2_EDID;
 300
 301         u32                     dp_gui_master_cntl;
 302
 303         struct pll_info         pll;
 304
 305         struct ram_info         ram;
 306
 307         int                     mtrr_hdl;
 308
 309         int                     pm_reg;
 310         u32                     save_regs[64];
 311         int                     asleep;
 312         int                     lock_blank;
 313
 314         /* Lock on register access */
 315         spinlock_t              reg_lock;
 316
 317         /* Timer used for delayed LVDS operations */
 318         struct timer_list       lvds_timer;
 319         u32                     pending_lvds_gen_cntl;
 320         u32                     pending_pixclks_cntl;
 321
 322 #ifdef CONFIG_FB_RADEON_I2C
 323         struct radeon_i2c_chan  i2c[4];
 324 #endif
 325 };
 326
 327
 328 #define PRIMARY_MONITOR(rinfo)  (rinfo->mon1_type)
 329
 330
 331 /*
 332  * Debugging stuffs
 333  */
 334 #ifdef CONFIG_FB_RADEON_DEBUG
 335 #define DEBUG           1
 336 #else
 337 #define DEBUG           0
 338 #endif
 339
 340 #if DEBUG
 341 #define RTRACE          printk
 342 #else
 343 #define RTRACE          if(0) printk
 344 #endif
 345
 346
 347 /*
 348  * IO macros
 349  */
 350
 351 #define INREG8(addr)            readb((rinfo->mmio_base)+addr)
 352 #define OUTREG8(addr,val)       writeb(val, (rinfo->mmio_base)+addr)
 353 #define INREG(addr)             readl((rinfo->mmio_base)+addr)
 354 #define OUTREG(addr,val)        writel(val, (rinfo->mmio_base)+addr)
 355
 356 static inline void R300_cg_workardound(struct radeonfb_info *rinfo)
 357 {
 358         u32 save, tmp;
 359         save = INREG(CLOCK_CNTL_INDEX);
 360         tmp = save & ~(0x3f | PLL_WR_EN);
 361         OUTREG(CLOCK_CNTL_INDEX, tmp);
 362         tmp = INREG(CLOCK_CNTL_DATA);
 363         OUTREG(CLOCK_CNTL_INDEX, save);
 364 }
 365
 366 #define __OUTPLL(addr,val)      \
 367         do {    \
 368                 OUTREG8(CLOCK_CNTL_INDEX, (addr & 0x0000003f) | 0x00000080); \
 369                 OUTREG(CLOCK_CNTL_DATA, val); \
 370 } while(0)
 371
 372
 373 static inline u32 __INPLL(struct radeonfb_info *rinfo, u32 addr)
 374 {
 375         u32 data;
 376         OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f);
 377         data = (INREG(CLOCK_CNTL_DATA));
 378         if (rinfo->R300_cg_workaround)
 379                 R300_cg_workardound(rinfo);
 380         return data;
 381 }
 382
 383 static inline u32 _INPLL(struct radeonfb_info *rinfo, u32 addr)
 384 {
 385         unsigned long flags;
 386         u32 data;
 387
 388         spin_lock_irqsave(&rinfo->reg_lock, flags);
 389         data = __INPLL(rinfo, addr);
 390         spin_unlock_irqrestore(&rinfo->reg_lock, flags);
 391         return data;
 392 }
 393
 394 #define INPLL(addr)             _INPLL(rinfo, addr)
 395
 396 #define OUTPLL(addr,val)        \
 397         do {    \
 398                 unsigned long flags;\
 399                 spin_lock_irqsave(&rinfo->reg_lock, flags); \
 400                 __OUTPLL(addr, val); \
 401                 spin_unlock_irqrestore(&rinfo->reg_lock, flags); \
 402         } while(0)
 403
 404 #define OUTPLLP(addr,val,mask)                                          \
 405         do {                                                            \
 406                 unsigned long flags;                                    \
 407                 unsigned int _tmp;                                      \
 408                 spin_lock_irqsave(&rinfo->reg_lock, flags);             \
 409                 _tmp  = __INPLL(rinfo,addr);                            \
 410                 _tmp &= (mask);                                         \
 411                 _tmp |= (val);                                          \
 412                 __OUTPLL(addr, _tmp);                                   \
 413                 spin_unlock_irqrestore(&rinfo->reg_lock, flags);        \
 414         } while (0)
 415
 416 #define OUTREGP(addr,val,mask)                                          \
 417         do {                                                            \
 418                 unsigned long flags;                                    \
 419                 unsigned int _tmp;                                      \
 420                 spin_lock_irqsave(&rinfo->reg_lock, flags);             \
 421                 _tmp = INREG(addr);                                     \
 422                 _tmp &= (mask);                                         \
 423                 _tmp |= (val);                                          \
 424                 OUTREG(addr, _tmp);                                     \
 425                 spin_unlock_irqrestore(&rinfo->reg_lock, flags);        \
 426         } while (0)
 427
 428 #define MS_TO_HZ(ms)       ((ms * HZ + 999) / 1000)
 429
 430 #define BIOS_IN8(v)     (readb(rinfo->bios_seg + (v)))
 431 #define BIOS_IN16(v)    (readb(rinfo->bios_seg + (v)) | \
 432                           (readb(rinfo->bios_seg + (v) + 1) << 8))
 433 #define BIOS_IN32(v)    (readb(rinfo->bios_seg + (v)) | \
 434                           (readb(rinfo->bios_seg + (v) + 1) << 8) | \
 435                           (readb(rinfo->bios_seg + (v) + 2) << 16) | \
 436                           (readb(rinfo->bios_seg + (v) + 3) << 24))
 437
 438 /*
 439  * Inline utilities
 440  */
 441 static inline int round_div(int num, int den)
 442 {
 443         return (num + (den / 2)) / den;
 444 }
 445
 446 static inline int var_to_depth(const struct fb_var_screeninfo *var)
 447 {
 448         if (var->bits_per_pixel != 16)
 449                 return var->bits_per_pixel;
 450         return (var->green.length == 5) ? 15 : 16;
 451 }
 452
 453 static inline u32 radeon_get_dstbpp(u16 depth)
 454 {
 455         switch (depth) {
 456         case 8:
 457                 return DST_8BPP;
 458         case 15:
 459                 return DST_15BPP;
 460         case 16:
 461                 return DST_16BPP;
 462         case 32:
 463                 return DST_32BPP;
 464         default:
 465                 return 0;
 466         }
 467 }
 468
 469 /*
 470  * 2D Engine helper routines
 471  */
 472 static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
 473 {
 474         int i;
 475
 476         /* initiate flush */
 477         OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
 478                 ~RB2D_DC_FLUSH_ALL);
 479
 480         for (i=0; i < 2000000; i++) {
 481                 if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
 482                         return;
 483                 udelay(1);
 484         }
 485         printk(KERN_ERR "radeonfb: Flush Timeout !\n");
 486 }
 487
 488
 489 static inline void _radeon_fifo_wait (struct radeonfb_info *rinfo, int entries)
 490 {
 491         int i;
 492
 493         for (i=0; i<2000000; i++) {
 494                 if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
 495                         return;
 496                 udelay(1);
 497         }
 498         printk(KERN_ERR "radeonfb: FIFO Timeout !\n");
 499 }
 500
 501
 502 static inline void _radeon_engine_idle (struct radeonfb_info *rinfo)
 503 {
 504         int i;
 505
 506         /* ensure FIFO is empty before waiting for idle */
 507         _radeon_fifo_wait (rinfo, 64);
 508
 509         for (i=0; i<2000000; i++) {
 510                 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
 511                         radeon_engine_flush (rinfo);
 512                         return;
 513                 }
 514                 udelay(1);
 515         }
 516         printk(KERN_ERR "radeonfb: Idle Timeout !\n");
 517 }
 518
 519 static inline int radeon_accel_disabled(void)
 520 {
 521         extern int radeonfb_noaccel;
 522         return radeonfb_noaccel;
 523 }
 524
 525 #define radeon_engine_idle()            _radeon_engine_idle(rinfo)
 526 #define radeon_fifo_wait(entries)       _radeon_fifo_wait(rinfo,entries)
 527
 528
 529 /* I2C Functions */
 530 extern void radeon_create_i2c_busses(struct radeonfb_info *rinfo);
 531 extern void radeon_delete_i2c_busses(struct radeonfb_info *rinfo);
 532 extern int radeon_probe_i2c_connector(struct radeonfb_info *rinfo, int conn, u8 **out_edid);
 533
 534 /* PM Functions */
 535 extern void radeon_pm_disable_dynamic_mode(struct radeonfb_info *rinfo);
 536 extern void radeon_pm_enable_dynamic_mode(struct radeonfb_info *rinfo);
 537 extern int radeonfb_pci_suspend(struct pci_dev *pdev, u32 state);
 538 extern int radeonfb_pci_resume(struct pci_dev *pdev);
 539
 540 /* Monitor probe functions */
 541 extern void radeon_probe_screens(struct radeonfb_info *rinfo,
 542                                  const char *monitor_layout, int ignore_edid);
 543 extern void radeon_check_modes(struct radeonfb_info *rinfo, const char *mode_option);
 544 extern int radeon_match_mode(struct radeonfb_info *rinfo,
 545                              struct fb_var_screeninfo *dest,
 546                              const struct fb_var_screeninfo *src);
 547
 548 /* Accel functions */
 549 extern void radeonfb_fillrect(struct fb_info *info, const struct fb_fillrect *region);
 550 extern void radeonfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
 551 extern void radeonfb_imageblit(struct fb_info *p, const struct fb_image *image);
 552 extern int radeonfb_sync(struct fb_info *info);
 553 extern void radeonfb_engine_init (struct radeonfb_info *rinfo);
 554 extern void radeonfb_engine_reset(struct radeonfb_info *rinfo);
 555
 556 /* Other functions */
 557 extern int radeonfb_blank(int blank, struct fb_info *info);
 558 extern int radeonfb_set_par(struct fb_info *info);
 559
 560 #endif /* __RADEONFB_H__ */