3 * Hardware accelerated Matrox Millennium I, II, Mystique, G100, G200, G400 and G450
5 * (c) 1998-2002 Petr Vandrovec <vandrove@vc.cvut.cz>
11 /* general, but fairly heavy, debugging */
14 /* heavy debugging: */
15 /* -- logs putc[s], so everytime a char is displayed, it's logged */
16 #undef MATROXFB_DEBUG_HEAVY
18 /* This one _could_ cause infinite loops */
19 /* It _does_ cause lots and lots of messages during idle loops */
20 #undef MATROXFB_DEBUG_LOOP
22 /* Debug register calls, too? */
23 #undef MATROXFB_DEBUG_REG
25 /* Guard accelerator accesses with spin_lock_irqsave... */
26 #undef MATROXFB_USE_SPINLOCKS
28 #include <linux/config.h>
29 #include <linux/module.h>
30 #include <linux/kernel.h>
31 #include <linux/errno.h>
32 #include <linux/string.h>
34 #include <linux/tty.h>
35 #include <linux/slab.h>
36 #include <linux/delay.h>
38 #include <linux/console.h>
39 #include <linux/selection.h>
40 #include <linux/ioport.h>
41 #include <linux/init.h>
42 #include <linux/timer.h>
43 #include <linux/pci.h>
44 #include <linux/spinlock.h>
48 #include <asm/unaligned.h>
53 #include "../console/fbcon.h"
55 #if defined(CONFIG_PPC_PMAC)
57 #include <asm/pci-bridge.h>
58 #include "../macmodes.h"
61 /* always compile support for 32MB... It cost almost nothing */
62 #define CONFIG_FB_MATROX_32MB
67 #define DBG(x) printk(KERN_DEBUG "matroxfb: %s\n", (x));
69 #ifdef MATROXFB_DEBUG_HEAVY
70 #define DBG_HEAVY(x) DBG(x)
71 #else /* MATROXFB_DEBUG_HEAVY */
72 #define DBG_HEAVY(x) /* DBG_HEAVY */
73 #endif /* MATROXFB_DEBUG_HEAVY */
75 #ifdef MATROXFB_DEBUG_LOOP
76 #define DBG_LOOP(x) DBG(x)
77 #else /* MATROXFB_DEBUG_LOOP */
78 #define DBG_LOOP(x) /* DBG_LOOP */
79 #endif /* MATROXFB_DEBUG_LOOP */
81 #ifdef MATROXFB_DEBUG_REG
82 #define DBG_REG(x) DBG(x)
83 #else /* MATROXFB_DEBUG_REG */
84 #define DBG_REG(x) /* DBG_REG */
85 #endif /* MATROXFB_DEBUG_REG */
87 #else /* MATROXFB_DEBUG */
89 #define DBG(x) /* DBG */
90 #define DBG_HEAVY(x) /* DBG_HEAVY */
91 #define DBG_REG(x) /* DBG_REG */
92 #define DBG_LOOP(x) /* DBG_LOOP */
94 #endif /* MATROXFB_DEBUG */
96 #if !defined(__i386__) && !defined(__x86_64__)
97 #ifndef ioremap_nocache
98 #define ioremap_nocache(X,Y) ioremap(X,Y)
102 #if defined(__alpha__) || defined(__mc68000__) || defined(__i386__) || defined(__x86_64__)
104 #define MEMCPYTOIO_WORKS
106 /* ppc/ppc64 must use __raw_{read,write}[bwl] as we drive adapter
107 in big-endian mode for compatibility with XFree mga driver, and
108 so we do not want little-endian {read,write}[bwl] */
110 #define MEMCPYTOIO_WRITEL
113 #if defined(__mc68000__)
114 #define MAP_BUSTOVIRT
120 #define dprintk(X...) printk(X)
122 #define dprintk(X...)
125 #ifndef PCI_SS_VENDOR_ID_SIEMENS_NIXDORF
126 #define PCI_SS_VENDOR_ID_SIEMENS_NIXDORF 0x110A
128 #ifndef PCI_SS_VENDOR_ID_MATROX
129 #define PCI_SS_VENDOR_ID_MATROX PCI_VENDOR_ID_MATROX
132 #ifndef PCI_SS_ID_MATROX_PRODUCTIVA_G100_AGP
133 #define PCI_SS_ID_MATROX_GENERIC 0xFF00
134 #define PCI_SS_ID_MATROX_PRODUCTIVA_G100_AGP 0xFF01
135 #define PCI_SS_ID_MATROX_MYSTIQUE_G200_AGP 0xFF02
136 #define PCI_SS_ID_MATROX_MILLENIUM_G200_AGP 0xFF03
137 #define PCI_SS_ID_MATROX_MARVEL_G200_AGP 0xFF04
138 #define PCI_SS_ID_MATROX_MGA_G100_PCI 0xFF05
139 #define PCI_SS_ID_MATROX_MGA_G100_AGP 0x1001
140 #define PCI_SS_ID_MATROX_MILLENNIUM_G400_MAX_AGP 0x2179
141 #define PCI_SS_ID_SIEMENS_MGA_G100_AGP 0x001E /* 30 */
142 #define PCI_SS_ID_SIEMENS_MGA_G200_AGP 0x0032 /* 50 */
145 #define MX_VISUAL_TRUECOLOR FB_VISUAL_DIRECTCOLOR
146 #define MX_VISUAL_DIRECTCOLOR FB_VISUAL_TRUECOLOR
147 #define MX_VISUAL_PSEUDOCOLOR FB_VISUAL_PSEUDOCOLOR
149 #define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16)
151 /* G-series and Mystique have (almost) same DAC */
153 #if defined(CONFIG_FB_MATROX_MYSTIQUE) || defined(CONFIG_FB_MATROX_G100)
154 #define NEED_DAC1064 1
158 u_int8_t __iomem* vaddr;
162 static inline unsigned int mga_readb(vaddr_t va, unsigned int offs) {
163 return readb(va.vaddr + offs);
166 static inline unsigned int mga_readw(vaddr_t va, unsigned int offs) {
167 return readw(va.vaddr + offs);
170 static inline u_int32_t mga_readl(vaddr_t va, unsigned int offs) {
171 return readl(va.vaddr + offs);
174 static inline void mga_writeb(vaddr_t va, unsigned int offs, u_int8_t value) {
175 writeb(value, va.vaddr + offs);
178 static inline void mga_writew(vaddr_t va, unsigned int offs, u_int16_t value) {
179 writew(value, va.vaddr + offs);
182 static inline void mga_writel(vaddr_t va, unsigned int offs, u_int32_t value) {
183 writel(value, va.vaddr + offs);
186 static inline unsigned int mga_readb(vaddr_t va, unsigned int offs) {
187 return __raw_readb(va.vaddr + offs);
190 static inline unsigned int mga_readw(vaddr_t va, unsigned int offs) {
191 return __raw_readw(va.vaddr + offs);
194 static inline u_int32_t mga_readl(vaddr_t va, unsigned int offs) {
195 return __raw_readl(va.vaddr + offs);
198 static inline void mga_writeb(vaddr_t va, unsigned int offs, u_int8_t value) {
199 __raw_writeb(value, va.vaddr + offs);
202 static inline void mga_writew(vaddr_t va, unsigned int offs, u_int16_t value) {
203 __raw_writew(value, va.vaddr + offs);
206 static inline void mga_writel(vaddr_t va, unsigned int offs, u_int32_t value) {
207 __raw_writel(value, va.vaddr + offs);
211 static inline void mga_memcpy_toio(vaddr_t va, unsigned int offs, const void* src, int len) {
212 #ifdef MEMCPYTOIO_WORKS
213 memcpy_toio(va.vaddr + offs, src, len);
214 #elif defined(MEMCPYTOIO_WRITEL)
217 mga_writel(va, offs, get_unaligned((u32 *)src));
224 mga_writel(va, offs, *(u32 *)src);
233 memcpy(&tmp, src, len);
234 mga_writel(va, offs, tmp);
237 #error "Sorry, do not know how to write block of data to device"
241 static inline void vaddr_add(vaddr_t* va, unsigned long offs) {
245 static inline void __iomem* vaddr_va(vaddr_t va) {
249 #define MGA_IOREMAP_NORMAL 0
250 #define MGA_IOREMAP_NOCACHE 1
252 #define MGA_IOREMAP_FB MGA_IOREMAP_NOCACHE
253 #define MGA_IOREMAP_MMIO MGA_IOREMAP_NOCACHE
254 static inline int mga_ioremap(unsigned long phys, unsigned long size, int flags, vaddr_t* virt) {
256 if (flags & MGA_IOREMAP_NOCACHE)
257 virt->vaddr = ioremap_nocache(phys, size);
259 virt->vaddr = ioremap(phys, size);
262 virt->vaddr = bus_to_virt(phys);
264 #error "Your architecture does not have neither ioremap nor bus_to_virt... Giving up"
267 return (virt->vaddr == 0); /* 0, !0... 0, error_code in future */
270 static inline void mga_iounmap(vaddr_t va) {
277 unsigned int pixclock;
280 unsigned int HDisplay;
281 unsigned int HSyncStart;
282 unsigned int HSyncEnd;
284 unsigned int VDisplay;
285 unsigned int VSyncStart;
286 unsigned int VSyncEnd;
291 unsigned int delay; /* CRTC delay */
294 enum { M_SYSTEM_PLL, M_PIXEL_PLL_A, M_PIXEL_PLL_B, M_PIXEL_PLL_C, M_VIDEO_PLL };
296 struct matrox_pll_cache {
299 unsigned int mnp_key;
300 unsigned int mnp_value;
304 struct matrox_pll_limits {
309 struct matrox_pll_features {
310 unsigned int vco_freq_min;
311 unsigned int ref_freq;
312 unsigned int feed_div_min;
313 unsigned int feed_div_max;
314 unsigned int in_div_min;
315 unsigned int in_div_max;
316 unsigned int post_shift_max;
321 unsigned int final_bppShift;
322 unsigned int cmap_len;
330 struct matrox_fb_info;
332 struct matrox_DAC1064_features {
337 struct matrox_accel_features {
341 /* current hardware status */
353 struct matrox_crtc2 {
357 struct matrox_hw_state {
358 u_int32_t MXoptionReg;
359 unsigned char DACclk[6];
360 unsigned char DACreg[80];
361 unsigned char MiscOutReg;
362 unsigned char DACpal[768];
363 unsigned char CRTC[25];
364 unsigned char CRTCEXT[9];
365 unsigned char SEQ[5];
366 /* unused for MGA mode, but who knows... */
367 unsigned char GCTL[9];
368 /* unused for MGA mode, but who knows... */
369 unsigned char ATTR[21];
372 struct mavenregs maven;
374 struct matrox_crtc2 crtc2;
377 struct matrox_accel_data {
378 #ifdef CONFIG_FB_MATROX_MILLENIUM
379 unsigned char ramdac_rev;
381 u_int32_t m_dwg_rect;
385 struct v4l2_queryctrl;
388 struct matrox_altout {
390 int (*compute)(void* altout_dev, struct my_timming* input);
391 int (*program)(void* altout_dev);
392 int (*start)(void* altout_dev);
393 int (*verifymode)(void* altout_dev, u_int32_t mode);
394 int (*getqueryctrl)(void* altout_dev,
395 struct v4l2_queryctrl* ctrl);
396 int (*getctrl)(void* altout_dev,
397 struct v4l2_control* ctrl);
398 int (*setctrl)(void* altout_dev,
399 struct v4l2_control* ctrl);
402 #define MATROXFB_SRC_NONE 0
403 #define MATROXFB_SRC_CRTC1 1
404 #define MATROXFB_SRC_CRTC2 2
406 enum mga_chip { MGA_2064, MGA_2164, MGA_1064, MGA_1164, MGA_G100, MGA_G200, MGA_G400, MGA_G450, MGA_G550 };
409 unsigned int bios_valid : 1;
410 unsigned int pins_len;
411 unsigned char pins[128];
413 unsigned char vMaj, vMin, vRev;
416 unsigned char state, tvout;
420 extern struct display fb_display[];
422 struct matrox_switch;
423 struct matroxfb_driver;
424 struct matroxfb_dh_fb_info;
426 struct matrox_vsync {
427 wait_queue_head_t wait;
431 struct matrox_fb_info {
432 struct fb_info fbcon;
434 struct list_head next_fb;
437 unsigned int usecount;
439 unsigned int userusecount;
440 unsigned long irq_flags;
442 struct matroxfb_par curr;
443 struct matrox_hw_state hw;
445 struct matrox_accel_data accel;
447 struct pci_dev* pcidev;
450 struct matrox_vsync vsync;
451 unsigned int pixclock;
456 struct matrox_vsync vsync;
457 unsigned int pixclock;
459 struct matroxfb_dh_fb_info* info;
460 struct rw_semaphore lock;
463 struct rw_semaphore lock;
465 int brightness, contrast, saturation, hue, gamma;
466 int testout, deflicker;
469 #define MATROXFB_MAX_OUTPUTS 3
472 struct matrox_altout* output;
475 unsigned int default_src;
476 } outputs[MATROXFB_MAX_OUTPUTS];
478 #define MATROXFB_MAX_FB_DRIVERS 5
479 struct matroxfb_driver* (drivers[MATROXFB_MAX_FB_DRIVERS]);
480 void* (drivers_data[MATROXFB_MAX_FB_DRIVERS]);
481 unsigned int drivers_count;
484 unsigned long base; /* physical */
485 vaddr_t vbase; /* CPU view */
487 unsigned int len_usable;
488 unsigned int len_maximum;
492 unsigned long base; /* physical */
493 vaddr_t vbase; /* CPU view */
497 unsigned int max_pixel_clock;
499 struct matrox_switch* hw_switch;
502 struct matrox_pll_features pll;
503 struct matrox_DAC1064_features DAC1064;
504 struct matrox_accel_features accel;
538 #ifdef CONFIG_FB_MATROX_32MB
547 unsigned int vgastep;
548 unsigned int textmode;
549 unsigned int textstep;
550 unsigned int textvram; /* character cells */
551 unsigned int ydstorg; /* offset in bytes from video start to usable memory */
552 /* 0 except for 6MB Millenium */
556 int panellink; /* G400 DFP possible (not G450/G550) */
558 unsigned int fbResource;
561 struct matrox_bios bios;
563 struct matrox_pll_limits pixel;
564 struct matrox_pll_limits system;
565 struct matrox_pll_limits video;
568 struct matrox_pll_cache pixel;
569 struct matrox_pll_cache system;
570 struct matrox_pll_cache video;
582 u_int32_t mctlwtst_core;
596 #define info2minfo(info) container_of(info, struct matrox_fb_info, fbcon)
598 #ifdef CONFIG_FB_MATROX_MULTIHEAD
599 #define ACCESS_FBINFO2(info, x) (info->x)
600 #define ACCESS_FBINFO(x) ACCESS_FBINFO2(minfo,x)
604 #define WPMINFO2 struct matrox_fb_info* minfo
605 #define WPMINFO WPMINFO2 ,
606 #define CPMINFO2 const struct matrox_fb_info* minfo
607 #define CPMINFO CPMINFO2 ,
608 #define PMINFO2 minfo
609 #define PMINFO PMINFO2 ,
611 #define MINFO_FROM(x) struct matrox_fb_info* minfo = x
614 extern struct matrox_fb_info matroxfb_global_mxinfo;
616 #define ACCESS_FBINFO(x) (matroxfb_global_mxinfo.x)
617 #define ACCESS_FBINFO2(info, x) (matroxfb_global_mxinfo.x)
619 #define MINFO (&matroxfb_global_mxinfo)
621 #define WPMINFO2 void
623 #define CPMINFO2 void
628 #define MINFO_FROM(x)
632 #define MINFO_FROM_INFO(x) MINFO_FROM(info2minfo(x))
634 struct matrox_switch {
635 int (*preinit)(WPMINFO2);
636 void (*reset)(WPMINFO2);
637 int (*init)(WPMINFO struct my_timming*);
638 void (*restore)(WPMINFO2);
641 struct matroxfb_driver {
642 struct list_head node;
644 void* (*probe)(struct matrox_fb_info* info);
645 void (*remove)(struct matrox_fb_info* info, void* data);
648 int matroxfb_register_driver(struct matroxfb_driver* drv);
649 void matroxfb_unregister_driver(struct matroxfb_driver* drv);
651 #define PCI_OPTION_REG 0x40
652 #define PCI_OPTION_ENABLE_ROM 0x40000000
654 #define PCI_MGA_INDEX 0x44
655 #define PCI_MGA_DATA 0x48
656 #define PCI_OPTION2_REG 0x50
657 #define PCI_OPTION3_REG 0x54
658 #define PCI_MEMMISC_REG 0x58
660 #define M_DWGCTL 0x1C00
661 #define M_MACCESS 0x1C04
662 #define M_CTLWTST 0x1C08
664 #define M_PLNWT 0x1C1C
666 #define M_BCOL 0x1C20
667 #define M_FCOL 0x1C24
679 #define M_CXBNDRY 0x1C80
680 #define M_FXBNDRY 0x1C84
681 #define M_YDSTLEN 0x1C88
682 #define M_PITCH 0x1C8C
683 #define M_YDST 0x1C90
684 #define M_YDSTORG 0x1C94
685 #define M_YTOP 0x1C98
686 #define M_YBOT 0x1C9C
689 #define M_CACHEFLUSH 0x1FFF
691 #define M_EXEC 0x0100
693 #define M_DWG_TRAP 0x04
694 #define M_DWG_BITBLT 0x08
695 #define M_DWG_ILOAD 0x09
697 #define M_DWG_LINEAR 0x0080
698 #define M_DWG_SOLID 0x0800
699 #define M_DWG_ARZERO 0x1000
700 #define M_DWG_SGNZERO 0x2000
701 #define M_DWG_SHIFTZERO 0x4000
703 #define M_DWG_REPLACE 0x000C0000
704 #define M_DWG_REPLACE2 (M_DWG_REPLACE | 0x40)
705 #define M_DWG_XOR 0x00060010
707 #define M_DWG_BFCOL 0x04000000
708 #define M_DWG_BMONOWF 0x08000000
710 #define M_DWG_TRANSC 0x40000000
712 #define M_FIFOSTATUS 0x1E10
713 #define M_STATUS 0x1E14
714 #define M_ICLEAR 0x1E18
717 #define M_VCOUNT 0x1E20
719 #define M_RESET 0x1E40
720 #define M_MEMRDBK 0x1E44
722 #define M_AGP2PLL 0x1E4C
724 #define M_OPMODE 0x1E54
725 #define M_OPMODE_DMA_GEN_WRITE 0x00
726 #define M_OPMODE_DMA_BLIT 0x04
727 #define M_OPMODE_DMA_VECTOR_WRITE 0x08
728 #define M_OPMODE_DMA_LE 0x0000 /* little endian - no transformation */
729 #define M_OPMODE_DMA_BE_8BPP 0x0000
730 #define M_OPMODE_DMA_BE_16BPP 0x0100
731 #define M_OPMODE_DMA_BE_32BPP 0x0200
732 #define M_OPMODE_DIR_LE 0x000000 /* little endian - no transformation */
733 #define M_OPMODE_DIR_BE_8BPP 0x000000
734 #define M_OPMODE_DIR_BE_16BPP 0x010000
735 #define M_OPMODE_DIR_BE_32BPP 0x020000
737 #define M_ATTR_INDEX 0x1FC0
738 #define M_ATTR_DATA 0x1FC1
740 #define M_MISC_REG 0x1FC2
741 #define M_3C2_RD 0x1FC2
743 #define M_SEQ_INDEX 0x1FC4
744 #define M_SEQ_DATA 0x1FC5
746 #define M_MISC_REG_READ 0x1FCC
748 #define M_GRAPHICS_INDEX 0x1FCE
749 #define M_GRAPHICS_DATA 0x1FCF
751 #define M_CRTC_INDEX 0x1FD4
753 #define M_ATTR_RESET 0x1FDA
754 #define M_3DA_WR 0x1FDA
755 #define M_INSTS1 0x1FDA
757 #define M_EXTVGA_INDEX 0x1FDE
758 #define M_EXTVGA_DATA 0x1FDF
761 #define M_SRCORG 0x2CB4
762 #define M_DSTORG 0x2CB8
764 #define M_RAMDAC_BASE 0x3C00
766 /* fortunately, same on TVP3026 and MGA1064 */
767 #define M_DAC_REG (M_RAMDAC_BASE+0)
768 #define M_DAC_VAL (M_RAMDAC_BASE+1)
769 #define M_PALETTE_MASK (M_RAMDAC_BASE+2)
771 #define M_X_INDEX 0x00
772 #define M_X_DATAREG 0x0A
774 #define DAC_XGENIOCTRL 0x2A
775 #define DAC_XGENIODATA 0x2B
777 #define M_C2CTL 0x3E10
779 #ifdef __LITTLE_ENDIAN
780 #define MX_OPTION_BSWAP 0x00000000
782 #define M_OPMODE_4BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
783 #define M_OPMODE_8BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
784 #define M_OPMODE_16BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
785 #define M_OPMODE_24BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
786 #define M_OPMODE_32BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
789 #define MX_OPTION_BSWAP 0x80000000
791 #define M_OPMODE_4BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT) /* TODO */
792 #define M_OPMODE_8BPP (M_OPMODE_DMA_BE_8BPP | M_OPMODE_DIR_BE_8BPP | M_OPMODE_DMA_BLIT)
793 #define M_OPMODE_16BPP (M_OPMODE_DMA_BE_16BPP | M_OPMODE_DIR_BE_16BPP | M_OPMODE_DMA_BLIT)
794 #define M_OPMODE_24BPP (M_OPMODE_DMA_BE_8BPP | M_OPMODE_DIR_BE_8BPP | M_OPMODE_DMA_BLIT) /* TODO, ?32 */
795 #define M_OPMODE_32BPP (M_OPMODE_DMA_BE_32BPP | M_OPMODE_DIR_BE_32BPP | M_OPMODE_DMA_BLIT)
797 #error "Byte ordering have to be defined. Cannot continue."
801 #define mga_inb(addr) mga_readb(ACCESS_FBINFO(mmio.vbase), (addr))
802 #define mga_inl(addr) mga_readl(ACCESS_FBINFO(mmio.vbase), (addr))
803 #define mga_outb(addr,val) mga_writeb(ACCESS_FBINFO(mmio.vbase), (addr), (val))
804 #define mga_outw(addr,val) mga_writew(ACCESS_FBINFO(mmio.vbase), (addr), (val))
805 #define mga_outl(addr,val) mga_writel(ACCESS_FBINFO(mmio.vbase), (addr), (val))
806 #define mga_readr(port,idx) (mga_outb((port),(idx)), mga_inb((port)+1))
807 #ifdef __LITTLE_ENDIAN
808 #define mga_setr(addr,port,val) mga_outw(addr, ((val)<<8) | (port))
810 #define mga_setr(addr,port,val) do { mga_outb(addr, port); mga_outb((addr)+1, val); } while (0)
813 #define mga_fifo(n) do {} while ((mga_inl(M_FIFOSTATUS) & 0xFF) < (n))
815 #define WaitTillIdle() do {} while (mga_inl(M_STATUS) & 0x10000)
818 #ifdef CONFIG_FB_MATROX_MILLENIUM
819 #define isInterleave(x) (x->interleave)
820 #define isMillenium(x) (x->millenium)
821 #define isMilleniumII(x) (x->milleniumII)
823 #define isInterleave(x) (0)
824 #define isMillenium(x) (0)
825 #define isMilleniumII(x) (0)
828 #define matroxfb_DAC_lock() spin_lock(&ACCESS_FBINFO(lock.DAC))
829 #define matroxfb_DAC_unlock() spin_unlock(&ACCESS_FBINFO(lock.DAC))
830 #define matroxfb_DAC_lock_irqsave(flags) spin_lock_irqsave(&ACCESS_FBINFO(lock.DAC),flags)
831 #define matroxfb_DAC_unlock_irqrestore(flags) spin_unlock_irqrestore(&ACCESS_FBINFO(lock.DAC),flags)
832 extern void matroxfb_DAC_out(CPMINFO int reg, int val);
833 extern int matroxfb_DAC_in(CPMINFO int reg);
834 extern struct list_head matroxfb_list;
835 extern void matroxfb_var2my(struct fb_var_screeninfo* fvsi, struct my_timming* mt);
836 extern int matroxfb_wait_for_sync(WPMINFO u_int32_t crtc);
837 extern int matroxfb_enable_irq(WPMINFO int reenable);
839 #ifdef MATROXFB_USE_SPINLOCKS
840 #define CRITBEGIN spin_lock_irqsave(&ACCESS_FBINFO(lock.accel), critflags);
841 #define CRITEND spin_unlock_irqrestore(&ACCESS_FBINFO(lock.accel), critflags);
842 #define CRITFLAGS unsigned long critflags;
849 #endif /* __MATROXFB_H__ */