drivers/video/nvidia/nv_hw.c

   1  /***************************************************************************\
   2 |*                                                                           *|
   3 |*       Copyright 1993-2003 NVIDIA, Corporation.  All rights reserved.      *|
   4 |*                                                                           *|
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   9 |*                                                                           *|
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  12 |*     as follows:                                                           *|
  13 |*                                                                           *|
  14 |*       Copyright 1993-2003 NVIDIA, Corporation.  All rights reserved.      *|
  15 |*                                                                           *|
  16 |*     NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY     *|
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  31 |*     computer  software  documentation,"  as such  terms  are  used in     *|
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  35 |*     all U.S. Government End Users  acquire the source code  with only     *|
  36 |*     those rights set forth herein.                                        *|
  37 |*                                                                           *|
  38  \***************************************************************************/
  39
  40 /*
  41  * GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/
  42  * XFree86 'nv' driver, this source code is provided under MIT-style licensing
  43  * where the source code is provided "as is" without warranty of any kind.
  44  * The only usage restriction is for the copyright notices to be retained
  45  * whenever code is used.
  46  *
  47  * Antonino Daplas <adaplas@pol.net> 2005-03-11
  48  */
  49
  50 /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_hw.c,v 1.4 2003/11/03 05:11:25 tsi Exp $ */
  51
  52 #include <linux/pci.h>
  53 #include "nv_type.h"
  54 #include "nv_local.h"
  55 #include "nv_proto.h"
  56
  57 void NVLockUnlock(struct nvidia_par *par, int Lock)
  58 {
  59         u8 cr11;
  60
  61         VGA_WR08(par->PCIO, 0x3D4, 0x1F);
  62         VGA_WR08(par->PCIO, 0x3D5, Lock ? 0x99 : 0x57);
  63
  64         VGA_WR08(par->PCIO, 0x3D4, 0x11);
  65         cr11 = VGA_RD08(par->PCIO, 0x3D5);
  66         if (Lock)
  67                 cr11 |= 0x80;
  68         else
  69                 cr11 &= ~0x80;
  70         VGA_WR08(par->PCIO, 0x3D5, cr11);
  71 }
  72
  73 int NVShowHideCursor(struct nvidia_par *par, int ShowHide)
  74 {
  75         int cur = par->CurrentState->cursor1;
  76
  77         par->CurrentState->cursor1 = (par->CurrentState->cursor1 & 0xFE) |
  78             (ShowHide & 0x01);
  79         VGA_WR08(par->PCIO, 0x3D4, 0x31);
  80         VGA_WR08(par->PCIO, 0x3D5, par->CurrentState->cursor1);
  81
  82         if (par->Architecture == NV_ARCH_40)
  83                 NV_WR32(par->PRAMDAC, 0x0300, NV_RD32(par->PRAMDAC, 0x0300));
  84
  85         return (cur & 0x01);
  86 }
  87
  88 /****************************************************************************\
  89 *                                                                            *
  90 * The video arbitration routines calculate some "magic" numbers.  Fixes      *
  91 * the snow seen when accessing the framebuffer without it.                   *
  92 * It just works (I hope).                                                    *
  93 *                                                                            *
  94 \****************************************************************************/
  95
  96 typedef struct {
  97         int graphics_lwm;
  98         int video_lwm;
  99         int graphics_burst_size;
 100         int video_burst_size;
 101         int valid;
 102 } nv4_fifo_info;
 103
 104 typedef struct {
 105         int pclk_khz;
 106         int mclk_khz;
 107         int nvclk_khz;
 108         char mem_page_miss;
 109         char mem_latency;
 110         int memory_width;
 111         char enable_video;
 112         char gr_during_vid;
 113         char pix_bpp;
 114         char mem_aligned;
 115         char enable_mp;
 116 } nv4_sim_state;
 117
 118 typedef struct {
 119         int graphics_lwm;
 120         int video_lwm;
 121         int graphics_burst_size;
 122         int video_burst_size;
 123         int valid;
 124 } nv10_fifo_info;
 125
 126 typedef struct {
 127         int pclk_khz;
 128         int mclk_khz;
 129         int nvclk_khz;
 130         char mem_page_miss;
 131         char mem_latency;
 132         int memory_type;
 133         int memory_width;
 134         char enable_video;
 135         char gr_during_vid;
 136         char pix_bpp;
 137         char mem_aligned;
 138         char enable_mp;
 139 } nv10_sim_state;
 140
 141 static void nvGetClocks(struct nvidia_par *par, unsigned int *MClk,
 142                         unsigned int *NVClk)
 143 {
 144         unsigned int pll, N, M, MB, NB, P;
 145
 146         if (par->Architecture >= NV_ARCH_40) {
 147                 pll = NV_RD32(par->PMC, 0x4020);
 148                 P = (pll >> 16) & 0x07;
 149                 pll = NV_RD32(par->PMC, 0x4024);
 150                 M = pll & 0xFF;
 151                 N = (pll >> 8) & 0xFF;
 152                 if (((par->Chipset & 0xfff0) == 0x0290) ||
 153                                 ((par->Chipset & 0xfff0) == 0x0390)) {
 154                         MB = 1;
 155                         NB = 1;
 156                 } else {
 157                         MB = (pll >> 16) & 0xFF;
 158                         NB = (pll >> 24) & 0xFF;
 159                 }
 160                 *MClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
 161
 162                 pll = NV_RD32(par->PMC, 0x4000);
 163                 P = (pll >> 16) & 0x03;
 164                 pll = NV_RD32(par->PMC, 0x4004);
 165                 M = pll & 0xFF;
 166                 N = (pll >> 8) & 0xFF;
 167                 MB = (pll >> 16) & 0xFF;
 168                 NB = (pll >> 24) & 0xFF;
 169
 170                 *NVClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
 171         } else if (par->twoStagePLL) {
 172                 pll = NV_RD32(par->PRAMDAC0, 0x0504);
 173                 M = pll & 0xFF;
 174                 N = (pll >> 8) & 0xFF;
 175                 P = (pll >> 16) & 0x0F;
 176                 pll = NV_RD32(par->PRAMDAC0, 0x0574);
 177                 if (pll & 0x80000000) {
 178                         MB = pll & 0xFF;
 179                         NB = (pll >> 8) & 0xFF;
 180                 } else {
 181                         MB = 1;
 182                         NB = 1;
 183                 }
 184                 *MClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
 185
 186                 pll = NV_RD32(par->PRAMDAC0, 0x0500);
 187                 M = pll & 0xFF;
 188                 N = (pll >> 8) & 0xFF;
 189                 P = (pll >> 16) & 0x0F;
 190                 pll = NV_RD32(par->PRAMDAC0, 0x0570);
 191                 if (pll & 0x80000000) {
 192                         MB = pll & 0xFF;
 193                         NB = (pll >> 8) & 0xFF;
 194                 } else {
 195                         MB = 1;
 196                         NB = 1;
 197                 }
 198                 *NVClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
 199         } else
 200             if (((par->Chipset & 0x0ff0) == 0x0300) ||
 201                 ((par->Chipset & 0x0ff0) == 0x0330)) {
 202                 pll = NV_RD32(par->PRAMDAC0, 0x0504);
 203                 M = pll & 0x0F;
 204                 N = (pll >> 8) & 0xFF;
 205                 P = (pll >> 16) & 0x07;
 206                 if (pll & 0x00000080) {
 207                         MB = (pll >> 4) & 0x07;
 208                         NB = (pll >> 19) & 0x1f;
 209                 } else {
 210                         MB = 1;
 211                         NB = 1;
 212                 }
 213                 *MClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
 214
 215                 pll = NV_RD32(par->PRAMDAC0, 0x0500);
 216                 M = pll & 0x0F;
 217                 N = (pll >> 8) & 0xFF;
 218                 P = (pll >> 16) & 0x07;
 219                 if (pll & 0x00000080) {
 220                         MB = (pll >> 4) & 0x07;
 221                         NB = (pll >> 19) & 0x1f;
 222                 } else {
 223                         MB = 1;
 224                         NB = 1;
 225                 }
 226                 *NVClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
 227         } else {
 228                 pll = NV_RD32(par->PRAMDAC0, 0x0504);
 229                 M = pll & 0xFF;
 230                 N = (pll >> 8) & 0xFF;
 231                 P = (pll >> 16) & 0x0F;
 232                 *MClk = (N * par->CrystalFreqKHz / M) >> P;
 233
 234                 pll = NV_RD32(par->PRAMDAC0, 0x0500);
 235                 M = pll & 0xFF;
 236                 N = (pll >> 8) & 0xFF;
 237                 P = (pll >> 16) & 0x0F;
 238                 *NVClk = (N * par->CrystalFreqKHz / M) >> P;
 239         }
 240 }
 241
 242 static void nv4CalcArbitration(nv4_fifo_info * fifo, nv4_sim_state * arb)
 243 {
 244         int data, pagemiss, cas, width, video_enable, bpp;
 245         int nvclks, mclks, pclks, vpagemiss, crtpagemiss, vbs;
 246         int found, mclk_extra, mclk_loop, cbs, m1, p1;
 247         int mclk_freq, pclk_freq, nvclk_freq, mp_enable;
 248         int us_m, us_n, us_p, video_drain_rate, crtc_drain_rate;
 249         int vpm_us, us_video, vlwm, video_fill_us, cpm_us, us_crt, clwm;
 250
 251         fifo->valid = 1;
 252         pclk_freq = arb->pclk_khz;
 253         mclk_freq = arb->mclk_khz;
 254         nvclk_freq = arb->nvclk_khz;
 255         pagemiss = arb->mem_page_miss;
 256         cas = arb->mem_latency;
 257         width = arb->memory_width >> 6;
 258         video_enable = arb->enable_video;
 259         bpp = arb->pix_bpp;
 260         mp_enable = arb->enable_mp;
 261         clwm = 0;
 262         vlwm = 0;
 263         cbs = 128;
 264         pclks = 2;
 265         nvclks = 2;
 266         nvclks += 2;
 267         nvclks += 1;
 268         mclks = 5;
 269         mclks += 3;
 270         mclks += 1;
 271         mclks += cas;
 272         mclks += 1;
 273         mclks += 1;
 274         mclks += 1;
 275         mclks += 1;
 276         mclk_extra = 3;
 277         nvclks += 2;
 278         nvclks += 1;
 279         nvclks += 1;
 280         nvclks += 1;
 281         if (mp_enable)
 282                 mclks += 4;
 283         nvclks += 0;
 284         pclks += 0;
 285         found = 0;
 286         vbs = 0;
 287         while (found != 1) {
 288                 fifo->valid = 1;
 289                 found = 1;
 290                 mclk_loop = mclks + mclk_extra;
 291                 us_m = mclk_loop * 1000 * 1000 / mclk_freq;
 292                 us_n = nvclks * 1000 * 1000 / nvclk_freq;
 293                 us_p = nvclks * 1000 * 1000 / pclk_freq;
 294                 if (video_enable) {
 295                         video_drain_rate = pclk_freq * 2;
 296                         crtc_drain_rate = pclk_freq * bpp / 8;
 297                         vpagemiss = 2;
 298                         vpagemiss += 1;
 299                         crtpagemiss = 2;
 300                         vpm_us =
 301                             (vpagemiss * pagemiss) * 1000 * 1000 / mclk_freq;
 302                         if (nvclk_freq * 2 > mclk_freq * width)
 303                                 video_fill_us =
 304                                     cbs * 1000 * 1000 / 16 / nvclk_freq;
 305                         else
 306                                 video_fill_us =
 307                                     cbs * 1000 * 1000 / (8 * width) /
 308                                     mclk_freq;
 309                         us_video = vpm_us + us_m + us_n + us_p + video_fill_us;
 310                         vlwm = us_video * video_drain_rate / (1000 * 1000);
 311                         vlwm++;
 312                         vbs = 128;
 313                         if (vlwm > 128)
 314                                 vbs = 64;
 315                         if (vlwm > (256 - 64))
 316                                 vbs = 32;
 317                         if (nvclk_freq * 2 > mclk_freq * width)
 318                                 video_fill_us =
 319                                     vbs * 1000 * 1000 / 16 / nvclk_freq;
 320                         else
 321                                 video_fill_us =
 322                                     vbs * 1000 * 1000 / (8 * width) /
 323                                     mclk_freq;
 324                         cpm_us =
 325                             crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq;
 326                         us_crt =
 327                             us_video + video_fill_us + cpm_us + us_m + us_n +
 328                             us_p;
 329                         clwm = us_crt * crtc_drain_rate / (1000 * 1000);
 330                         clwm++;
 331                 } else {
 332                         crtc_drain_rate = pclk_freq * bpp / 8;
 333                         crtpagemiss = 2;
 334                         crtpagemiss += 1;
 335                         cpm_us =
 336                             crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq;
 337                         us_crt = cpm_us + us_m + us_n + us_p;
 338                         clwm = us_crt * crtc_drain_rate / (1000 * 1000);
 339                         clwm++;
 340                 }
 341                 m1 = clwm + cbs - 512;
 342                 p1 = m1 * pclk_freq / mclk_freq;
 343                 p1 = p1 * bpp / 8;
 344                 if ((p1 < m1) && (m1 > 0)) {
 345                         fifo->valid = 0;
 346                         found = 0;
 347                         if (mclk_extra == 0)
 348                                 found = 1;
 349                         mclk_extra--;
 350                 } else if (video_enable) {
 351                         if ((clwm > 511) || (vlwm > 255)) {
 352                                 fifo->valid = 0;
 353                                 found = 0;
 354                                 if (mclk_extra == 0)
 355                                         found = 1;
 356                                 mclk_extra--;
 357                         }
 358                 } else {
 359                         if (clwm > 519) {
 360                                 fifo->valid = 0;
 361                                 found = 0;
 362                                 if (mclk_extra == 0)
 363                                         found = 1;
 364                                 mclk_extra--;
 365                         }
 366                 }
 367                 if (clwm < 384)
 368                         clwm = 384;
 369                 if (vlwm < 128)
 370                         vlwm = 128;
 371                 data = (int)(clwm);
 372                 fifo->graphics_lwm = data;
 373                 fifo->graphics_burst_size = 128;
 374                 data = (int)((vlwm + 15));
 375                 fifo->video_lwm = data;
 376                 fifo->video_burst_size = vbs;
 377         }
 378 }
 379
 380 static void nv4UpdateArbitrationSettings(unsigned VClk,
 381                                          unsigned pixelDepth,
 382                                          unsigned *burst,
 383                                          unsigned *lwm, struct nvidia_par *par)
 384 {
 385         nv4_fifo_info fifo_data;
 386         nv4_sim_state sim_data;
 387         unsigned int MClk, NVClk, cfg1;
 388
 389         nvGetClocks(par, &MClk, &NVClk);
 390
 391         cfg1 = NV_RD32(par->PFB, 0x00000204);
 392         sim_data.pix_bpp = (char)pixelDepth;
 393         sim_data.enable_video = 0;
 394         sim_data.enable_mp = 0;
 395         sim_data.memory_width = (NV_RD32(par->PEXTDEV, 0x0000) & 0x10) ?
 396             128 : 64;
 397         sim_data.mem_latency = (char)cfg1 & 0x0F;
 398         sim_data.mem_aligned = 1;
 399         sim_data.mem_page_miss =
 400             (char)(((cfg1 >> 4) & 0x0F) + ((cfg1 >> 31) & 0x01));
 401         sim_data.gr_during_vid = 0;
 402         sim_data.pclk_khz = VClk;
 403         sim_data.mclk_khz = MClk;
 404         sim_data.nvclk_khz = NVClk;
 405         nv4CalcArbitration(&fifo_data, &sim_data);
 406         if (fifo_data.valid) {
 407                 int b = fifo_data.graphics_burst_size >> 4;
 408                 *burst = 0;
 409                 while (b >>= 1)
 410                         (*burst)++;
 411                 *lwm = fifo_data.graphics_lwm >> 3;
 412         }
 413 }
 414
 415 static void nv10CalcArbitration(nv10_fifo_info * fifo, nv10_sim_state * arb)
 416 {
 417         int data, pagemiss, width, video_enable, bpp;
 418         int nvclks, mclks, pclks, vpagemiss, crtpagemiss;
 419         int nvclk_fill;
 420         int found, mclk_extra, mclk_loop, cbs, m1;
 421         int mclk_freq, pclk_freq, nvclk_freq, mp_enable;
 422         int us_m, us_m_min, us_n, us_p, crtc_drain_rate;
 423         int vus_m;
 424         int vpm_us, us_video, cpm_us, us_crt, clwm;
 425         int clwm_rnd_down;
 426         int m2us, us_pipe_min, p1clk, p2;
 427         int min_mclk_extra;
 428         int us_min_mclk_extra;
 429
 430         fifo->valid = 1;
 431         pclk_freq = arb->pclk_khz;      /* freq in KHz */
 432         mclk_freq = arb->mclk_khz;
 433         nvclk_freq = arb->nvclk_khz;
 434         pagemiss = arb->mem_page_miss;
 435         width = arb->memory_width / 64;
 436         video_enable = arb->enable_video;
 437         bpp = arb->pix_bpp;
 438         mp_enable = arb->enable_mp;
 439         clwm = 0;
 440
 441         cbs = 512;
 442
 443         pclks = 4;      /* lwm detect. */
 444
 445         nvclks = 3;     /* lwm -> sync. */
 446         nvclks += 2;    /* fbi bus cycles (1 req + 1 busy) */
 447         /* 2 edge sync.  may be very close to edge so just put one. */
 448         mclks = 1;
 449         mclks += 1;     /* arb_hp_req */
 450         mclks += 5;     /* ap_hp_req   tiling pipeline */
 451
 452         mclks += 2;     /* tc_req     latency fifo */
 453         mclks += 2;     /* fb_cas_n_  memory request to fbio block */
 454         mclks += 7;     /* sm_d_rdv   data returned from fbio block */
 455
 456         /* fb.rd.d.Put_gc   need to accumulate 256 bits for read */
 457         if (arb->memory_type == 0)
 458                 if (arb->memory_width == 64)    /* 64 bit bus */
 459                         mclks += 4;
 460                 else
 461                         mclks += 2;
 462         else if (arb->memory_width == 64)       /* 64 bit bus */
 463                 mclks += 2;
 464         else
 465                 mclks += 1;
 466
 467         if ((!video_enable) && (arb->memory_width == 128)) {
 468                 mclk_extra = (bpp == 32) ? 31 : 42;     /* Margin of error */
 469                 min_mclk_extra = 17;
 470         } else {
 471                 mclk_extra = (bpp == 32) ? 8 : 4;       /* Margin of error */
 472                 /* mclk_extra = 4; *//* Margin of error */
 473                 min_mclk_extra = 18;
 474         }
 475
 476         /* 2 edge sync.  may be very close to edge so just put one. */
 477         nvclks += 1;
 478         nvclks += 1;            /* fbi_d_rdv_n */
 479         nvclks += 1;            /* Fbi_d_rdata */
 480         nvclks += 1;            /* crtfifo load */
 481
 482         if (mp_enable)
 483                 mclks += 4;     /* Mp can get in with a burst of 8. */
 484         /* Extra clocks determined by heuristics */
 485
 486         nvclks += 0;
 487         pclks += 0;
 488         found = 0;
 489         while (found != 1) {
 490                 fifo->valid = 1;
 491                 found = 1;
 492                 mclk_loop = mclks + mclk_extra;
 493                 /* Mclk latency in us */
 494                 us_m = mclk_loop * 1000 * 1000 / mclk_freq;
 495                 /* Minimum Mclk latency in us */
 496                 us_m_min = mclks * 1000 * 1000 / mclk_freq;
 497                 us_min_mclk_extra = min_mclk_extra * 1000 * 1000 / mclk_freq;
 498                 /* nvclk latency in us */
 499                 us_n = nvclks * 1000 * 1000 / nvclk_freq;
 500                 /* nvclk latency in us */
 501                 us_p = pclks * 1000 * 1000 / pclk_freq;
 502                 us_pipe_min = us_m_min + us_n + us_p;
 503
 504                 /* Mclk latency in us */
 505                 vus_m = mclk_loop * 1000 * 1000 / mclk_freq;
 506
 507                 if (video_enable) {
 508                         crtc_drain_rate = pclk_freq * bpp / 8;  /* MB/s */
 509
 510                         vpagemiss = 1;  /* self generating page miss */
 511                         vpagemiss += 1; /* One higher priority before */
 512
 513                         crtpagemiss = 2;        /* self generating page miss */
 514                         if (mp_enable)
 515                                 crtpagemiss += 1;       /* if MA0 conflict */
 516
 517                         vpm_us =
 518                             (vpagemiss * pagemiss) * 1000 * 1000 / mclk_freq;
 519
 520                         /* Video has separate read return path */
 521                         us_video = vpm_us + vus_m;
 522
 523                         cpm_us =
 524                             crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq;
 525                         /* Wait for video */
 526                         us_crt = us_video
 527                             + cpm_us    /* CRT Page miss */
 528                             + us_m + us_n + us_p        /* other latency */
 529                             ;
 530
 531                         clwm = us_crt * crtc_drain_rate / (1000 * 1000);
 532                         /* fixed point <= float_point - 1.  Fixes that */
 533                         clwm++;
 534                 } else {
 535                     /* bpp * pclk/8 */
 536                         crtc_drain_rate = pclk_freq * bpp / 8;
 537
 538                         crtpagemiss = 1;        /* self generating page miss */
 539                         crtpagemiss += 1;       /* MA0 page miss */
 540                         if (mp_enable)
 541                                 crtpagemiss += 1;       /* if MA0 conflict */
 542                         cpm_us =
 543                             crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq;
 544                         us_crt = cpm_us + us_m + us_n + us_p;
 545                         clwm = us_crt * crtc_drain_rate / (1000 * 1000);
 546                         /* fixed point <= float_point - 1.  Fixes that */
 547                         clwm++;
 548
 549                         /* Finally, a heuristic check when width == 64 bits */
 550                         if (width == 1) {
 551                                 nvclk_fill = nvclk_freq * 8;
 552                                 if (crtc_drain_rate * 100 >= nvclk_fill * 102)
 553                                         /*Large number to fail */
 554                                         clwm = 0xfff;
 555
 556                                 else if (crtc_drain_rate * 100 >=
 557                                          nvclk_fill * 98) {
 558                                         clwm = 1024;
 559                                         cbs = 512;
 560                                 }
 561                         }
 562                 }
 563
 564                 /*
 565                    Overfill check:
 566                  */
 567
 568                 clwm_rnd_down = ((int)clwm / 8) * 8;
 569                 if (clwm_rnd_down < clwm)
 570                         clwm += 8;
 571
 572                 m1 = clwm + cbs - 1024; /* Amount of overfill */
 573                 m2us = us_pipe_min + us_min_mclk_extra;
 574
 575                 /* pclk cycles to drain */
 576                 p1clk = m2us * pclk_freq / (1000 * 1000);
 577                 p2 = p1clk * bpp / 8;   /* bytes drained. */
 578
 579                 if ((p2 < m1) && (m1 > 0)) {
 580                         fifo->valid = 0;
 581                         found = 0;
 582                         if (min_mclk_extra == 0) {
 583                                 if (cbs <= 32) {
 584                                         /* Can't adjust anymore! */
 585                                         found = 1;
 586                                 } else {
 587                                         /* reduce the burst size */
 588                                         cbs = cbs / 2;
 589                                 }
 590                         } else {
 591                                 min_mclk_extra--;
 592                         }
 593                 } else {
 594                         if (clwm > 1023) {      /* Have some margin */
 595                                 fifo->valid = 0;
 596                                 found = 0;
 597                                 if (min_mclk_extra == 0)
 598                                         /* Can't adjust anymore! */
 599                                         found = 1;
 600                                 else
 601                                         min_mclk_extra--;
 602                         }
 603                 }
 604
 605                 if (clwm < (1024 - cbs + 8))
 606                         clwm = 1024 - cbs + 8;
 607                 data = (int)(clwm);
 608                 /*  printf("CRT LWM: %f bytes, prog: 0x%x, bs: 256\n",
 609                     clwm, data ); */
 610                 fifo->graphics_lwm = data;
 611                 fifo->graphics_burst_size = cbs;
 612
 613                 fifo->video_lwm = 1024;
 614                 fifo->video_burst_size = 512;
 615         }
 616 }
 617
 618 static void nv10UpdateArbitrationSettings(unsigned VClk,
 619                                           unsigned pixelDepth,
 620                                           unsigned *burst,
 621                                           unsigned *lwm,
 622                                           struct nvidia_par *par)
 623 {
 624         nv10_fifo_info fifo_data;
 625         nv10_sim_state sim_data;
 626         unsigned int MClk, NVClk, cfg1;
 627
 628         nvGetClocks(par, &MClk, &NVClk);
 629
 630         cfg1 = NV_RD32(par->PFB, 0x0204);
 631         sim_data.pix_bpp = (char)pixelDepth;
 632         sim_data.enable_video = 1;
 633         sim_data.enable_mp = 0;
 634         sim_data.memory_type = (NV_RD32(par->PFB, 0x0200) & 0x01) ? 1 : 0;
 635         sim_data.memory_width = (NV_RD32(par->PEXTDEV, 0x0000) & 0x10) ?
 636             128 : 64;
 637         sim_data.mem_latency = (char)cfg1 & 0x0F;
 638         sim_data.mem_aligned = 1;
 639         sim_data.mem_page_miss =
 640             (char)(((cfg1 >> 4) & 0x0F) + ((cfg1 >> 31) & 0x01));
 641         sim_data.gr_during_vid = 0;
 642         sim_data.pclk_khz = VClk;
 643         sim_data.mclk_khz = MClk;
 644         sim_data.nvclk_khz = NVClk;
 645         nv10CalcArbitration(&fifo_data, &sim_data);
 646         if (fifo_data.valid) {
 647                 int b = fifo_data.graphics_burst_size >> 4;
 648                 *burst = 0;
 649                 while (b >>= 1)
 650                         (*burst)++;
 651                 *lwm = fifo_data.graphics_lwm >> 3;
 652         }
 653 }
 654
 655 static void nv30UpdateArbitrationSettings (
 656     struct nvidia_par *par,
 657     unsigned int      *burst,
 658     unsigned int      *lwm
 659 )
 660 {
 661     unsigned int MClk, NVClk;
 662     unsigned int fifo_size, burst_size, graphics_lwm;
 663
 664     fifo_size = 2048;
 665     burst_size = 512;
 666     graphics_lwm = fifo_size - burst_size;
 667
 668     nvGetClocks(par, &MClk, &NVClk);
 669
 670     *burst = 0;
 671     burst_size >>= 5;
 672     while(burst_size >>= 1) (*burst)++;
 673     *lwm = graphics_lwm >> 3;
 674 }
 675
 676 static void nForceUpdateArbitrationSettings(unsigned VClk,
 677                                             unsigned pixelDepth,
 678                                             unsigned *burst,
 679                                             unsigned *lwm,
 680                                             struct nvidia_par *par)
 681 {
 682         nv10_fifo_info fifo_data;
 683         nv10_sim_state sim_data;
 684         unsigned int M, N, P, pll, MClk, NVClk, memctrl;
 685         struct pci_dev *dev;
 686
 687         if ((par->Chipset & 0x0FF0) == 0x01A0) {
 688                 unsigned int uMClkPostDiv;
 689                 dev = pci_find_slot(0, 3);
 690                 pci_read_config_dword(dev, 0x6C, &uMClkPostDiv);
 691                 uMClkPostDiv = (uMClkPostDiv >> 8) & 0xf;
 692
 693                 if (!uMClkPostDiv)
 694                         uMClkPostDiv = 4;
 695                 MClk = 400000 / uMClkPostDiv;
 696         } else {
 697                 dev = pci_find_slot(0, 5);
 698                 pci_read_config_dword(dev, 0x4c, &MClk);
 699                 MClk /= 1000;
 700         }
 701
 702         pll = NV_RD32(par->PRAMDAC0, 0x0500);
 703         M = (pll >> 0) & 0xFF;
 704         N = (pll >> 8) & 0xFF;
 705         P = (pll >> 16) & 0x0F;
 706         NVClk = (N * par->CrystalFreqKHz / M) >> P;
 707         sim_data.pix_bpp = (char)pixelDepth;
 708         sim_data.enable_video = 0;
 709         sim_data.enable_mp = 0;
 710         pci_find_slot(0, 1);
 711         pci_read_config_dword(dev, 0x7C, &sim_data.memory_type);
 712         sim_data.memory_type = (sim_data.memory_type >> 12) & 1;
 713         sim_data.memory_width = 64;
 714
 715         dev = pci_find_slot(0, 3);
 716         pci_read_config_dword(dev, 0, &memctrl);
 717         memctrl >>= 16;
 718
 719         if ((memctrl == 0x1A9) || (memctrl == 0x1AB) || (memctrl == 0x1ED)) {
 720                 int dimm[3];
 721
 722                 pci_find_slot(0, 2);
 723                 pci_read_config_dword(dev, 0x40, &dimm[0]);
 724                 dimm[0] = (dimm[0] >> 8) & 0x4f;
 725                 pci_read_config_dword(dev, 0x44, &dimm[1]);
 726                 dimm[1] = (dimm[1] >> 8) & 0x4f;
 727                 pci_read_config_dword(dev, 0x48, &dimm[2]);
 728                 dimm[2] = (dimm[2] >> 8) & 0x4f;
 729
 730                 if ((dimm[0] + dimm[1]) != dimm[2]) {
 731                         printk("nvidiafb: your nForce DIMMs are not arranged "
 732                                "in optimal banks!\n");
 733                 }
 734         }
 735
 736         sim_data.mem_latency = 3;
 737         sim_data.mem_aligned = 1;
 738         sim_data.mem_page_miss = 10;
 739         sim_data.gr_during_vid = 0;
 740         sim_data.pclk_khz = VClk;
 741         sim_data.mclk_khz = MClk;
 742         sim_data.nvclk_khz = NVClk;
 743         nv10CalcArbitration(&fifo_data, &sim_data);
 744         if (fifo_data.valid) {
 745                 int b = fifo_data.graphics_burst_size >> 4;
 746                 *burst = 0;
 747                 while (b >>= 1)
 748                         (*burst)++;
 749                 *lwm = fifo_data.graphics_lwm >> 3;
 750         }
 751 }
 752
 753 /****************************************************************************\
 754 *                                                                            *
 755 *                          RIVA Mode State Routines                          *
 756 *                                                                            *
 757 \****************************************************************************/
 758
 759 /*
 760  * Calculate the Video Clock parameters for the PLL.
 761  */
 762 static void CalcVClock(int clockIn,
 763                        int *clockOut, u32 * pllOut, struct nvidia_par *par)
 764 {
 765         unsigned lowM, highM;
 766         unsigned DeltaNew, DeltaOld;
 767         unsigned VClk, Freq;
 768         unsigned M, N, P;
 769
 770         DeltaOld = 0xFFFFFFFF;
 771
 772         VClk = (unsigned)clockIn;
 773
 774         if (par->CrystalFreqKHz == 13500) {
 775                 lowM = 7;
 776                 highM = 13;
 777         } else {
 778                 lowM = 8;
 779                 highM = 14;
 780         }
 781
 782         for (P = 0; P <= 4; P++) {
 783                 Freq = VClk << P;
 784                 if ((Freq >= 128000) && (Freq <= 350000)) {
 785                         for (M = lowM; M <= highM; M++) {
 786                                 N = ((VClk << P) * M) / par->CrystalFreqKHz;
 787                                 if (N <= 255) {
 788                                         Freq =
 789                                             ((par->CrystalFreqKHz * N) /
 790                                              M) >> P;
 791                                         if (Freq > VClk)
 792                                                 DeltaNew = Freq - VClk;
 793                                         else
 794                                                 DeltaNew = VClk - Freq;
 795                                         if (DeltaNew < DeltaOld) {
 796                                                 *pllOut =
 797                                                     (P << 16) | (N << 8) | M;
 798                                                 *clockOut = Freq;
 799                                                 DeltaOld = DeltaNew;
 800                                         }
 801                                 }
 802                         }
 803                 }
 804         }
 805 }
 806
 807 static void CalcVClock2Stage(int clockIn,
 808                              int *clockOut,
 809                              u32 * pllOut,
 810                              u32 * pllBOut, struct nvidia_par *par)
 811 {
 812         unsigned DeltaNew, DeltaOld;
 813         unsigned VClk, Freq;
 814         unsigned M, N, P;
 815
 816         DeltaOld = 0xFFFFFFFF;
 817
 818         *pllBOut = 0x80000401;  /* fixed at x4 for now */
 819
 820         VClk = (unsigned)clockIn;
 821
 822         for (P = 0; P <= 6; P++) {
 823                 Freq = VClk << P;
 824                 if ((Freq >= 400000) && (Freq <= 1000000)) {
 825                         for (M = 1; M <= 13; M++) {
 826                                 N = ((VClk << P) * M) /
 827                                     (par->CrystalFreqKHz << 2);
 828                                 if ((N >= 5) && (N <= 255)) {
 829                                         Freq =
 830                                             (((par->CrystalFreqKHz << 2) * N) /
 831                                              M) >> P;
 832                                         if (Freq > VClk)
 833                                                 DeltaNew = Freq - VClk;
 834                                         else
 835                                                 DeltaNew = VClk - Freq;
 836                                         if (DeltaNew < DeltaOld) {
 837                                                 *pllOut =
 838                                                     (P << 16) | (N << 8) | M;
 839                                                 *clockOut = Freq;
 840                                                 DeltaOld = DeltaNew;
 841                                         }
 842                                 }
 843                         }
 844                 }
 845         }
 846 }
 847
 848 /*
 849  * Calculate extended mode parameters (SVGA) and save in a
 850  * mode state structure.
 851  */
 852 void NVCalcStateExt(struct nvidia_par *par,
 853                     RIVA_HW_STATE * state,
 854                     int bpp,
 855                     int width,
 856                     int hDisplaySize, int height, int dotClock, int flags)
 857 {
 858         int pixelDepth, VClk = 0;
 859         /*
 860          * Save mode parameters.
 861          */
 862         state->bpp = bpp;       /* this is not bitsPerPixel, it's 8,15,16,32 */
 863         state->width = width;
 864         state->height = height;
 865         /*
 866          * Extended RIVA registers.
 867          */
 868         pixelDepth = (bpp + 1) / 8;
 869         if (par->twoStagePLL)
 870                 CalcVClock2Stage(dotClock, &VClk, &state->pll, &state->pllB,
 871                                  par);
 872         else
 873                 CalcVClock(dotClock, &VClk, &state->pll, par);
 874
 875         switch (par->Architecture) {
 876         case NV_ARCH_04:
 877                 nv4UpdateArbitrationSettings(VClk,
 878                                              pixelDepth * 8,
 879                                              &(state->arbitration0),
 880                                              &(state->arbitration1), par);
 881                 state->cursor0 = 0x00;
 882                 state->cursor1 = 0xbC;
 883                 if (flags & FB_VMODE_DOUBLE)
 884                         state->cursor1 |= 2;
 885                 state->cursor2 = 0x00000000;
 886                 state->pllsel = 0x10000700;
 887                 state->config = 0x00001114;
 888                 state->general = bpp == 16 ? 0x00101100 : 0x00100100;
 889                 state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;
 890                 break;
 891         case NV_ARCH_10:
 892         case NV_ARCH_20:
 893         case NV_ARCH_30:
 894         default:
 895                 if ((par->Chipset & 0xfff0) == 0x0240) {
 896                         state->arbitration0 = 256;
 897                         state->arbitration1 = 0x0480;
 898                 } else if (((par->Chipset & 0xffff) == 0x01A0) ||
 899                     ((par->Chipset & 0xffff) == 0x01f0)) {
 900                         nForceUpdateArbitrationSettings(VClk,
 901                                                         pixelDepth * 8,
 902                                                         &(state->arbitration0),
 903                                                         &(state->arbitration1),
 904                                                         par);
 905                 } else if (par->Architecture < NV_ARCH_30) {
 906                         nv10UpdateArbitrationSettings(VClk,
 907                                                       pixelDepth * 8,
 908                                                       &(state->arbitration0),
 909                                                       &(state->arbitration1),
 910                                                       par);
 911                 } else {
 912                         nv30UpdateArbitrationSettings(par,
 913                                                       &(state->arbitration0),
 914                                                       &(state->arbitration1));
 915                 }
 916
 917                 state->cursor0 = 0x80 | (par->CursorStart >> 17);
 918                 state->cursor1 = (par->CursorStart >> 11) << 2;
 919                 state->cursor2 = par->CursorStart >> 24;
 920                 if (flags & FB_VMODE_DOUBLE)
 921                         state->cursor1 |= 2;
 922                 state->pllsel = 0x10000700;
 923                 state->config = NV_RD32(par->PFB, 0x00000200);
 924                 state->general = bpp == 16 ? 0x00101100 : 0x00100100;
 925                 state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;
 926                 break;
 927         }
 928
 929         if (bpp != 8)           /* DirectColor */
 930                 state->general |= 0x00000030;
 931
 932         state->repaint0 = (((width / 8) * pixelDepth) & 0x700) >> 3;
 933         state->pixel = (pixelDepth > 2) ? 3 : pixelDepth;
 934 }
 935
 936 void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state)
 937 {
 938         int i;
 939
 940         NV_WR32(par->PMC, 0x0140, 0x00000000);
 941         NV_WR32(par->PMC, 0x0200, 0xFFFF00FF);
 942         NV_WR32(par->PMC, 0x0200, 0xFFFFFFFF);
 943
 944         NV_WR32(par->PTIMER, 0x0200 * 4, 0x00000008);
 945         NV_WR32(par->PTIMER, 0x0210 * 4, 0x00000003);
 946         NV_WR32(par->PTIMER, 0x0140 * 4, 0x00000000);
 947         NV_WR32(par->PTIMER, 0x0100 * 4, 0xFFFFFFFF);
 948
 949         if (par->Architecture == NV_ARCH_04) {
 950                 NV_WR32(par->PFB, 0x0200, state->config);
 951         } else if ((par->Architecture < NV_ARCH_40) ||
 952                    (par->Chipset & 0xfff0) == 0x0040) {
 953                 for (i = 0; i < 8; i++) {
 954                         NV_WR32(par->PFB, 0x0240 + (i * 0x10), 0);
 955                         NV_WR32(par->PFB, 0x0244 + (i * 0x10),
 956                                 par->FbMapSize - 1);
 957                 }
 958         } else {
 959                 int regions = 12;
 960
 961                 if (((par->Chipset & 0xfff0) == 0x0090) ||
 962                     ((par->Chipset & 0xfff0) == 0x01D0) ||
 963                     ((par->Chipset & 0xfff0) == 0x0290))
 964                         regions = 15;
 965                 for(i = 0; i < regions; i++) {
 966                         NV_WR32(par->PFB, 0x0600 + (i * 0x10), 0);
 967                         NV_WR32(par->PFB, 0x0604 + (i * 0x10),
 968                                 par->FbMapSize - 1);
 969                 }
 970         }
 971
 972         if (par->Architecture >= NV_ARCH_40) {
 973                 NV_WR32(par->PRAMIN, 0x0000 * 4, 0x80000010);
 974                 NV_WR32(par->PRAMIN, 0x0001 * 4, 0x00101202);
 975                 NV_WR32(par->PRAMIN, 0x0002 * 4, 0x80000011);
 976                 NV_WR32(par->PRAMIN, 0x0003 * 4, 0x00101204);
 977                 NV_WR32(par->PRAMIN, 0x0004 * 4, 0x80000012);
 978                 NV_WR32(par->PRAMIN, 0x0005 * 4, 0x00101206);
 979                 NV_WR32(par->PRAMIN, 0x0006 * 4, 0x80000013);
 980                 NV_WR32(par->PRAMIN, 0x0007 * 4, 0x00101208);
 981                 NV_WR32(par->PRAMIN, 0x0008 * 4, 0x80000014);
 982                 NV_WR32(par->PRAMIN, 0x0009 * 4, 0x0010120A);
 983                 NV_WR32(par->PRAMIN, 0x000A * 4, 0x80000015);
 984                 NV_WR32(par->PRAMIN, 0x000B * 4, 0x0010120C);
 985                 NV_WR32(par->PRAMIN, 0x000C * 4, 0x80000016);
 986                 NV_WR32(par->PRAMIN, 0x000D * 4, 0x0010120E);
 987                 NV_WR32(par->PRAMIN, 0x000E * 4, 0x80000017);
 988                 NV_WR32(par->PRAMIN, 0x000F * 4, 0x00101210);
 989                 NV_WR32(par->PRAMIN, 0x0800 * 4, 0x00003000);
 990                 NV_WR32(par->PRAMIN, 0x0801 * 4, par->FbMapSize - 1);
 991                 NV_WR32(par->PRAMIN, 0x0802 * 4, 0x00000002);
 992                 NV_WR32(par->PRAMIN, 0x0808 * 4, 0x02080062);
 993                 NV_WR32(par->PRAMIN, 0x0809 * 4, 0x00000000);
 994                 NV_WR32(par->PRAMIN, 0x080A * 4, 0x00001200);
 995                 NV_WR32(par->PRAMIN, 0x080B * 4, 0x00001200);
 996                 NV_WR32(par->PRAMIN, 0x080C * 4, 0x00000000);
 997                 NV_WR32(par->PRAMIN, 0x080D * 4, 0x00000000);
 998                 NV_WR32(par->PRAMIN, 0x0810 * 4, 0x02080043);
 999                 NV_WR32(par->PRAMIN, 0x0811 * 4, 0x00000000);
1000                 NV_WR32(par->PRAMIN, 0x0812 * 4, 0x00000000);
1001                 NV_WR32(par->PRAMIN, 0x0813 * 4, 0x00000000);
1002                 NV_WR32(par->PRAMIN, 0x0814 * 4, 0x00000000);
1003                 NV_WR32(par->PRAMIN, 0x0815 * 4, 0x00000000);
1004                 NV_WR32(par->PRAMIN, 0x0818 * 4, 0x02080044);
1005                 NV_WR32(par->PRAMIN, 0x0819 * 4, 0x02000000);
1006                 NV_WR32(par->PRAMIN, 0x081A * 4, 0x00000000);
1007                 NV_WR32(par->PRAMIN, 0x081B * 4, 0x00000000);
1008                 NV_WR32(par->PRAMIN, 0x081C * 4, 0x00000000);
1009                 NV_WR32(par->PRAMIN, 0x081D * 4, 0x00000000);
1010                 NV_WR32(par->PRAMIN, 0x0820 * 4, 0x02080019);
1011                 NV_WR32(par->PRAMIN, 0x0821 * 4, 0x00000000);
1012                 NV_WR32(par->PRAMIN, 0x0822 * 4, 0x00000000);
1013                 NV_WR32(par->PRAMIN, 0x0823 * 4, 0x00000000);
1014                 NV_WR32(par->PRAMIN, 0x0824 * 4, 0x00000000);
1015                 NV_WR32(par->PRAMIN, 0x0825 * 4, 0x00000000);
1016                 NV_WR32(par->PRAMIN, 0x0828 * 4, 0x020A005C);
1017                 NV_WR32(par->PRAMIN, 0x0829 * 4, 0x00000000);
1018                 NV_WR32(par->PRAMIN, 0x082A * 4, 0x00000000);
1019                 NV_WR32(par->PRAMIN, 0x082B * 4, 0x00000000);
1020                 NV_WR32(par->PRAMIN, 0x082C * 4, 0x00000000);
1021                 NV_WR32(par->PRAMIN, 0x082D * 4, 0x00000000);
1022                 NV_WR32(par->PRAMIN, 0x0830 * 4, 0x0208009F);
1023                 NV_WR32(par->PRAMIN, 0x0831 * 4, 0x00000000);
1024                 NV_WR32(par->PRAMIN, 0x0832 * 4, 0x00001200);
1025                 NV_WR32(par->PRAMIN, 0x0833 * 4, 0x00001200);
1026                 NV_WR32(par->PRAMIN, 0x0834 * 4, 0x00000000);
1027                 NV_WR32(par->PRAMIN, 0x0835 * 4, 0x00000000);
1028                 NV_WR32(par->PRAMIN, 0x0838 * 4, 0x0208004A);
1029                 NV_WR32(par->PRAMIN, 0x0839 * 4, 0x02000000);
1030                 NV_WR32(par->PRAMIN, 0x083A * 4, 0x00000000);
1031                 NV_WR32(par->PRAMIN, 0x083B * 4, 0x00000000);
1032                 NV_WR32(par->PRAMIN, 0x083C * 4, 0x00000000);
1033                 NV_WR32(par->PRAMIN, 0x083D * 4, 0x00000000);
1034                 NV_WR32(par->PRAMIN, 0x0840 * 4, 0x02080077);
1035                 NV_WR32(par->PRAMIN, 0x0841 * 4, 0x00000000);
1036                 NV_WR32(par->PRAMIN, 0x0842 * 4, 0x00001200);
1037                 NV_WR32(par->PRAMIN, 0x0843 * 4, 0x00001200);
1038                 NV_WR32(par->PRAMIN, 0x0844 * 4, 0x00000000);
1039                 NV_WR32(par->PRAMIN, 0x0845 * 4, 0x00000000);
1040                 NV_WR32(par->PRAMIN, 0x084C * 4, 0x00003002);
1041                 NV_WR32(par->PRAMIN, 0x084D * 4, 0x00007FFF);
1042                 NV_WR32(par->PRAMIN, 0x084E * 4,
1043                         par->FbUsableSize | 0x00000002);
1044
1045 #ifdef __BIG_ENDIAN
1046                 NV_WR32(par->PRAMIN, 0x080A * 4,
1047                         NV_RD32(par->PRAMIN, 0x080A * 4) | 0x01000000);
1048                 NV_WR32(par->PRAMIN, 0x0812 * 4,
1049                         NV_RD32(par->PRAMIN, 0x0812 * 4) | 0x01000000);
1050                 NV_WR32(par->PRAMIN, 0x081A * 4,
1051                         NV_RD32(par->PRAMIN, 0x081A * 4) | 0x01000000);
1052                 NV_WR32(par->PRAMIN, 0x0822 * 4,
1053                         NV_RD32(par->PRAMIN, 0x0822 * 4) | 0x01000000);
1054                 NV_WR32(par->PRAMIN, 0x082A * 4,
1055                         NV_RD32(par->PRAMIN, 0x082A * 4) | 0x01000000);
1056                 NV_WR32(par->PRAMIN, 0x0832 * 4,
1057                         NV_RD32(par->PRAMIN, 0x0832 * 4) | 0x01000000);
1058                 NV_WR32(par->PRAMIN, 0x083A * 4,
1059                         NV_RD32(par->PRAMIN, 0x083A * 4) | 0x01000000);
1060                 NV_WR32(par->PRAMIN, 0x0842 * 4,
1061                         NV_RD32(par->PRAMIN, 0x0842 * 4) | 0x01000000);
1062                 NV_WR32(par->PRAMIN, 0x0819 * 4, 0x01000000);
1063                 NV_WR32(par->PRAMIN, 0x0839 * 4, 0x01000000);
1064 #endif
1065         } else {
1066                 NV_WR32(par->PRAMIN, 0x0000 * 4, 0x80000010);
1067                 NV_WR32(par->PRAMIN, 0x0001 * 4, 0x80011201);
1068                 NV_WR32(par->PRAMIN, 0x0002 * 4, 0x80000011);
1069                 NV_WR32(par->PRAMIN, 0x0003 * 4, 0x80011202);
1070                 NV_WR32(par->PRAMIN, 0x0004 * 4, 0x80000012);
1071                 NV_WR32(par->PRAMIN, 0x0005 * 4, 0x80011203);
1072                 NV_WR32(par->PRAMIN, 0x0006 * 4, 0x80000013);
1073                 NV_WR32(par->PRAMIN, 0x0007 * 4, 0x80011204);
1074                 NV_WR32(par->PRAMIN, 0x0008 * 4, 0x80000014);
1075                 NV_WR32(par->PRAMIN, 0x0009 * 4, 0x80011205);
1076                 NV_WR32(par->PRAMIN, 0x000A * 4, 0x80000015);
1077                 NV_WR32(par->PRAMIN, 0x000B * 4, 0x80011206);
1078                 NV_WR32(par->PRAMIN, 0x000C * 4, 0x80000016);
1079                 NV_WR32(par->PRAMIN, 0x000D * 4, 0x80011207);
1080                 NV_WR32(par->PRAMIN, 0x000E * 4, 0x80000017);
1081                 NV_WR32(par->PRAMIN, 0x000F * 4, 0x80011208);
1082                 NV_WR32(par->PRAMIN, 0x0800 * 4, 0x00003000);
1083                 NV_WR32(par->PRAMIN, 0x0801 * 4, par->FbMapSize - 1);
1084                 NV_WR32(par->PRAMIN, 0x0802 * 4, 0x00000002);
1085                 NV_WR32(par->PRAMIN, 0x0803 * 4, 0x00000002);
1086                 if (par->Architecture >= NV_ARCH_10)
1087                         NV_WR32(par->PRAMIN, 0x0804 * 4, 0x01008062);
1088                 else
1089                         NV_WR32(par->PRAMIN, 0x0804 * 4, 0x01008042);
1090                 NV_WR32(par->PRAMIN, 0x0805 * 4, 0x00000000);
1091                 NV_WR32(par->PRAMIN, 0x0806 * 4, 0x12001200);
1092                 NV_WR32(par->PRAMIN, 0x0807 * 4, 0x00000000);
1093                 NV_WR32(par->PRAMIN, 0x0808 * 4, 0x01008043);
1094                 NV_WR32(par->PRAMIN, 0x0809 * 4, 0x00000000);
1095                 NV_WR32(par->PRAMIN, 0x080A * 4, 0x00000000);
1096                 NV_WR32(par->PRAMIN, 0x080B * 4, 0x00000000);
1097                 NV_WR32(par->PRAMIN, 0x080C * 4, 0x01008044);
1098                 NV_WR32(par->PRAMIN, 0x080D * 4, 0x00000002);
1099                 NV_WR32(par->PRAMIN, 0x080E * 4, 0x00000000);
1100                 NV_WR32(par->PRAMIN, 0x080F * 4, 0x00000000);
1101                 NV_WR32(par->PRAMIN, 0x0810 * 4, 0x01008019);
1102                 NV_WR32(par->PRAMIN, 0x0811 * 4, 0x00000000);
1103                 NV_WR32(par->PRAMIN, 0x0812 * 4, 0x00000000);
1104                 NV_WR32(par->PRAMIN, 0x0813 * 4, 0x00000000);
1105                 NV_WR32(par->PRAMIN, 0x0814 * 4, 0x0100A05C);
1106                 NV_WR32(par->PRAMIN, 0x0815 * 4, 0x00000000);
1107                 NV_WR32(par->PRAMIN, 0x0816 * 4, 0x00000000);
1108                 NV_WR32(par->PRAMIN, 0x0817 * 4, 0x00000000);
1109                 if (par->WaitVSyncPossible)
1110                         NV_WR32(par->PRAMIN, 0x0818 * 4, 0x0100809F);
1111                 else
1112                         NV_WR32(par->PRAMIN, 0x0818 * 4, 0x0100805F);
1113                 NV_WR32(par->PRAMIN, 0x0819 * 4, 0x00000000);
1114                 NV_WR32(par->PRAMIN, 0x081A * 4, 0x12001200);
1115                 NV_WR32(par->PRAMIN, 0x081B * 4, 0x00000000);
1116                 NV_WR32(par->PRAMIN, 0x081C * 4, 0x0100804A);
1117                 NV_WR32(par->PRAMIN, 0x081D * 4, 0x00000002);
1118                 NV_WR32(par->PRAMIN, 0x081E * 4, 0x00000000);
1119                 NV_WR32(par->PRAMIN, 0x081F * 4, 0x00000000);
1120                 NV_WR32(par->PRAMIN, 0x0820 * 4, 0x01018077);
1121                 NV_WR32(par->PRAMIN, 0x0821 * 4, 0x00000000);
1122                 NV_WR32(par->PRAMIN, 0x0822 * 4, 0x12001200);
1123                 NV_WR32(par->PRAMIN, 0x0823 * 4, 0x00000000);
1124                 NV_WR32(par->PRAMIN, 0x0824 * 4, 0x00003002);
1125                 NV_WR32(par->PRAMIN, 0x0825 * 4, 0x00007FFF);
1126                 NV_WR32(par->PRAMIN, 0x0826 * 4,
1127                         par->FbUsableSize | 0x00000002);
1128                 NV_WR32(par->PRAMIN, 0x0827 * 4, 0x00000002);
1129 #ifdef __BIG_ENDIAN
1130                 NV_WR32(par->PRAMIN, 0x0804 * 4,
1131                         NV_RD32(par->PRAMIN, 0x0804 * 4) | 0x00080000);
1132                 NV_WR32(par->PRAMIN, 0x0808 * 4,
1133                         NV_RD32(par->PRAMIN, 0x0808 * 4) | 0x00080000);
1134                 NV_WR32(par->PRAMIN, 0x080C * 4,
1135                         NV_RD32(par->PRAMIN, 0x080C * 4) | 0x00080000);
1136                 NV_WR32(par->PRAMIN, 0x0810 * 4,
1137                         NV_RD32(par->PRAMIN, 0x0810 * 4) | 0x00080000);
1138                 NV_WR32(par->PRAMIN, 0x0814 * 4,
1139                         NV_RD32(par->PRAMIN, 0x0814 * 4) | 0x00080000);
1140                 NV_WR32(par->PRAMIN, 0x0818 * 4,
1141                         NV_RD32(par->PRAMIN, 0x0818 * 4) | 0x00080000);
1142                 NV_WR32(par->PRAMIN, 0x081C * 4,
1143                         NV_RD32(par->PRAMIN, 0x081C * 4) | 0x00080000);
1144                 NV_WR32(par->PRAMIN, 0x0820 * 4,
1145                         NV_RD32(par->PRAMIN, 0x0820 * 4) | 0x00080000);
1146                 NV_WR32(par->PRAMIN, 0x080D * 4, 0x00000001);
1147                 NV_WR32(par->PRAMIN, 0x081D * 4, 0x00000001);
1148 #endif
1149         }
1150         if (par->Architecture < NV_ARCH_10) {
1151                 if ((par->Chipset & 0x0fff) == 0x0020) {
1152                         NV_WR32(par->PRAMIN, 0x0824 * 4,
1153                                 NV_RD32(par->PRAMIN, 0x0824 * 4) | 0x00020000);
1154                         NV_WR32(par->PRAMIN, 0x0826 * 4,
1155                                 NV_RD32(par->PRAMIN,
1156                                         0x0826 * 4) + par->FbAddress);
1157                 }
1158                 NV_WR32(par->PGRAPH, 0x0080, 0x000001FF);
1159                 NV_WR32(par->PGRAPH, 0x0080, 0x1230C000);
1160                 NV_WR32(par->PGRAPH, 0x0084, 0x72111101);
1161                 NV_WR32(par->PGRAPH, 0x0088, 0x11D5F071);
1162                 NV_WR32(par->PGRAPH, 0x008C, 0x0004FF31);
1163                 NV_WR32(par->PGRAPH, 0x008C, 0x4004FF31);
1164                 NV_WR32(par->PGRAPH, 0x0140, 0x00000000);
1165                 NV_WR32(par->PGRAPH, 0x0100, 0xFFFFFFFF);
1166                 NV_WR32(par->PGRAPH, 0x0170, 0x10010100);
1167                 NV_WR32(par->PGRAPH, 0x0710, 0xFFFFFFFF);
1168                 NV_WR32(par->PGRAPH, 0x0720, 0x00000001);
1169                 NV_WR32(par->PGRAPH, 0x0810, 0x00000000);
1170                 NV_WR32(par->PGRAPH, 0x0608, 0xFFFFFFFF);
1171         } else {
1172                 NV_WR32(par->PGRAPH, 0x0080, 0xFFFFFFFF);
1173                 NV_WR32(par->PGRAPH, 0x0080, 0x00000000);
1174
1175                 NV_WR32(par->PGRAPH, 0x0140, 0x00000000);
1176                 NV_WR32(par->PGRAPH, 0x0100, 0xFFFFFFFF);
1177                 NV_WR32(par->PGRAPH, 0x0144, 0x10010100);
1178                 NV_WR32(par->PGRAPH, 0x0714, 0xFFFFFFFF);
1179                 NV_WR32(par->PGRAPH, 0x0720, 0x00000001);
1180                 NV_WR32(par->PGRAPH, 0x0710,
1181                         NV_RD32(par->PGRAPH, 0x0710) & 0x0007ff00);
1182                 NV_WR32(par->PGRAPH, 0x0710,
1183                         NV_RD32(par->PGRAPH, 0x0710) | 0x00020100);
1184
1185                 if (par->Architecture == NV_ARCH_10) {
1186                         NV_WR32(par->PGRAPH, 0x0084, 0x00118700);
1187                         NV_WR32(par->PGRAPH, 0x0088, 0x24E00810);
1188                         NV_WR32(par->PGRAPH, 0x008C, 0x55DE0030);
1189
1190                         for (i = 0; i < 32; i++)
1191                                 NV_WR32(&par->PGRAPH[(0x0B00 / 4) + i], 0,
1192                                         NV_RD32(&par->PFB[(0x0240 / 4) + i],
1193                                                 0));
1194
1195                         NV_WR32(par->PGRAPH, 0x640, 0);
1196                         NV_WR32(par->PGRAPH, 0x644, 0);
1197                         NV_WR32(par->PGRAPH, 0x684, par->FbMapSize - 1);
1198                         NV_WR32(par->PGRAPH, 0x688, par->FbMapSize - 1);
1199
1200                         NV_WR32(par->PGRAPH, 0x0810, 0x00000000);
1201                         NV_WR32(par->PGRAPH, 0x0608, 0xFFFFFFFF);
1202                 } else {
1203                         if (par->Architecture >= NV_ARCH_40) {
1204                                 u32 tmp;
1205
1206                                 NV_WR32(par->PGRAPH, 0x0084, 0x401287c0);
1207                                 NV_WR32(par->PGRAPH, 0x008C, 0x60de8051);
1208                                 NV_WR32(par->PGRAPH, 0x0090, 0x00008000);
1209                                 NV_WR32(par->PGRAPH, 0x0610, 0x00be3c5f);
1210
1211                                 tmp = NV_RD32(par->REGS, 0x1540) & 0xff;
1212                                 for(i = 0; tmp && !(tmp & 1); tmp >>= 1, i++);
1213                                 NV_WR32(par->PGRAPH, 0x5000, i);
1214
1215                                 if ((par->Chipset & 0xfff0) == 0x0040) {
1216                                         NV_WR32(par->PGRAPH, 0x09b0,
1217                                                 0x83280fff);
1218                                         NV_WR32(par->PGRAPH, 0x09b4,
1219                                                 0x000000a0);
1220                                 } else {
1221                                         NV_WR32(par->PGRAPH, 0x0820,
1222                                                 0x83280eff);
1223                                         NV_WR32(par->PGRAPH, 0x0824,
1224                                                 0x000000a0);
1225                                 }
1226
1227                                 switch (par->Chipset & 0xfff0) {
1228                                 case 0x0040:
1229                                 case 0x0210:
1230                                         NV_WR32(par->PGRAPH, 0x09b8,
1231                                                 0x0078e366);
1232                                         NV_WR32(par->PGRAPH, 0x09bc,
1233                                                 0x0000014c);
1234                                         NV_WR32(par->PFB, 0x033C,
1235                                                 NV_RD32(par->PFB, 0x33C) &
1236                                                 0xffff7fff);
1237                                         break;
1238                                 case 0x00C0:
1239                                 case 0x0120:
1240                                         NV_WR32(par->PGRAPH, 0x0828,
1241                                                 0x007596ff);
1242                                         NV_WR32(par->PGRAPH, 0x082C,
1243                                                 0x00000108);
1244                                         break;
1245                                 case 0x0160:
1246                                 case 0x01D0:
1247                                 case 0x0240:
1248                                         NV_WR32(par->PMC, 0x1700,
1249                                                 NV_RD32(par->PFB, 0x020C));
1250                                         NV_WR32(par->PMC, 0x1704, 0);
1251                                         NV_WR32(par->PMC, 0x1708, 0);
1252                                         NV_WR32(par->PMC, 0x170C,
1253                                                 NV_RD32(par->PFB, 0x020C));
1254                                         NV_WR32(par->PGRAPH, 0x0860, 0);
1255                                         NV_WR32(par->PGRAPH, 0x0864, 0);
1256                                         NV_WR32(par->PRAMDAC, 0x0608,
1257                                                 NV_RD32(par->PRAMDAC,
1258                                                         0x0608) | 0x00100000);
1259                                         break;
1260                                 case 0x0140:
1261                                         NV_WR32(par->PGRAPH, 0x0828,
1262                                                 0x0072cb77);
1263                                         NV_WR32(par->PGRAPH, 0x082C,
1264                                                 0x00000108);
1265                                         break;
1266                                 case 0x0220:
1267                                 case 0x0230:
1268                                         NV_WR32(par->PGRAPH, 0x0860, 0);
1269                                         NV_WR32(par->PGRAPH, 0x0864, 0);
1270                                         NV_WR32(par->PRAMDAC, 0x0608,
1271                                                 NV_RD32(par->PRAMDAC, 0x0608) |
1272                                                 0x00100000);
1273                                         break;
1274                                 case 0x0090:
1275                                 case 0x0290:
1276                                         NV_WR32(par->PRAMDAC, 0x0608,
1277                                                 NV_RD32(par->PRAMDAC, 0x0608) |
1278                                                 0x00100000);
1279                                         NV_WR32(par->PGRAPH, 0x0828,
1280                                                 0x07830610);
1281                                         NV_WR32(par->PGRAPH, 0x082C,
1282                                                 0x0000016A);
1283                                         break;
1284                                 default:
1285                                         break;
1286                                 };
1287
1288                                 NV_WR32(par->PGRAPH, 0x0b38, 0x2ffff800);
1289                                 NV_WR32(par->PGRAPH, 0x0b3c, 0x00006000);
1290                                 NV_WR32(par->PGRAPH, 0x032C, 0x01000000);
1291                                 NV_WR32(par->PGRAPH, 0x0220, 0x00001200);
1292                         } else if (par->Architecture == NV_ARCH_30) {
1293                                 NV_WR32(par->PGRAPH, 0x0084, 0x40108700);
1294                                 NV_WR32(par->PGRAPH, 0x0890, 0x00140000);
1295                                 NV_WR32(par->PGRAPH, 0x008C, 0xf00e0431);
1296                                 NV_WR32(par->PGRAPH, 0x0090, 0x00008000);
1297                                 NV_WR32(par->PGRAPH, 0x0610, 0xf04b1f36);
1298                                 NV_WR32(par->PGRAPH, 0x0B80, 0x1002d888);
1299                                 NV_WR32(par->PGRAPH, 0x0B88, 0x62ff007f);
1300                         } else {
1301                                 NV_WR32(par->PGRAPH, 0x0084, 0x00118700);
1302                                 NV_WR32(par->PGRAPH, 0x008C, 0xF20E0431);
1303                                 NV_WR32(par->PGRAPH, 0x0090, 0x00000000);
1304                                 NV_WR32(par->PGRAPH, 0x009C, 0x00000040);
1305
1306                                 if ((par->Chipset & 0x0ff0) >= 0x0250) {
1307                                         NV_WR32(par->PGRAPH, 0x0890,
1308                                                 0x00080000);
1309                                         NV_WR32(par->PGRAPH, 0x0610,
1310                                                 0x304B1FB6);
1311                                         NV_WR32(par->PGRAPH, 0x0B80,
1312                                                 0x18B82880);
1313                                         NV_WR32(par->PGRAPH, 0x0B84,
1314                                                 0x44000000);
1315                                         NV_WR32(par->PGRAPH, 0x0098,
1316                                                 0x40000080);
1317                                         NV_WR32(par->PGRAPH, 0x0B88,
1318                                                 0x000000ff);
1319                                 } else {
1320                                         NV_WR32(par->PGRAPH, 0x0880,
1321                                                 0x00080000);
1322                                         NV_WR32(par->PGRAPH, 0x0094,
1323                                                 0x00000005);
1324                                         NV_WR32(par->PGRAPH, 0x0B80,
1325                                                 0x45CAA208);
1326                                         NV_WR32(par->PGRAPH, 0x0B84,
1327                                                 0x24000000);
1328                                         NV_WR32(par->PGRAPH, 0x0098,
1329                                                 0x00000040);
1330                                         NV_WR32(par->PGRAPH, 0x0750,
1331                                                 0x00E00038);
1332                                         NV_WR32(par->PGRAPH, 0x0754,
1333                                                 0x00000030);
1334                                         NV_WR32(par->PGRAPH, 0x0750,
1335                                                 0x00E10038);
1336                                         NV_WR32(par->PGRAPH, 0x0754,
1337                                                 0x00000030);
1338                                 }
1339                         }
1340
1341                         if ((par->Architecture < NV_ARCH_40) ||
1342                             ((par->Chipset & 0xfff0) == 0x0040)) {
1343                                 for (i = 0; i < 32; i++) {
1344                                         NV_WR32(par->PGRAPH, 0x0900 + i*4,
1345                                                 NV_RD32(par->PFB, 0x0240 +i*4));
1346                                         NV_WR32(par->PGRAPH, 0x6900 + i*4,
1347                                                 NV_RD32(par->PFB, 0x0240 +i*4));
1348                                 }
1349                         } else {
1350                                 if (((par->Chipset & 0xfff0) == 0x0090) ||
1351                                     ((par->Chipset & 0xfff0) == 0x01D0) ||
1352                                     ((par->Chipset & 0xfff0) == 0x0290)) {
1353                                         for (i = 0; i < 60; i++) {
1354                                                 NV_WR32(par->PGRAPH,
1355                                                         0x0D00 + i*4,
1356                                                         NV_RD32(par->PFB,
1357                                                                 0x0600 + i*4));
1358                                                 NV_WR32(par->PGRAPH,
1359                                                         0x6900 + i*4,
1360                                                         NV_RD32(par->PFB,
1361                                                                 0x0600 + i*4));
1362                                         }
1363                                 } else {
1364                                         for (i = 0; i < 48; i++) {
1365                                                 NV_WR32(par->PGRAPH,
1366                                                         0x0900 + i*4,
1367                                                         NV_RD32(par->PFB,
1368                                                                 0x0600 + i*4));
1369                                                 if(((par->Chipset & 0xfff0)
1370                                                     != 0x0160) &&
1371                                                    ((par->Chipset & 0xfff0)
1372                                                     != 0x0220) &&
1373                                                    ((par->Chipset & 0xfff0)
1374                                                     != 0x240))
1375                                                         NV_WR32(par->PGRAPH,
1376                                                                 0x6900 + i*4,
1377                                                                 NV_RD32(par->PFB,
1378                                                                         0x0600 + i*4));
1379                                         }
1380                                 }
1381                         }
1382
1383                         if (par->Architecture >= NV_ARCH_40) {
1384                                 if ((par->Chipset & 0xfff0) == 0x0040) {
1385                                         NV_WR32(par->PGRAPH, 0x09A4,
1386                                                 NV_RD32(par->PFB, 0x0200));
1387                                         NV_WR32(par->PGRAPH, 0x09A8,
1388                                                 NV_RD32(par->PFB, 0x0204));
1389                                         NV_WR32(par->PGRAPH, 0x69A4,
1390                                                 NV_RD32(par->PFB, 0x0200));
1391                                         NV_WR32(par->PGRAPH, 0x69A8,
1392                                                 NV_RD32(par->PFB, 0x0204));
1393
1394                                         NV_WR32(par->PGRAPH, 0x0820, 0);
1395                                         NV_WR32(par->PGRAPH, 0x0824, 0);
1396                                         NV_WR32(par->PGRAPH, 0x0864,
1397                                                 par->FbMapSize - 1);
1398                                         NV_WR32(par->PGRAPH, 0x0868,
1399                                                 par->FbMapSize - 1);
1400                                 } else {
1401                                         if ((par->Chipset & 0xfff0) == 0x0090 ||
1402                                             (par->Chipset & 0xfff0) == 0x01D0 ||
1403                                             (par->Chipset & 0xfff0) == 0x0290) {
1404                                                 NV_WR32(par->PGRAPH, 0x0DF0,
1405                                                         NV_RD32(par->PFB, 0x0200));
1406                                                 NV_WR32(par->PGRAPH, 0x0DF4,
1407                                                         NV_RD32(par->PFB, 0x0204));
1408                                         } else {
1409                                                 NV_WR32(par->PGRAPH, 0x09F0,
1410                                                         NV_RD32(par->PFB, 0x0200));
1411                                                 NV_WR32(par->PGRAPH, 0x09F4,
1412                                                         NV_RD32(par->PFB, 0x0204));
1413                                         }
1414                                         NV_WR32(par->PGRAPH, 0x69F0,
1415                                                 NV_RD32(par->PFB, 0x0200));
1416                                         NV_WR32(par->PGRAPH, 0x69F4,
1417                                                 NV_RD32(par->PFB, 0x0204));
1418
1419                                         NV_WR32(par->PGRAPH, 0x0840, 0);
1420                                         NV_WR32(par->PGRAPH, 0x0844, 0);
1421                                         NV_WR32(par->PGRAPH, 0x08a0,
1422                                                 par->FbMapSize - 1);
1423                                         NV_WR32(par->PGRAPH, 0x08a4,
1424                                                 par->FbMapSize - 1);
1425                                 }
1426                         } else {
1427                                 NV_WR32(par->PGRAPH, 0x09A4,
1428                                         NV_RD32(par->PFB, 0x0200));
1429                                 NV_WR32(par->PGRAPH, 0x09A8,
1430                                         NV_RD32(par->PFB, 0x0204));
1431                                 NV_WR32(par->PGRAPH, 0x0750, 0x00EA0000);
1432                                 NV_WR32(par->PGRAPH, 0x0754,
1433                                         NV_RD32(par->PFB, 0x0200));
1434                                 NV_WR32(par->PGRAPH, 0x0750, 0x00EA0004);
1435                                 NV_WR32(par->PGRAPH, 0x0754,
1436                                         NV_RD32(par->PFB, 0x0204));
1437
1438                                 NV_WR32(par->PGRAPH, 0x0820, 0);
1439                                 NV_WR32(par->PGRAPH, 0x0824, 0);
1440                                 NV_WR32(par->PGRAPH, 0x0864,
1441                                         par->FbMapSize - 1);
1442                                 NV_WR32(par->PGRAPH, 0x0868,
1443                                         par->FbMapSize - 1);
1444                         }
1445                         NV_WR32(par->PGRAPH, 0x0B20, 0x00000000);
1446                         NV_WR32(par->PGRAPH, 0x0B04, 0xFFFFFFFF);
1447                 }
1448         }
1449         NV_WR32(par->PGRAPH, 0x053C, 0);
1450         NV_WR32(par->PGRAPH, 0x0540, 0);
1451         NV_WR32(par->PGRAPH, 0x0544, 0x00007FFF);
1452         NV_WR32(par->PGRAPH, 0x0548, 0x00007FFF);
1453
1454         NV_WR32(par->PFIFO, 0x0140 * 4, 0x00000000);
1455         NV_WR32(par->PFIFO, 0x0141 * 4, 0x00000001);
1456         NV_WR32(par->PFIFO, 0x0480 * 4, 0x00000000);
1457         NV_WR32(par->PFIFO, 0x0494 * 4, 0x00000000);
1458         if (par->Architecture >= NV_ARCH_40)
1459                 NV_WR32(par->PFIFO, 0x0481 * 4, 0x00010000);
1460         else
1461                 NV_WR32(par->PFIFO, 0x0481 * 4, 0x00000100);
1462         NV_WR32(par->PFIFO, 0x0490 * 4, 0x00000000);
1463         NV_WR32(par->PFIFO, 0x0491 * 4, 0x00000000);
1464         if (par->Architecture >= NV_ARCH_40)
1465                 NV_WR32(par->PFIFO, 0x048B * 4, 0x00001213);
1466         else
1467                 NV_WR32(par->PFIFO, 0x048B * 4, 0x00001209);
1468         NV_WR32(par->PFIFO, 0x0400 * 4, 0x00000000);
1469         NV_WR32(par->PFIFO, 0x0414 * 4, 0x00000000);
1470         NV_WR32(par->PFIFO, 0x0084 * 4, 0x03000100);
1471         NV_WR32(par->PFIFO, 0x0085 * 4, 0x00000110);
1472         NV_WR32(par->PFIFO, 0x0086 * 4, 0x00000112);
1473         NV_WR32(par->PFIFO, 0x0143 * 4, 0x0000FFFF);
1474         NV_WR32(par->PFIFO, 0x0496 * 4, 0x0000FFFF);
1475         NV_WR32(par->PFIFO, 0x0050 * 4, 0x00000000);
1476         NV_WR32(par->PFIFO, 0x0040 * 4, 0xFFFFFFFF);
1477         NV_WR32(par->PFIFO, 0x0415 * 4, 0x00000001);
1478         NV_WR32(par->PFIFO, 0x048C * 4, 0x00000000);
1479         NV_WR32(par->PFIFO, 0x04A0 * 4, 0x00000000);
1480 #ifdef __BIG_ENDIAN
1481         NV_WR32(par->PFIFO, 0x0489 * 4, 0x800F0078);
1482 #else
1483         NV_WR32(par->PFIFO, 0x0489 * 4, 0x000F0078);
1484 #endif
1485         NV_WR32(par->PFIFO, 0x0488 * 4, 0x00000001);
1486         NV_WR32(par->PFIFO, 0x0480 * 4, 0x00000001);
1487         NV_WR32(par->PFIFO, 0x0494 * 4, 0x00000001);
1488         NV_WR32(par->PFIFO, 0x0495 * 4, 0x00000001);
1489         NV_WR32(par->PFIFO, 0x0140 * 4, 0x00000001);
1490         if (par->Architecture >= NV_ARCH_10) {
1491                 if (par->twoHeads) {
1492                         NV_WR32(par->PCRTC0, 0x0860, state->head);
1493                         NV_WR32(par->PCRTC0, 0x2860, state->head2);
1494                 }
1495                 NV_WR32(par->PRAMDAC, 0x0404, NV_RD32(par->PRAMDAC, 0x0404) |
1496                         (1 << 25));
1497
1498                 NV_WR32(par->PMC, 0x8704, 1);
1499                 NV_WR32(par->PMC, 0x8140, 0);
1500                 NV_WR32(par->PMC, 0x8920, 0);
1501                 NV_WR32(par->PMC, 0x8924, 0);
1502                 NV_WR32(par->PMC, 0x8908, par->FbMapSize - 1);
1503                 NV_WR32(par->PMC, 0x890C, par->FbMapSize - 1);
1504                 NV_WR32(par->PMC, 0x1588, 0);
1505
1506                 NV_WR32(par->PCRTC, 0x0810, state->cursorConfig);
1507                 NV_WR32(par->PCRTC, 0x0830, state->displayV - 3);
1508                 NV_WR32(par->PCRTC, 0x0834, state->displayV - 1);
1509
1510                 if (par->FlatPanel) {
1511                         if ((par->Chipset & 0x0ff0) == 0x0110) {
1512                                 NV_WR32(par->PRAMDAC, 0x0528, state->dither);
1513                         } else if (par->twoHeads) {
1514                                 NV_WR32(par->PRAMDAC, 0x083C, state->dither);
1515                         }
1516
1517                         VGA_WR08(par->PCIO, 0x03D4, 0x53);
1518                         VGA_WR08(par->PCIO, 0x03D5, state->timingH);
1519                         VGA_WR08(par->PCIO, 0x03D4, 0x54);
1520                         VGA_WR08(par->PCIO, 0x03D5, state->timingV);
1521                         VGA_WR08(par->PCIO, 0x03D4, 0x21);
1522                         VGA_WR08(par->PCIO, 0x03D5, 0xfa);
1523                 }
1524
1525                 VGA_WR08(par->PCIO, 0x03D4, 0x41);
1526                 VGA_WR08(par->PCIO, 0x03D5, state->extra);
1527         }
1528
1529         VGA_WR08(par->PCIO, 0x03D4, 0x19);
1530         VGA_WR08(par->PCIO, 0x03D5, state->repaint0);
1531         VGA_WR08(par->PCIO, 0x03D4, 0x1A);
1532         VGA_WR08(par->PCIO, 0x03D5, state->repaint1);
1533         VGA_WR08(par->PCIO, 0x03D4, 0x25);
1534         VGA_WR08(par->PCIO, 0x03D5, state->screen);
1535         VGA_WR08(par->PCIO, 0x03D4, 0x28);
1536         VGA_WR08(par->PCIO, 0x03D5, state->pixel);
1537         VGA_WR08(par->PCIO, 0x03D4, 0x2D);
1538         VGA_WR08(par->PCIO, 0x03D5, state->horiz);
1539         VGA_WR08(par->PCIO, 0x03D4, 0x1C);
1540         VGA_WR08(par->PCIO, 0x03D5, state->fifo);
1541         VGA_WR08(par->PCIO, 0x03D4, 0x1B);
1542         VGA_WR08(par->PCIO, 0x03D5, state->arbitration0);
1543         VGA_WR08(par->PCIO, 0x03D4, 0x20);
1544         VGA_WR08(par->PCIO, 0x03D5, state->arbitration1);
1545
1546         if(par->Architecture >= NV_ARCH_30) {
1547                 VGA_WR08(par->PCIO, 0x03D4, 0x47);
1548                 VGA_WR08(par->PCIO, 0x03D5, state->arbitration1 >> 8);
1549         }
1550
1551         VGA_WR08(par->PCIO, 0x03D4, 0x30);
1552         VGA_WR08(par->PCIO, 0x03D5, state->cursor0);
1553         VGA_WR08(par->PCIO, 0x03D4, 0x31);
1554         VGA_WR08(par->PCIO, 0x03D5, state->cursor1);
1555         VGA_WR08(par->PCIO, 0x03D4, 0x2F);
1556         VGA_WR08(par->PCIO, 0x03D5, state->cursor2);
1557         VGA_WR08(par->PCIO, 0x03D4, 0x39);
1558         VGA_WR08(par->PCIO, 0x03D5, state->interlace);
1559
1560         if (!par->FlatPanel) {
1561                 NV_WR32(par->PRAMDAC0, 0x050C, state->pllsel);
1562                 NV_WR32(par->PRAMDAC0, 0x0508, state->vpll);
1563                 if (par->twoHeads)
1564                         NV_WR32(par->PRAMDAC0, 0x0520, state->vpll2);
1565                 if (par->twoStagePLL) {
1566                         NV_WR32(par->PRAMDAC0, 0x0578, state->vpllB);
1567                         NV_WR32(par->PRAMDAC0, 0x057C, state->vpll2B);
1568                 }
1569         } else {
1570                 NV_WR32(par->PRAMDAC, 0x0848, state->scale);
1571                 NV_WR32(par->PRAMDAC, 0x0828, state->crtcSync +
1572                         par->PanelTweak);
1573         }
1574
1575         NV_WR32(par->PRAMDAC, 0x0600, state->general);
1576
1577         NV_WR32(par->PCRTC, 0x0140, 0);
1578         NV_WR32(par->PCRTC, 0x0100, 1);
1579
1580         par->CurrentState = state;
1581 }
1582
1583 void NVUnloadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state) {
1584         VGA_WR08(par->PCIO, 0x03D4, 0x19);
1585         state->repaint0 = VGA_RD08(par->PCIO, 0x03D5);
1586         VGA_WR08(par->PCIO, 0x03D4, 0x1A);
1587         state->repaint1 = VGA_RD08(par->PCIO, 0x03D5);
1588         VGA_WR08(par->PCIO, 0x03D4, 0x25);
1589         state->screen = VGA_RD08(par->PCIO, 0x03D5);
1590         VGA_WR08(par->PCIO, 0x03D4, 0x28);
1591         state->pixel = VGA_RD08(par->PCIO, 0x03D5);
1592         VGA_WR08(par->PCIO, 0x03D4, 0x2D);
1593         state->horiz = VGA_RD08(par->PCIO, 0x03D5);
1594         VGA_WR08(par->PCIO, 0x03D4, 0x1C);
1595         state->fifo         = VGA_RD08(par->PCIO, 0x03D5);
1596         VGA_WR08(par->PCIO, 0x03D4, 0x1B);
1597         state->arbitration0 = VGA_RD08(par->PCIO, 0x03D5);
1598         VGA_WR08(par->PCIO, 0x03D4, 0x20);
1599         state->arbitration1 = VGA_RD08(par->PCIO, 0x03D5);
1600
1601         if(par->Architecture >= NV_ARCH_30) {
1602                 VGA_WR08(par->PCIO, 0x03D4, 0x47);
1603                 state->arbitration1 |= (VGA_RD08(par->PCIO, 0x03D5) & 1) << 8;
1604         }
1605
1606         VGA_WR08(par->PCIO, 0x03D4, 0x30);
1607         state->cursor0 = VGA_RD08(par->PCIO, 0x03D5);
1608         VGA_WR08(par->PCIO, 0x03D4, 0x31);
1609         state->cursor1 = VGA_RD08(par->PCIO, 0x03D5);
1610         VGA_WR08(par->PCIO, 0x03D4, 0x2F);
1611         state->cursor2 = VGA_RD08(par->PCIO, 0x03D5);
1612         VGA_WR08(par->PCIO, 0x03D4, 0x39);
1613         state->interlace = VGA_RD08(par->PCIO, 0x03D5);
1614         state->vpll = NV_RD32(par->PRAMDAC0, 0x0508);
1615         if (par->twoHeads)
1616                 state->vpll2 = NV_RD32(par->PRAMDAC0, 0x0520);
1617         if (par->twoStagePLL) {
1618                 state->vpllB = NV_RD32(par->PRAMDAC0, 0x0578);
1619                 state->vpll2B = NV_RD32(par->PRAMDAC0, 0x057C);
1620         }
1621         state->pllsel = NV_RD32(par->PRAMDAC0, 0x050C);
1622         state->general = NV_RD32(par->PRAMDAC, 0x0600);
1623         state->scale = NV_RD32(par->PRAMDAC, 0x0848);
1624         state->config = NV_RD32(par->PFB, 0x0200);
1625
1626         if (par->Architecture >= NV_ARCH_10) {
1627                 if (par->twoHeads) {
1628                         state->head = NV_RD32(par->PCRTC0, 0x0860);
1629                         state->head2 = NV_RD32(par->PCRTC0, 0x2860);
1630                         VGA_WR08(par->PCIO, 0x03D4, 0x44);
1631                         state->crtcOwner = VGA_RD08(par->PCIO, 0x03D5);
1632                 }
1633                 VGA_WR08(par->PCIO, 0x03D4, 0x41);
1634                 state->extra = VGA_RD08(par->PCIO, 0x03D5);
1635                 state->cursorConfig = NV_RD32(par->PCRTC, 0x0810);
1636
1637                 if ((par->Chipset & 0x0ff0) == 0x0110) {
1638                         state->dither = NV_RD32(par->PRAMDAC, 0x0528);
1639                 } else if (par->twoHeads) {
1640                         state->dither = NV_RD32(par->PRAMDAC, 0x083C);
1641                 }
1642
1643                 if (par->FlatPanel) {
1644                         VGA_WR08(par->PCIO, 0x03D4, 0x53);
1645                         state->timingH = VGA_RD08(par->PCIO, 0x03D5);
1646                         VGA_WR08(par->PCIO, 0x03D4, 0x54);
1647                         state->timingV = VGA_RD08(par->PCIO, 0x03D5);
1648                 }
1649         }
1650 }
1651
1652 void NVSetStartAddress(struct nvidia_par *par, u32 start)
1653 {
1654         NV_WR32(par->PCRTC, 0x800, start);
1655 }