drivers/video/pxafb.c

   1 /*
   2  *  linux/drivers/video/pxafb.c
   3  *
   4  *  Copyright (C) 1999 Eric A. Thomas.
   5  *  Copyright (C) 2004 Jean-Frederic Clere.
   6  *  Copyright (C) 2004 Ian Campbell.
   7  *  Copyright (C) 2004 Jeff Lackey.
   8  *   Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
   9  *  which in turn is
  10  *   Based on acornfb.c Copyright (C) Russell King.
  11  *
  12  * This file is subject to the terms and conditions of the GNU General Public
  13  * License.  See the file COPYING in the main directory of this archive for
  14  * more details.
  15  *
  16  *              Intel PXA250/210 LCD Controller Frame Buffer Driver
  17  *
  18  * Please direct your questions and comments on this driver to the following
  19  * email address:
  20  *
  21  *      linux-arm-kernel@lists.arm.linux.org.uk
  22  *
  23  */
  24
  25 #include <linux/config.h>
  26 #include <linux/module.h>
  27 #include <linux/moduleparam.h>
  28 #include <linux/kernel.h>
  29 #include <linux/sched.h>
  30 #include <linux/errno.h>
  31 #include <linux/string.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/slab.h>
  34 #include <linux/fb.h>
  35 #include <linux/delay.h>
  36 #include <linux/init.h>
  37 #include <linux/ioport.h>
  38 #include <linux/cpufreq.h>
  39 #include <linux/device.h>
  40 #include <linux/dma-mapping.h>
  41
  42 #include <asm/hardware.h>
  43 #include <asm/io.h>
  44 #include <asm/irq.h>
  45 #include <asm/mach-types.h>
  46 #include <asm/uaccess.h>
  47 #include <asm/arch/bitfield.h>
  48 #include <asm/arch/pxafb.h>
  49
  50 /*
  51  * Complain if VAR is out of range.
  52  */
  53 #define DEBUG_VAR 1
  54
  55 #include "pxafb.h"
  56
  57 /* Bits which should not be set in machine configuration structures */
  58 #define LCCR0_INVALID_CONFIG_MASK (LCCR0_OUM|LCCR0_BM|LCCR0_QDM|LCCR0_DIS|LCCR0_EFM|LCCR0_IUM|LCCR0_SFM|LCCR0_LDM|LCCR0_ENB)
  59 #define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP|LCCR3_VSP|LCCR3_PCD|LCCR3_BPP)
  60
  61 static void (*pxafb_backlight_power)(int);
  62 static void (*pxafb_lcd_power)(int);
  63
  64 static int pxafb_activate_var(struct fb_var_screeninfo *var, struct pxafb_info *);
  65 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
  66
  67 #ifdef CONFIG_FB_PXA_PARAMETERS
  68 #define PXAFB_OPTIONS_SIZE 256
  69 static char g_options[PXAFB_OPTIONS_SIZE] __initdata = "";
  70 #endif
  71
  72 static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state)
  73 {
  74         unsigned long flags;
  75
  76         local_irq_save(flags);
  77         /*
  78          * We need to handle two requests being made at the same time.
  79          * There are two important cases:
  80          *  1. When we are changing VT (C_REENABLE) while unblanking (C_ENABLE)
  81          *     We must perform the unblanking, which will do our REENABLE for us.
  82          *  2. When we are blanking, but immediately unblank before we have
  83          *     blanked.  We do the "REENABLE" thing here as well, just to be sure.
  84          */
  85         if (fbi->task_state == C_ENABLE && state == C_REENABLE)
  86                 state = (u_int) -1;
  87         if (fbi->task_state == C_DISABLE && state == C_ENABLE)
  88                 state = C_REENABLE;
  89
  90         if (state != (u_int)-1) {
  91                 fbi->task_state = state;
  92                 schedule_work(&fbi->task);
  93         }
  94         local_irq_restore(flags);
  95 }
  96
  97 static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
  98 {
  99         chan &= 0xffff;
 100         chan >>= 16 - bf->length;
 101         return chan << bf->offset;
 102 }
 103
 104 static int
 105 pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
 106                        u_int trans, struct fb_info *info)
 107 {
 108         struct pxafb_info *fbi = (struct pxafb_info *)info;
 109         u_int val, ret = 1;
 110
 111         if (regno < fbi->palette_size) {
 112                 val  = ((red   >>  0) & 0xf800);
 113                 val |= ((green >>  5) & 0x07e0);
 114                 val |= ((blue  >> 11) & 0x001f);
 115
 116                 fbi->palette_cpu[regno] = val;
 117                 ret = 0;
 118         }
 119         return ret;
 120 }
 121
 122 static int
 123 pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
 124                    u_int trans, struct fb_info *info)
 125 {
 126         struct pxafb_info *fbi = (struct pxafb_info *)info;
 127         unsigned int val;
 128         int ret = 1;
 129
 130         /*
 131          * If inverse mode was selected, invert all the colours
 132          * rather than the register number.  The register number
 133          * is what you poke into the framebuffer to produce the
 134          * colour you requested.
 135          */
 136         if (fbi->cmap_inverse) {
 137                 red   = 0xffff - red;
 138                 green = 0xffff - green;
 139                 blue  = 0xffff - blue;
 140         }
 141
 142         /*
 143          * If greyscale is true, then we convert the RGB value
 144          * to greyscale no matter what visual we are using.
 145          */
 146         if (fbi->fb.var.grayscale)
 147                 red = green = blue = (19595 * red + 38470 * green +
 148                                         7471 * blue) >> 16;
 149
 150         switch (fbi->fb.fix.visual) {
 151         case FB_VISUAL_TRUECOLOR:
 152                 /*
 153                  * 12 or 16-bit True Colour.  We encode the RGB value
 154                  * according to the RGB bitfield information.
 155                  */
 156                 if (regno < 16) {
 157                         u32 *pal = fbi->fb.pseudo_palette;
 158
 159                         val  = chan_to_field(red, &fbi->fb.var.red);
 160                         val |= chan_to_field(green, &fbi->fb.var.green);
 161                         val |= chan_to_field(blue, &fbi->fb.var.blue);
 162
 163                         pal[regno] = val;
 164                         ret = 0;
 165                 }
 166                 break;
 167
 168         case FB_VISUAL_STATIC_PSEUDOCOLOR:
 169         case FB_VISUAL_PSEUDOCOLOR:
 170                 ret = pxafb_setpalettereg(regno, red, green, blue, trans, info);
 171                 break;
 172         }
 173
 174         return ret;
 175 }
 176
 177 /*
 178  *  pxafb_bpp_to_lccr3():
 179  *    Convert a bits per pixel value to the correct bit pattern for LCCR3
 180  */
 181 static int pxafb_bpp_to_lccr3(struct fb_var_screeninfo *var)
 182 {
 183         int ret = 0;
 184         switch (var->bits_per_pixel) {
 185         case 1:  ret = LCCR3_1BPP; break;
 186         case 2:  ret = LCCR3_2BPP; break;
 187         case 4:  ret = LCCR3_4BPP; break;
 188         case 8:  ret = LCCR3_8BPP; break;
 189         case 16: ret = LCCR3_16BPP; break;
 190         }
 191         return ret;
 192 }
 193
 194 #ifdef CONFIG_CPU_FREQ
 195 /*
 196  *  pxafb_display_dma_period()
 197  *    Calculate the minimum period (in picoseconds) between two DMA
 198  *    requests for the LCD controller.  If we hit this, it means we're
 199  *    doing nothing but LCD DMA.
 200  */
 201 static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var)
 202 {
 203        /*
 204         * Period = pixclock * bits_per_byte * bytes_per_transfer
 205         *              / memory_bits_per_pixel;
 206         */
 207        return var->pixclock * 8 * 16 / var->bits_per_pixel;
 208 }
 209
 210 extern unsigned int get_clk_frequency_khz(int info);
 211 #endif
 212
 213 /*
 214  *  pxafb_check_var():
 215  *    Get the video params out of 'var'. If a value doesn't fit, round it up,
 216  *    if it's too big, return -EINVAL.
 217  *
 218  *    Round up in the following order: bits_per_pixel, xres,
 219  *    yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
 220  *    bitfields, horizontal timing, vertical timing.
 221  */
 222 static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
 223 {
 224         struct pxafb_info *fbi = (struct pxafb_info *)info;
 225
 226         if (var->xres < MIN_XRES)
 227                 var->xres = MIN_XRES;
 228         if (var->yres < MIN_YRES)
 229                 var->yres = MIN_YRES;
 230         if (var->xres > fbi->max_xres)
 231                 var->xres = fbi->max_xres;
 232         if (var->yres > fbi->max_yres)
 233                 var->yres = fbi->max_yres;
 234         var->xres_virtual =
 235                 max(var->xres_virtual, var->xres);
 236         var->yres_virtual =
 237                 max(var->yres_virtual, var->yres);
 238
 239         /*
 240          * Setup the RGB parameters for this display.
 241          *
 242          * The pixel packing format is described on page 7-11 of the
 243          * PXA2XX Developer's Manual.
 244          */
 245         if ( var->bits_per_pixel == 16 ) {
 246                 var->red.offset   = 11; var->red.length   = 5;
 247                 var->green.offset = 5;  var->green.length = 6;
 248                 var->blue.offset  = 0;  var->blue.length  = 5;
 249                 var->transp.offset = var->transp.length = 0;
 250         } else {
 251                 var->red.offset = var->green.offset = var->blue.offset = var->transp.offset = 0;
 252                 var->red.length   = 8;
 253                 var->green.length = 8;
 254                 var->blue.length  = 8;
 255                 var->transp.length = 0;
 256         }
 257
 258 #ifdef CONFIG_CPU_FREQ
 259         DPRINTK("dma period = %d ps, clock = %d kHz\n",
 260                 pxafb_display_dma_period(var),
 261                 get_clk_frequency_khz(0));
 262 #endif
 263
 264         return 0;
 265 }
 266
 267 static inline void pxafb_set_truecolor(u_int is_true_color)
 268 {
 269         DPRINTK("true_color = %d\n", is_true_color);
 270         // do your machine-specific setup if needed
 271 }
 272
 273 /*
 274  * pxafb_set_par():
 275  *      Set the user defined part of the display for the specified console
 276  */
 277 static int pxafb_set_par(struct fb_info *info)
 278 {
 279         struct pxafb_info *fbi = (struct pxafb_info *)info;
 280         struct fb_var_screeninfo *var = &info->var;
 281         unsigned long palette_mem_size;
 282
 283         DPRINTK("set_par\n");
 284
 285         if (var->bits_per_pixel == 16)
 286                 fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
 287         else if (!fbi->cmap_static)
 288                 fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
 289         else {
 290                 /*
 291                  * Some people have weird ideas about wanting static
 292                  * pseudocolor maps.  I suspect their user space
 293                  * applications are broken.
 294                  */
 295                 fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
 296         }
 297
 298         fbi->fb.fix.line_length = var->xres_virtual *
 299                                   var->bits_per_pixel / 8;
 300         fbi->palette_size = var->bits_per_pixel == 8 ? 256 : 16;
 301
 302         palette_mem_size = fbi->palette_size * sizeof(u16);
 303
 304         DPRINTK("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
 305
 306         fbi->palette_cpu = (u16 *)(fbi->map_cpu + PAGE_SIZE - palette_mem_size);
 307         fbi->palette_dma = fbi->map_dma + PAGE_SIZE - palette_mem_size;
 308
 309         /*
 310          * Set (any) board control register to handle new color depth
 311          */
 312         pxafb_set_truecolor(fbi->fb.fix.visual == FB_VISUAL_TRUECOLOR);
 313
 314         pxafb_activate_var(var, fbi);
 315
 316         return 0;
 317 }
 318
 319 /*
 320  * Formal definition of the VESA spec:
 321  *  On
 322  *      This refers to the state of the display when it is in full operation
 323  *  Stand-By
 324  *      This defines an optional operating state of minimal power reduction with
 325  *      the shortest recovery time
 326  *  Suspend
 327  *      This refers to a level of power management in which substantial power
 328  *      reduction is achieved by the display.  The display can have a longer
 329  *      recovery time from this state than from the Stand-by state
 330  *  Off
 331  *      This indicates that the display is consuming the lowest level of power
 332  *      and is non-operational. Recovery from this state may optionally require
 333  *      the user to manually power on the monitor
 334  *
 335  *  Now, the fbdev driver adds an additional state, (blank), where they
 336  *  turn off the video (maybe by colormap tricks), but don't mess with the
 337  *  video itself: think of it semantically between on and Stand-By.
 338  *
 339  *  So here's what we should do in our fbdev blank routine:
 340  *
 341  *      VESA_NO_BLANKING (mode 0)       Video on,  front/back light on
 342  *      VESA_VSYNC_SUSPEND (mode 1)     Video on,  front/back light off
 343  *      VESA_HSYNC_SUSPEND (mode 2)     Video on,  front/back light off
 344  *      VESA_POWERDOWN (mode 3)         Video off, front/back light off
 345  *
 346  *  This will match the matrox implementation.
 347  */
 348
 349 /*
 350  * pxafb_blank():
 351  *      Blank the display by setting all palette values to zero.  Note, the
 352  *      12 and 16 bpp modes don't really use the palette, so this will not
 353  *      blank the display in all modes.
 354  */
 355 static int pxafb_blank(int blank, struct fb_info *info)
 356 {
 357         struct pxafb_info *fbi = (struct pxafb_info *)info;
 358         int i;
 359
 360         DPRINTK("pxafb_blank: blank=%d\n", blank);
 361
 362         switch (blank) {
 363         case VESA_POWERDOWN:
 364         case VESA_VSYNC_SUSPEND:
 365         case VESA_HSYNC_SUSPEND:
 366                 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
 367                     fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
 368                         for (i = 0; i < fbi->palette_size; i++)
 369                                 pxafb_setpalettereg(i, 0, 0, 0, 0, info);
 370
 371                 pxafb_schedule_work(fbi, C_DISABLE);
 372                 //TODO if (pxafb_blank_helper) pxafb_blank_helper(blank);
 373                 break;
 374
 375         case VESA_NO_BLANKING:
 376                 //TODO if (pxafb_blank_helper) pxafb_blank_helper(blank);
 377                 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
 378                     fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
 379                         fb_set_cmap(&fbi->fb.cmap, 1, info);
 380                 pxafb_schedule_work(fbi, C_ENABLE);
 381         }
 382         return 0;
 383 }
 384
 385 static struct fb_ops pxafb_ops = {
 386         .owner          = THIS_MODULE,
 387         .fb_check_var   = pxafb_check_var,
 388         .fb_set_par     = pxafb_set_par,
 389         .fb_setcolreg   = pxafb_setcolreg,
 390         .fb_fillrect    = cfb_fillrect,
 391         .fb_copyarea    = cfb_copyarea,
 392         .fb_imageblit   = cfb_imageblit,
 393         .fb_blank       = pxafb_blank,
 394         .fb_cursor      = soft_cursor,
 395 };
 396
 397 /*
 398  * Calculate the PCD value from the clock rate (in picoseconds).
 399  * We take account of the PPCR clock setting.
 400  * From PXA Developer's Manual:
 401  *
 402  *   PixelClock =      LCLK
 403  *                -------------
 404  *                2 ( PCD + 1 )
 405  *
 406  *   PCD =      LCLK
 407  *         ------------- - 1
 408  *         2(PixelClock)
 409  *
 410  * Where:
 411  *   LCLK = LCD/Memory Clock
 412  *   PCD = LCCR3[7:0]
 413  *
 414  * PixelClock here is in Hz while the pixclock argument given is the
 415  * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 )
 416  *
 417  * The function get_lclk_frequency_10khz returns LCLK in units of
 418  * 10khz. Calling the result of this function lclk gives us the
 419  * following
 420  *
 421  *    PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 )
 422  *          -------------------------------------- - 1
 423  *                          2
 424  *
 425  * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
 426  */
 427 static inline unsigned int get_pcd(unsigned int pixclock)
 428 {
 429         unsigned long long pcd;
 430
 431         /* FIXME: Need to take into account Double Pixel Clock mode
 432          * (DPC) bit? or perhaps set it based on the various clock
 433          * speeds */
 434
 435         pcd = (unsigned long long)get_lcdclk_frequency_10khz() * pixclock;
 436         pcd /= 100000000 * 2;
 437         /* no need for this, since we should subtract 1 anyway. they cancel */
 438         /* pcd += 1; */ /* make up for integer math truncations */
 439         return (unsigned int)pcd;
 440 }
 441
 442 /*
 443  * pxafb_activate_var():
 444  *      Configures LCD Controller based on entries in var parameter.  Settings are
 445  *      only written to the controller if changes were made.
 446  */
 447 static int pxafb_activate_var(struct fb_var_screeninfo *var, struct pxafb_info *fbi)
 448 {
 449         struct pxafb_lcd_reg new_regs;
 450         u_long flags;
 451         u_int lines_per_panel, pcd = get_pcd(var->pixclock);
 452
 453         DPRINTK("Configuring PXA LCD\n");
 454
 455         DPRINTK("var: xres=%d hslen=%d lm=%d rm=%d\n",
 456                 var->xres, var->hsync_len,
 457                 var->left_margin, var->right_margin);
 458         DPRINTK("var: yres=%d vslen=%d um=%d bm=%d\n",
 459                 var->yres, var->vsync_len,
 460                 var->upper_margin, var->lower_margin);
 461         DPRINTK("var: pixclock=%d pcd=%d\n", var->pixclock, pcd);
 462
 463 #if DEBUG_VAR
 464         if (var->xres < 16        || var->xres > 1024)
 465                 printk(KERN_ERR "%s: invalid xres %d\n",
 466                         fbi->fb.fix.id, var->xres);
 467         switch(var->bits_per_pixel) {
 468         case 1:
 469         case 2:
 470         case 4:
 471         case 8:
 472         case 16:
 473                 break;
 474         default:
 475                 printk(KERN_ERR "%s: invalid bit depth %d\n",
 476                        fbi->fb.fix.id, var->bits_per_pixel);
 477                 break;
 478         }
 479         if (var->hsync_len < 1    || var->hsync_len > 64)
 480                 printk(KERN_ERR "%s: invalid hsync_len %d\n",
 481                         fbi->fb.fix.id, var->hsync_len);
 482         if (var->left_margin < 1  || var->left_margin > 255)
 483                 printk(KERN_ERR "%s: invalid left_margin %d\n",
 484                         fbi->fb.fix.id, var->left_margin);
 485         if (var->right_margin < 1 || var->right_margin > 255)
 486                 printk(KERN_ERR "%s: invalid right_margin %d\n",
 487                         fbi->fb.fix.id, var->right_margin);
 488         if (var->yres < 1         || var->yres > 1024)
 489                 printk(KERN_ERR "%s: invalid yres %d\n",
 490                         fbi->fb.fix.id, var->yres);
 491         if (var->vsync_len < 1    || var->vsync_len > 64)
 492                 printk(KERN_ERR "%s: invalid vsync_len %d\n",
 493                         fbi->fb.fix.id, var->vsync_len);
 494         if (var->upper_margin < 0 || var->upper_margin > 255)
 495                 printk(KERN_ERR "%s: invalid upper_margin %d\n",
 496                         fbi->fb.fix.id, var->upper_margin);
 497         if (var->lower_margin < 0 || var->lower_margin > 255)
 498                 printk(KERN_ERR "%s: invalid lower_margin %d\n",
 499                         fbi->fb.fix.id, var->lower_margin);
 500 #endif
 501
 502         new_regs.lccr0 = fbi->lccr0 |
 503                 (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM |
 504                  LCCR0_QDM | LCCR0_BM  | LCCR0_OUM);
 505
 506         new_regs.lccr1 =
 507                 LCCR1_DisWdth(var->xres) +
 508                 LCCR1_HorSnchWdth(var->hsync_len) +
 509                 LCCR1_BegLnDel(var->left_margin) +
 510                 LCCR1_EndLnDel(var->right_margin);
 511
 512         /*
 513          * If we have a dual scan LCD, we need to halve
 514          * the YRES parameter.
 515          */
 516         lines_per_panel = var->yres;
 517         if (fbi->lccr0 & LCCR0_SDS)
 518                 lines_per_panel /= 2;
 519
 520         new_regs.lccr2 =
 521                 LCCR2_DisHght(lines_per_panel) +
 522                 LCCR2_VrtSnchWdth(var->vsync_len) +
 523                 LCCR2_BegFrmDel(var->upper_margin) +
 524                 LCCR2_EndFrmDel(var->lower_margin);
 525
 526         new_regs.lccr3 = fbi->lccr3 |
 527                 pxafb_bpp_to_lccr3(var) |
 528                 (var->sync & FB_SYNC_HOR_HIGH_ACT ? LCCR3_HorSnchH : LCCR3_HorSnchL) |
 529                 (var->sync & FB_SYNC_VERT_HIGH_ACT ? LCCR3_VrtSnchH : LCCR3_VrtSnchL);
 530
 531         if (pcd)
 532                 new_regs.lccr3 |= LCCR3_PixClkDiv(pcd);
 533
 534         DPRINTK("nlccr0 = 0x%08x\n", new_regs.lccr0);
 535         DPRINTK("nlccr1 = 0x%08x\n", new_regs.lccr1);
 536         DPRINTK("nlccr2 = 0x%08x\n", new_regs.lccr2);
 537         DPRINTK("nlccr3 = 0x%08x\n", new_regs.lccr3);
 538
 539         /* Update shadow copy atomically */
 540         local_irq_save(flags);
 541
 542         /* setup dma descriptors */
 543         fbi->dmadesc_fblow_cpu = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette_cpu - 3*16);
 544         fbi->dmadesc_fbhigh_cpu = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette_cpu - 2*16);
 545         fbi->dmadesc_palette_cpu = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette_cpu - 1*16);
 546
 547         fbi->dmadesc_fblow_dma = fbi->palette_dma - 3*16;
 548         fbi->dmadesc_fbhigh_dma = fbi->palette_dma - 2*16;
 549         fbi->dmadesc_palette_dma = fbi->palette_dma - 1*16;
 550
 551 #define BYTES_PER_PANEL (lines_per_panel * fbi->fb.fix.line_length)
 552
 553         /* populate descriptors */
 554         fbi->dmadesc_fblow_cpu->fdadr = fbi->dmadesc_fblow_dma;
 555         fbi->dmadesc_fblow_cpu->fsadr = fbi->screen_dma + BYTES_PER_PANEL;
 556         fbi->dmadesc_fblow_cpu->fidr  = 0;
 557         fbi->dmadesc_fblow_cpu->ldcmd = BYTES_PER_PANEL;
 558
 559         fbi->fdadr1 = fbi->dmadesc_fblow_dma; /* only used in dual-panel mode */
 560
 561         fbi->dmadesc_fbhigh_cpu->fsadr = fbi->screen_dma;
 562         fbi->dmadesc_fbhigh_cpu->fidr = 0;
 563         fbi->dmadesc_fbhigh_cpu->ldcmd = BYTES_PER_PANEL;
 564
 565         fbi->dmadesc_palette_cpu->fsadr = fbi->palette_dma;
 566         fbi->dmadesc_palette_cpu->fidr  = 0;
 567         fbi->dmadesc_palette_cpu->ldcmd = (fbi->palette_size * 2) | LDCMD_PAL;
 568
 569         if( var->bits_per_pixel < 12)
 570         {
 571                 /* assume any mode with <12 bpp is palette driven */
 572                 fbi->dmadesc_palette_cpu->fdadr = fbi->dmadesc_fbhigh_dma;
 573                 fbi->dmadesc_fbhigh_cpu->fdadr = fbi->dmadesc_palette_dma;
 574                 fbi->fdadr0 = fbi->dmadesc_palette_dma; /* flips back and forth between pal and fbhigh */
 575         }
 576         else
 577         {
 578                 /* palette shouldn't be loaded in true-color mode */
 579                 fbi->dmadesc_fbhigh_cpu->fdadr = fbi->dmadesc_fbhigh_dma;
 580                 fbi->fdadr0 = fbi->dmadesc_fbhigh_dma; /* no pal just fbhigh */
 581                 /* init it to something, even though we won't be using it */
 582                 fbi->dmadesc_palette_cpu->fdadr = fbi->dmadesc_palette_dma;
 583         }
 584
 585 #if 0
 586         DPRINTK("fbi->dmadesc_fblow_cpu = 0x%p\n", fbi->dmadesc_fblow_cpu);
 587         DPRINTK("fbi->dmadesc_fbhigh_cpu = 0x%p\n", fbi->dmadesc_fbhigh_cpu);
 588         DPRINTK("fbi->dmadesc_palette_cpu = 0x%p\n", fbi->dmadesc_palette_cpu);
 589         DPRINTK("fbi->dmadesc_fblow_dma = 0x%x\n", fbi->dmadesc_fblow_dma);
 590         DPRINTK("fbi->dmadesc_fbhigh_dma = 0x%x\n", fbi->dmadesc_fbhigh_dma);
 591         DPRINTK("fbi->dmadesc_palette_dma = 0x%x\n", fbi->dmadesc_palette_dma);
 592
 593         DPRINTK("fbi->dmadesc_fblow_cpu->fdadr = 0x%x\n", fbi->dmadesc_fblow_cpu->fdadr);
 594         DPRINTK("fbi->dmadesc_fbhigh_cpu->fdadr = 0x%x\n", fbi->dmadesc_fbhigh_cpu->fdadr);
 595         DPRINTK("fbi->dmadesc_palette_cpu->fdadr = 0x%x\n", fbi->dmadesc_palette_cpu->fdadr);
 596
 597         DPRINTK("fbi->dmadesc_fblow_cpu->fsadr = 0x%x\n", fbi->dmadesc_fblow_cpu->fsadr);
 598         DPRINTK("fbi->dmadesc_fbhigh_cpu->fsadr = 0x%x\n", fbi->dmadesc_fbhigh_cpu->fsadr);
 599         DPRINTK("fbi->dmadesc_palette_cpu->fsadr = 0x%x\n", fbi->dmadesc_palette_cpu->fsadr);
 600
 601         DPRINTK("fbi->dmadesc_fblow_cpu->ldcmd = 0x%x\n", fbi->dmadesc_fblow_cpu->ldcmd);
 602         DPRINTK("fbi->dmadesc_fbhigh_cpu->ldcmd = 0x%x\n", fbi->dmadesc_fbhigh_cpu->ldcmd);
 603         DPRINTK("fbi->dmadesc_palette_cpu->ldcmd = 0x%x\n", fbi->dmadesc_palette_cpu->ldcmd);
 604 #endif
 605
 606         fbi->reg_lccr0 = new_regs.lccr0;
 607         fbi->reg_lccr1 = new_regs.lccr1;
 608         fbi->reg_lccr2 = new_regs.lccr2;
 609         fbi->reg_lccr3 = new_regs.lccr3;
 610         local_irq_restore(flags);
 611
 612         /*
 613          * Only update the registers if the controller is enabled
 614          * and something has changed.
 615          */
 616         if ((LCCR0  != fbi->reg_lccr0) || (LCCR1  != fbi->reg_lccr1) ||
 617             (LCCR2  != fbi->reg_lccr2) || (LCCR3  != fbi->reg_lccr3) ||
 618             (FDADR0 != fbi->fdadr0)    || (FDADR1 != fbi->fdadr1))
 619                 pxafb_schedule_work(fbi, C_REENABLE);
 620
 621         return 0;
 622 }
 623
 624 /*
 625  * NOTE!  The following functions are purely helpers for set_ctrlr_state.
 626  * Do not call them directly; set_ctrlr_state does the correct serialisation
 627  * to ensure that things happen in the right way 100% of time time.
 628  *      -- rmk
 629  */
 630 static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on)
 631 {
 632         DPRINTK("backlight o%s\n", on ? "n" : "ff");
 633
 634         if (pxafb_backlight_power)
 635                 pxafb_backlight_power(on);
 636 }
 637
 638 static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on)
 639 {
 640         DPRINTK("LCD power o%s\n", on ? "n" : "ff");
 641
 642         if (pxafb_lcd_power)
 643                 pxafb_lcd_power(on);
 644 }
 645
 646 static void pxafb_setup_gpio(struct pxafb_info *fbi)
 647 {
 648         unsigned int lccr0 = fbi->lccr0;
 649
 650         /*
 651          * setup is based on type of panel supported
 652         */
 653
 654         /* 4 bit interface */
 655         if ((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
 656             (lccr0 & LCCR0_SDS) == LCCR0_Sngl &&
 657             (lccr0 & LCCR0_DPD) == LCCR0_4PixMono)
 658         {
 659                 // bits 58-61
 660                 GPDR1 |= (0xf << 26);
 661                 GAFR1_U = (GAFR1_U & ~(0xff << 20)) | (0xaa << 20);
 662
 663                 // bits 74-77
 664                 GPDR2 |= (0xf << 10);
 665                 GAFR2_L = (GAFR2_L & ~(0xff << 20)) | (0xaa << 20);
 666         }
 667
 668         /* 8 bit interface */
 669         else if (((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
 670                   ((lccr0 & LCCR0_SDS) == LCCR0_Dual || (lccr0 & LCCR0_DPD) == LCCR0_8PixMono)) ||
 671                  ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
 672                   (lccr0 & LCCR0_PAS) == LCCR0_Pas && (lccr0 & LCCR0_SDS) == LCCR0_Sngl))
 673         {
 674                 // bits 58-65
 675                 GPDR1 |= (0x3f << 26);
 676                 GPDR2 |= (0x3);
 677
 678                 GAFR1_U = (GAFR1_U & ~(0xfff << 20)) | (0xaaa << 20);
 679                 GAFR2_L = (GAFR2_L & ~0xf) | (0xa);
 680
 681                 // bits 74-77
 682                 GPDR2 |= (0xf << 10);
 683                 GAFR2_L = (GAFR2_L & ~(0xff << 20)) | (0xaa << 20);
 684         }
 685
 686         /* 16 bit interface */
 687         else if ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
 688                  ((lccr0 & LCCR0_SDS) == LCCR0_Dual || (lccr0 & LCCR0_PAS) == LCCR0_Act))
 689         {
 690                 // bits 58-77
 691                 GPDR1 |= (0x3f << 26);
 692                 GPDR2 |= 0x00003fff;
 693
 694                 GAFR1_U = (GAFR1_U & ~(0xfff << 20)) | (0xaaa << 20);
 695                 GAFR2_L = (GAFR2_L & 0xf0000000) | 0x0aaaaaaa;
 696         }
 697
 698         else {
 699                 printk( KERN_ERR "pxafb_setup_gpio: unable to determine bits per pixel\n");
 700         }
 701 }
 702
 703 static void pxafb_enable_controller(struct pxafb_info *fbi)
 704 {
 705         DPRINTK("Enabling LCD controller\n");
 706         DPRINTK("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr0);
 707         DPRINTK("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr1);
 708         DPRINTK("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0);
 709         DPRINTK("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1);
 710         DPRINTK("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2);
 711         DPRINTK("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
 712
 713         /* Sequence from 11.7.10 */
 714         LCCR3 = fbi->reg_lccr3;
 715         LCCR2 = fbi->reg_lccr2;
 716         LCCR1 = fbi->reg_lccr1;
 717         LCCR0 = fbi->reg_lccr0 & ~LCCR0_ENB;
 718
 719         FDADR0 = fbi->fdadr0;
 720         FDADR1 = fbi->fdadr1;
 721         LCCR0 |= LCCR0_ENB;
 722
 723         DPRINTK("FDADR0 0x%08x\n", (unsigned int) FDADR0);
 724         DPRINTK("FDADR1 0x%08x\n", (unsigned int) FDADR1);
 725         DPRINTK("LCCR0 0x%08x\n", (unsigned int) LCCR0);
 726         DPRINTK("LCCR1 0x%08x\n", (unsigned int) LCCR1);
 727         DPRINTK("LCCR2 0x%08x\n", (unsigned int) LCCR2);
 728         DPRINTK("LCCR3 0x%08x\n", (unsigned int) LCCR3);
 729 }
 730
 731 static void pxafb_disable_controller(struct pxafb_info *fbi)
 732 {
 733         DECLARE_WAITQUEUE(wait, current);
 734
 735         DPRINTK("Disabling LCD controller\n");
 736
 737         add_wait_queue(&fbi->ctrlr_wait, &wait);
 738         set_current_state(TASK_UNINTERRUPTIBLE);
 739
 740         LCSR = 0xffffffff;      /* Clear LCD Status Register */
 741         LCCR0 &= ~LCCR0_LDM;    /* Enable LCD Disable Done Interrupt */
 742         LCCR0 |= LCCR0_DIS;     /* Disable LCD Controller */
 743
 744         schedule_timeout(20 * HZ / 1000);
 745         remove_wait_queue(&fbi->ctrlr_wait, &wait);
 746 }
 747
 748 /*
 749  *  pxafb_handle_irq: Handle 'LCD DONE' interrupts.
 750  */
 751 static irqreturn_t pxafb_handle_irq(int irq, void *dev_id, struct pt_regs *regs)
 752 {
 753         struct pxafb_info *fbi = dev_id;
 754         unsigned int lcsr = LCSR;
 755
 756         if (lcsr & LCSR_LDD) {
 757                 LCCR0 |= LCCR0_LDM;
 758                 wake_up(&fbi->ctrlr_wait);
 759         }
 760
 761         LCSR = lcsr;
 762         return IRQ_HANDLED;
 763 }
 764
 765 /*
 766  * This function must be called from task context only, since it will
 767  * sleep when disabling the LCD controller, or if we get two contending
 768  * processes trying to alter state.
 769  */
 770 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
 771 {
 772         u_int old_state;
 773
 774         down(&fbi->ctrlr_sem);
 775
 776         old_state = fbi->state;
 777
 778         /*
 779          * Hack around fbcon initialisation.
 780          */
 781         if (old_state == C_STARTUP && state == C_REENABLE)
 782                 state = C_ENABLE;
 783
 784         switch (state) {
 785         case C_DISABLE_CLKCHANGE:
 786                 /*
 787                  * Disable controller for clock change.  If the
 788                  * controller is already disabled, then do nothing.
 789                  */
 790                 if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
 791                         fbi->state = state;
 792                         //TODO __pxafb_lcd_power(fbi, 0);
 793                         pxafb_disable_controller(fbi);
 794                 }
 795                 break;
 796
 797         case C_DISABLE_PM:
 798         case C_DISABLE:
 799                 /*
 800                  * Disable controller
 801                  */
 802                 if (old_state != C_DISABLE) {
 803                         fbi->state = state;
 804                         __pxafb_backlight_power(fbi, 0);
 805                         __pxafb_lcd_power(fbi, 0);
 806                         if (old_state != C_DISABLE_CLKCHANGE)
 807                                 pxafb_disable_controller(fbi);
 808                 }
 809                 break;
 810
 811         case C_ENABLE_CLKCHANGE:
 812                 /*
 813                  * Enable the controller after clock change.  Only
 814                  * do this if we were disabled for the clock change.
 815                  */
 816                 if (old_state == C_DISABLE_CLKCHANGE) {
 817                         fbi->state = C_ENABLE;
 818                         pxafb_enable_controller(fbi);
 819                         //TODO __pxafb_lcd_power(fbi, 1);
 820                 }
 821                 break;
 822
 823         case C_REENABLE:
 824                 /*
 825                  * Re-enable the controller only if it was already
 826                  * enabled.  This is so we reprogram the control
 827                  * registers.
 828                  */
 829                 if (old_state == C_ENABLE) {
 830                         pxafb_disable_controller(fbi);
 831                         pxafb_setup_gpio(fbi);
 832                         pxafb_enable_controller(fbi);
 833                 }
 834                 break;
 835
 836         case C_ENABLE_PM:
 837                 /*
 838                  * Re-enable the controller after PM.  This is not
 839                  * perfect - think about the case where we were doing
 840                  * a clock change, and we suspended half-way through.
 841                  */
 842                 if (old_state != C_DISABLE_PM)
 843                         break;
 844                 /* fall through */
 845
 846         case C_ENABLE:
 847                 /*
 848                  * Power up the LCD screen, enable controller, and
 849                  * turn on the backlight.
 850                  */
 851                 if (old_state != C_ENABLE) {
 852                         fbi->state = C_ENABLE;
 853                         pxafb_setup_gpio(fbi);
 854                         pxafb_enable_controller(fbi);
 855                         __pxafb_lcd_power(fbi, 1);
 856                         __pxafb_backlight_power(fbi, 1);
 857                 }
 858                 break;
 859         }
 860         up(&fbi->ctrlr_sem);
 861 }
 862
 863 /*
 864  * Our LCD controller task (which is called when we blank or unblank)
 865  * via keventd.
 866  */
 867 static void pxafb_task(void *dummy)
 868 {
 869         struct pxafb_info *fbi = dummy;
 870         u_int state = xchg(&fbi->task_state, -1);
 871
 872         set_ctrlr_state(fbi, state);
 873 }
 874
 875 #ifdef CONFIG_CPU_FREQ
 876 /*
 877  * CPU clock speed change handler.  We need to adjust the LCD timing
 878  * parameters when the CPU clock is adjusted by the power management
 879  * subsystem.
 880  *
 881  * TODO: Determine why f->new != 10*get_lclk_frequency_10khz()
 882  */
 883 static int
 884 pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data)
 885 {
 886         struct pxafb_info *fbi = TO_INF(nb, freq_transition);
 887         //TODO struct cpufreq_freqs *f = data;
 888         u_int pcd;
 889
 890         switch (val) {
 891         case CPUFREQ_PRECHANGE:
 892                 set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
 893                 break;
 894
 895         case CPUFREQ_POSTCHANGE:
 896                 pcd = get_pcd(fbi->fb.var.pixclock);
 897                 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) | LCCR3_PixClkDiv(pcd);
 898                 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
 899                 break;
 900         }
 901         return 0;
 902 }
 903
 904 static int
 905 pxafb_freq_policy(struct notifier_block *nb, unsigned long val, void *data)
 906 {
 907         struct pxafb_info *fbi = TO_INF(nb, freq_policy);
 908         struct fb_var_screeninfo *var = &fbi->fb.var;
 909         struct cpufreq_policy *policy = data;
 910
 911         switch (val) {
 912         case CPUFREQ_ADJUST:
 913         case CPUFREQ_INCOMPATIBLE:
 914                 printk(KERN_DEBUG "min dma period: %d ps, "
 915                         "new clock %d kHz\n", pxafb_display_dma_period(var),
 916                         policy->max);
 917                 // TODO: fill in min/max values
 918                 break;
 919 #if 0
 920         case CPUFREQ_NOTIFY:
 921                 printk(KERN_ERR "%s: got CPUFREQ_NOTIFY\n", __FUNCTION__);
 922                 do {} while(0);
 923                 /* todo: panic if min/max values aren't fulfilled
 924                  * [can't really happen unless there's a bug in the
 925                  * CPU policy verification process *
 926                  */
 927                 break;
 928 #endif
 929         }
 930         return 0;
 931 }
 932 #endif
 933
 934 #ifdef CONFIG_PM
 935 /*
 936  * Power management hooks.  Note that we won't be called from IRQ context,
 937  * unlike the blank functions above, so we may sleep.
 938  */
 939 static int pxafb_suspend(struct device *dev, u32 state, u32 level)
 940 {
 941         struct pxafb_info *fbi = dev_get_drvdata(dev);
 942
 943         if (level == SUSPEND_DISABLE || level == SUSPEND_POWER_DOWN)
 944                 set_ctrlr_state(fbi, C_DISABLE_PM);
 945         return 0;
 946 }
 947
 948 static int pxafb_resume(struct device *dev, u32 level)
 949 {
 950         struct pxafb_info *fbi = dev_get_drvdata(dev);
 951
 952         if (level == RESUME_ENABLE)
 953                 set_ctrlr_state(fbi, C_ENABLE_PM);
 954         return 0;
 955 }
 956 #else
 957 #define pxafb_suspend   NULL
 958 #define pxafb_resume    NULL
 959 #endif
 960
 961 /*
 962  * pxafb_map_video_memory():
 963  *      Allocates the DRAM memory for the frame buffer.  This buffer is
 964  *      remapped into a non-cached, non-buffered, memory region to
 965  *      allow palette and pixel writes to occur without flushing the
 966  *      cache.  Once this area is remapped, all virtual memory
 967  *      access to the video memory should occur at the new region.
 968  */
 969 static int __init pxafb_map_video_memory(struct pxafb_info *fbi)
 970 {
 971         u_long palette_mem_size;
 972
 973         /*
 974          * We reserve one page for the palette, plus the size
 975          * of the framebuffer.
 976          */
 977         fbi->map_size = PAGE_ALIGN(fbi->fb.fix.smem_len + PAGE_SIZE);
 978         fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size,
 979                                               &fbi->map_dma, GFP_KERNEL);
 980
 981         if (fbi->map_cpu) {
 982                 /* prevent initial garbage on screen */
 983                 memset(fbi->map_cpu, 0, fbi->map_size);
 984                 fbi->fb.screen_base = fbi->map_cpu + PAGE_SIZE;
 985                 fbi->screen_dma = fbi->map_dma + PAGE_SIZE;
 986                 /*
 987                  * FIXME: this is actually the wrong thing to place in
 988                  * smem_start.  But fbdev suffers from the problem that
 989                  * it needs an API which doesn't exist (in this case,
 990                  * dma_writecombine_mmap)
 991                  */
 992                 fbi->fb.fix.smem_start = fbi->screen_dma;
 993
 994                 fbi->palette_size = fbi->fb.var.bits_per_pixel == 8 ? 256 : 16;
 995
 996                 palette_mem_size = fbi->palette_size * sizeof(u16);
 997                 DPRINTK("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
 998
 999                 fbi->palette_cpu = (u16 *)(fbi->map_cpu + PAGE_SIZE - palette_mem_size);
1000                 fbi->palette_dma = fbi->map_dma + PAGE_SIZE - palette_mem_size;
1001         }
1002
1003         return fbi->map_cpu ? 0 : -ENOMEM;
1004 }
1005
1006 static struct pxafb_info * __init pxafb_init_fbinfo(struct device *dev)
1007 {
1008         struct pxafb_info *fbi;
1009         void *addr;
1010         struct pxafb_mach_info *inf = dev->platform_data;
1011
1012         /* Alloc the pxafb_info and pseudo_palette in one step */
1013         fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 17, GFP_KERNEL);
1014         if (!fbi)
1015                 return NULL;
1016
1017         memset(fbi, 0, sizeof(struct pxafb_info));
1018         fbi->dev = dev;
1019
1020         strcpy(fbi->fb.fix.id, PXA_NAME);
1021
1022         fbi->fb.fix.type        = FB_TYPE_PACKED_PIXELS;
1023         fbi->fb.fix.type_aux    = 0;
1024         fbi->fb.fix.xpanstep    = 0;
1025         fbi->fb.fix.ypanstep    = 0;
1026         fbi->fb.fix.ywrapstep   = 0;
1027         fbi->fb.fix.accel       = FB_ACCEL_NONE;
1028
1029         fbi->fb.var.nonstd      = 0;
1030         fbi->fb.var.activate    = FB_ACTIVATE_NOW;
1031         fbi->fb.var.height      = -1;
1032         fbi->fb.var.width       = -1;
1033         fbi->fb.var.accel_flags = 0;
1034         fbi->fb.var.vmode       = FB_VMODE_NONINTERLACED;
1035
1036         fbi->fb.fbops           = &pxafb_ops;
1037         fbi->fb.flags           = FBINFO_FLAG_DEFAULT;
1038         fbi->fb.node            = -1;
1039         fbi->fb.currcon         = -1;
1040
1041         addr = fbi;
1042         addr = addr + sizeof(struct pxafb_info);
1043         fbi->fb.pseudo_palette  = addr;
1044
1045         fbi->max_xres                   = inf->xres;
1046         fbi->fb.var.xres                = inf->xres;
1047         fbi->fb.var.xres_virtual        = inf->xres;
1048         fbi->max_yres                   = inf->yres;
1049         fbi->fb.var.yres                = inf->yres;
1050         fbi->fb.var.yres_virtual        = inf->yres;
1051         fbi->max_bpp                    = inf->bpp;
1052         fbi->fb.var.bits_per_pixel      = inf->bpp;
1053         fbi->fb.var.pixclock            = inf->pixclock;
1054         fbi->fb.var.hsync_len           = inf->hsync_len;
1055         fbi->fb.var.left_margin         = inf->left_margin;
1056         fbi->fb.var.right_margin        = inf->right_margin;
1057         fbi->fb.var.vsync_len           = inf->vsync_len;
1058         fbi->fb.var.upper_margin        = inf->upper_margin;
1059         fbi->fb.var.lower_margin        = inf->lower_margin;
1060         fbi->fb.var.sync                = inf->sync;
1061         fbi->fb.var.grayscale           = inf->cmap_greyscale;
1062         fbi->cmap_inverse               = inf->cmap_inverse;
1063         fbi->cmap_static                = inf->cmap_static;
1064         fbi->lccr0                      = inf->lccr0;
1065         fbi->lccr3                      = inf->lccr3;
1066         fbi->state                      = C_STARTUP;
1067         fbi->task_state                 = (u_char)-1;
1068         fbi->fb.fix.smem_len            = fbi->max_xres * fbi->max_yres *
1069                                           fbi->max_bpp / 8;
1070
1071         init_waitqueue_head(&fbi->ctrlr_wait);
1072         INIT_WORK(&fbi->task, pxafb_task, fbi);
1073         init_MUTEX(&fbi->ctrlr_sem);
1074
1075         return fbi;
1076 }
1077
1078 #ifdef CONFIG_FB_PXA_PARAMETERS
1079 static int __init pxafb_parse_options(struct device *dev, char *options)
1080 {
1081         struct pxafb_mach_info *inf = dev->platform_data;
1082         char *this_opt;
1083
1084         if (!options || !*options)
1085                 return 0;
1086
1087         dev_dbg(dev, "options are \"%s\"\n", options ? options : "null");
1088
1089         /* could be made table driven or similar?... */
1090         while ((this_opt = strsep(&options, ",")) != NULL) {
1091                 if (!strncmp(this_opt, "mode:", 5)) {
1092                         const char *name = this_opt+5;
1093                         unsigned int namelen = strlen(name);
1094                         int res_specified = 0, bpp_specified = 0;
1095                         unsigned int xres = 0, yres = 0, bpp = 0;
1096                         int yres_specified = 0;
1097                         int i;
1098                         for (i = namelen-1; i >= 0; i--) {
1099                                 switch (name[i]) {
1100                                 case '-':
1101                                         namelen = i;
1102                                         if (!bpp_specified && !yres_specified) {
1103                                                 bpp = simple_strtoul(&name[i+1], NULL, 0);
1104                                                 bpp_specified = 1;
1105                                         } else
1106                                                 goto done;
1107                                         break;
1108                                 case 'x':
1109                                         if (!yres_specified) {
1110                                                 yres = simple_strtoul(&name[i+1], NULL, 0);
1111                                                 yres_specified = 1;
1112                                         } else
1113                                                 goto done;
1114                                         break;
1115                                 case '0'...'9':
1116                                         break;
1117                                 default:
1118                                         goto done;
1119                                 }
1120                         }
1121                         if (i < 0 && yres_specified) {
1122                                 xres = simple_strtoul(name, NULL, 0);
1123                                 res_specified = 1;
1124                         }
1125                 done:
1126                         if ( res_specified ) {
1127                                 dev_info(dev, "overriding resolution: %dx%x\n", xres, yres);
1128                                 inf->xres = xres; inf->yres = yres;
1129                         }
1130                         if ( bpp_specified )
1131                                 switch (bpp) {
1132                                 case 1:
1133                                 case 2:
1134                                 case 4:
1135                                 case 8:
1136                                 case 16:
1137                                         inf->bpp = bpp;
1138                                         dev_info(dev, "overriding bit depth: %d\n", bpp);
1139                                         break;
1140                                 default:
1141                                         dev_err(dev, "Depth %d is not valid\n", bpp);
1142                                 }
1143                 } else if (!strncmp(this_opt, "pixclock:", 9)) {
1144                         inf->pixclock = simple_strtoul(this_opt+9, NULL, 0);
1145                         dev_info(dev, "override pixclock: %u\n", inf->pixclock);
1146                 } else if (!strncmp(this_opt, "left:", 5)) {
1147                         inf->left_margin = simple_strtoul(this_opt+5, NULL, 0);
1148                         dev_info(dev, "override left: %u\n", inf->left_margin);
1149                 } else if (!strncmp(this_opt, "right:", 6)) {
1150                         inf->right_margin = simple_strtoul(this_opt+6, NULL, 0);
1151                         dev_info(dev, "override right: %u\n", inf->right_margin);
1152                 } else if (!strncmp(this_opt, "upper:", 6)) {
1153                         inf->upper_margin = simple_strtoul(this_opt+6, NULL, 0);
1154                         dev_info(dev, "override upper: %u\n", inf->upper_margin);
1155                 } else if (!strncmp(this_opt, "lower:", 6)) {
1156                         inf->lower_margin = simple_strtoul(this_opt+6, NULL, 0);
1157                         dev_info(dev, "override lower: %u\n", inf->lower_margin);
1158                 } else if (!strncmp(this_opt, "hsynclen:", 9)) {
1159                         inf->hsync_len = simple_strtoul(this_opt+9, NULL, 0);
1160                         dev_info(dev, "override hsynclen: %u\n", inf->hsync_len);
1161                 } else if (!strncmp(this_opt, "vsynclen:", 9)) {
1162                         inf->vsync_len = simple_strtoul(this_opt+9, NULL, 0);
1163                         dev_info(dev, "override vsynclen: %u\n", inf->vsync_len);
1164                 } else if (!strncmp(this_opt, "hsync:", 6)) {
1165                         if ( simple_strtoul(this_opt+6, NULL, 0) == 0 ) {
1166                                 dev_info(dev, "override hsync: Active Low\n");
1167                                 inf->sync &= ~FB_SYNC_HOR_HIGH_ACT;
1168                         } else {
1169                                 dev_info(dev, "override hsync: Active High\n");
1170                                 inf->sync |= FB_SYNC_HOR_HIGH_ACT;
1171                         }
1172                 } else if (!strncmp(this_opt, "vsync:", 6)) {
1173                         if ( simple_strtoul(this_opt+6, NULL, 0) == 0 ) {
1174                                 dev_info(dev, "override vsync: Active Low\n");
1175                                 inf->sync &= ~FB_SYNC_VERT_HIGH_ACT;
1176                         } else {
1177                                 dev_info(dev, "override vsync: Active High\n");
1178                                 inf->sync |= FB_SYNC_VERT_HIGH_ACT;
1179                         }
1180                 } else if (!strncmp(this_opt, "dpc:", 4)) {
1181                         if ( simple_strtoul(this_opt+4, NULL, 0) == 0 ) {
1182                                 dev_info(dev, "override double pixel clock: false\n");
1183                                 inf->lccr3 &= ~LCCR3_DPC;
1184                         } else {
1185                                 dev_info(dev, "override double pixel clock: true\n");
1186                                 inf->lccr3 |= LCCR3_DPC;
1187                         }
1188                 } else if (!strncmp(this_opt, "outputen:", 9)) {
1189                         if ( simple_strtoul(this_opt+9, NULL, 0) == 0 ) {
1190                                 dev_info(dev, "override output enable: active low\n");
1191                                 inf->lccr3 = ( inf->lccr3 & ~LCCR3_OEP ) | LCCR3_OutEnL;
1192                         } else {
1193                                 dev_info(dev, "override output enable: active high\n");
1194                                 inf->lccr3 = ( inf->lccr3 & ~LCCR3_OEP ) | LCCR3_OutEnH;
1195                         }
1196                 } else if (!strncmp(this_opt, "pixclockpol:", 12)) {
1197                         if ( simple_strtoul(this_opt+12, NULL, 0) == 0 ) {
1198                                 dev_info(dev, "override pixel clock polarity: falling edge\n");
1199                                 inf->lccr3 = ( inf->lccr3 & ~LCCR3_PCP ) | LCCR3_PixFlEdg;
1200                         } else {
1201                                 dev_info(dev, "override pixel clock polarity: rising edge\n");
1202                                 inf->lccr3 = ( inf->lccr3 & ~LCCR3_PCP ) | LCCR3_PixRsEdg;
1203                         }
1204                 } else if (!strncmp(this_opt, "color", 5)) {
1205                         inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color;
1206                 } else if (!strncmp(this_opt, "mono", 4)) {
1207                         inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono;
1208                 } else if (!strncmp(this_opt, "active", 6)) {
1209                         inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act;
1210                 } else if (!strncmp(this_opt, "passive", 7)) {
1211                         inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas;
1212                 } else if (!strncmp(this_opt, "single", 6)) {
1213                         inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl;
1214                 } else if (!strncmp(this_opt, "dual", 4)) {
1215                         inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual;
1216                 } else if (!strncmp(this_opt, "4pix", 4)) {
1217                         inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono;
1218                 } else if (!strncmp(this_opt, "8pix", 4)) {
1219                         inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono;
1220                 } else {
1221                         dev_err(dev, "unknown option: %s\n", this_opt);
1222                         return -EINVAL;
1223                 }
1224         }
1225         return 0;
1226
1227 }
1228 #endif
1229
1230 int __init pxafb_probe(struct device *dev)
1231 {
1232         struct pxafb_info *fbi;
1233         struct pxafb_mach_info *inf;
1234         unsigned long flags;
1235         int ret;
1236
1237         dev_dbg(dev, "pxafb_probe\n");
1238
1239         inf = dev->platform_data;
1240         ret = -ENOMEM;
1241         fbi = NULL;
1242         if (!inf)
1243                 goto failed;
1244
1245 #ifdef CONFIG_FB_PXA_PARAMETERS
1246         ret = pxafb_parse_options(dev, g_options);
1247         if ( ret < 0 )
1248                 goto failed;
1249 #endif
1250
1251 #ifdef DEBUG_VAR
1252         /* Check for various illegal bit-combinations. Currently only
1253          * a warning is given. */
1254
1255         if ( inf->lccr0 & LCCR0_INVALID_CONFIG_MASK )
1256                 dev_warn(dev, "machine LCCR0 setting contains illegal bits: %08x\n",
1257                         inf->lccr0 & LCCR0_INVALID_CONFIG_MASK);
1258         if ( inf->lccr3 & LCCR3_INVALID_CONFIG_MASK )
1259                 dev_warn(dev, "machine LCCR3 setting contains illegal bits: %08x\n",
1260                         inf->lccr3 & LCCR3_INVALID_CONFIG_MASK);
1261         if ( inf->lccr0 & LCCR0_DPD &&
1262              ( ( inf->lccr0 & LCCR0_PAS ) != LCCR0_Pas ||
1263                ( inf->lccr0 & LCCR0_SDS ) != LCCR0_Sngl ||
1264                ( inf->lccr0 & LCCR0_CMS ) != LCCR0_Mono ) )
1265                 dev_warn(dev, "Double Pixel Data (DPD) mode is only valid in passive mono"
1266                          " single panel mode\n");
1267         if ( (inf->lccr0 & LCCR0_PAS) == LCCR0_Act &&
1268              ( inf->lccr0 & LCCR0_SDS ) == LCCR0_Dual )
1269                 dev_warn(dev, "Dual panel only valid in passive mode\n");
1270         if ( (inf->lccr0 & LCCR0_PAS ) == LCCR0_Pas &&
1271              (inf->upper_margin || inf->lower_margin) )
1272                 dev_warn(dev, "Upper and lower margins must be 0 in passive mode\n");
1273 #endif
1274
1275         dev_dbg(dev, "got a %dx%dx%d LCD\n",inf->xres, inf->yres, inf->bpp);
1276         if (inf->xres == 0 || inf->yres == 0 || inf->bpp == 0) {
1277                 dev_err(dev, "Invalid resolution or bit depth\n");
1278                 ret = -EINVAL;
1279                 goto failed;
1280         }
1281         pxafb_backlight_power = inf->pxafb_backlight_power;
1282         pxafb_lcd_power = inf->pxafb_lcd_power;
1283         fbi = pxafb_init_fbinfo(dev);
1284         if (!fbi) {
1285                 dev_err(dev, "Failed to initialize framebuffer device\n");
1286                 ret = -ENOMEM; // only reason for pxafb_init_fbinfo to fail is kmalloc
1287                 goto failed;
1288         }
1289
1290         /* Initialize video memory */
1291         ret = pxafb_map_video_memory(fbi);
1292         if (ret) {
1293                 dev_err(dev, "Failed to allocate video RAM: %d\n", ret);
1294                 ret = -ENOMEM;
1295                 goto failed;
1296         }
1297         /* enable LCD controller clock */
1298         local_irq_save(flags);
1299         CKEN |= CKEN16_LCD;
1300         local_irq_restore(flags);
1301
1302         ret = request_irq(IRQ_LCD, pxafb_handle_irq, SA_INTERRUPT, "LCD", fbi);
1303         if (ret) {
1304                 dev_err(dev, "request_irq failed: %d\n", ret);
1305                 ret = -EBUSY;
1306                 goto failed;
1307         }
1308
1309         /*
1310          * This makes sure that our colour bitfield
1311          * descriptors are correctly initialised.
1312          */
1313         pxafb_check_var(&fbi->fb.var, &fbi->fb);
1314         pxafb_set_par(&fbi->fb);
1315
1316         dev_set_drvdata(dev, fbi);
1317
1318         ret = register_framebuffer(&fbi->fb);
1319         if (ret < 0) {
1320                 dev_err(dev, "Failed to register framebuffer device: %d\n", ret);
1321                 goto failed;
1322         }
1323
1324 #ifdef CONFIG_PM
1325         // TODO
1326 #endif
1327
1328 #ifdef CONFIG_CPU_FREQ
1329         fbi->freq_transition.notifier_call = pxafb_freq_transition;
1330         fbi->freq_policy.notifier_call = pxafb_freq_policy;
1331         cpufreq_register_notifier(&fbi->freq_transition, CPUFREQ_TRANSITION_NOTIFIER);
1332         cpufreq_register_notifier(&fbi->freq_policy, CPUFREQ_POLICY_NOTIFIER);
1333 #endif
1334
1335         /*
1336          * Ok, now enable the LCD controller
1337          */
1338         set_ctrlr_state(fbi, C_ENABLE);
1339
1340         return 0;
1341
1342 failed:
1343         dev_set_drvdata(dev, NULL);
1344         if (fbi)
1345                 kfree(fbi);
1346         return ret;
1347 }
1348
1349 static struct device_driver pxafb_driver = {
1350         .name           = "pxafb",
1351         .bus            = &platform_bus_type,
1352         .probe          = pxafb_probe,
1353 #ifdef CONFIG_PM
1354         .suspend        = pxafb_suspend,
1355         .resume         = pxafb_resume,
1356 #endif
1357 };
1358
1359 int __devinit pxafb_init(void)
1360 {
1361         return driver_register(&pxafb_driver);
1362 }
1363
1364 #ifndef MODULE
1365 int __devinit pxafb_setup(char *options)
1366 {
1367 # ifdef CONFIG_FB_PXA_PARAMETERS
1368         strlcpy(g_options, options, sizeof(g_options));
1369 # endif
1370         return 0;
1371 }
1372 #else
1373 module_init(pxafb_init);
1374 # ifdef CONFIG_FB_PXA_PARAMETERS
1375 module_param_string(options, g_options, sizeof(g_options), 0);
1376 MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.txt)");
1377 # endif
1378 #endif
1379
1380 MODULE_DESCRIPTION("loadable framebuffer driver for PXA");
1381 MODULE_LICENSE("GPL");