drivers/video/radeonfb.c

   1 /*
   2  *      drivers/video/radeonfb.c
   3  *      framebuffer driver for ATI Radeon chipset video boards
   4  *
   5  *      Copyright 2000  Ani Joshi <ajoshi@kernel.crashing.org>
   6  *
   7  *
   8  *      ChangeLog:
   9  *      2000-08-03      initial version 0.0.1
  10  *      2000-09-10      more bug fixes, public release 0.0.5
  11  *      2001-02-19      mode bug fixes, 0.0.7
  12  *      2001-07-05      fixed scrolling issues, engine initialization,
  13  *                      and minor mode tweaking, 0.0.9
  14  *      2001-09-07      Radeon VE support, Nick Kurshev
  15  *                      blanking, pan_display, and cmap fixes, 0.1.0
  16  *      2001-10-10      Radeon 7500 and 8500 support, and experimental
  17  *                      flat panel support, 0.1.1
  18  *      2001-11-17      Radeon M6 (ppc) support, Daniel Berlin, 0.1.2
  19  *      2001-11-18      DFP fixes, Kevin Hendricks, 0.1.3
  20  *      2001-11-29      more cmap, backlight fixes, Benjamin Herrenschmidt
  21  *      2002-01-18      DFP panel detection via BIOS, Michael Clark, 0.1.4
  22  *      2002-06-02      console switching, mode set fixes, accel fixes
  23  *      2002-06-03      MTRR support, Peter Horton, 0.1.5
  24  *      2002-09-21      rv250, r300, m9 initial support,
  25  *                      added mirror option, 0.1.6
  26  *
  27  *      Special thanks to ATI DevRel team for their hardware donations.
  28  *
  29  */
  30
  31
  32 #define RADEON_VERSION  "0.1.6"
  33
  34
  35 #include <linux/config.h>
  36 #include <linux/module.h>
  37 #include <linux/kernel.h>
  38 #include <linux/errno.h>
  39 #include <linux/string.h>
  40 #include <linux/mm.h>
  41 #include <linux/tty.h>
  42 #include <linux/slab.h>
  43 #include <linux/delay.h>
  44 #include <linux/fb.h>
  45 #include <linux/ioport.h>
  46 #include <linux/init.h>
  47 #include <linux/pci.h>
  48 #include <linux/vmalloc.h>
  49
  50 #include <asm/io.h>
  51 #include <asm/uaccess.h>
  52 #if defined(__powerpc__)
  53 #include <asm/prom.h>
  54 #include <asm/pci-bridge.h>
  55 #include "macmodes.h"
  56
  57 #ifdef CONFIG_NVRAM
  58 #include <linux/nvram.h>
  59 #endif
  60
  61 #ifdef CONFIG_PMAC_BACKLIGHT
  62 #include <asm/backlight.h>
  63 #endif
  64
  65 #ifdef CONFIG_BOOTX_TEXT
  66 #include <asm/btext.h>
  67 #endif
  68
  69 #ifdef CONFIG_ADB_PMU
  70 #include <linux/adb.h>
  71 #include <linux/pmu.h>
  72 #endif
  73
  74 #endif /* __powerpc__ */
  75
  76 #ifdef CONFIG_MTRR
  77 #include <asm/mtrr.h>
  78 #endif
  79
  80 #include <video/radeon.h>
  81 #include <linux/radeonfb.h>
  82
  83 #define DEBUG   1
  84
  85 #if DEBUG
  86 #define RTRACE          printk
  87 #else
  88 #define RTRACE          if(0) printk
  89 #endif
  90
  91 // XXX
  92 #undef CONFIG_PMAC_PBOOK
  93
  94
  95 enum radeon_chips {
  96         RADEON_QD,
  97         RADEON_QE,
  98         RADEON_QF,
  99         RADEON_QG,
 100         RADEON_QY,
 101         RADEON_QZ,
 102         RADEON_LW,
 103         RADEON_LX,
 104         RADEON_LY,
 105         RADEON_LZ,
 106         RADEON_QL,
 107         RADEON_QN,
 108         RADEON_QO,
 109         RADEON_Ql,
 110         RADEON_BB,
 111         RADEON_QW,
 112         RADEON_QX,
 113         RADEON_Id,
 114         RADEON_Ie,
 115         RADEON_If,
 116         RADEON_Ig,
 117         RADEON_Ya,
 118         RADEON_Yd,
 119         RADEON_Ld,
 120         RADEON_Le,
 121         RADEON_Lf,
 122         RADEON_Lg,
 123         RADEON_ND,
 124         RADEON_NE,
 125         RADEON_NF,
 126         RADEON_NG,
 127         RADEON_QM
 128 };
 129
 130 enum radeon_arch {
 131         RADEON_R100,
 132         RADEON_RV100,
 133         RADEON_R200,
 134         RADEON_RV200,
 135         RADEON_RV250,
 136         RADEON_R300,
 137         RADEON_M6,
 138         RADEON_M7,
 139         RADEON_M9
 140 };
 141
 142 static struct radeon_chip_info {
 143         const char *name;
 144         unsigned char arch;
 145 } radeon_chip_info[] __devinitdata = {
 146         { "QD", RADEON_R100 },
 147         { "QE", RADEON_R100 },
 148         { "QF", RADEON_R100 },
 149         { "QG", RADEON_R100 },
 150         { "VE QY", RADEON_RV100 },
 151         { "VE QZ", RADEON_RV100 },
 152         { "M7 LW", RADEON_M7 },
 153         { "M7 LX", RADEON_M7 },
 154         { "M6 LY", RADEON_M6 },
 155         { "M6 LZ", RADEON_M6 },
 156         { "8500 QL", RADEON_R200 },
 157         { "8500 QN", RADEON_R200 },
 158         { "8500 QO", RADEON_R200 },
 159         { "8500 Ql", RADEON_R200 },
 160         { "8500 BB", RADEON_R200 },
 161         { "7500 QW", RADEON_RV200 },
 162         { "7500 QX", RADEON_RV200 },
 163         { "9000 Id", RADEON_RV250 },
 164         { "9000 Ie", RADEON_RV250 },
 165         { "9000 If", RADEON_RV250 },
 166         { "9000 Ig", RADEON_RV250 },
 167         { "M9 Ld", RADEON_M9 },
 168         { "M9 Le", RADEON_M9 },
 169         { "M9 Lf", RADEON_M9 },
 170         { "M9 Lg", RADEON_M9 },
 171         { "9700 ND", RADEON_R300 },
 172         { "9700 NE", RADEON_R300 },
 173         { "9700 NF", RADEON_R300 },
 174         { "9700 NG", RADEON_R300 },
 175         { "9100 QM", RADEON_R200 }
 176 };
 177
 178
 179 enum radeon_montype
 180 {
 181         MT_NONE,
 182         MT_CRT,         /* CRT */
 183         MT_LCD,         /* LCD */
 184         MT_DFP,         /* DVI */
 185         MT_CTV,         /* composite TV */
 186         MT_STV          /* S-Video out */
 187 };
 188
 189
 190 static struct pci_device_id radeonfb_pci_table[] = {
 191         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QD},
 192         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QE},
 193         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QF},
 194         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QG, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QG},
 195         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QY, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QY},
 196         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QZ, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QZ},
 197         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_LW, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LW},
 198         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_LX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LX},
 199         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_LY, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LY},
 200         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_LZ, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LZ},
 201         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QL, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QL},
 202         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QN, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QN},
 203         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QO, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QO},
 204         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Ql, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Ql},
 205         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_BB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_BB},
 206         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QW, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QW},
 207         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QX},
 208         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Id},
 209         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Ie, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Ie},
 210         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_If, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_If},
 211         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Ig, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Ig},
 212         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Ya, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Ya},
 213         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Yd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Yd},
 214         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Ld, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Ld},
 215         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Le, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Le},
 216         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Lf, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Lf},
 217         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Lg, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Lg},
 218         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_ND, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_ND},
 219         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_NE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_NE},
 220         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_NF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_NF},
 221         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_NG, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_NG},
 222         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QM, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QM},
 223         { 0, }
 224 };
 225 MODULE_DEVICE_TABLE(pci, radeonfb_pci_table);
 226
 227
 228 typedef struct {
 229         u16 reg;
 230         u32 val;
 231 } reg_val;
 232
 233
 234 /* these common regs are cleared before mode setting so they do not
 235  * interfere with anything
 236  */
 237 static reg_val common_regs[] = {
 238         { OVR_CLR, 0 },
 239         { OVR_WID_LEFT_RIGHT, 0 },
 240         { OVR_WID_TOP_BOTTOM, 0 },
 241         { OV0_SCALE_CNTL, 0 },
 242         { SUBPIC_CNTL, 0 },
 243         { VIPH_CONTROL, 0 },
 244         { I2C_CNTL_1, 0 },
 245         { GEN_INT_CNTL, 0 },
 246         { CAP0_TRIG_CNTL, 0 },
 247 };
 248
 249 static reg_val common_regs_m6[] = {
 250         { OVR_CLR,      0 },
 251         { OVR_WID_LEFT_RIGHT,   0 },
 252         { OVR_WID_TOP_BOTTOM,   0 },
 253         { OV0_SCALE_CNTL,   0 },
 254         { SUBPIC_CNTL,      0 },
 255         { GEN_INT_CNTL,     0 },
 256         { CAP0_TRIG_CNTL,   0 }
 257 };
 258
 259 typedef struct {
 260         u8 clock_chip_type;
 261         u8 struct_size;
 262         u8 accelerator_entry;
 263         u8 VGA_entry;
 264         u16 VGA_table_offset;
 265         u16 POST_table_offset;
 266         u16 XCLK;
 267         u16 MCLK;
 268         u8 num_PLL_blocks;
 269         u8 size_PLL_blocks;
 270         u16 PCLK_ref_freq;
 271         u16 PCLK_ref_divider;
 272         u32 PCLK_min_freq;
 273         u32 PCLK_max_freq;
 274         u16 MCLK_ref_freq;
 275         u16 MCLK_ref_divider;
 276         u32 MCLK_min_freq;
 277         u32 MCLK_max_freq;
 278         u16 XCLK_ref_freq;
 279         u16 XCLK_ref_divider;
 280         u32 XCLK_min_freq;
 281         u32 XCLK_max_freq;
 282 } __attribute__ ((packed)) PLL_BLOCK;
 283
 284
 285 struct pll_info {
 286         int ppll_max;
 287         int ppll_min;
 288         int xclk;
 289         int ref_div;
 290         int ref_clk;
 291 };
 292
 293
 294 struct ram_info {
 295         int ml;
 296         int mb;
 297         int trcd;
 298         int trp;
 299         int twr;
 300         int cl;
 301         int tr2w;
 302         int loop_latency;
 303         int rloop;
 304 };
 305
 306
 307 struct radeon_regs {
 308         /* CRTC regs */
 309         u32 crtc_h_total_disp;
 310         u32 crtc_h_sync_strt_wid;
 311         u32 crtc_v_total_disp;
 312         u32 crtc_v_sync_strt_wid;
 313         u32 crtc_pitch;
 314         u32 crtc_gen_cntl;
 315         u32 crtc_ext_cntl;
 316         u32 dac_cntl;
 317
 318         u32 flags;
 319         u32 pix_clock;
 320         int xres, yres;
 321
 322         /* DDA regs */
 323         u32 dda_config;
 324         u32 dda_on_off;
 325
 326         /* PLL regs */
 327         u32 ppll_div_3;
 328         u32 ppll_ref_div;
 329         u32 vclk_ecp_cntl;
 330
 331         /* Flat panel regs */
 332         u32 fp_crtc_h_total_disp;
 333         u32 fp_crtc_v_total_disp;
 334         u32 fp_gen_cntl;
 335         u32 fp_h_sync_strt_wid;
 336         u32 fp_horz_stretch;
 337         u32 fp_panel_cntl;
 338         u32 fp_v_sync_strt_wid;
 339         u32 fp_vert_stretch;
 340         u32 lvds_gen_cntl;
 341         u32 lvds_pll_cntl;
 342         u32 tmds_crc;
 343         u32 tmds_transmitter_cntl;
 344
 345 #if defined(__BIG_ENDIAN)
 346         u32 surface_cntl;
 347 #endif
 348 };
 349
 350
 351 struct radeonfb_info {
 352         struct fb_info info;
 353
 354         struct radeon_regs state;
 355         struct radeon_regs init_state;
 356
 357         char name[32];
 358         char ram_type[12];
 359
 360         unsigned long mmio_base_phys;
 361         unsigned long fb_base_phys;
 362
 363         void __iomem *mmio_base;
 364         void __iomem *fb_base;
 365
 366         struct pci_dev *pdev;
 367
 368         unsigned char *EDID;
 369         unsigned char __iomem *bios_seg;
 370
 371         u32 pseudo_palette[17];
 372         struct { u8 red, green, blue, pad; } palette[256];
 373
 374         int chipset;
 375         unsigned char arch;
 376         int video_ram;
 377         u8 rev;
 378         int pitch, bpp, depth;
 379         int xres, yres, pixclock;
 380         int xres_virtual, yres_virtual;
 381         u32 accel_flags;
 382
 383         int use_default_var;
 384         int got_dfpinfo;
 385
 386         int hasCRTC2;
 387         int crtDisp_type;
 388         int dviDisp_type;
 389
 390         int panel_xres, panel_yres;
 391         int clock;
 392         int hOver_plus, hSync_width, hblank;
 393         int vOver_plus, vSync_width, vblank;
 394         int hAct_high, vAct_high, interlaced;
 395         int synct, misc;
 396
 397         u32 dp_gui_master_cntl;
 398
 399         struct pll_info pll;
 400         int pll_output_freq, post_div, fb_div;
 401
 402         struct ram_info ram;
 403
 404         int mtrr_hdl;
 405
 406 #ifdef CONFIG_PMAC_PBOOK
 407         int pm_reg;
 408         u32 save_regs[64];
 409         u32 mdll, mdll2;
 410 #endif /* CONFIG_PMAC_PBOOK */
 411         int asleep;
 412
 413         struct radeonfb_info *next;
 414 };
 415
 416
 417 static struct fb_var_screeninfo radeonfb_default_var = {
 418         640, 480, 640, 480, 0, 0, 8, 0,
 419         {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0},
 420         0, 0, -1, -1, 0, 39721, 40, 24, 32, 11, 96, 2,
 421         0, FB_VMODE_NONINTERLACED
 422 };
 423
 424 /*
 425  * IO macros
 426  */
 427
 428 #define INREG8(addr)            readb((rinfo->mmio_base)+addr)
 429 #define OUTREG8(addr,val)       writeb(val, (rinfo->mmio_base)+addr)
 430 #define INREG(addr)             readl((rinfo->mmio_base)+addr)
 431 #define OUTREG(addr,val)        writel(val, (rinfo->mmio_base)+addr)
 432
 433 #define OUTPLL(addr,val)        \
 434         do {    \
 435                 OUTREG8(CLOCK_CNTL_INDEX, (addr & 0x0000003f) | 0x00000080); \
 436                 OUTREG(CLOCK_CNTL_DATA, val); \
 437         } while(0)
 438
 439 #define OUTPLLP(addr,val,mask)                                          \
 440         do {                                                            \
 441                 unsigned int _tmp = INPLL(addr);                        \
 442                 _tmp &= (mask);                                         \
 443                 _tmp |= (val);                                          \
 444                 OUTPLL(addr, _tmp);                                     \
 445         } while (0)
 446
 447 #define OUTREGP(addr,val,mask)                                          \
 448         do {                                                            \
 449                 unsigned int _tmp = INREG(addr);                        \
 450                 _tmp &= (mask);                                         \
 451                 _tmp |= (val);                                          \
 452                 OUTREG(addr, _tmp);                                     \
 453         } while (0)
 454
 455
 456 static __inline__ u32 _INPLL(struct radeonfb_info *rinfo, u32 addr)
 457 {
 458         OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f);
 459         return (INREG(CLOCK_CNTL_DATA));
 460 }
 461
 462 #define INPLL(addr)             _INPLL(rinfo, addr)
 463
 464 #define PRIMARY_MONITOR(rinfo)  ((rinfo->dviDisp_type != MT_NONE) &&    \
 465                                  (rinfo->dviDisp_type != MT_STV) &&     \
 466                                  (rinfo->dviDisp_type != MT_CTV) ?      \
 467                                  rinfo->dviDisp_type : rinfo->crtDisp_type)
 468
 469 static char *GET_MON_NAME(int type)
 470 {
 471         char *pret = NULL;
 472
 473         switch (type) {
 474                 case MT_NONE:
 475                         pret = "no";
 476                         break;
 477                 case MT_CRT:
 478                         pret = "CRT";
 479                         break;
 480                 case MT_DFP:
 481                         pret = "DFP";
 482                         break;
 483                 case MT_LCD:
 484                         pret = "LCD";
 485                         break;
 486                 case MT_CTV:
 487                         pret = "CTV";
 488                         break;
 489                 case MT_STV:
 490                         pret = "STV";
 491                         break;
 492         }
 493
 494         return pret;
 495 }
 496
 497
 498 /*
 499  * 2D engine routines
 500  */
 501
 502 static __inline__ void radeon_engine_flush (struct radeonfb_info *rinfo)
 503 {
 504         int i;
 505
 506         /* initiate flush */
 507         OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
 508                 ~RB2D_DC_FLUSH_ALL);
 509
 510         for (i=0; i < 2000000; i++) {
 511                 if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
 512                         break;
 513         }
 514 }
 515
 516
 517 static __inline__ void _radeon_fifo_wait (struct radeonfb_info *rinfo, int entries)
 518 {
 519         int i;
 520
 521         for (i=0; i<2000000; i++)
 522                 if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
 523                         return;
 524 }
 525
 526
 527 static __inline__ void _radeon_engine_idle (struct radeonfb_info *rinfo)
 528 {
 529         int i;
 530
 531         /* ensure FIFO is empty before waiting for idle */
 532         _radeon_fifo_wait (rinfo, 64);
 533
 534         for (i=0; i<2000000; i++) {
 535                 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
 536                         radeon_engine_flush (rinfo);
 537                         return;
 538                 }
 539         }
 540 }
 541
 542
 543 #define radeon_engine_idle()            _radeon_engine_idle(rinfo)
 544 #define radeon_fifo_wait(entries)       _radeon_fifo_wait(rinfo,entries)
 545
 546
 547
 548 /*
 549  * helper routines
 550  */
 551
 552 static __inline__ u32 radeon_get_dstbpp(u16 depth)
 553 {
 554         switch (depth) {
 555                 case 8:
 556                         return DST_8BPP;
 557                 case 15:
 558                         return DST_15BPP;
 559                 case 16:
 560                         return DST_16BPP;
 561                 case 32:
 562                         return DST_32BPP;
 563                 default:
 564                         return 0;
 565         }
 566 }
 567
 568
 569 static inline int var_to_depth(const struct fb_var_screeninfo *var)
 570 {
 571         if (var->bits_per_pixel != 16)
 572                 return var->bits_per_pixel;
 573         return (var->green.length == 6) ? 16 : 15;
 574 }
 575
 576
 577 static void _radeon_engine_reset(struct radeonfb_info *rinfo)
 578 {
 579         u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
 580
 581         radeon_engine_flush (rinfo);
 582
 583         clock_cntl_index = INREG(CLOCK_CNTL_INDEX);
 584         mclk_cntl = INPLL(MCLK_CNTL);
 585
 586         OUTPLL(MCLK_CNTL, (mclk_cntl |
 587                            FORCEON_MCLKA |
 588                            FORCEON_MCLKB |
 589                            FORCEON_YCLKA |
 590                            FORCEON_YCLKB |
 591                            FORCEON_MC |
 592                            FORCEON_AIC));
 593         rbbm_soft_reset = INREG(RBBM_SOFT_RESET);
 594
 595         OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset |
 596                                 SOFT_RESET_CP |
 597                                 SOFT_RESET_HI |
 598                                 SOFT_RESET_SE |
 599                                 SOFT_RESET_RE |
 600                                 SOFT_RESET_PP |
 601                                 SOFT_RESET_E2 |
 602                                 SOFT_RESET_RB);
 603         INREG(RBBM_SOFT_RESET);
 604         OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset & (u32)
 605                                 ~(SOFT_RESET_CP |
 606                                   SOFT_RESET_HI |
 607                                   SOFT_RESET_SE |
 608                                   SOFT_RESET_RE |
 609                                   SOFT_RESET_PP |
 610                                   SOFT_RESET_E2 |
 611                                   SOFT_RESET_RB));
 612         INREG(RBBM_SOFT_RESET);
 613
 614         OUTPLL(MCLK_CNTL, mclk_cntl);
 615         OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index);
 616         OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset);
 617
 618         return;
 619 }
 620
 621 #define radeon_engine_reset()           _radeon_engine_reset(rinfo)
 622
 623
 624 static __inline__ int round_div(int num, int den)
 625 {
 626         return (num + (den / 2)) / den;
 627 }
 628
 629
 630
 631 static __inline__ int min_bits_req(int val)
 632 {
 633         int bits_req = 0;
 634
 635         if (val == 0)
 636                 bits_req = 1;
 637
 638         while (val) {
 639                 val >>= 1;
 640                 bits_req++;
 641         }
 642
 643         return (bits_req);
 644 }
 645
 646
 647 static __inline__ int _max(int val1, int val2)
 648 {
 649         if (val1 >= val2)
 650                 return val1;
 651         else
 652                 return val2;
 653 }
 654
 655
 656
 657 /*
 658  * globals
 659  */
 660
 661 static char *mode_option __initdata;
 662 static char noaccel = 0;
 663 static char mirror = 0;
 664 static int panel_yres __initdata = 0;
 665 static char force_dfp __initdata = 0;
 666 static struct radeonfb_info *board_list = NULL;
 667 static char nomtrr __initdata = 0;
 668
 669 /*
 670  * prototypes
 671  */
 672
 673 static void radeon_save_state (struct radeonfb_info *rinfo,
 674                                struct radeon_regs *save);
 675 static void radeon_engine_init (struct radeonfb_info *rinfo);
 676 static void radeon_write_mode (struct radeonfb_info *rinfo,
 677                                struct radeon_regs *mode);
 678 static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo);
 679 static int __devinit radeon_init_disp (struct radeonfb_info *rinfo);
 680 static int radeon_init_disp_var (struct radeonfb_info *rinfo, struct fb_var_screeninfo *var);
 681 static void __iomem *radeon_find_rom(struct radeonfb_info *rinfo);
 682 static void radeon_get_pllinfo(struct radeonfb_info *rinfo, void __iomem *bios_seg);
 683 static void radeon_get_moninfo (struct radeonfb_info *rinfo);
 684 static int radeon_get_dfpinfo (struct radeonfb_info *rinfo);
 685 static int radeon_get_dfpinfo_BIOS(struct radeonfb_info *rinfo);
 686 static void radeon_get_EDID(struct radeonfb_info *rinfo);
 687 static int radeon_dfp_parse_EDID(struct radeonfb_info *rinfo);
 688 static void radeon_update_default_var(struct radeonfb_info *rinfo);
 689
 690 #ifdef CONFIG_PPC_OF
 691
 692 static int radeon_read_OF (struct radeonfb_info *rinfo);
 693 static int radeon_get_EDID_OF(struct radeonfb_info *rinfo);
 694 extern struct device_node *pci_device_to_OF_node(struct pci_dev *dev);
 695
 696 #ifdef CONFIG_PMAC_PBOOK
 697 int radeon_sleep_notify(struct pmu_sleep_notifier *self, int when);
 698 static struct pmu_sleep_notifier radeon_sleep_notifier = {
 699         radeon_sleep_notify, SLEEP_LEVEL_VIDEO,
 700 };
 701 #endif /* CONFIG_PMAC_PBOOK */
 702 #ifdef CONFIG_PMAC_BACKLIGHT
 703 static int radeon_set_backlight_enable(int on, int level, void *data);
 704 static int radeon_set_backlight_level(int level, void *data);
 705 static struct backlight_controller radeon_backlight_controller = {
 706         radeon_set_backlight_enable,
 707         radeon_set_backlight_level
 708 };
 709 #endif /* CONFIG_PMAC_BACKLIGHT */
 710
 711 #endif /* CONFIG_PPC_OF */
 712
 713
 714 static void __iomem *radeon_find_rom(struct radeonfb_info *rinfo)
 715 {
 716 #if defined(__i386__)
 717         u32  segstart;
 718         char __iomem *rom_base;
 719         char __iomem *rom;
 720         int  stage;
 721         int  i,j;
 722         char aty_rom_sig[] = "761295520";
 723         char *radeon_sig[] = {
 724           "RG6",
 725           "RADEON"
 726         };
 727
 728         for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
 729
 730                 stage = 1;
 731
 732                 rom_base = ioremap(segstart, 0x1000);
 733
 734                 if ((*rom_base == 0x55) && (((*(rom_base + 1)) & 0xff) == 0xaa))
 735                         stage = 2;
 736
 737
 738                 if (stage != 2) {
 739                         iounmap(rom_base);
 740                         continue;
 741                 }
 742
 743                 rom = rom_base;
 744
 745                 for (i = 0; (i < 128 - strlen(aty_rom_sig)) && (stage != 3); i++) {
 746                         if (aty_rom_sig[0] == *rom)
 747                                 if (strncmp(aty_rom_sig, rom,
 748                                                 strlen(aty_rom_sig)) == 0)
 749                                         stage = 3;
 750                         rom++;
 751                 }
 752                 if (stage != 3) {
 753                         iounmap(rom_base);
 754                         continue;
 755                 }
 756                 rom = rom_base;
 757
 758                 for (i = 0; (i < 512) && (stage != 4); i++) {
 759                     for(j = 0;j < sizeof(radeon_sig)/sizeof(char *);j++) {
 760                         if (radeon_sig[j][0] == *rom)
 761                                 if (strncmp(radeon_sig[j], rom,
 762                                             strlen(radeon_sig[j])) == 0) {
 763                                               stage = 4;
 764                                               break;
 765                                             }
 766                     }
 767                         rom++;
 768                 }
 769                 if (stage != 4) {
 770                         iounmap(rom_base);
 771                         continue;
 772                 }
 773
 774                 return rom_base;
 775         }
 776 #endif
 777         return NULL;
 778 }
 779
 780
 781
 782
 783 static void radeon_get_pllinfo(struct radeonfb_info *rinfo, void __iomem *bios_seg)
 784 {
 785         void __iomem *bios_header;
 786         void __iomem *header_ptr;
 787         u16 bios_header_offset, pll_info_offset;
 788         PLL_BLOCK pll;
 789
 790         if (bios_seg) {
 791                 bios_header = bios_seg + 0x48L;
 792                 header_ptr  = bios_header;
 793
 794                 bios_header_offset = readw(header_ptr);
 795                 bios_header = bios_seg + bios_header_offset;
 796                 bios_header += 0x30;
 797
 798                 header_ptr = bios_header;
 799                 pll_info_offset = readw(header_ptr);
 800                 header_ptr = bios_seg + pll_info_offset;
 801
 802                 memcpy_fromio(&pll, header_ptr, 50);
 803
 804                 rinfo->pll.xclk = (u32)pll.XCLK;
 805                 rinfo->pll.ref_clk = (u32)pll.PCLK_ref_freq;
 806                 rinfo->pll.ref_div = (u32)pll.PCLK_ref_divider;
 807                 rinfo->pll.ppll_min = pll.PCLK_min_freq;
 808                 rinfo->pll.ppll_max = pll.PCLK_max_freq;
 809
 810                 printk("radeonfb: ref_clk=%d, ref_div=%d, xclk=%d from BIOS\n",
 811                         rinfo->pll.ref_clk, rinfo->pll.ref_div, rinfo->pll.xclk);
 812         } else {
 813 #ifdef CONFIG_PPC_OF
 814                 if (radeon_read_OF(rinfo)) {
 815                         unsigned int tmp, Nx, M, ref_div, xclk;
 816
 817                         tmp = INPLL(M_SPLL_REF_FB_DIV);
 818                         ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;
 819
 820                         Nx = (tmp & 0xff00) >> 8;
 821                         M = (tmp & 0xff);
 822                         xclk = ((((2 * Nx * rinfo->pll.ref_clk) + (M)) /
 823                                 (2 * M)));
 824
 825                         rinfo->pll.xclk = xclk;
 826                         rinfo->pll.ref_div = ref_div;
 827                         rinfo->pll.ppll_min = 12000;
 828                         rinfo->pll.ppll_max = 35000;
 829
 830                         printk("radeonfb: ref_clk=%d, ref_div=%d, xclk=%d from OF\n",
 831                                 rinfo->pll.ref_clk, rinfo->pll.ref_div, rinfo->pll.xclk);
 832
 833                         return;
 834                 }
 835 #endif
 836                 /* no BIOS or BIOS not found, use defaults */
 837                 switch (rinfo->chipset) {
 838                         case PCI_DEVICE_ID_ATI_RADEON_QW:
 839                         case PCI_DEVICE_ID_ATI_RADEON_QX:
 840                                 rinfo->pll.ppll_max = 35000;
 841                                 rinfo->pll.ppll_min = 12000;
 842                                 rinfo->pll.xclk = 23000;
 843                                 rinfo->pll.ref_div = 12;
 844                                 rinfo->pll.ref_clk = 2700;
 845                                 break;
 846                         case PCI_DEVICE_ID_ATI_RADEON_QL:
 847                         case PCI_DEVICE_ID_ATI_RADEON_QN:
 848                         case PCI_DEVICE_ID_ATI_RADEON_QO:
 849                         case PCI_DEVICE_ID_ATI_RADEON_Ql:
 850                         case PCI_DEVICE_ID_ATI_RADEON_BB:
 851                                 rinfo->pll.ppll_max = 35000;
 852                                 rinfo->pll.ppll_min = 12000;
 853                                 rinfo->pll.xclk = 27500;
 854                                 rinfo->pll.ref_div = 12;
 855                                 rinfo->pll.ref_clk = 2700;
 856                                 break;
 857                         case PCI_DEVICE_ID_ATI_RADEON_Id:
 858                         case PCI_DEVICE_ID_ATI_RADEON_Ie:
 859                         case PCI_DEVICE_ID_ATI_RADEON_If:
 860                         case PCI_DEVICE_ID_ATI_RADEON_Ig:
 861                                 rinfo->pll.ppll_max = 35000;
 862                                 rinfo->pll.ppll_min = 12000;
 863                                 rinfo->pll.xclk = 25000;
 864                                 rinfo->pll.ref_div = 12;
 865                                 rinfo->pll.ref_clk = 2700;
 866                                 break;
 867                         case PCI_DEVICE_ID_ATI_RADEON_ND:
 868                         case PCI_DEVICE_ID_ATI_RADEON_NE:
 869                         case PCI_DEVICE_ID_ATI_RADEON_NF:
 870                         case PCI_DEVICE_ID_ATI_RADEON_NG:
 871                                 rinfo->pll.ppll_max = 40000;
 872                                 rinfo->pll.ppll_min = 20000;
 873                                 rinfo->pll.xclk = 27000;
 874                                 rinfo->pll.ref_div = 12;
 875                                 rinfo->pll.ref_clk = 2700;
 876                                 break;
 877                         case PCI_DEVICE_ID_ATI_RADEON_QD:
 878                         case PCI_DEVICE_ID_ATI_RADEON_QE:
 879                         case PCI_DEVICE_ID_ATI_RADEON_QF:
 880                         case PCI_DEVICE_ID_ATI_RADEON_QG:
 881                         default:
 882                                 rinfo->pll.ppll_max = 35000;
 883                                 rinfo->pll.ppll_min = 12000;
 884                                 rinfo->pll.xclk = 16600;
 885                                 rinfo->pll.ref_div = 67;
 886                                 rinfo->pll.ref_clk = 2700;
 887                                 break;
 888                 }
 889
 890                 printk("radeonfb: ref_clk=%d, ref_div=%d, xclk=%d defaults\n",
 891                         rinfo->pll.ref_clk, rinfo->pll.ref_div, rinfo->pll.xclk);
 892         }
 893 }
 894
 895
 896 static void radeon_get_moninfo (struct radeonfb_info *rinfo)
 897 {
 898         unsigned int tmp;
 899
 900         if (force_dfp) {
 901                 rinfo->dviDisp_type = MT_DFP;
 902                 return;
 903         }
 904
 905         tmp = INREG(BIOS_4_SCRATCH);
 906         printk(KERN_DEBUG "radeon_get_moninfo: bios 4 scratch = %x\n", tmp);
 907
 908         if (rinfo->hasCRTC2) {
 909                 /* primary DVI port */
 910                 if (tmp & 0x08)
 911                         rinfo->dviDisp_type = MT_DFP;
 912                 else if (tmp & 0x4)
 913                         rinfo->dviDisp_type = MT_LCD;
 914                 else if (tmp & 0x200)
 915                         rinfo->dviDisp_type = MT_CRT;
 916                 else if (tmp & 0x10)
 917                         rinfo->dviDisp_type = MT_CTV;
 918                 else if (tmp & 0x20)
 919                         rinfo->dviDisp_type = MT_STV;
 920
 921                 /* secondary CRT port */
 922                 if (tmp & 0x2)
 923                         rinfo->crtDisp_type = MT_CRT;
 924                 else if (tmp & 0x800)
 925                         rinfo->crtDisp_type = MT_DFP;
 926                 else if (tmp & 0x400)
 927                         rinfo->crtDisp_type = MT_LCD;
 928                 else if (tmp & 0x1000)
 929                         rinfo->crtDisp_type = MT_CTV;
 930                 else if (tmp & 0x2000)
 931                         rinfo->crtDisp_type = MT_STV;
 932         } else {
 933                 rinfo->dviDisp_type = MT_NONE;
 934
 935                 tmp = INREG(FP_GEN_CNTL);
 936
 937                 if (tmp & FP_EN_TMDS)
 938                         rinfo->crtDisp_type = MT_DFP;
 939                 else
 940                         rinfo->crtDisp_type = MT_CRT;
 941         }
 942 }
 943
 944
 945
 946 static void radeon_get_EDID(struct radeonfb_info *rinfo)
 947 {
 948 #ifdef CONFIG_PPC_OF
 949         if (!radeon_get_EDID_OF(rinfo))
 950                 RTRACE("radeonfb: could not retrieve EDID from OF\n");
 951 #else
 952         /* XXX use other methods later */
 953 #endif
 954 }
 955
 956
 957 #ifdef CONFIG_PPC_OF
 958 static int radeon_get_EDID_OF(struct radeonfb_info *rinfo)
 959 {
 960         struct device_node *dp;
 961         unsigned char *pedid = NULL;
 962         static char *propnames[] = { "DFP,EDID", "LCD,EDID", "EDID", "EDID1", NULL };
 963         int i;
 964
 965         dp = pci_device_to_OF_node(rinfo->pdev);
 966         while (dp != NULL) {
 967                 for (i = 0; propnames[i] != NULL; ++i) {
 968                         pedid = (unsigned char *)
 969                                 get_property(dp, propnames[i], NULL);
 970                         if (pedid != NULL) {
 971                                 rinfo->EDID = pedid;
 972                                 return 1;
 973                         }
 974                 }
 975                 dp = dp->child;
 976         }
 977         return 0;
 978 }
 979 #endif /* CONFIG_PPC_OF */
 980
 981
 982 static int radeon_dfp_parse_EDID(struct radeonfb_info *rinfo)
 983 {
 984         unsigned char *block = rinfo->EDID;
 985
 986         if (!block)
 987                 return 0;
 988
 989         /* jump to the detailed timing block section */
 990         block += 54;
 991
 992         rinfo->clock = (block[0] + (block[1] << 8));
 993         rinfo->panel_xres = (block[2] + ((block[4] & 0xf0) << 4));
 994         rinfo->hblank = (block[3] + ((block[4] & 0x0f) << 8));
 995         rinfo->panel_yres = (block[5] + ((block[7] & 0xf0) << 4));
 996         rinfo->vblank = (block[6] + ((block[7] & 0x0f) << 8));
 997         rinfo->hOver_plus = (block[8] + ((block[11] & 0xc0) << 2));
 998         rinfo->hSync_width = (block[9] + ((block[11] & 0x30) << 4));
 999         rinfo->vOver_plus = ((block[10] >> 4) + ((block[11] & 0x0c) << 2));
1000         rinfo->vSync_width = ((block[10] & 0x0f) + ((block[11] & 0x03) << 4));
1001         rinfo->interlaced = ((block[17] & 0x80) >> 7);
1002         rinfo->synct = ((block[17] & 0x18) >> 3);
1003         rinfo->misc = ((block[17] & 0x06) >> 1);
1004         rinfo->hAct_high = rinfo->vAct_high = 0;
1005         if (rinfo->synct == 3) {
1006                 if (rinfo->misc & 2)
1007                         rinfo->hAct_high = 1;
1008                 if (rinfo->misc & 1)
1009                         rinfo->vAct_high = 1;
1010         }
1011
1012         printk("radeonfb: detected DFP panel size from EDID: %dx%d\n",
1013                 rinfo->panel_xres, rinfo->panel_yres);
1014
1015         rinfo->got_dfpinfo = 1;
1016
1017         return 1;
1018 }
1019
1020
1021 static void radeon_update_default_var(struct radeonfb_info *rinfo)
1022 {
1023         struct fb_var_screeninfo *var = &radeonfb_default_var;
1024
1025         var->xres = rinfo->panel_xres;
1026         var->yres = rinfo->panel_yres;
1027         var->xres_virtual = rinfo->panel_xres;
1028         var->yres_virtual = rinfo->panel_yres;
1029         var->xoffset = var->yoffset = 0;
1030         var->bits_per_pixel = 8;
1031         var->pixclock = 100000000 / rinfo->clock;
1032         var->left_margin = (rinfo->hblank - rinfo->hOver_plus - rinfo->hSync_width);
1033         var->right_margin = rinfo->hOver_plus;
1034         var->upper_margin = (rinfo->vblank - rinfo->vOver_plus - rinfo->vSync_width);
1035         var->lower_margin = rinfo->vOver_plus;
1036         var->hsync_len = rinfo->hSync_width;
1037         var->vsync_len = rinfo->vSync_width;
1038         var->sync = 0;
1039         if (rinfo->synct == 3) {
1040                 if (rinfo->hAct_high)
1041                         var->sync |= FB_SYNC_HOR_HIGH_ACT;
1042                 if (rinfo->vAct_high)
1043                         var->sync |= FB_SYNC_VERT_HIGH_ACT;
1044         }
1045
1046         var->vmode = 0;
1047         if (rinfo->interlaced)
1048                 var->vmode |= FB_VMODE_INTERLACED;
1049
1050         rinfo->use_default_var = 1;
1051 }
1052
1053
1054 static int radeon_get_dfpinfo_BIOS(struct radeonfb_info *rinfo)
1055 {
1056         char __iomem *fpbiosstart, *tmp, *tmp0;
1057         char stmp[30];
1058         int i;
1059
1060         if (!rinfo->bios_seg)
1061                 return 0;
1062
1063         if (!(fpbiosstart = rinfo->bios_seg + readw(rinfo->bios_seg + 0x48))) {
1064                 printk("radeonfb: Failed to detect DFP panel info using BIOS\n");
1065                 return 0;
1066         }
1067
1068         if (!(tmp = rinfo->bios_seg + readw(fpbiosstart + 0x40))) {
1069                 printk("radeonfb: Failed to detect DFP panel info using BIOS\n");
1070                 return 0;
1071         }
1072
1073         for(i=0; i<24; i++)
1074                 stmp[i] = readb(tmp+i+1);
1075         stmp[24] = 0;
1076         printk("radeonfb: panel ID string: %s\n", stmp);
1077         rinfo->panel_xres = readw(tmp + 25);
1078         rinfo->panel_yres = readw(tmp + 27);
1079         printk("radeonfb: detected DFP panel size from BIOS: %dx%d\n",
1080                 rinfo->panel_xres, rinfo->panel_yres);
1081
1082         for(i=0; i<32; i++) {
1083                 tmp0 = rinfo->bios_seg + readw(tmp+64+i*2);
1084                 if (tmp0 == 0)
1085                         break;
1086                 if ((readw(tmp0) == rinfo->panel_xres) &&
1087                     (readw(tmp0+2) == rinfo->panel_yres)) {
1088                         rinfo->hblank = (readw(tmp0+17) - readw(tmp0+19)) * 8;
1089                         rinfo->hOver_plus = ((readw(tmp0+21) - readw(tmp0+19) -1) * 8) & 0x7fff;
1090                         rinfo->hSync_width = readb(tmp0+23) * 8;
1091                         rinfo->vblank = readw(tmp0+24) - readw(tmp0+26);
1092                         rinfo->vOver_plus = (readw(tmp0+28) & 0x7ff) - readw(tmp0+26);
1093                         rinfo->vSync_width = (readw(tmp0+28) & 0xf800) >> 11;
1094                         rinfo->clock = readw(tmp0+9);
1095
1096                         rinfo->got_dfpinfo = 1;
1097                         return 1;
1098                 }
1099         }
1100
1101         return 0;
1102 }
1103
1104
1105
1106 static int radeon_get_dfpinfo (struct radeonfb_info *rinfo)
1107 {
1108         unsigned int tmp;
1109         unsigned short a, b;
1110
1111         if (radeon_get_dfpinfo_BIOS(rinfo))
1112                 radeon_update_default_var(rinfo);
1113
1114         if (radeon_dfp_parse_EDID(rinfo))
1115                 radeon_update_default_var(rinfo);
1116
1117         if (!rinfo->got_dfpinfo) {
1118                 /*
1119                  * it seems all else has failed now and we
1120                  * resort to probing registers for our DFP info
1121                  */
1122                 if (panel_yres) {
1123                         rinfo->panel_yres = panel_yres;
1124                 } else {
1125                         tmp = INREG(FP_VERT_STRETCH);
1126                         tmp &= 0x00fff000;
1127                         rinfo->panel_yres = (unsigned short)(tmp >> 0x0c) + 1;
1128                 }
1129
1130                 switch (rinfo->panel_yres) {
1131                         case 480:
1132                                 rinfo->panel_xres = 640;
1133                                 break;
1134                         case 600:
1135                                 rinfo->panel_xres = 800;
1136                                 break;
1137                         case 768:
1138 #if defined(__powerpc__)
1139                                 if (rinfo->dviDisp_type == MT_LCD)
1140                                         rinfo->panel_xres = 1152;
1141                                 else
1142 #endif
1143                                 rinfo->panel_xres = 1024;
1144                                 break;
1145                         case 1024:
1146                                 rinfo->panel_xres = 1280;
1147                                 break;
1148                         case 1050:
1149                                 rinfo->panel_xres = 1400;
1150                                 break;
1151                         case 1200:
1152                                 rinfo->panel_xres = 1600;
1153                                 break;
1154                         default:
1155                                 printk("radeonfb: Failed to detect DFP panel size\n");
1156                                 return 0;
1157                 }
1158
1159                 printk("radeonfb: detected DFP panel size from registers: %dx%d\n",
1160                         rinfo->panel_xres, rinfo->panel_yres);
1161
1162                 tmp = INREG(FP_CRTC_H_TOTAL_DISP);
1163                 a = (tmp & FP_CRTC_H_TOTAL_MASK) + 4;
1164                 b = (tmp & 0x01ff0000) >> FP_CRTC_H_DISP_SHIFT;
1165                 rinfo->hblank = (a - b + 1) * 8;
1166
1167                 tmp = INREG(FP_H_SYNC_STRT_WID);
1168                 rinfo->hOver_plus = (unsigned short) ((tmp & FP_H_SYNC_STRT_CHAR_MASK) >>
1169                                         FP_H_SYNC_STRT_CHAR_SHIFT) - b - 1;
1170                 rinfo->hOver_plus *= 8;
1171                 rinfo->hSync_width = (unsigned short) ((tmp & FP_H_SYNC_WID_MASK) >>
1172                                         FP_H_SYNC_WID_SHIFT);
1173                 rinfo->hSync_width *= 8;
1174                 tmp = INREG(FP_CRTC_V_TOTAL_DISP);
1175                 a = (tmp & FP_CRTC_V_TOTAL_MASK) + 1;
1176                 b = (tmp & FP_CRTC_V_DISP_MASK) >> FP_CRTC_V_DISP_SHIFT;
1177                 rinfo->vblank = a - b /* + 24 */ ;
1178
1179                 tmp = INREG(FP_V_SYNC_STRT_WID);
1180                 rinfo->vOver_plus = (unsigned short) (tmp & FP_V_SYNC_STRT_MASK)
1181                                         - b + 1;
1182                 rinfo->vSync_width = (unsigned short) ((tmp & FP_V_SYNC_WID_MASK) >>
1183                                         FP_V_SYNC_WID_SHIFT);
1184
1185                 return 1;
1186         }
1187
1188         return 1;
1189 }
1190
1191
1192 #ifdef CONFIG_PPC_OF
1193 static int radeon_read_OF (struct radeonfb_info *rinfo)
1194 {
1195         struct device_node *dp;
1196         unsigned int *xtal;
1197
1198         dp = pci_device_to_OF_node(rinfo->pdev);
1199
1200         xtal = (unsigned int *) get_property(dp, "ATY,RefCLK", NULL);
1201
1202         rinfo->pll.ref_clk = *xtal / 10;
1203
1204         if (*xtal)
1205                 return 1;
1206         else
1207                 return 0;
1208 }
1209 #endif
1210
1211
1212 static void radeon_engine_init (struct radeonfb_info *rinfo)
1213 {
1214         u32 temp;
1215
1216         /* disable 3D engine */
1217         OUTREG(RB3D_CNTL, 0);
1218
1219         radeon_engine_reset ();
1220
1221         radeon_fifo_wait (1);
1222         OUTREG(RB2D_DSTCACHE_MODE, 0);
1223
1224         radeon_fifo_wait (1);
1225         temp = INREG(DEFAULT_PITCH_OFFSET);
1226         OUTREG(DEFAULT_PITCH_OFFSET, ((temp & 0xc0000000) |
1227                                       (rinfo->pitch << 0x16)));
1228
1229         radeon_fifo_wait (1);
1230         OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN);
1231
1232         radeon_fifo_wait (1);
1233         OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX |
1234                                          DEFAULT_SC_BOTTOM_MAX));
1235
1236         temp = radeon_get_dstbpp(rinfo->depth);
1237         rinfo->dp_gui_master_cntl = ((temp << 8) | GMC_CLR_CMP_CNTL_DIS);
1238         radeon_fifo_wait (1);
1239         OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl |
1240                                     GMC_BRUSH_SOLID_COLOR |
1241                                     GMC_SRC_DATATYPE_COLOR));
1242
1243         radeon_fifo_wait (7);
1244
1245         /* clear line drawing regs */
1246         OUTREG(DST_LINE_START, 0);
1247         OUTREG(DST_LINE_END, 0);
1248
1249         /* set brush color regs */
1250         OUTREG(DP_BRUSH_FRGD_CLR, 0xffffffff);
1251         OUTREG(DP_BRUSH_BKGD_CLR, 0x00000000);
1252
1253         /* set source color regs */
1254         OUTREG(DP_SRC_FRGD_CLR, 0xffffffff);
1255         OUTREG(DP_SRC_BKGD_CLR, 0x00000000);
1256
1257         /* default write mask */
1258         OUTREG(DP_WRITE_MSK, 0xffffffff);
1259
1260         radeon_engine_idle ();
1261 }
1262
1263
1264 static int __devinit radeon_init_disp (struct radeonfb_info *rinfo)
1265 {
1266         struct fb_info *info = &rinfo->info;
1267         struct fb_var_screeninfo var;
1268
1269         var = radeonfb_default_var;
1270         if ((radeon_init_disp_var(rinfo, &var)) < 0)
1271                 return -1;
1272
1273         rinfo->depth = var_to_depth(&var);
1274         rinfo->bpp = var.bits_per_pixel;
1275
1276         info->var = var;
1277         fb_alloc_cmap(&info->cmap, 256, 0);
1278
1279         var.activate = FB_ACTIVATE_NOW;
1280         return 0;
1281 }
1282
1283
1284 static int radeon_init_disp_var (struct radeonfb_info *rinfo,
1285                                  struct fb_var_screeninfo *var)
1286 {
1287 #ifndef MODULE
1288         if (mode_option)
1289                 fb_find_mode (var, &rinfo->info, mode_option,
1290                               NULL, 0, NULL, 8);
1291         else
1292 #endif
1293         if (rinfo->use_default_var)
1294                 /* We will use the modified default far */
1295                 *var = radeonfb_default_var;
1296         else
1297
1298                 fb_find_mode (var, &rinfo->info, "640x480-8@60",
1299                               NULL, 0, NULL, 0);
1300
1301         if (noaccel)
1302                 var->accel_flags &= ~FB_ACCELF_TEXT;
1303         else
1304                 var->accel_flags |= FB_ACCELF_TEXT;
1305
1306         return 0;
1307 }
1308
1309
1310 static int radeon_do_maximize(struct radeonfb_info *rinfo,
1311                                 struct fb_var_screeninfo *var,
1312                                 struct fb_var_screeninfo *v,
1313                                 int nom, int den)
1314 {
1315         static struct {
1316                 int xres, yres;
1317         } modes[] = {
1318                 {1600, 1280},
1319                 {1280, 1024},
1320                 {1024, 768},
1321                 {800, 600},
1322                 {640, 480},
1323                 {-1, -1}
1324         };
1325         int i;
1326
1327         /* use highest possible virtual resolution */
1328         if (v->xres_virtual == -1 && v->yres_virtual == -1) {
1329                 printk("radeonfb: using max available virtual resolution\n");
1330                 for (i=0; modes[i].xres != -1; i++) {
1331                         if (modes[i].xres * nom / den * modes[i].yres <
1332                             rinfo->video_ram / 2)
1333                                 break;
1334                 }
1335                 if (modes[i].xres == -1) {
1336                         printk("radeonfb: could not find virtual resolution that fits into video memory!\n");
1337                         return -EINVAL;
1338                 }
1339                 v->xres_virtual = modes[i].xres;
1340                 v->yres_virtual = modes[i].yres;
1341
1342                 printk("radeonfb: virtual resolution set to max of %dx%d\n",
1343                         v->xres_virtual, v->yres_virtual);
1344         } else if (v->xres_virtual == -1) {
1345                 v->xres_virtual = (rinfo->video_ram * den /
1346                                 (nom * v->yres_virtual * 2)) & ~15;
1347         } else if (v->yres_virtual == -1) {
1348                 v->xres_virtual = (v->xres_virtual + 15) & ~15;
1349                 v->yres_virtual = rinfo->video_ram * den /
1350                         (nom * v->xres_virtual *2);
1351         } else {
1352                 if (v->xres_virtual * nom / den * v->yres_virtual >
1353                         rinfo->video_ram) {
1354                         return -EINVAL;
1355                 }
1356         }
1357
1358         if (v->xres_virtual * nom / den >= 8192) {
1359                 v->xres_virtual = 8192 * den / nom - 16;
1360         }
1361
1362         if (v->xres_virtual < v->xres)
1363                 return -EINVAL;
1364
1365         if (v->yres_virtual < v->yres)
1366                 return -EINVAL;
1367
1368         return 0;
1369 }
1370
1371
1372 static int radeonfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info)
1373 {
1374         struct radeonfb_info *rinfo = (struct radeonfb_info *) info->par;
1375         struct fb_var_screeninfo v;
1376         int nom, den;
1377
1378         memcpy (&v, var, sizeof (v));
1379
1380         switch (v.bits_per_pixel) {
1381                 case 0 ... 8:
1382                         v.bits_per_pixel = 8;
1383                         break;
1384                 case 9 ... 16:
1385                         v.bits_per_pixel = 16;
1386                         break;
1387                 case 17 ... 24:
1388 #if 0 /* Doesn't seem to work */
1389                         v.bits_per_pixel = 24;
1390                         break;
1391 #endif
1392                         return -EINVAL;
1393                 case 25 ... 32:
1394                         v.bits_per_pixel = 32;
1395                         break;
1396                 default:
1397                         return -EINVAL;
1398         }
1399
1400         switch (var_to_depth(&v)) {
1401                 case 8:
1402                         nom = den = 1;
1403                         v.red.offset = v.green.offset = v.blue.offset = 0;
1404                         v.red.length = v.green.length = v.blue.length = 8;
1405                         v.transp.offset = v.transp.length = 0;
1406                         break;
1407                 case 15:
1408                         nom = 2;
1409                         den = 1;
1410                         v.red.offset = 10;
1411                         v.green.offset = 5;
1412                         v.blue.offset = 0;
1413                         v.red.length = v.green.length = v.blue.length = 5;
1414                         v.transp.offset = v.transp.length = 0;
1415                         break;
1416                 case 16:
1417                         nom = 2;
1418                         den = 1;
1419                         v.red.offset = 11;
1420                         v.green.offset = 5;
1421                         v.blue.offset = 0;
1422                         v.red.length = 5;
1423                         v.green.length = 6;
1424                         v.blue.length = 5;
1425                         v.transp.offset = v.transp.length = 0;
1426                         break;
1427                 case 24:
1428                         nom = 4;
1429                         den = 1;
1430                         v.red.offset = 16;
1431                         v.green.offset = 8;
1432                         v.blue.offset = 0;
1433                         v.red.length = v.blue.length = v.green.length = 8;
1434                         v.transp.offset = v.transp.length = 0;
1435                         break;
1436                 case 32:
1437                         nom = 4;
1438                         den = 1;
1439                         v.red.offset = 16;
1440                         v.green.offset = 8;
1441                         v.blue.offset = 0;
1442                         v.red.length = v.blue.length = v.green.length = 8;
1443                         v.transp.offset = 24;
1444                         v.transp.length = 8;
1445                         break;
1446                 default:
1447                         printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n",
1448                                 var->xres, var->yres, var->bits_per_pixel);
1449                         return -EINVAL;
1450         }
1451
1452         if (radeon_do_maximize(rinfo, var, &v, nom, den) < 0)
1453                 return -EINVAL;
1454
1455         if (v.xoffset < 0)
1456                 v.xoffset = 0;
1457         if (v.yoffset < 0)
1458                 v.yoffset = 0;
1459
1460         if (v.xoffset > v.xres_virtual - v.xres)
1461                 v.xoffset = v.xres_virtual - v.xres - 1;
1462
1463         if (v.yoffset > v.yres_virtual - v.yres)
1464                 v.yoffset = v.yres_virtual - v.yres - 1;
1465
1466         v.red.msb_right = v.green.msb_right = v.blue.msb_right =
1467                           v.transp.offset = v.transp.length =
1468                           v.transp.msb_right = 0;
1469
1470         if (noaccel)
1471                 v.accel_flags = 0;
1472
1473         memcpy(var, &v, sizeof(v));
1474
1475         return 0;
1476 }
1477
1478
1479 static int radeonfb_pan_display (struct fb_var_screeninfo *var,
1480                                  struct fb_info *info)
1481 {
1482         struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
1483
1484         if ((var->xoffset + var->xres > var->xres_virtual)
1485             || (var->yoffset + var->yres > var->yres_virtual))
1486                return -EINVAL;
1487
1488         if (rinfo->asleep)
1489                 return 0;
1490
1491         OUTREG(CRTC_OFFSET, ((var->yoffset * var->xres_virtual + var->xoffset)
1492                              * var->bits_per_pixel / 8) & ~7);
1493         return 0;
1494 }
1495
1496
1497 static int radeonfb_ioctl (struct inode *inode, struct file *file, unsigned int cmd,
1498                            unsigned long arg, struct fb_info *info)
1499 {
1500         struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
1501         unsigned int tmp;
1502         u32 value = 0;
1503         int rc;
1504
1505         switch (cmd) {
1506                 /*
1507                  * TODO:  set mirror accordingly for non-Mobility chipsets with 2 CRTC's
1508                  */
1509                 case FBIO_RADEON_SET_MIRROR:
1510                         switch (rinfo->arch) {
1511                                 case RADEON_R100:
1512                                 case RADEON_RV100:
1513                                 case RADEON_R200:
1514                                 case RADEON_RV200:
1515                                 case RADEON_RV250:
1516                                 case RADEON_R300:
1517                                         return -EINVAL;
1518                                 default:
1519                                         /* RADEON M6, RADEON_M7, RADEON_M9 */
1520                                         break;
1521                         }
1522
1523                         rc = get_user(value, (__u32 __user *)arg);
1524
1525                         if (rc)
1526                                 return rc;
1527
1528                         if (value & 0x01) {
1529                                 tmp = INREG(LVDS_GEN_CNTL);
1530
1531                                 tmp |= (LVDS_ON | LVDS_BLON);
1532                         } else {
1533                                 tmp = INREG(LVDS_GEN_CNTL);
1534
1535                                 tmp &= ~(LVDS_ON | LVDS_BLON);
1536                         }
1537
1538                         OUTREG(LVDS_GEN_CNTL, tmp);
1539
1540                         if (value & 0x02) {
1541                                 tmp = INREG(CRTC_EXT_CNTL);
1542                                 tmp |= CRTC_CRT_ON;
1543
1544                                 mirror = 1;
1545                         } else {
1546                                 tmp = INREG(CRTC_EXT_CNTL);
1547                                 tmp &= ~CRTC_CRT_ON;
1548
1549                                 mirror = 0;
1550                         }
1551
1552                         OUTREG(CRTC_EXT_CNTL, tmp);
1553
1554                         break;
1555                 case FBIO_RADEON_GET_MIRROR:
1556                         switch (rinfo->arch) {
1557                                 case RADEON_R100:
1558                                 case RADEON_RV100:
1559                                 case RADEON_R200:
1560                                 case RADEON_RV200:
1561                                 case RADEON_RV250:
1562                                 case RADEON_R300:
1563                                         return -EINVAL;
1564                                 default:
1565                                         /* RADEON M6, RADEON_M7, RADEON_M9 */
1566                                         break;
1567                         }
1568
1569                         tmp = INREG(LVDS_GEN_CNTL);
1570                         if ((LVDS_ON | LVDS_BLON) & tmp)
1571                                 value |= 0x01;
1572
1573                         tmp = INREG(CRTC_EXT_CNTL);
1574                         if (CRTC_CRT_ON & tmp)
1575                                 value |= 0x02;
1576
1577                         return put_user(value, (__u32 __user *)arg);
1578                 default:
1579                         return -EINVAL;
1580         }
1581
1582         return -EINVAL;
1583 }
1584
1585
1586 static int radeonfb_blank (int blank, struct fb_info *info)
1587 {
1588         struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
1589         u32 val = INREG(CRTC_EXT_CNTL);
1590         u32 val2 = INREG(LVDS_GEN_CNTL);
1591
1592         if (rinfo->asleep)
1593                 return 0;
1594
1595 #ifdef CONFIG_PMAC_BACKLIGHT
1596         if (rinfo->dviDisp_type == MT_LCD && _machine == _MACH_Pmac) {
1597                 set_backlight_enable(!blank);
1598                 return 0;
1599         }
1600 #endif
1601
1602         /* reset it */
1603         val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
1604                  CRTC_VSYNC_DIS);
1605         val2 &= ~(LVDS_DISPLAY_DIS);
1606
1607         switch (blank) {
1608                 case FB_BLANK_UNBLANK:
1609                 case FB_BLANK_NORMAL:
1610                         break;
1611                 case FB_BLANK_VSYNC_SUSPEND:
1612                         val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS);
1613                         break;
1614                 case FB_BLANK_HSYNC_SUSPEND:
1615                         val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS);
1616                         break;
1617                 case FB_BLANK_POWERDOWN:
1618                         val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS |
1619                                 CRTC_HSYNC_DIS);
1620                         val2 |= (LVDS_DISPLAY_DIS);
1621                         break;
1622         }
1623
1624         switch (rinfo->dviDisp_type) {
1625                 case MT_LCD:
1626                         OUTREG(LVDS_GEN_CNTL, val2);
1627                         break;
1628                 case MT_CRT:
1629                 default:
1630                         OUTREG(CRTC_EXT_CNTL, val);
1631                         break;
1632         }
1633
1634         /* let fbcon do a soft blank for us */
1635         return (blank == FB_BLANK_NORMAL) ? 1 : 0;
1636 }
1637
1638
1639 static int radeonfb_setcolreg (unsigned regno, unsigned red, unsigned green,
1640                              unsigned blue, unsigned transp, struct fb_info *info)
1641 {
1642         struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
1643         u32 pindex, vclk_cntl;
1644         unsigned int i;
1645
1646         if (regno > 255)
1647                 return 1;
1648
1649         red >>= 8;
1650         green >>= 8;
1651         blue >>= 8;
1652         rinfo->palette[regno].red = red;
1653         rinfo->palette[regno].green = green;
1654         rinfo->palette[regno].blue = blue;
1655
1656         /* default */
1657         pindex = regno;
1658
1659         if (!rinfo->asleep) {
1660                 vclk_cntl = INPLL(VCLK_ECP_CNTL);
1661                 OUTPLL(VCLK_ECP_CNTL, vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1662
1663                 if (rinfo->bpp == 16) {
1664                         pindex = regno * 8;
1665
1666                         if (rinfo->depth == 16 && regno > 63)
1667                                 return 1;
1668                         if (rinfo->depth == 15 && regno > 31)
1669                                 return 1;
1670
1671                         /* For 565, the green component is mixed one order below */
1672                         if (rinfo->depth == 16) {
1673                                 OUTREG(PALETTE_INDEX, pindex>>1);
1674                                 OUTREG(PALETTE_DATA, (rinfo->palette[regno>>1].red << 16) |
1675                                         (green << 8) | (rinfo->palette[regno>>1].blue));
1676                                 green = rinfo->palette[regno<<1].green;
1677                         }
1678                 }
1679
1680                 if (rinfo->depth != 16 || regno < 32) {
1681                         OUTREG(PALETTE_INDEX, pindex);
1682                         OUTREG(PALETTE_DATA, (red << 16) | (green << 8) | blue);
1683                 }
1684
1685                 OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1686         }
1687         if (regno < 16) {
1688                 switch (rinfo->depth) {
1689                 case 15:
1690                         ((u16 *) (info->pseudo_palette))[regno] =
1691                             (regno << 10) | (regno << 5) | regno;
1692                         break;
1693                 case 16:
1694                         ((u16 *) (info->pseudo_palette))[regno] =
1695                             (regno << 11) | (regno << 6) | regno;
1696                         break;
1697                 case 24:
1698                         ((u32 *) (info->pseudo_palette))[regno] =
1699                             (regno << 16) | (regno << 8) | regno;
1700                         break;
1701                 case 32:
1702                         i = (regno << 8) | regno;
1703                         ((u32 *) (info->pseudo_palette))[regno] =
1704                             (i << 16) | i;
1705                         break;
1706                 }
1707         }
1708         return 0;
1709 }
1710
1711
1712
1713 static void radeon_save_state (struct radeonfb_info *rinfo,
1714                                struct radeon_regs *save)
1715 {
1716         /* CRTC regs */
1717         save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1718         save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1719         save->dac_cntl = INREG(DAC_CNTL);
1720         save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP);
1721         save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID);
1722         save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP);
1723         save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID);
1724         save->crtc_pitch = INREG(CRTC_PITCH);
1725 #if defined(__BIG_ENDIAN)
1726         save->surface_cntl = INREG(SURFACE_CNTL);
1727 #endif
1728
1729         /* FP regs */
1730         save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP);
1731         save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP);
1732         save->fp_gen_cntl = INREG(FP_GEN_CNTL);
1733         save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID);
1734         save->fp_horz_stretch = INREG(FP_HORZ_STRETCH);
1735         save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID);
1736         save->fp_vert_stretch = INREG(FP_VERT_STRETCH);
1737         save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
1738         save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL);
1739         save->tmds_crc = INREG(TMDS_CRC);
1740         save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL);
1741         save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL);
1742 }
1743
1744
1745
1746 static int radeonfb_set_par (struct fb_info *info)
1747 {
1748         struct radeonfb_info *rinfo = (struct radeonfb_info *)info->par;
1749         struct fb_var_screeninfo *mode = &info->var;
1750         struct radeon_regs newmode;
1751         int hTotal, vTotal, hSyncStart, hSyncEnd,
1752             hSyncPol, vSyncStart, vSyncEnd, vSyncPol, cSync;
1753         u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5};
1754         u8 hsync_fudge_fp[] = {2, 2, 0, 0, 5, 5};
1755         u32 dotClock = 1000000000 / mode->pixclock,
1756             sync, h_sync_pol, v_sync_pol;
1757         int freq = dotClock / 10;  /* x 100 */
1758         int xclk_freq, vclk_freq, xclk_per_trans, xclk_per_trans_precise;
1759         int useable_precision, roff, ron;
1760         int min_bits, format = 0;
1761         int hsync_start, hsync_fudge, bytpp, hsync_wid, vsync_wid;
1762         int primary_mon = PRIMARY_MONITOR(rinfo);
1763         int depth = var_to_depth(mode);
1764         int accel = (mode->accel_flags & FB_ACCELF_TEXT) != 0;
1765
1766         rinfo->xres = mode->xres;
1767         rinfo->yres = mode->yres;
1768         rinfo->xres_virtual = mode->xres_virtual;
1769         rinfo->yres_virtual = mode->yres_virtual;
1770         rinfo->pixclock = mode->pixclock;
1771
1772         hSyncStart = mode->xres + mode->right_margin;
1773         hSyncEnd = hSyncStart + mode->hsync_len;
1774         hTotal = hSyncEnd + mode->left_margin;
1775
1776         vSyncStart = mode->yres + mode->lower_margin;
1777         vSyncEnd = vSyncStart + mode->vsync_len;
1778         vTotal = vSyncEnd + mode->upper_margin;
1779
1780         if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1781                 if (rinfo->panel_xres < mode->xres)
1782                         rinfo->xres = mode->xres = rinfo->panel_xres;
1783                 if (rinfo->panel_yres < mode->yres)
1784                         rinfo->yres = mode->yres = rinfo->panel_yres;
1785
1786                 hTotal = mode->xres + rinfo->hblank;
1787                 hSyncStart = mode->xres + rinfo->hOver_plus;
1788                 hSyncEnd = hSyncStart + rinfo->hSync_width;
1789
1790                 vTotal = mode->yres + rinfo->vblank;
1791                 vSyncStart = mode->yres + rinfo->vOver_plus;
1792                 vSyncEnd = vSyncStart + rinfo->vSync_width;
1793         }
1794
1795         sync = mode->sync;
1796         h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1797         v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1798
1799         RTRACE("hStart = %d, hEnd = %d, hTotal = %d\n",
1800                 hSyncStart, hSyncEnd, hTotal);
1801         RTRACE("vStart = %d, vEnd = %d, vTotal = %d\n",
1802                 vSyncStart, vSyncEnd, vTotal);
1803
1804         hsync_wid = (hSyncEnd - hSyncStart) / 8;
1805         vsync_wid = vSyncEnd - vSyncStart;
1806         if (hsync_wid == 0)
1807                 hsync_wid = 1;
1808         else if (hsync_wid > 0x3f)      /* max */
1809                 hsync_wid = 0x3f;
1810
1811         if (vsync_wid == 0)
1812                 vsync_wid = 1;
1813         else if (vsync_wid > 0x1f)      /* max */
1814                 vsync_wid = 0x1f;
1815
1816         hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1817         vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1818
1819         cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
1820
1821         format = radeon_get_dstbpp(depth);
1822         bytpp = mode->bits_per_pixel >> 3;
1823
1824         if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD))
1825                 hsync_fudge = hsync_fudge_fp[format-1];
1826         else
1827                 hsync_fudge = hsync_adj_tab[format-1];
1828
1829         hsync_start = hSyncStart - 8 + hsync_fudge;
1830
1831         newmode.crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN |
1832                                 (format << 8);
1833
1834         if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1835                 newmode.crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN;
1836                 if (mirror)
1837                         newmode.crtc_ext_cntl |= CRTC_CRT_ON;
1838
1839                 newmode.crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN |
1840                                            CRTC_INTERLACE_EN);
1841         } else {
1842                 newmode.crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN |
1843                                         CRTC_CRT_ON;
1844         }
1845
1846         newmode.dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN |
1847                            DAC_8BIT_EN;
1848
1849         newmode.crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) |
1850                                      (((mode->xres / 8) - 1) << 16));
1851
1852         newmode.crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
1853                                         (hsync_wid << 16) | (h_sync_pol << 23));
1854
1855         newmode.crtc_v_total_disp = ((vTotal - 1) & 0xffff) |
1856                                     ((mode->yres - 1) << 16);
1857
1858         newmode.crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) |
1859                                          (vsync_wid << 16) | (v_sync_pol  << 23));
1860
1861         if (accel) {
1862                 /* We first calculate the engine pitch */
1863                 rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
1864                                 & ~(0x3f)) >> 6;
1865
1866                 /* Then, re-multiply it to get the CRTC pitch */
1867                 newmode.crtc_pitch = (rinfo->pitch << 3) / ((mode->bits_per_pixel + 1) / 8);
1868         } else
1869                 newmode.crtc_pitch = (mode->xres_virtual >> 3);
1870         newmode.crtc_pitch |= (newmode.crtc_pitch << 16);
1871
1872 #if defined(__BIG_ENDIAN)
1873         /*
1874          * It looks like recent chips have a problem with SURFACE_CNTL,
1875          * setting SURF_TRANSLATION_DIS completely disables the
1876          * swapper as well, so we leave it unset now.
1877          */
1878         newmode.surface_cntl = 0;
1879
1880         /* Setup swapping on both apertures, though we currently
1881          * only use aperture 0, enabling swapper on aperture 1
1882          * won't harm
1883          */
1884         switch (mode->bits_per_pixel) {
1885                 case 16:
1886                         newmode.surface_cntl |= NONSURF_AP0_SWP_16BPP;
1887                         newmode.surface_cntl |= NONSURF_AP1_SWP_16BPP;
1888                         break;
1889                 case 24:
1890                 case 32:
1891                         newmode.surface_cntl |= NONSURF_AP0_SWP_32BPP;
1892                         newmode.surface_cntl |= NONSURF_AP1_SWP_32BPP;
1893                         break;
1894         }
1895 #endif
1896
1897         rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
1898                         & ~(0x3f)) / 64;
1899
1900         RTRACE("h_total_disp = 0x%x\t   hsync_strt_wid = 0x%x\n",
1901                 newmode.crtc_h_total_disp, newmode.crtc_h_sync_strt_wid);
1902         RTRACE("v_total_disp = 0x%x\t   vsync_strt_wid = 0x%x\n",
1903                 newmode.crtc_v_total_disp, newmode.crtc_v_sync_strt_wid);
1904
1905         newmode.xres = mode->xres;
1906         newmode.yres = mode->yres;
1907
1908         rinfo->bpp = mode->bits_per_pixel;
1909         rinfo->depth = depth;
1910
1911         if (freq > rinfo->pll.ppll_max)
1912                 freq = rinfo->pll.ppll_max;
1913         if (freq*12 < rinfo->pll.ppll_min)
1914                 freq = rinfo->pll.ppll_min / 12;
1915
1916         {
1917                 struct {
1918                         int divider;
1919                         int bitvalue;
1920                 } *post_div,
1921                   post_divs[] = {
1922                         { 1,  0 },
1923                         { 2,  1 },
1924                         { 4,  2 },
1925                         { 8,  3 },
1926                         { 3,  4 },
1927                         { 16, 5 },
1928                         { 6,  6 },
1929                         { 12, 7 },
1930                         { 0,  0 },
1931                 };
1932
1933                 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
1934                         rinfo->pll_output_freq = post_div->divider * freq;
1935                         if (rinfo->pll_output_freq >= rinfo->pll.ppll_min  &&
1936                             rinfo->pll_output_freq <= rinfo->pll.ppll_max)
1937                                 break;
1938                 }
1939
1940                 rinfo->post_div = post_div->divider;
1941                 rinfo->fb_div = round_div(rinfo->pll.ref_div*rinfo->pll_output_freq,
1942                                           rinfo->pll.ref_clk);
1943                 newmode.ppll_ref_div = rinfo->pll.ref_div;
1944                 newmode.ppll_div_3 = rinfo->fb_div | (post_div->bitvalue << 16);
1945         }
1946         newmode.vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl;
1947
1948 #ifdef CONFIG_PPC_OF
1949         /* Gross hack for iBook with M7 until I find out a proper fix */
1950         if (machine_is_compatible("PowerBook4,3") && rinfo->arch == RADEON_M7)
1951                 newmode.ppll_div_3 = 0x000600ad;
1952 #endif /* CONFIG_PPC_OF */
1953
1954         RTRACE("post div = 0x%x\n", rinfo->post_div);
1955         RTRACE("fb_div = 0x%x\n", rinfo->fb_div);
1956         RTRACE("ppll_div_3 = 0x%x\n", newmode.ppll_div_3);
1957
1958         /* DDA */
1959         vclk_freq = round_div(rinfo->pll.ref_clk * rinfo->fb_div,
1960                               rinfo->pll.ref_div * rinfo->post_div);
1961         xclk_freq = rinfo->pll.xclk;
1962
1963         xclk_per_trans = round_div(xclk_freq * 128, vclk_freq * mode->bits_per_pixel);
1964
1965         min_bits = min_bits_req(xclk_per_trans);
1966         useable_precision = min_bits + 1;
1967
1968         xclk_per_trans_precise = round_div((xclk_freq * 128) << (11 - useable_precision),
1969                                            vclk_freq * mode->bits_per_pixel);
1970
1971         ron = (4 * rinfo->ram.mb + 3 * _max(rinfo->ram.trcd - 2, 0) +
1972                2 * rinfo->ram.trp + rinfo->ram.twr + rinfo->ram.cl + rinfo->ram.tr2w +
1973                xclk_per_trans) << (11 - useable_precision);
1974         roff = xclk_per_trans_precise * (32 - 4);
1975
1976         RTRACE("ron = %d, roff = %d\n", ron, roff);
1977         RTRACE("vclk_freq = %d, per = %d\n", vclk_freq, xclk_per_trans_precise);
1978
1979         if ((ron + rinfo->ram.rloop) >= roff) {
1980                 printk("radeonfb: error ron out of range\n");
1981                 return -EINVAL;
1982         }
1983
1984         newmode.dda_config = (xclk_per_trans_precise |
1985                               (useable_precision << 16) |
1986                               (rinfo->ram.rloop << 20));
1987         newmode.dda_on_off = (ron << 16) | roff;
1988
1989         if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1990                 unsigned int hRatio, vRatio;
1991
1992                 /* We force the pixel clock to be always enabled. Allowing it
1993                  * to be power managed during blanking would save power, but has
1994                  * nasty interactions with the 2D engine & sleep code that haven't
1995                  * been solved yet. --BenH
1996                  */
1997                 newmode.vclk_ecp_cntl &= ~PIXCLK_DAC_ALWAYS_ONb;
1998
1999                 if (mode->xres > rinfo->panel_xres)
2000                         mode->xres = rinfo->panel_xres;
2001                 if (mode->yres > rinfo->panel_yres)
2002                         mode->yres = rinfo->panel_yres;
2003
2004                 newmode.fp_horz_stretch = (((rinfo->panel_xres / 8) - 1)
2005                                            << HORZ_PANEL_SHIFT);
2006                 newmode.fp_vert_stretch = ((rinfo->panel_yres - 1)
2007                                            << VERT_PANEL_SHIFT);
2008
2009                 if (mode->xres != rinfo->panel_xres) {
2010                         hRatio = round_div(mode->xres * HORZ_STRETCH_RATIO_MAX,
2011                                            rinfo->panel_xres);
2012                         newmode.fp_horz_stretch = (((((unsigned long)hRatio) & HORZ_STRETCH_RATIO_MASK)) |
2013                                                    (newmode.fp_horz_stretch &
2014                                                     (HORZ_PANEL_SIZE | HORZ_FP_LOOP_STRETCH |
2015                                                      HORZ_AUTO_RATIO_INC)));
2016                         newmode.fp_horz_stretch |= (HORZ_STRETCH_BLEND |
2017                                                     HORZ_STRETCH_ENABLE);
2018                 }
2019                 newmode.fp_horz_stretch &= ~HORZ_AUTO_RATIO;
2020
2021                 if (mode->yres != rinfo->panel_yres) {
2022                         vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX,
2023                                            rinfo->panel_yres);
2024                         newmode.fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) |
2025                                                    (newmode.fp_vert_stretch &
2026                                                    (VERT_PANEL_SIZE | VERT_STRETCH_RESERVED)));
2027                         newmode.fp_vert_stretch |= (VERT_STRETCH_BLEND |
2028                                                     VERT_STRETCH_ENABLE);
2029                 }
2030                 newmode.fp_vert_stretch &= ~VERT_AUTO_RATIO_EN;
2031
2032                 newmode.fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32)
2033                                        ~(FP_SEL_CRTC2 |
2034                                          FP_RMX_HVSYNC_CONTROL_EN |
2035                                          FP_DFP_SYNC_SEL |
2036                                          FP_CRT_SYNC_SEL |
2037                                          FP_CRTC_LOCK_8DOT |
2038                                          FP_USE_SHADOW_EN |
2039                                          FP_CRTC_USE_SHADOW_VEND |
2040                                          FP_CRT_SYNC_ALT));
2041
2042                 newmode.fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR |
2043                                         FP_CRTC_DONT_SHADOW_HEND);
2044
2045                 newmode.lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl;
2046                 newmode.lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl;
2047                 newmode.tmds_crc = rinfo->init_state.tmds_crc;
2048                 newmode.tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl;
2049
2050                 if (primary_mon == MT_LCD) {
2051                         newmode.lvds_gen_cntl |= (LVDS_ON | LVDS_BLON);
2052                         newmode.fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN);
2053                 } else {
2054                         /* DFP */
2055                         newmode.fp_gen_cntl |= (FP_FPON | FP_TMDS_EN);
2056                         newmode.tmds_transmitter_cntl = (TMDS_RAN_PAT_RST |
2057                                                          TMDS_ICHCSEL | TMDS_PLL_EN) &
2058                                                          ~(TMDS_PLLRST);
2059                         newmode.crtc_ext_cntl &= ~CRTC_CRT_ON;
2060                 }
2061
2062                 newmode.fp_crtc_h_total_disp = (((rinfo->hblank / 8) & 0x3ff) |
2063                                 (((mode->xres / 8) - 1) << 16));
2064                 newmode.fp_crtc_v_total_disp = (rinfo->vblank & 0xffff) |
2065                                 ((mode->yres - 1) << 16);
2066                 newmode.fp_h_sync_strt_wid = ((rinfo->hOver_plus & 0x1fff) |
2067                                 (hsync_wid << 16) | (h_sync_pol << 23));
2068                 newmode.fp_v_sync_strt_wid = ((rinfo->vOver_plus & 0xfff) |
2069                                 (vsync_wid << 16) | (v_sync_pol  << 23));
2070         }
2071
2072         /* do it! */
2073         if (!rinfo->asleep) {
2074                 radeon_write_mode (rinfo, &newmode);
2075                 /* (re)initialize the engine */
2076                 if (noaccel)
2077                         radeon_engine_init (rinfo);
2078
2079         }
2080         /* Update fix */
2081         if (accel)
2082                 info->fix.line_length = rinfo->pitch*64;
2083         else
2084                 info->fix.line_length = mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8);
2085         info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
2086
2087 #ifdef CONFIG_BOOTX_TEXT
2088         /* Update debug text engine */
2089         btext_update_display(rinfo->fb_base_phys, mode->xres, mode->yres,
2090                              rinfo->depth, info->fix.line_length);
2091 #endif
2092
2093         return 0;
2094 }
2095
2096
2097 static void radeon_write_mode (struct radeonfb_info *rinfo,
2098                                struct radeon_regs *mode)
2099 {
2100         int i;
2101         int primary_mon = PRIMARY_MONITOR(rinfo);
2102
2103         radeonfb_blank(VESA_POWERDOWN, (struct fb_info *)rinfo);
2104
2105
2106         if (rinfo->arch == RADEON_M6) {
2107                 for (i=0; i<8; i++)
2108                         OUTREG(common_regs_m6[i].reg, common_regs_m6[i].val);
2109         } else {
2110                 for (i=0; i<9; i++)
2111                         OUTREG(common_regs[i].reg, common_regs[i].val);
2112         }
2113
2114         OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
2115         OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
2116                 CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS);
2117         OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
2118         OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
2119         OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
2120         OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
2121         OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
2122         OUTREG(CRTC_OFFSET, 0);
2123         OUTREG(CRTC_OFFSET_CNTL, 0);
2124         OUTREG(CRTC_PITCH, mode->crtc_pitch);
2125
2126 #if defined(__BIG_ENDIAN)
2127         OUTREG(SURFACE_CNTL, mode->surface_cntl);
2128 #endif
2129
2130         while ((INREG(CLOCK_CNTL_INDEX) & PPLL_DIV_SEL_MASK) !=
2131                PPLL_DIV_SEL_MASK) {
2132                 OUTREGP(CLOCK_CNTL_INDEX, PPLL_DIV_SEL_MASK, 0xffff);
2133         }
2134
2135         OUTPLLP(PPLL_CNTL, PPLL_RESET, 0xffff);
2136
2137         while ((INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK) !=
2138                (mode->ppll_ref_div & PPLL_REF_DIV_MASK)) {
2139                 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK);
2140         }
2141
2142         while ((INPLL(PPLL_DIV_3) & PPLL_FB3_DIV_MASK) !=
2143                (mode->ppll_div_3 & PPLL_FB3_DIV_MASK)) {
2144                 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK);
2145         }
2146
2147         while ((INPLL(PPLL_DIV_3) & PPLL_POST3_DIV_MASK) !=
2148                (mode->ppll_div_3 & PPLL_POST3_DIV_MASK)) {
2149                 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK);
2150         }
2151
2152         OUTPLL(HTOTAL_CNTL, 0);
2153
2154         OUTPLLP(PPLL_CNTL, 0, ~PPLL_RESET);
2155
2156 //      OUTREG(DDA_CONFIG, mode->dda_config);
2157 //      OUTREG(DDA_ON_OFF, mode->dda_on_off);
2158
2159         if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
2160                 OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);
2161                 OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);
2162                 OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);
2163                 OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid);
2164                 OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch);
2165                 OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch);
2166                 OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl);
2167                 OUTREG(TMDS_CRC, mode->tmds_crc);
2168                 OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl);
2169
2170                 if (primary_mon == MT_LCD) {
2171                         unsigned int tmp = INREG(LVDS_GEN_CNTL);
2172
2173                         mode->lvds_gen_cntl &= ~LVDS_STATE_MASK;
2174                         mode->lvds_gen_cntl |= (rinfo->init_state.lvds_gen_cntl & LVDS_STATE_MASK);
2175
2176                         if ((tmp & (LVDS_ON | LVDS_BLON)) ==
2177                             (mode->lvds_gen_cntl & (LVDS_ON | LVDS_BLON))) {
2178                                 OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl);
2179                         } else {
2180                                 if (mode->lvds_gen_cntl & (LVDS_ON | LVDS_BLON)) {
2181                                         udelay(1000);
2182                                         OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl);
2183                                 } else {
2184                                         OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl |
2185                                                LVDS_BLON);
2186                                         udelay(1000);
2187                                         OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl);
2188                                 }
2189                         }
2190                 }
2191         }
2192
2193         radeonfb_blank(VESA_NO_BLANKING, (struct fb_info *)rinfo);
2194
2195         OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl);
2196
2197         return;
2198 }
2199
2200 static struct fb_ops radeonfb_ops = {
2201         .owner                  = THIS_MODULE,
2202         .fb_check_var           = radeonfb_check_var,
2203         .fb_set_par             = radeonfb_set_par,
2204         .fb_setcolreg           = radeonfb_setcolreg,
2205         .fb_pan_display         = radeonfb_pan_display,
2206         .fb_blank               = radeonfb_blank,
2207         .fb_ioctl               = radeonfb_ioctl,
2208 #if 0
2209         .fb_fillrect    = radeonfb_fillrect,
2210         .fb_copyarea    = radeonfb_copyarea,
2211         .fb_imageblit   = radeonfb_imageblit,
2212         .fb_rasterimg   = radeonfb_rasterimg,
2213 #else
2214         .fb_fillrect    = cfb_fillrect,
2215         .fb_copyarea    = cfb_copyarea,
2216         .fb_imageblit   = cfb_imageblit,
2217 #endif
2218         .fb_cursor      = soft_cursor,
2219 };
2220
2221
2222 static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
2223 {
2224         struct fb_info *info;
2225
2226         info = &rinfo->info;
2227
2228         info->par = rinfo;
2229         info->pseudo_palette = rinfo->pseudo_palette;
2230         info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
2231         info->fbops = &radeonfb_ops;
2232         info->screen_base = rinfo->fb_base;
2233
2234         /* Fill fix common fields */
2235         strlcpy(info->fix.id, rinfo->name, sizeof(info->fix.id));
2236         info->fix.smem_start = rinfo->fb_base_phys;
2237         info->fix.smem_len = rinfo->video_ram;
2238         info->fix.type = FB_TYPE_PACKED_PIXELS;
2239         info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
2240         info->fix.xpanstep = 8;
2241         info->fix.ypanstep = 1;
2242         info->fix.ywrapstep = 0;
2243         info->fix.type_aux = 0;
2244         info->fix.mmio_start = rinfo->mmio_base_phys;
2245         info->fix.mmio_len = RADEON_REGSIZE;
2246         if (noaccel)
2247                 info->fix.accel = FB_ACCEL_NONE;
2248         else
2249                 info->fix.accel = FB_ACCEL_ATI_RADEON;
2250
2251         if (radeon_init_disp (rinfo) < 0)
2252                 return -1;
2253
2254         return 0;
2255 }
2256
2257
2258 #ifdef CONFIG_PMAC_BACKLIGHT
2259
2260 /* TODO: Dbl check these tables, we don't go up to full ON backlight
2261  * in these, possibly because we noticed MacOS doesn't, but I'd prefer
2262  * having some more official numbers from ATI
2263  */
2264 static int backlight_conv_m6[] = {
2265         0xff, 0xc0, 0xb5, 0xaa, 0x9f, 0x94, 0x89, 0x7e,
2266         0x73, 0x68, 0x5d, 0x52, 0x47, 0x3c, 0x31, 0x24
2267 };
2268 static int backlight_conv_m7[] = {
2269         0x00, 0x3f, 0x4a, 0x55, 0x60, 0x6b, 0x76, 0x81,
2270         0x8c, 0x97, 0xa2, 0xad, 0xb8, 0xc3, 0xce, 0xd9
2271 };
2272
2273 #define BACKLIGHT_LVDS_OFF
2274 #undef BACKLIGHT_DAC_OFF
2275
2276 /* We turn off the LCD completely instead of just dimming the backlight.
2277  * This provides some greater power saving and the display is useless
2278  * without backlight anyway.
2279  */
2280
2281 static int radeon_set_backlight_enable(int on, int level, void *data)
2282 {
2283         struct radeonfb_info *rinfo = (struct radeonfb_info *)data;
2284         unsigned int lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
2285         int* conv_table;
2286
2287         /* Pardon me for that hack... maybe some day we can figure
2288          * out in what direction backlight should work on a given
2289          * panel ?
2290          */
2291         if ((rinfo->arch == RADEON_M7 || rinfo->arch == RADEON_M9)
2292                 && !machine_is_compatible("PowerBook4,3"))
2293                 conv_table = backlight_conv_m7;
2294         else
2295                 conv_table = backlight_conv_m6;
2296
2297         lvds_gen_cntl |= (LVDS_BL_MOD_EN | LVDS_BLON);
2298         if (on && (level > BACKLIGHT_OFF)) {
2299                 lvds_gen_cntl |= LVDS_DIGON;
2300                 if (!(lvds_gen_cntl & LVDS_ON)) {
2301                         lvds_gen_cntl &= ~LVDS_BLON;
2302                         OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
2303                         (void)INREG(LVDS_GEN_CNTL);
2304                         mdelay(10);
2305                         lvds_gen_cntl |= LVDS_BLON;
2306                         OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
2307                 }
2308                 lvds_gen_cntl &= ~LVDS_BL_MOD_LEVEL_MASK;
2309                 lvds_gen_cntl |= (conv_table[level] <<
2310                                   LVDS_BL_MOD_LEVEL_SHIFT);
2311                 lvds_gen_cntl |= (LVDS_ON | LVDS_EN);
2312                 lvds_gen_cntl &= ~LVDS_DISPLAY_DIS;
2313         } else {
2314                 lvds_gen_cntl &= ~LVDS_BL_MOD_LEVEL_MASK;
2315                 lvds_gen_cntl |= (conv_table[0] <<
2316                                   LVDS_BL_MOD_LEVEL_SHIFT);
2317                 lvds_gen_cntl |= LVDS_DISPLAY_DIS;
2318                 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
2319                 udelay(10);
2320                 lvds_gen_cntl &= ~(LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGON);
2321         }
2322
2323         OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
2324         rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
2325         rinfo->init_state.lvds_gen_cntl |= (lvds_gen_cntl & LVDS_STATE_MASK);
2326
2327         return 0;
2328 }
2329
2330 static int radeon_set_backlight_level(int level, void *data)
2331 {
2332         return radeon_set_backlight_enable(1, level, data);
2333 }
2334 #endif /* CONFIG_PMAC_BACKLIGHT */
2335
2336
2337 #ifdef CONFIG_PMAC_PBOOK
2338
2339 static u32 dbg_clk;
2340
2341 /*
2342  * Radeon M6 Power Management code. This code currently only supports
2343  * the mobile chips, it's based from some informations provided by ATI
2344  * along with hours of tracing of MacOS drivers
2345  */
2346
2347 static void radeon_pm_save_regs(struct radeonfb_info *rinfo)
2348 {
2349         rinfo->save_regs[0] = INPLL(PLL_PWRMGT_CNTL);
2350         rinfo->save_regs[1] = INPLL(CLK_PWRMGT_CNTL);
2351         rinfo->save_regs[2] = INPLL(MCLK_CNTL);
2352         rinfo->save_regs[3] = INPLL(SCLK_CNTL);
2353         rinfo->save_regs[4] = INPLL(CLK_PIN_CNTL);
2354         rinfo->save_regs[5] = INPLL(VCLK_ECP_CNTL);
2355         rinfo->save_regs[6] = INPLL(PIXCLKS_CNTL);
2356         rinfo->save_regs[7] = INPLL(MCLK_MISC);
2357         rinfo->save_regs[8] = INPLL(P2PLL_CNTL);
2358
2359         rinfo->save_regs[9] = INREG(DISP_MISC_CNTL);
2360         rinfo->save_regs[10] = INREG(DISP_PWR_MAN);
2361         rinfo->save_regs[11] = INREG(LVDS_GEN_CNTL);
2362         rinfo->save_regs[12] = INREG(LVDS_PLL_CNTL);
2363         rinfo->save_regs[13] = INREG(TV_DAC_CNTL);
2364         rinfo->save_regs[14] = INREG(BUS_CNTL1);
2365         rinfo->save_regs[15] = INREG(CRTC_OFFSET_CNTL);
2366         rinfo->save_regs[16] = INREG(AGP_CNTL);
2367         rinfo->save_regs[17] = (INREG(CRTC_GEN_CNTL) & 0xfdffffff) | 0x04000000;
2368         rinfo->save_regs[18] = (INREG(CRTC2_GEN_CNTL) & 0xfdffffff) | 0x04000000;
2369         rinfo->save_regs[19] = INREG(GPIOPAD_A);
2370         rinfo->save_regs[20] = INREG(GPIOPAD_EN);
2371         rinfo->save_regs[21] = INREG(GPIOPAD_MASK);
2372         rinfo->save_regs[22] = INREG(ZV_LCDPAD_A);
2373         rinfo->save_regs[23] = INREG(ZV_LCDPAD_EN);
2374         rinfo->save_regs[24] = INREG(ZV_LCDPAD_MASK);
2375         rinfo->save_regs[25] = INREG(GPIO_VGA_DDC);
2376         rinfo->save_regs[26] = INREG(GPIO_DVI_DDC);
2377         rinfo->save_regs[27] = INREG(GPIO_MONID);
2378         rinfo->save_regs[28] = INREG(GPIO_CRT2_DDC);
2379
2380         rinfo->save_regs[29] = INREG(SURFACE_CNTL);
2381         rinfo->save_regs[30] = INREG(MC_FB_LOCATION);
2382         rinfo->save_regs[31] = INREG(DISPLAY_BASE_ADDR);
2383         rinfo->save_regs[32] = INREG(MC_AGP_LOCATION);
2384         rinfo->save_regs[33] = INREG(CRTC2_DISPLAY_BASE_ADDR);
2385 }
2386
2387 static void radeon_pm_restore_regs(struct radeonfb_info *rinfo)
2388 {
2389         OUTPLL(P2PLL_CNTL, rinfo->save_regs[8] & 0xFFFFFFFE); /* First */
2390
2391         OUTPLL(PLL_PWRMGT_CNTL, rinfo->save_regs[0]);
2392         OUTPLL(CLK_PWRMGT_CNTL, rinfo->save_regs[1]);
2393         OUTPLL(MCLK_CNTL, rinfo->save_regs[2]);
2394         OUTPLL(SCLK_CNTL, rinfo->save_regs[3]);
2395         OUTPLL(CLK_PIN_CNTL, rinfo->save_regs[4]);
2396         OUTPLL(VCLK_ECP_CNTL, rinfo->save_regs[5]);
2397         OUTPLL(PIXCLKS_CNTL, rinfo->save_regs[6]);
2398         OUTPLL(MCLK_MISC, rinfo->save_regs[7]);
2399
2400         OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
2401         OUTREG(DISP_PWR_MAN, rinfo->save_regs[10]);
2402         OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11]);
2403         OUTREG(LVDS_PLL_CNTL,rinfo->save_regs[12]);
2404         OUTREG(TV_DAC_CNTL, rinfo->save_regs[13]);
2405         OUTREG(BUS_CNTL1, rinfo->save_regs[14]);
2406         OUTREG(CRTC_OFFSET_CNTL, rinfo->save_regs[15]);
2407         OUTREG(AGP_CNTL, rinfo->save_regs[16]);
2408         OUTREG(CRTC_GEN_CNTL, rinfo->save_regs[17]);
2409         OUTREG(CRTC2_GEN_CNTL, rinfo->save_regs[18]);
2410
2411         // wait VBL before that one  ?
2412         OUTPLL(P2PLL_CNTL, rinfo->save_regs[8]);
2413
2414         OUTREG(GPIOPAD_A, rinfo->save_regs[19]);
2415         OUTREG(GPIOPAD_EN, rinfo->save_regs[20]);
2416         OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]);
2417         OUTREG(ZV_LCDPAD_A, rinfo->save_regs[22]);
2418         OUTREG(ZV_LCDPAD_EN, rinfo->save_regs[23]);
2419         OUTREG(ZV_LCDPAD_MASK, rinfo->save_regs[24]);
2420         OUTREG(GPIO_VGA_DDC, rinfo->save_regs[25]);
2421         OUTREG(GPIO_DVI_DDC, rinfo->save_regs[26]);
2422         OUTREG(GPIO_MONID, rinfo->save_regs[27]);
2423         OUTREG(GPIO_CRT2_DDC, rinfo->save_regs[28]);
2424 }
2425
2426 static void radeon_pm_disable_iopad(struct radeonfb_info *rinfo)
2427 {
2428         OUTREG(GPIOPAD_MASK, 0x0001ffff);
2429         OUTREG(GPIOPAD_EN, 0x00000400);
2430         OUTREG(GPIOPAD_A, 0x00000000);
2431         OUTREG(ZV_LCDPAD_MASK, 0x00000000);
2432         OUTREG(ZV_LCDPAD_EN, 0x00000000);
2433         OUTREG(ZV_LCDPAD_A, 0x00000000);
2434         OUTREG(GPIO_VGA_DDC, 0x00030000);
2435         OUTREG(GPIO_DVI_DDC, 0x00000000);
2436         OUTREG(GPIO_MONID, 0x00030000);
2437         OUTREG(GPIO_CRT2_DDC, 0x00000000);
2438 }
2439
2440 static void radeon_pm_program_v2clk(struct radeonfb_info *rinfo)
2441 {
2442 //
2443 //      u32 reg;
2444 //
2445 //      OUTPLL(P2PLL_REF_DIV, 0x0c);
2446 //
2447 //      .../... figure out what macos does here
2448 }
2449
2450 static void radeon_pm_low_current(struct radeonfb_info *rinfo)
2451 {
2452         u32 reg;
2453
2454         reg  = INREG(BUS_CNTL1);
2455         reg &= ~BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK;
2456         reg |= BUS_CNTL1_AGPCLK_VALID | (1<<BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT);
2457         OUTREG(BUS_CNTL1, reg);
2458
2459         reg  = INPLL(PLL_PWRMGT_CNTL);
2460         reg |= PLL_PWRMGT_CNTL_SPLL_TURNOFF | PLL_PWRMGT_CNTL_PPLL_TURNOFF |
2461                 PLL_PWRMGT_CNTL_P2PLL_TURNOFF | PLL_PWRMGT_CNTL_TVPLL_TURNOFF;
2462         reg &= ~PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK;
2463         reg &= ~PLL_PWRMGT_CNTL_MOBILE_SU;
2464         OUTPLL(PLL_PWRMGT_CNTL, reg);
2465
2466 //      reg  = INPLL(TV_PLL_CNTL1);
2467 //      reg |= TV_PLL_CNTL1__TVPLL_RESET | TV_PLL_CNTL1__TVPLL_SLEEP;
2468 //      OUTPLL(TV_PLL_CNTL1, reg);
2469
2470         reg  = INREG(TV_DAC_CNTL);
2471         reg &= ~(TV_DAC_CNTL_BGADJ_MASK |TV_DAC_CNTL_DACADJ_MASK);
2472         reg |=TV_DAC_CNTL_BGSLEEP | TV_DAC_CNTL_RDACPD | TV_DAC_CNTL_GDACPD |
2473                 TV_DAC_CNTL_BDACPD |
2474                 (8<<TV_DAC_CNTL_BGADJ__SHIFT) | (8<<TV_DAC_CNTL_DACADJ__SHIFT);
2475         OUTREG(TV_DAC_CNTL, reg);
2476
2477         reg  = INREG(TMDS_TRANSMITTER_CNTL);
2478         reg &= ~(TMDS_PLL_EN |TMDS_PLLRST);
2479         OUTREG(TMDS_TRANSMITTER_CNTL, reg);
2480
2481 //      lvds_pll_cntl  = regr32(g, LVDS_PLL_CNTL);
2482 //      lvds_pll_cntl &= ~LVDS_PLL_CNTL__LVDS_PLL_EN;
2483 //      lvds_pll_cntl |=  LVDS_PLL_CNTL__LVDS_PLL_RESET;
2484 //      regw32(g, LVDS_PLL_CNTL, lvds_pll_cntl);
2485
2486         reg = INREG(DAC_CNTL);
2487         reg &= ~DAC_CMP_EN;
2488         OUTREG(DAC_CNTL, reg);
2489
2490         reg = INREG(DAC_CNTL2);
2491         reg &= ~DAC2_CMP_EN;
2492         OUTREG(DAC_CNTL2, reg);
2493
2494         reg  = INREG(TV_DAC_CNTL);
2495         reg &= ~TV_DAC_CNTL_DETECT;
2496         OUTREG(TV_DAC_CNTL, reg);
2497 }
2498
2499 static void radeon_pm_setup_for_suspend(struct radeonfb_info *rinfo)
2500 {
2501         /* This code is disabled. It does what is in the pm_init
2502          * function of the MacOS driver code ATI sent me. However,
2503          * it doesn't fix my sleep problem, and is causing other issues
2504          * on wakeup (bascially the machine dying when switching consoles
2505          * I haven't had time to investigate this yet
2506          */
2507 #if 0
2508         u32 disp_misc_cntl;
2509         u32 disp_pwr_man;
2510         u32 temp;
2511
2512         // set SPLL, MPLL, PPLL, P2PLL, TVPLL, SCLK, MCLK, PCLK, P2CLK,
2513         // TCLK and TEST_MODE to 0
2514         temp = INPLL(CLK_PWRMGT_CNTL);
2515         OUTPLL(CLK_PWRMGT_CNTL , temp & ~0xc00002ff);
2516
2517         // Turn on Power Management
2518         temp = INPLL(CLK_PWRMGT_CNTL);
2519         OUTPLL(CLK_PWRMGT_CNTL , temp | 0x00000400);
2520
2521         // Turn off display clock if using mobile chips
2522         temp = INPLL(CLK_PWRMGT_CNTL);
2523         OUTREG(CLK_PWRMGT_CNTL , temp | 0x00100000);
2524
2525         // Force PIXCLK_ALWAYS_ON and PIXCLK_DAC_ALWAYS_ON
2526         temp = INPLL(VCLK_ECP_CNTL);
2527         OUTPLL(VCLK_ECP_CNTL, temp & ~0x000000c0);
2528
2529         // Force ECP_FORCE_ON to 1
2530         temp = INPLL(VCLK_ECP_CNTL);
2531         OUTPLL(VCLK_ECP_CNTL, temp | 0x00040000);
2532
2533         // Force PIXCLK_BLEND_ALWAYS_ON and PIXCLK_GV_ALWAYS_ON
2534         temp = INPLL(PIXCLKS_CNTL);
2535         OUTPLL(PIXCLKS_CNTL, temp & ~0x00001800);
2536
2537         // Forcing SCLK_CNTL to ON
2538         OUTPLL(SCLK_CNTL, (INPLL(SCLK_CNTL)& 0x00000007) | 0xffff8000 );
2539
2540         // Set PM control over XTALIN pad
2541         temp = INPLL(CLK_PIN_CNTL);
2542         OUTPLL(CLK_PIN_CNTL, temp | 0x00080000);
2543
2544         // Force MCLK and YCLK and MC as dynamic
2545         temp = INPLL(MCLK_CNTL);
2546         OUTPLL(MCLK_CNTL, temp & 0xffeaffff);
2547
2548         // PLL_TURNOFF
2549         temp = INPLL(PLL_PWRMGT_CNTL);
2550         OUTPLL(PLL_PWRMGT_CNTL, temp | 0x0000001f);
2551
2552         // set MOBILE_SU to 1 if M6 or DDR64 is detected
2553         temp = INPLL(PLL_PWRMGT_CNTL);
2554         OUTPLL(PLL_PWRMGT_CNTL, temp | 0x00010000);
2555
2556         // select PM access mode (PM_MODE_SEL) (use ACPI mode)
2557 //      temp = INPLL(PLL_PWRMGT_CNTL);
2558 //      OUTPLL(PLL_PWRMGT_CNTL, temp | 0x00002000);
2559         temp = INPLL(PLL_PWRMGT_CNTL);
2560         OUTPLL(PLL_PWRMGT_CNTL, temp & ~0x00002000);
2561
2562         // set DISP_MISC_CNTL register
2563         disp_misc_cntl = INREG(DISP_MISC_CNTL);
2564         disp_misc_cntl &= ~(    DISP_MISC_CNTL_SOFT_RESET_GRPH_PP |
2565                                 DISP_MISC_CNTL_SOFT_RESET_SUBPIC_PP |
2566                                 DISP_MISC_CNTL_SOFT_RESET_OV0_PP |
2567                                 DISP_MISC_CNTL_SOFT_RESET_GRPH_SCLK |
2568                                 DISP_MISC_CNTL_SOFT_RESET_SUBPIC_SCLK |
2569                                 DISP_MISC_CNTL_SOFT_RESET_OV0_SCLK |
2570                                 DISP_MISC_CNTL_SOFT_RESET_GRPH2_PP |
2571                                 DISP_MISC_CNTL_SOFT_RESET_GRPH2_SCLK |
2572                                 DISP_MISC_CNTL_SOFT_RESET_LVDS |
2573                                 DISP_MISC_CNTL_SOFT_RESET_TMDS |
2574                                 DISP_MISC_CNTL_SOFT_RESET_DIG_TMDS |
2575                                 DISP_MISC_CNTL_SOFT_RESET_TV);
2576         OUTREG(DISP_MISC_CNTL, disp_misc_cntl);
2577
2578         // set DISP_PWR_MAN register
2579         disp_pwr_man = INREG(DISP_PWR_MAN);
2580         // clau - 9.29.2000 - changes made to bit23:18 to set to 1 as requested by George
2581         disp_pwr_man |= (DISP_PWR_MAN_DIG_TMDS_ENABLE_RST |
2582                     DISP_PWR_MAN_TV_ENABLE_RST |
2583  //                 DISP_PWR_MAN_AUTO_PWRUP_EN |
2584                     DISP_PWR_MAN_DISP_D3_GRPH_RST |
2585                     DISP_PWR_MAN_DISP_D3_SUBPIC_RST |
2586                     DISP_PWR_MAN_DISP_D3_OV0_RST |
2587                     DISP_PWR_MAN_DISP_D1D2_GRPH_RST |
2588                     DISP_PWR_MAN_DISP_D1D2_SUBPIC_RST |
2589                     DISP_PWR_MAN_DISP_D1D2_OV0_RST);
2590         disp_pwr_man &= ~(DISP_PWR_MAN_DISP_PWR_MAN_D3_CRTC_EN |
2591                     DISP_PWR_MAN_DISP2_PWR_MAN_D3_CRTC2_EN|
2592                     DISP_PWR_MAN_DISP_D3_RST |
2593                     DISP_PWR_MAN_DISP_D3_REG_RST);
2594         OUTREG(DISP_PWR_MAN, disp_pwr_man);
2595
2596         // clau - 10.24.2000
2597         // - add in setting for BUS_CNTL1 b27:26 = 0x01 and b31 = 0x1
2598         // - add in setting for AGP_CNTL  b7:0 = 0x20
2599         // - add in setting for DVI_DDC_DATA_OUT_EN b17:16 = 0x0
2600
2601         // the following settings (two lines) are applied at a later part of this function, only on mobile platform
2602         // requres -mobile flag
2603         OUTREG(BUS_CNTL1, (INREG(BUS_CNTL1) & 0xf3ffffff) | 0x04000000);
2604         OUTREG(BUS_CNTL1,  INREG(BUS_CNTL1) | 0x80000000);
2605         OUTREG(AGP_CNTL, (INREG(AGP_CNTL) & 0xffffff00) | 0x20);
2606         OUTREG(GPIO_DVI_DDC, INREG(GPIO_DVI_DDC) & 0xfffcffff);
2607
2608         // yulee - 12.12.2000
2609         // A12 only
2610         // EN_MCLK_TRISTATE_IN_SUSPEND@MCLK_MISC = 1
2611         // ACCESS_REGS_IN_SUSPEND@CLK_PIN_CNTL = 0
2612         // only on mobile platform
2613         OUTPLL(MCLK_MISC, INPLL(MCLK_MISC) | 0x00040000 );
2614
2615         // yulee -12.12.2000
2616         // AGPCLK_VALID@BUS_CNTL1 = 1
2617         // MOBILE_PLATFORM_SEL@BUS_CNTL1 = 01
2618         // CRTC_STEREO_SYNC_OUT_EN@CRTC_OFFSET_CNTL = 0
2619         // CG_CLK_TO_OUTPIN@CLK_PIN_CNTL = 0
2620         // only on mobile platform
2621         OUTPLL(CLK_PIN_CNTL, INPLL(CLK_PIN_CNTL ) & 0xFFFFF7FF );
2622         OUTREG(BUS_CNTL1, (INREG(BUS_CNTL1 ) & 0xF3FFFFFF) | 0x84000000 );
2623         OUTREG(CRTC_OFFSET_CNTL, INREG(CRTC_OFFSET_CNTL ) & 0xFFEFFFFF );
2624
2625         mdelay(100);
2626 #endif
2627
2628         /* Disable CRTCs */
2629         OUTREG(CRTC_GEN_CNTL, (INREG(CRTC_GEN_CNTL) & ~CRTC_EN) | CRTC_DISP_REQ_EN_B);
2630         OUTREG(CRTC2_GEN_CNTL, (INREG(CRTC2_GEN_CNTL) & ~CRTC2_EN) | CRTC2_DISP_REQ_EN_B);
2631         (void)INREG(CRTC2_GEN_CNTL);
2632         mdelay(17);
2633 }
2634
2635 static void radeon_set_suspend(struct radeonfb_info *rinfo, int suspend)
2636 {
2637         u16 pwr_cmd;
2638
2639         if (!rinfo->pm_reg)
2640                 return;
2641
2642         /* Set the chip into appropriate suspend mode (we use D2,
2643          * D3 would require a compete re-initialization of the chip,
2644          * including PCI config registers, clocks, AGP conf, ...)
2645          */
2646         if (suspend) {
2647                 /* According to ATI, we should program V2CLK here, I have
2648                  * to verify what's up exactly
2649                  */
2650                 /* Save some registers */
2651                 radeon_pm_save_regs(rinfo);
2652
2653                 /* Check that on M7 too, might work might not. M7 may also
2654                  * need explicit enabling of PM
2655                  */
2656                 if (rinfo->arch == RADEON_M6) {
2657                         /* Program V2CLK */
2658                         radeon_pm_program_v2clk(rinfo);
2659
2660                         /* Disable IO PADs */
2661                         radeon_pm_disable_iopad(rinfo);
2662
2663                         /* Set low current */
2664                         radeon_pm_low_current(rinfo);
2665
2666                         /* Prepare chip for power management */
2667                         radeon_pm_setup_for_suspend(rinfo);
2668
2669                         /* Reset the MDLL */
2670                         OUTPLL(MDLL_CKO, INPLL(MDLL_CKO) | MCKOA_RESET);
2671                         (void)INPLL(MDLL_RDCKA);
2672                         OUTPLL(MDLL_CKO, INPLL(MDLL_CKO) & ~MCKOA_RESET);
2673                         (void)INPLL(MDLL_RDCKA);
2674                 }
2675
2676                 /* Switch PCI power managment to D2. */
2677                 for (;;) {
2678                         pci_read_config_word(
2679                                 rinfo->pdev, rinfo->pm_reg+PCI_PM_CTRL,
2680                                 &pwr_cmd);
2681                         if (pwr_cmd & 2)
2682                                 break;
2683                         pci_write_config_word(
2684                                 rinfo->pdev, rinfo->pm_reg+PCI_PM_CTRL,
2685                                 (pwr_cmd & ~PCI_PM_CTRL_STATE_MASK) | 2);
2686                         mdelay(500);
2687                 }
2688         } else {
2689                 /* Switch back PCI powermanagment to D0 */
2690                 mdelay(200);
2691                 pci_write_config_word(rinfo->pdev, rinfo->pm_reg+PCI_PM_CTRL, 0);
2692                 mdelay(500);
2693
2694                 dbg_clk = INPLL(1);
2695
2696                 /* Do we need that on M7 ? */
2697                 if (rinfo->arch == RADEON_M6) {
2698                         /* Restore the MDLL */
2699                         OUTPLL(MDLL_CKO, INPLL(MDLL_CKO) & ~MCKOA_RESET);
2700                         (void)INPLL(MDLL_CKO);
2701                 }
2702
2703                 /* Restore some registers */
2704                 radeon_pm_restore_regs(rinfo);
2705         }
2706 }
2707
2708 /*
2709  * Save the contents of the framebuffer when we go to sleep,
2710  * and restore it when we wake up again.
2711  */
2712
2713 int radeon_sleep_notify(struct pmu_sleep_notifier *self, int when)
2714 {
2715         struct radeonfb_info *rinfo;
2716
2717         for (rinfo = board_list; rinfo != NULL; rinfo = rinfo->next) {
2718                 struct fb_fix_screeninfo fix;
2719                 int nb;
2720                 struct display *disp;
2721
2722                 disp = (rinfo->currcon < 0) ? rinfo->info.disp : &fb_display[rinfo->currcon];
2723
2724                 switch (rinfo->arch) {
2725                         case RADEON_M6:
2726                         case RADEON_M7:
2727                         case RADEON_M9:
2728                                 break;
2729                         default:
2730                                 return PBOOK_SLEEP_REFUSE;
2731                 }
2732
2733                 radeonfb_get_fix(&fix, fg_console, (struct fb_info *)rinfo);
2734                 nb = fb_display[fg_console].var.yres * fix.line_length;
2735
2736                 switch (when) {
2737                         case PBOOK_SLEEP_NOW:
2738                                 acquire_console_sem();
2739                                 disp->dispsw = &fbcon_dummy;
2740
2741                                 if (!noaccel) {
2742                                         /* Make sure engine is reset */
2743                                         radeon_engine_reset();
2744                                         radeon_engine_idle();
2745                                 }
2746
2747                                 /* Blank display and LCD */
2748                                 radeonfb_blank(VESA_POWERDOWN+1,
2749                                                (struct fb_info *)rinfo);
2750
2751                                 /* Sleep */
2752                                 rinfo->asleep = 1;
2753                                 radeon_set_suspend(rinfo, 1);
2754                                 release_console_sem();
2755
2756                                 break;
2757                         case PBOOK_WAKE:
2758                                 acquire_console_sem();
2759                                 /* Wakeup */
2760                                 radeon_set_suspend(rinfo, 0);
2761
2762                                 if (!noaccel)
2763                                         radeon_engine_init(rinfo);
2764                                 rinfo->asleep = 0;
2765                                 radeon_set_dispsw(rinfo, disp);
2766                                 radeon_load_video_mode(rinfo, &disp->var);
2767                                 do_install_cmap(rinfo->currcon < 0 ? 0 : rinfo->currcon,
2768                                                 (struct fb_info *)rinfo);
2769
2770                                 radeonfb_blank(0, (struct fb_info *)rinfo);
2771                                 release_console_sem();
2772                                 printk("CLK_PIN_CNTL on wakeup was: %08x\n", dbg_clk);
2773                                 break;
2774                 }
2775         }
2776
2777         return PBOOK_SLEEP_OK;
2778 }
2779
2780 #endif /* CONFIG_PMAC_PBOOK */
2781
2782 static int radeonfb_pci_register (struct pci_dev *pdev,
2783                                   const struct pci_device_id *ent)
2784 {
2785         struct radeonfb_info *rinfo;
2786         struct radeon_chip_info *rci = &radeon_chip_info[ent->driver_data];
2787         u32 tmp;
2788
2789         RTRACE("radeonfb_pci_register BEGIN\n");
2790
2791         /* Enable device in PCI config */
2792         if (pci_enable_device(pdev) != 0) {
2793                 printk(KERN_ERR "radeonfb: Cannot enable PCI device\n");
2794                 return -ENODEV;
2795         }
2796
2797         rinfo = kmalloc (sizeof (struct radeonfb_info), GFP_KERNEL);
2798         if (!rinfo) {
2799                 printk ("radeonfb: could not allocate memory\n");
2800                 return -ENODEV;
2801         }
2802
2803         memset (rinfo, 0, sizeof (struct radeonfb_info));
2804         //info = &rinfo->info;
2805         rinfo->pdev = pdev;
2806         strcpy(rinfo->name, rci->name);
2807         rinfo->arch = rci->arch;
2808
2809         /* Set base addrs */
2810         rinfo->fb_base_phys = pci_resource_start (pdev, 0);
2811         rinfo->mmio_base_phys = pci_resource_start (pdev, 2);
2812
2813         /* request the mem regions */
2814         if (!request_mem_region (rinfo->fb_base_phys,
2815                                  pci_resource_len(pdev, 0), "radeonfb")) {
2816                 printk ("radeonfb: cannot reserve FB region\n");
2817                 kfree (rinfo);
2818                 return -ENODEV;
2819         }
2820
2821         if (!request_mem_region (rinfo->mmio_base_phys,
2822                                  pci_resource_len(pdev, 2), "radeonfb")) {
2823                 printk ("radeonfb: cannot reserve MMIO region\n");
2824                 release_mem_region (rinfo->fb_base_phys,
2825                                     pci_resource_len(pdev, 0));
2826                 kfree (rinfo);
2827                 return -ENODEV;
2828         }
2829
2830         /* map the regions */
2831         rinfo->mmio_base = ioremap (rinfo->mmio_base_phys, RADEON_REGSIZE);
2832         if (!rinfo->mmio_base) {
2833                 printk ("radeonfb: cannot map MMIO\n");
2834                 release_mem_region (rinfo->mmio_base_phys,
2835                                     pci_resource_len(pdev, 2));
2836                 release_mem_region (rinfo->fb_base_phys,
2837                                     pci_resource_len(pdev, 0));
2838                 kfree (rinfo);
2839                 return -ENODEV;
2840         }
2841
2842         rinfo->chipset = pdev->device;
2843
2844         switch (rinfo->arch) {
2845                 case RADEON_R100:
2846                         rinfo->hasCRTC2 = 0;
2847                         break;
2848                 default:
2849                         /* all the rest have it */
2850                         rinfo->hasCRTC2 = 1;
2851                         break;
2852         }
2853 #if 0
2854         if (rinfo->arch == RADEON_M7) {
2855                 /*
2856                  * Noticed some errors in accel with M7, will have to work these out...
2857                  */
2858                 noaccel = 1;
2859         }
2860 #endif
2861         if (mirror)
2862                 printk("radeonfb: mirroring display to CRT\n");
2863
2864         /* framebuffer size */
2865         tmp = INREG(CONFIG_MEMSIZE);
2866
2867         /* mem size is bits [28:0], mask off the rest */
2868         rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK;
2869
2870         /* ram type */
2871         tmp = INREG(MEM_SDRAM_MODE_REG);
2872         switch ((MEM_CFG_TYPE & tmp) >> 30) {
2873                 case 0:
2874                         /* SDR SGRAM (2:1) */
2875                         strcpy(rinfo->ram_type, "SDR SGRAM");
2876                         rinfo->ram.ml = 4;
2877                         rinfo->ram.mb = 4;
2878                         rinfo->ram.trcd = 1;
2879                         rinfo->ram.trp = 2;
2880                         rinfo->ram.twr = 1;
2881                         rinfo->ram.cl = 2;
2882                         rinfo->ram.loop_latency = 16;
2883                         rinfo->ram.rloop = 16;
2884
2885                         break;
2886                 case 1:
2887                         /* DDR SGRAM */
2888                         strcpy(rinfo->ram_type, "DDR SGRAM");
2889                         rinfo->ram.ml = 4;
2890                         rinfo->ram.mb = 4;
2891                         rinfo->ram.trcd = 3;
2892                         rinfo->ram.trp = 3;
2893                         rinfo->ram.twr = 2;
2894                         rinfo->ram.cl = 3;
2895                         rinfo->ram.tr2w = 1;
2896                         rinfo->ram.loop_latency = 16;
2897                         rinfo->ram.rloop = 16;
2898
2899                         break;
2900                 default:
2901                         /* 64-bit SDR SGRAM */
2902                         strcpy(rinfo->ram_type, "SDR SGRAM 64");
2903                         rinfo->ram.ml = 4;
2904                         rinfo->ram.mb = 8;
2905                         rinfo->ram.trcd = 3;
2906                         rinfo->ram.trp = 3;
2907                         rinfo->ram.twr = 1;
2908                         rinfo->ram.cl = 3;
2909                         rinfo->ram.tr2w = 1;
2910                         rinfo->ram.loop_latency = 17;
2911                         rinfo->ram.rloop = 17;
2912
2913                         break;
2914         }
2915
2916         rinfo->bios_seg = radeon_find_rom(rinfo);
2917         radeon_get_pllinfo(rinfo, rinfo->bios_seg);
2918
2919         /*
2920          * Hack to get around some busted production M6's
2921          * reporting no ram
2922          */
2923         if (rinfo->video_ram == 0) {
2924                 switch (pdev->device) {
2925                         case PCI_DEVICE_ID_ATI_RADEON_LY:
2926                         case PCI_DEVICE_ID_ATI_RADEON_LZ:
2927                                 rinfo->video_ram = 8192 * 1024;
2928                                 break;
2929                         default:
2930                                 break;
2931                 }
2932         }
2933
2934
2935         RTRACE("radeonfb: probed %s %dk videoram\n", (rinfo->ram_type), (rinfo->video_ram/1024));
2936
2937 #if !defined(__powerpc__)
2938         radeon_get_moninfo(rinfo);
2939 #else
2940         switch (pdev->device) {
2941                 case PCI_DEVICE_ID_ATI_RADEON_LW:
2942                 case PCI_DEVICE_ID_ATI_RADEON_LX:
2943                 case PCI_DEVICE_ID_ATI_RADEON_LY:
2944                 case PCI_DEVICE_ID_ATI_RADEON_LZ:
2945                         rinfo->dviDisp_type = MT_LCD;
2946                         break;
2947                 default:
2948                         radeon_get_moninfo(rinfo);
2949                         break;
2950         }
2951 #endif
2952
2953         radeon_get_EDID(rinfo);
2954
2955         if ((rinfo->dviDisp_type == MT_DFP) || (rinfo->dviDisp_type == MT_LCD) ||
2956             (rinfo->crtDisp_type == MT_DFP)) {
2957                 if (!radeon_get_dfpinfo(rinfo)) {
2958                         iounmap(rinfo->mmio_base);
2959                         release_mem_region (rinfo->mmio_base_phys,
2960                                             pci_resource_len(pdev, 2));
2961                         release_mem_region (rinfo->fb_base_phys,
2962                                             pci_resource_len(pdev, 0));
2963                         kfree (rinfo);
2964                         return -ENODEV;
2965                 }
2966         }
2967
2968         rinfo->fb_base = ioremap (rinfo->fb_base_phys, rinfo->video_ram);
2969         if (!rinfo->fb_base) {
2970                 printk ("radeonfb: cannot map FB\n");
2971                 iounmap(rinfo->mmio_base);
2972                 release_mem_region (rinfo->mmio_base_phys,
2973                                     pci_resource_len(pdev, 2));
2974                 release_mem_region (rinfo->fb_base_phys,
2975                                     pci_resource_len(pdev, 0));
2976                 kfree (rinfo);
2977                 return -ENODEV;
2978         }
2979
2980         /* I SHOULD FIX THAT CRAP ! I should probably mimmic XFree DRI
2981          * driver setup here.
2982          *
2983          * On PPC, OF based cards setup the internal memory
2984          * mapping in strange ways. We change it so that the
2985          * framebuffer is mapped at 0 and given half of the card's
2986          * address space (2Gb). AGP is mapped high (0xe0000000) and
2987          * can use up to 512Mb. Once DRI is fully implemented, we
2988          * will have to setup the PCI remapper to remap the agp_special_page
2989          * memory page somewhere between those regions so that the card
2990          * use a normal PCI bus master cycle to access the ring read ptr.
2991          * --BenH.
2992          */
2993 #ifdef CONFIG_ALL_PPC
2994         if (rinfo->hasCRTC2)
2995                 OUTREG(CRTC2_GEN_CNTL,
2996                         (INREG(CRTC2_GEN_CNTL) & ~CRTC2_EN) | CRTC2_DISP_REQ_EN_B);
2997         OUTREG(CRTC_EXT_CNTL, INREG(CRTC_EXT_CNTL) | CRTC_DISPLAY_DIS);
2998         OUTREG(MC_FB_LOCATION, 0x7fff0000);
2999         OUTREG(MC_AGP_LOCATION, 0xffffe000);
3000         OUTREG(DISPLAY_BASE_ADDR, 0x00000000);
3001         if (rinfo->hasCRTC2)
3002                 OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0x00000000);
3003         OUTREG(SRC_OFFSET, 0x00000000);
3004         OUTREG(DST_OFFSET, 0x00000000);
3005         mdelay(10);
3006         OUTREG(CRTC_EXT_CNTL, INREG(CRTC_EXT_CNTL) & ~CRTC_DISPLAY_DIS);
3007 #endif /* CONFIG_ALL_PPC */
3008
3009         /* save current mode regs before we switch into the new one
3010          * so we can restore this upon __exit
3011          */
3012         radeon_save_state (rinfo, &rinfo->init_state);
3013
3014         /* set all the vital stuff */
3015         radeon_set_fbinfo (rinfo);
3016
3017         pci_set_drvdata(pdev, rinfo);
3018         rinfo->next = board_list;
3019         board_list = rinfo;
3020         ((struct fb_info *) rinfo)->device = &pdev->dev;
3021         if (register_framebuffer ((struct fb_info *) rinfo) < 0) {
3022                 printk ("radeonfb: could not register framebuffer\n");
3023                 iounmap(rinfo->fb_base);
3024                 iounmap(rinfo->mmio_base);
3025                 release_mem_region (rinfo->mmio_base_phys,
3026                                     pci_resource_len(pdev, 2));
3027                 release_mem_region (rinfo->fb_base_phys,
3028                                     pci_resource_len(pdev, 0));
3029                 kfree (rinfo);
3030                 return -ENODEV;
3031         }
3032
3033 #ifdef CONFIG_MTRR
3034         rinfo->mtrr_hdl = nomtrr ? -1 : mtrr_add(rinfo->fb_base_phys,
3035                                                  rinfo->video_ram,
3036                                                  MTRR_TYPE_WRCOMB, 1);
3037 #endif
3038
3039 #ifdef CONFIG_PMAC_BACKLIGHT
3040         if (rinfo->dviDisp_type == MT_LCD)
3041                 register_backlight_controller(&radeon_backlight_controller,
3042                                               rinfo, "ati");
3043 #endif
3044
3045 #ifdef CONFIG_PMAC_PBOOK
3046         if (rinfo->dviDisp_type == MT_LCD) {
3047                 rinfo->pm_reg = pci_find_capability(pdev, PCI_CAP_ID_PM);
3048                 pmu_register_sleep_notifier(&radeon_sleep_notifier);
3049         }
3050 #endif
3051
3052         printk ("radeonfb: ATI Radeon %s %s %d MB\n", rinfo->name, rinfo->ram_type,
3053                 (rinfo->video_ram/(1024*1024)));
3054
3055         if (rinfo->hasCRTC2) {
3056                 printk("radeonfb: DVI port %s monitor connected\n",
3057                         GET_MON_NAME(rinfo->dviDisp_type));
3058                 printk("radeonfb: CRT port %s monitor connected\n",
3059                         GET_MON_NAME(rinfo->crtDisp_type));
3060         } else {
3061                 printk("radeonfb: CRT port %s monitor connected\n",
3062                         GET_MON_NAME(rinfo->crtDisp_type));
3063         }
3064
3065         RTRACE("radeonfb_pci_register END\n");
3066
3067         return 0;
3068 }
3069
3070
3071
3072 static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev)
3073 {
3074         struct radeonfb_info *rinfo = pci_get_drvdata(pdev);
3075
3076         if (!rinfo)
3077                 return;
3078
3079         /* restore original state
3080          *
3081          * Doesn't quite work yet, possibly because of the PPC hacking
3082          * I do on startup, disable for now. --BenH
3083          */
3084         radeon_write_mode (rinfo, &rinfo->init_state);
3085
3086 #ifdef CONFIG_MTRR
3087         if (rinfo->mtrr_hdl >= 0)
3088                 mtrr_del(rinfo->mtrr_hdl, 0, 0);
3089 #endif
3090
3091         unregister_framebuffer ((struct fb_info *) rinfo);
3092
3093         iounmap(rinfo->mmio_base);
3094         iounmap(rinfo->fb_base);
3095
3096         release_mem_region (rinfo->mmio_base_phys,
3097                             pci_resource_len(pdev, 2));
3098         release_mem_region (rinfo->fb_base_phys,
3099                             pci_resource_len(pdev, 0));
3100
3101         kfree (rinfo);
3102 }
3103
3104
3105 static struct pci_driver radeonfb_driver = {
3106         .name           = "radeonfb",
3107         .id_table       = radeonfb_pci_table,
3108         .probe          = radeonfb_pci_register,
3109         .remove         = __devexit_p(radeonfb_pci_unregister),
3110 };
3111
3112 int __init radeonfb_old_setup (char *options);
3113
3114 int __init radeonfb_old_init (void)
3115 {
3116 #ifndef MODULE
3117         char *option = NULL;
3118
3119         if (fb_get_options("radeonfb_old", &option))
3120                 return -ENODEV;
3121         radeonfb_old_setup(option);
3122 #endif
3123         return pci_module_init (&radeonfb_driver);
3124 }
3125
3126
3127 void __exit radeonfb_old_exit (void)
3128 {
3129         pci_unregister_driver (&radeonfb_driver);
3130 }
3131
3132
3133 int __init radeonfb_old_setup (char *options)
3134 {
3135         char *this_opt;
3136
3137         if (!options || !*options)
3138                 return 0;
3139
3140         while ((this_opt = strsep (&options, ",")) != NULL) {
3141                 if (!*this_opt)
3142                         continue;
3143                 if (!strncmp(this_opt, "noaccel", 7)) {
3144                         noaccel = 1;
3145                 } else if (!strncmp(this_opt, "mirror", 6)) {
3146                         mirror = 1;
3147                 } else if (!strncmp(this_opt, "dfp", 3)) {
3148                         force_dfp = 1;
3149                 } else if (!strncmp(this_opt, "panel_yres:", 11)) {
3150                         panel_yres = simple_strtoul((this_opt+11), NULL, 0);
3151                 } else if (!strncmp(this_opt, "nomtrr", 6)) {
3152                         nomtrr = 1;
3153                 } else
3154                         mode_option = this_opt;
3155         }
3156
3157         return 0;
3158 }
3159
3160 module_init(radeonfb_old_init);
3161
3162 #ifdef MODULE
3163 module_exit(radeonfb_old_exit);
3164 #endif
3165
3166
3167 MODULE_AUTHOR("Ani Joshi");
3168 MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset");
3169 MODULE_LICENSE("GPL");