drivers/video/riva/nv_driver.c

   1 /* $XConsortium: nv_driver.c /main/3 1996/10/28 05:13:37 kaleb $ */
   2 /*
   3  * Copyright 1996-1997  David J. McKay
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * DAVID J. MCKAY BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  19  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  20  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 /*
  25  * GPL licensing note -- nVidia is allowing a liberal interpretation of
  26  * the documentation restriction above, to merely say that this nVidia's
  27  * copyright and disclaimer should be included with all code derived
  28  * from this source.  -- Jeff Garzik <jgarzik@pobox.com>, 01/Nov/99
  29  */
  30
  31 /* Hacked together from mga driver and 3.3.4 NVIDIA driver by Jarno Paananen
  32    <jpaana@s2.org> */
  33
  34 /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_setup.c,v 1.18 2002/08/0
  35 5 20:47:06 mvojkovi Exp $ */
  36
  37 #include <linux/delay.h>
  38 #include <linux/pci.h>
  39 #include <linux/pci_ids.h>
  40 #include "nv_type.h"
  41 #include "rivafb.h"
  42 #include "nvreg.h"
  43
  44
  45 #ifndef CONFIG_PCI              /* sanity check */
  46 #error This driver requires PCI support.
  47 #endif
  48
  49 #define PFX "rivafb: "
  50
  51 static inline unsigned char MISCin(struct riva_par *par)
  52 {
  53         return (VGA_RD08(par->riva.PVIO, 0x3cc));
  54 }
  55
  56 static Bool
  57 riva_is_connected(struct riva_par *par, Bool second)
  58 {
  59         volatile U032 *PRAMDAC = par->riva.PRAMDAC0;
  60         U032 reg52C, reg608;
  61         Bool present;
  62
  63         if(second) PRAMDAC += 0x800;
  64
  65         reg52C = PRAMDAC[0x052C/4];
  66         reg608 = PRAMDAC[0x0608/4];
  67
  68         PRAMDAC[0x0608/4] = reg608 & ~0x00010000;
  69
  70         PRAMDAC[0x052C/4] = reg52C & 0x0000FEEE;
  71         mdelay(1);
  72         PRAMDAC[0x052C/4] |= 1;
  73
  74         par->riva.PRAMDAC0[0x0610/4] = 0x94050140;
  75         par->riva.PRAMDAC0[0x0608/4] |= 0x00001000;
  76
  77         mdelay(1);
  78
  79         present = (PRAMDAC[0x0608/4] & (1 << 28)) ? TRUE : FALSE;
  80
  81         par->riva.PRAMDAC0[0x0608/4] &= 0x0000EFFF;
  82
  83         PRAMDAC[0x052C/4] = reg52C;
  84         PRAMDAC[0x0608/4] = reg608;
  85
  86         return present;
  87 }
  88
  89 static void
  90 riva_override_CRTC(struct riva_par *par)
  91 {
  92         printk(KERN_INFO PFX
  93                 "Detected CRTC controller %i being used\n",
  94                 par->SecondCRTC ? 1 : 0);
  95
  96         if(par->forceCRTC != -1) {
  97                 printk(KERN_INFO PFX
  98                         "Forcing usage of CRTC %i\n", par->forceCRTC);
  99                 par->SecondCRTC = par->forceCRTC;
 100         }
 101 }
 102
 103 static void
 104 riva_is_second(struct riva_par *par)
 105 {
 106         if (par->FlatPanel == 1) {
 107                 switch(par->Chipset) {
 108                 case NV_CHIP_GEFORCE4_440_GO:
 109                 case NV_CHIP_GEFORCE4_440_GO_M64:
 110                 case NV_CHIP_GEFORCE4_420_GO:
 111                 case NV_CHIP_GEFORCE4_420_GO_M32:
 112                 case NV_CHIP_QUADRO4_500_GOGL:
 113                         par->SecondCRTC = TRUE;
 114                         break;
 115                 default:
 116                         par->SecondCRTC = FALSE;
 117                         break;
 118                 }
 119         } else {
 120                 if(riva_is_connected(par, 0)) {
 121                         if(par->riva.PRAMDAC0[0x0000052C/4] & 0x100)
 122                                 par->SecondCRTC = TRUE;
 123                         else
 124                                 par->SecondCRTC = FALSE;
 125                 } else
 126                 if (riva_is_connected(par, 1)) {
 127                         if(par->riva.PRAMDAC0[0x0000252C/4] & 0x100)
 128                                 par->SecondCRTC = TRUE;
 129                         else
 130                                 par->SecondCRTC = FALSE;
 131                 } else /* default */
 132                         par->SecondCRTC = FALSE;
 133         }
 134         riva_override_CRTC(par);
 135 }
 136
 137 unsigned long riva_get_memlen(struct riva_par *par)
 138 {
 139         RIVA_HW_INST *chip = &par->riva;
 140         unsigned long memlen = 0;
 141         unsigned int chipset = par->Chipset;
 142         struct pci_dev* dev;
 143         int amt;
 144
 145         switch (chip->Architecture) {
 146         case NV_ARCH_03:
 147                 if (chip->PFB[0x00000000/4] & 0x00000020) {
 148                         if (((chip->PMC[0x00000000/4] & 0xF0) == 0x20)
 149                             && ((chip->PMC[0x00000000/4] & 0x0F) >= 0x02)) {
 150                                 /*
 151                                  * SDRAM 128 ZX.
 152                                  */
 153                                 switch (chip->PFB[0x00000000/4] & 0x03) {
 154                                 case 2:
 155                                         memlen = 1024 * 4;
 156                                         break;
 157                                 case 1:
 158                                         memlen = 1024 * 2;
 159                                         break;
 160                                 default:
 161                                         memlen = 1024 * 8;
 162                                         break;
 163                                 }
 164                         } else {
 165                                 memlen = 1024 * 8;
 166                         }
 167                 } else  {
 168                         /*
 169                          * SGRAM 128.
 170                          */
 171                         switch (chip->PFB[0x00000000/4] & 0x00000003) {
 172                         case 0:
 173                                 memlen = 1024 * 8;
 174                                 break;
 175                         case 2:
 176                                 memlen = 1024 * 4;
 177                                 break;
 178                         default:
 179                                 memlen = 1024 * 2;
 180                                 break;
 181                         }
 182                 }
 183                 break;
 184         case NV_ARCH_04:
 185                 if (chip->PFB[0x00000000/4] & 0x00000100) {
 186                         memlen = ((chip->PFB[0x00000000/4] >> 12) & 0x0F) *
 187                                 1024 * 2 + 1024 * 2;
 188                 } else {
 189                         switch (chip->PFB[0x00000000/4] & 0x00000003) {
 190                         case 0:
 191                                 memlen = 1024 * 32;
 192                                 break;
 193                         case 1:
 194                                 memlen = 1024 * 4;
 195                                 break;
 196                         case 2:
 197                                 memlen = 1024 * 8;
 198                                 break;
 199                         case 3:
 200                         default:
 201                                 memlen = 1024 * 16;
 202                                 break;
 203                         }
 204                 }
 205                 break;
 206         case NV_ARCH_10:
 207         case NV_ARCH_20:
 208         case NV_ARCH_30:
 209                 if(chipset == NV_CHIP_IGEFORCE2) {
 210
 211                         dev = pci_find_slot(0, 1);
 212                         pci_read_config_dword(dev, 0x7C, &amt);
 213                         memlen = (((amt >> 6) & 31) + 1) * 1024;
 214                 } else if (chipset == NV_CHIP_0x01F0) {
 215                         dev = pci_find_slot(0, 1);
 216                         pci_read_config_dword(dev, 0x84, &amt);
 217                         memlen = (((amt >> 4) & 127) + 1) * 1024;
 218                 } else {
 219                         switch ((chip->PFB[0x0000020C/4] >> 20) & 0x000000FF){
 220                         case 0x02:
 221                                 memlen = 1024 * 2;
 222                                 break;
 223                         case 0x04:
 224                                 memlen = 1024 * 4;
 225                                 break;
 226                         case 0x08:
 227                                 memlen = 1024 * 8;
 228                                 break;
 229                         case 0x10:
 230                                 memlen = 1024 * 16;
 231                                 break;
 232                         case 0x20:
 233                                 memlen = 1024 * 32;
 234                                 break;
 235                         case 0x40:
 236                                 memlen = 1024 * 64;
 237                                 break;
 238                         case 0x80:
 239                                 memlen = 1024 * 128;
 240                                 break;
 241                         default:
 242                                 memlen = 1024 * 16;
 243                                 break;
 244                         }
 245                 }
 246                 break;
 247         }
 248         return memlen;
 249 }
 250
 251 unsigned long riva_get_maxdclk(struct riva_par *par)
 252 {
 253         RIVA_HW_INST *chip = &par->riva;
 254         unsigned long dclk = 0;
 255
 256         switch (chip->Architecture) {
 257         case NV_ARCH_03:
 258                 if (chip->PFB[0x00000000/4] & 0x00000020) {
 259                         if (((chip->PMC[0x00000000/4] & 0xF0) == 0x20)
 260                             && ((chip->PMC[0x00000000/4] & 0x0F) >= 0x02)) {
 261                                 /*
 262                                  * SDRAM 128 ZX.
 263                                  */
 264                                 dclk = 800000;
 265                         } else {
 266                                 dclk = 1000000;
 267                         }
 268                 } else {
 269                         /*
 270                          * SGRAM 128.
 271                          */
 272                         dclk = 1000000;
 273                 }
 274                 break;
 275         case NV_ARCH_04:
 276         case NV_ARCH_10:
 277         case NV_ARCH_20:
 278         case NV_ARCH_30:
 279                 switch ((chip->PFB[0x00000000/4] >> 3) & 0x00000003) {
 280                 case 3:
 281                         dclk = 800000;
 282                         break;
 283                 default:
 284                         dclk = 1000000;
 285                         break;
 286                 }
 287                 break;
 288         }
 289         return dclk;
 290 }
 291
 292 void
 293 riva_common_setup(struct riva_par *par)
 294 {
 295         par->riva.EnableIRQ = 0;
 296         par->riva.PRAMDAC0 = (unsigned *)(par->ctrl_base + 0x00680000);
 297         par->riva.PFB = (unsigned *)(par->ctrl_base + 0x00100000);
 298         par->riva.PFIFO = (unsigned *)(par->ctrl_base + 0x00002000);
 299         par->riva.PGRAPH = (unsigned *)(par->ctrl_base + 0x00400000);
 300         par->riva.PEXTDEV = (unsigned *)(par->ctrl_base + 0x00101000);
 301         par->riva.PTIMER = (unsigned *)(par->ctrl_base + 0x00009000);
 302         par->riva.PMC = (unsigned *)(par->ctrl_base + 0x00000000);
 303         par->riva.FIFO = (unsigned *)(par->ctrl_base + 0x00800000);
 304         par->riva.PCIO0 = (U008 *)(par->ctrl_base + 0x00601000);
 305         par->riva.PDIO0 = (U008 *)(par->ctrl_base + 0x00681000);
 306         par->riva.PVIO = (U008 *)(par->ctrl_base + 0x000C0000);
 307
 308         par->riva.IO = (MISCin(par) & 0x01) ? 0x3D0 : 0x3B0;
 309
 310         if (par->FlatPanel == -1) {
 311                 switch (par->Chipset) {
 312                 case NV_CHIP_GEFORCE4_440_GO:
 313                 case NV_CHIP_GEFORCE4_440_GO_M64:
 314                 case NV_CHIP_GEFORCE4_420_GO:
 315                 case NV_CHIP_GEFORCE4_420_GO_M32:
 316                 case NV_CHIP_QUADRO4_500_GOGL:
 317                 case NV_CHIP_GEFORCE2_GO:
 318                         printk(KERN_INFO PFX
 319                                 "On a laptop.  Assuming Digital Flat Panel\n");
 320                         par->FlatPanel = 1;
 321                         break;
 322                 default:
 323                         break;
 324                 }
 325         }
 326
 327         switch (par->Chipset & 0x0ff0) {
 328         case 0x0110:
 329                 if (par->Chipset == NV_CHIP_GEFORCE2_GO)
 330                         par->SecondCRTC = TRUE;
 331 #if defined(__powerpc__)
 332                 if (par->FlatPanel == 1)
 333                         par->SecondCRTC = TRUE;
 334 #endif
 335                 riva_override_CRTC(par);
 336                 break;
 337         case 0x0170:
 338         case 0x0180:
 339         case 0x01F0:
 340         case 0x0250:
 341         case 0x0280:
 342                 riva_is_second(par);
 343                 break;
 344         default:
 345                 break;
 346         }
 347
 348         if (par->SecondCRTC) {
 349                 par->riva.PCIO = par->riva.PCIO0 + 0x2000;
 350                 par->riva.PCRTC = par->riva.PCRTC0 + 0x800;
 351                 par->riva.PRAMDAC = par->riva.PRAMDAC0 + 0x800;
 352                 par->riva.PDIO = par->riva.PDIO0 + 0x2000;
 353         } else {
 354                 par->riva.PCIO = par->riva.PCIO0;
 355                 par->riva.PCRTC = par->riva.PCRTC0;
 356                 par->riva.PRAMDAC = par->riva.PRAMDAC0;
 357                 par->riva.PDIO = par->riva.PDIO0;
 358         }
 359
 360         if (par->FlatPanel == -1) {
 361                 /* Fix me, need x86 DDC code */
 362                 par->FlatPanel = 0;
 363         }
 364         par->riva.flatPanel = (par->FlatPanel > 0) ? TRUE : FALSE;
 365 }
 366