drivers/xen/pciback/conf_space_capability_pm.c

   1 /*
   2  * PCI Backend - Configuration space overlay for power management
   3  *
   4  * Author: Ryan Wilson <hap9@epoch.ncsc.mil>
   5  */
   6
   7 #include <linux/pci.h>
   8 #include "conf_space.h"
   9 #include "conf_space_capability.h"
  10
  11 static int pm_caps_read(struct pci_dev *dev, int offset, u16 *value,
  12                         void *data)
  13 {
  14         int err;
  15         u16 real_value;
  16
  17         err = pci_read_config_word(dev, offset, &real_value);
  18         if (err)
  19                 goto out;
  20
  21         *value = real_value & ~PCI_PM_CAP_PME_MASK;
  22
  23       out:
  24         return err;
  25 }
  26
  27 /* PM_OK_BITS specifies the bits that the driver domain is allowed to change.
  28  * Can't allow driver domain to enable PMEs - they're shared */
  29 #define PM_OK_BITS (PCI_PM_CTRL_PME_STATUS|PCI_PM_CTRL_DATA_SEL_MASK)
  30
  31 static int pm_ctrl_write(struct pci_dev *dev, int offset, u16 new_value,
  32                          void *data)
  33 {
  34         int err;
  35         u16 cur_value;
  36         pci_power_t new_state;
  37
  38         /* Handle setting power state separately */
  39         new_state = (pci_power_t)(new_value & PCI_PM_CTRL_STATE_MASK);
  40
  41         err = pci_read_config_word(dev, offset, &cur_value);
  42         if (err)
  43                 goto out;
  44
  45         new_value &= PM_OK_BITS;
  46         if ((cur_value & PM_OK_BITS) != new_value) {
  47                 new_value = (cur_value & ~PM_OK_BITS) | new_value;
  48                 err = pci_write_config_word(dev, offset, new_value);
  49                 if (err)
  50                         goto out;
  51         }
  52
  53         /* Let pci core handle the power management change */
  54         dev_dbg(&dev->dev, "set power state to %x\n", new_state);
  55         err = pci_set_power_state(dev, new_state);
  56         if (err)
  57                 err = PCIBIOS_SET_FAILED;
  58
  59       out:
  60         return err;
  61 }
  62
  63 /* Ensure PMEs are disabled */
  64 static void *pm_ctrl_init(struct pci_dev *dev, int offset)
  65 {
  66         int err;
  67         u16 value;
  68
  69         err = pci_read_config_word(dev, offset, &value);
  70         if (err)
  71                 goto out;
  72
  73         if (value & PCI_PM_CTRL_PME_ENABLE) {
  74                 value &= ~PCI_PM_CTRL_PME_ENABLE;
  75                 err = pci_write_config_word(dev, offset, value);
  76         }
  77
  78       out:
  79         return ERR_PTR(err);
  80 }
  81
  82 static struct config_field caplist_pm[] = {
  83         {
  84                 .offset     = PCI_PM_PMC,
  85                 .size       = 2,
  86                 .u.w.read   = pm_caps_read,
  87         },
  88         {
  89                 .offset     = PCI_PM_CTRL,
  90                 .size       = 2,
  91                 .init       = pm_ctrl_init,
  92                 .u.w.read   = pciback_read_config_word,
  93                 .u.w.write  = pm_ctrl_write,
  94         },
  95         {
  96                 .offset     = PCI_PM_PPB_EXTENSIONS,
  97                 .size       = 1,
  98                 .u.b.read   = pciback_read_config_byte,
  99         },
 100         {
 101                 .offset     = PCI_PM_DATA_REGISTER,
 102                 .size       = 1,
 103                 .u.b.read   = pciback_read_config_byte,
 104         },
 105         {
 106                 .size = 0,
 107         },
 108 };
 109
 110 struct pciback_config_capability pciback_config_capability_pm = {
 111         .capability = PCI_CAP_ID_PM,
 112         .fields = caplist_pm,
 113 };