2 * linux/include/asm-arm/arch-h720x/h7202-regs.h
4 * Copyright (C) 2000 Jungjun Kim, Hynix Semiconductor Inc.
5 * (C) 2003 Thomas Gleixner <tglx@linutronix.de>
6 * (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
7 * (C) 2004 Sascha Hauer <s.hauer@pengutronix.de>
9 * This file contains the hardware definitions of the h720x processors
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
15 * Do not add implementations specific defines here. This files contains
16 * only defines of the onchip peripherals. Add those defines to boards.h,
17 * which is included by this file.
20 #define SERIAL2_VIRT (IO_VIRT + 0x2d000)
21 #define SERIAL3_VIRT (IO_VIRT + 0x2e000)
23 /* Matrix Keyboard Controller */
24 #define KBD_VIRT (IO_VIRT + 0x22000)
28 #define KBD_KBVR0 0x0C
29 #define KBD_KBVR1 0x10
32 #define KBD_KBCR_SCANENABLE (1 << 7)
33 #define KBD_KBCR_NPOWERDOWN (1 << 2)
34 #define KBD_KBCR_CLKSEL_MASK (3)
35 #define KBD_KBCR_CLKSEL_PCLK2 0x0
36 #define KBD_KBCR_CLKSEL_PCLK128 0x1
37 #define KBD_KBCR_CLKSEL_PCLK256 0x2
38 #define KBD_KBCR_CLKSEL_PCLK512 0x3
40 #define KBD_KBSR_INTR (1 << 0)
41 #define KBD_KBSR_WAKEUP (1 << 1)
43 /* USB device controller */
45 #define USBD_BASE (IO_VIRT + 0x12000)
46 #define USBD_LENGTH 0x3C
48 #define USBD_GCTRL 0x00
49 #define USBD_EPCTRL 0x04
50 #define USBD_INTMASK 0x08
51 #define USBD_INTSTAT 0x0C
53 #define USBD_DMARXTX 0x14
54 #define USBD_DEVID 0x18
55 #define USBD_DEVCLASS 0x1C
56 #define USBD_INTCLASS 0x20
57 #define USBD_SETUP0 0x24
58 #define USBD_SETUP1 0x28
59 #define USBD_ENDP0RD 0x2C
60 #define USBD_ENDP0WT 0x30
61 #define USBD_ENDP1RD 0x34
62 #define USBD_ENDP2WT 0x38
67 #define PSSTAT_TXEMPTY (1<<0)
68 #define PSSTAT_TXBUSY (1<<1)
69 #define PSSTAT_RXFULL (1<<2)
70 #define PSSTAT_RXBUSY (1<<3)
71 #define PSSTAT_CLKIN (1<<4)
72 #define PSSTAT_DATAIN (1<<5)
73 #define PSSTAT_PARITY (1<<6)
76 #define PSCONF_ENABLE (1<<0)
77 #define PSCONF_TXINTEN (1<<2)
78 #define PSCONF_RXINTEN (1<<3)
79 #define PSCONF_FORCECLKLOW (1<<4)
80 #define PSCONF_FORCEDATLOW (1<<5)
81 #define PSCONF_LCE (1<<6)
84 #define PSINTR_TXINT (1<<0)
85 #define PSINTR_RXINT (1<<1)
86 #define PSINTR_PAR (1<<2)
87 #define PSINTR_RXTO (1<<3)
88 #define PSINTR_TXTO (1<<4)
90 #define PSTDLO 0x10 /* clk low before start transmission */
91 #define PSTPRI 0x14 /* PRI clock */
92 #define PSTXMT 0x18 /* maximum transmission time */
93 #define PSTREC 0x20 /* maximum receive time */
97 #define ADC_BASE (IO_VIRT + 0x29000)
99 #define ADC_TSCTRL 0x04
100 #define ADC_BT_CTRL 0x08
101 #define ADC_MC_CTRL 0x0C
102 #define ADC_STATUS 0x10
104 /* ADC control register bits */
105 #define ADC_CR_PW_CTRL 0x80
106 #define ADC_CR_DIRECTC 0x04
107 #define ADC_CR_CONTIME_NO 0x00
108 #define ADC_CR_CONTIME_2 0x04
109 #define ADC_CR_CONTIME_4 0x08
110 #define ADC_CR_CONTIME_ADE 0x0c
111 #define ADC_CR_LONGCALTIME 0x01
113 /* ADC touch panel register bits */
114 #define ADC_TSCTRL_ENABLE 0x80
115 #define ADC_TSCTRL_INTR 0x40
116 #define ADC_TSCTRL_SWBYPSS 0x20
117 #define ADC_TSCTRL_SWINVT 0x10
118 #define ADC_TSCTRL_S400 0x03
119 #define ADC_TSCTRL_S200 0x02
120 #define ADC_TSCTRL_S100 0x01
121 #define ADC_TSCTRL_S50 0x00
123 /* ADC Interrupt Status Register bits */
124 #define ADC_STATUS_TS_BIT 0x80
125 #define ADC_STATUS_MBT_BIT 0x40
126 #define ADC_STATUS_BBT_BIT 0x20
127 #define ADC_STATUS_MIC_BIT 0x10
129 /* Touch data registers */
130 #define ADC_TS_X0X1 0x30
131 #define ADC_TS_X2X3 0x34
132 #define ADC_TS_Y0Y1 0x38
133 #define ADC_TS_Y2Y3 0x3c
134 #define ADC_TS_X4X5 0x40
135 #define ADC_TS_X6X7 0x44
136 #define ADC_TS_Y4Y5 0x48
137 #define ADC_TS_Y6Y7 0x50
140 #define ADC_MB_DATA 0x54
141 #define ADC_BB_DATA 0x58
143 /* Sound data register */
144 #define ADC_SD_DAT0 0x60
145 #define ADC_SD_DAT1 0x64
146 #define ADC_SD_DAT2 0x68
147 #define ADC_SD_DAT3 0x6c
148 #define ADC_SD_DAT4 0x70
149 #define ADC_SD_DAT5 0x74
150 #define ADC_SD_DAT6 0x78
151 #define ADC_SD_DAT7 0x7c