2 * linux/include/asm-arm/arch-iop80310/dma.h
4 * Copyright (C) 2001 MontaVista Software, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #ifndef _IOP310_DMA_H_
12 #define _IOP310_DMA_H_
14 /* 2 DMA on primary PCI and 1 on secondary for 80310 */
15 #define MAX_IOP310_DMA_CHANNEL 3
16 #define MAX_DMA_DESC 64 /*128 */
19 * Make the generic DMA bits go away since we don't use it
21 #define MAX_DMA_CHANNELS 0
23 #define MAX_DMA_ADDRESS 0xffffffff
25 #define IOP310_DMA_P0 0
26 #define IOP310_DMA_P1 1
27 #define IOP310_DMA_S0 2
29 #define DMA_MOD_READ 0x0001
30 #define DMA_MOD_WRITE 0x0002
31 #define DMA_MOD_CACHED 0x0004
32 #define DMA_MOD_NONCACHED 0x0008
35 #define DMA_DESC_DONE 0x0010
36 #define DMA_INCOMPLETE 0x0020
37 #define DMA_HOLD 0x0040
38 #define DMA_END_CHAIN 0x0080
39 #define DMA_COMPLETE 0x0100
40 #define DMA_NOTIFY 0x0200
41 #define DMA_NEW_HEAD 0x0400
43 #define DMA_USER_MASK (DMA_NOTIFY | DMA_INCOMPLETE | \
44 DMA_HOLD | DMA_COMPLETE)
46 #define DMA_DCR_DAC 0x00000020 /* Dual Addr Cycle Enab */
47 #define DMA_DCR_IE 0x00000010 /* Interrupt Enable */
48 #define DMA_DCR_PCI_IOR 0x00000002 /* I/O Read */
49 #define DMA_DCR_PCI_IOW 0x00000003 /* I/O Write */
50 #define DMA_DCR_PCI_MR 0x00000006 /* Memory Read */
51 #define DMA_DCR_PCI_MW 0x00000007 /* Memory Write */
52 #define DMA_DCR_PCI_CR 0x0000000A /* Configuration Read */
53 #define DMA_DCR_PCI_CW 0x0000000B /* Configuration Write */
54 #define DMA_DCR_PCI_MRM 0x0000000C /* Memory Read Multiple */
55 #define DMA_DCR_PCI_MRL 0x0000000E /* Memory Read Line */
56 #define DMA_DCR_PCI_MWI 0x0000000F /* Mem Write and Inval */
58 #define DMA_USER_CMD_IE 0x00000001 /* user request int */
59 #define DMA_USER_END_CHAIN 0x00000002 /* end of sgl chain flag */
62 #define IOP310_ATUCR_PRIM_OUT_ENAB /* Configuration */ 0x00000002
63 #define IOP310_ATUCR_DIR_ADDR_ENAB /* Configuration */ 0x00000080
66 typedef void (*dma_callback_t) (void *buf_context);
70 typedef struct _dma_desc
72 u32 NDAR; /* next descriptor address */
73 u32 PDAR; /* PCI address */
74 u32 PUADR; /* upper PCI address */
75 u32 LADR; /* local address */
76 u32 BC; /* byte count */
77 u32 DC; /* descriptor control */
80 typedef struct _dma_sgl
82 dma_desc_t dma_desc; /* DMA descriptor pointer */
83 u32 status; /* descriptor status */
84 void *data; /* local virt */
85 struct _dma_sgl *next; /* next descriptor */
89 typedef struct _dma_head
91 u32 total; /* total elements in SGL */
92 u32 status; /* status of sgl */
93 u32 mode; /* read or write mode */
94 dma_sgl_t *list; /* pointer to list */
95 dma_callback_t callback; /* callback function */
98 /* function prototypes */
99 int dma_request(dmach_t, const char *);
100 int dma_queue_buffer(dmach_t, dma_head_t *);
101 int dma_suspend(dmach_t);
102 int dma_resume(dmach_t);
103 int dma_flush_all(dmach_t);
104 void dma_free(dmach_t);
105 void dma_set_irq_threshold(dmach_t, int);
106 dma_sgl_t *dma_get_buffer(dmach_t, int);
107 void dma_return_buffer(dmach_t, dma_sgl_t *);
109 #endif /* _ASM_ARCH_DMA_H */