2 * linux/include/asm/arch-iop3xx/iop310.h
4 * Intel IOP310 Companion Chip definitions
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
15 * This is needed for mixed drivers that need to work on all
16 * IOP3xx variants but behave slightly differently on each.
19 #define iop_is_310() ((processor_id & 0xffffe3f0) == 0x69052000)
23 * IOP310 I/O and Mem space regions for PCI autoconfiguration
25 #define IOP310_PCISEC_LOWER_IO 0x90010000
26 #define IOP310_PCISEC_UPPER_IO 0x9001ffff
27 #define IOP310_PCISEC_LOWER_MEM 0x88000000
28 #define IOP310_PCISEC_UPPER_MEM 0x8bffffff
30 #define IOP310_PCIPRI_LOWER_IO 0x90000000
31 #define IOP310_PCIPRI_UPPER_IO 0x9000ffff
32 #define IOP310_PCIPRI_LOWER_MEM 0x80000000
33 #define IOP310_PCIPRI_UPPER_MEM 0x83ffffff
35 #define IOP310_PCI_WINDOW_SIZE 64 * 0x100000
38 * IOP310 chipset registers
40 #define IOP310_VIRT_MEM_BASE 0xe8001000 /* chip virtual mem address*/
41 #define IOP310_PHY_MEM_BASE 0x00001000 /* chip physical memory address */
42 #define IOP310_REG_ADDR(reg) (IOP310_VIRT_MEM_BASE | IOP310_PHY_MEM_BASE | (reg))
44 /* PCI-to-PCI Bridge Unit 0x00001000 through 0x000010FF */
45 #define IOP310_VIDR (volatile u16 *)IOP310_REG_ADDR(0x00001000)
46 #define IOP310_DIDR (volatile u16 *)IOP310_REG_ADDR(0x00001002)
47 #define IOP310_PCR (volatile u16 *)IOP310_REG_ADDR(0x00001004)
48 #define IOP310_PSR (volatile u16 *)IOP310_REG_ADDR(0x00001006)
49 #define IOP310_RIDR (volatile u8 *)IOP310_REG_ADDR(0x00001008)
50 #define IOP310_CCR (volatile u32 *)IOP310_REG_ADDR(0x00001009)
51 #define IOP310_CLSR (volatile u8 *)IOP310_REG_ADDR(0x0000100C)
52 #define IOP310_PLTR (volatile u8 *)IOP310_REG_ADDR(0x0000100D)
53 #define IOP310_HTR (volatile u8 *)IOP310_REG_ADDR(0x0000100E)
54 /* Reserved 0x0000100F through 0x00001017 */
55 #define IOP310_PBNR (volatile u8 *)IOP310_REG_ADDR(0x00001018)
56 #define IOP310_SBNR (volatile u8 *)IOP310_REG_ADDR(0x00001019)
57 #define IOP310_SUBBNR (volatile u8 *)IOP310_REG_ADDR(0x0000101A)
58 #define IOP310_SLTR (volatile u8 *)IOP310_REG_ADDR(0x0000101B)
59 #define IOP310_IOBR (volatile u8 *)IOP310_REG_ADDR(0x0000101C)
60 #define IOP310_IOLR (volatile u8 *)IOP310_REG_ADDR(0x0000101D)
61 #define IOP310_SSR (volatile u16 *)IOP310_REG_ADDR(0x0000101E)
62 #define IOP310_MBR (volatile u16 *)IOP310_REG_ADDR(0x00001020)
63 #define IOP310_MLR (volatile u16 *)IOP310_REG_ADDR(0x00001022)
64 #define IOP310_PMBR (volatile u16 *)IOP310_REG_ADDR(0x00001024)
65 #define IOP310_PMLR (volatile u16 *)IOP310_REG_ADDR(0x00001026)
66 /* Reserved 0x00001028 through 0x00001033 */
67 #define IOP310_CAPR (volatile u8 *)IOP310_REG_ADDR(0x00001034)
68 /* Reserved 0x00001035 through 0x0000103D */
69 #define IOP310_BCR (volatile u16 *)IOP310_REG_ADDR(0x0000103E)
70 #define IOP310_EBCR (volatile u16 *)IOP310_REG_ADDR(0x00001040)
71 #define IOP310_SISR (volatile u16 *)IOP310_REG_ADDR(0x00001042)
72 #define IOP310_PBISR (volatile u32 *)IOP310_REG_ADDR(0x00001044)
73 #define IOP310_SBISR (volatile u32 *)IOP310_REG_ADDR(0x00001048)
74 #define IOP310_SACR (volatile u32 *)IOP310_REG_ADDR(0x0000104C)
75 #define IOP310_PIRSR (volatile u32 *)IOP310_REG_ADDR(0x00001050)
76 #define IOP310_SIOBR (volatile u8 *)IOP310_REG_ADDR(0x00001054)
77 #define IOP310_SIOLR (volatile u8 *)IOP310_REG_ADDR(0x00001055)
78 #define IOP310_SCDR (volatile u8 *)IOP310_REG_ADDR(0x00001056)
80 #define IOP310_SMBR (volatile u16 *)IOP310_REG_ADDR(0x00001058)
81 #define IOP310_SMLR (volatile u16 *)IOP310_REG_ADDR(0x0000105A)
82 #define IOP310_SDER (volatile u16 *)IOP310_REG_ADDR(0x0000105C)
83 #define IOP310_QCR (volatile u16 *)IOP310_REG_ADDR(0x0000105E)
84 #define IOP310_CAPID (volatile u8 *)IOP310_REG_ADDR(0x00001068)
85 #define IOP310_NIPTR (volatile u8 *)IOP310_REG_ADDR(0x00001069)
86 #define IOP310_PMCR (volatile u16 *)IOP310_REG_ADDR(0x0000106A)
87 #define IOP310_PMCSR (volatile u16 *)IOP310_REG_ADDR(0x0000106C)
88 #define IOP310_PMCSRBSE (volatile u8 *)IOP310_REG_ADDR(0x0000106E)
89 /* Reserved 0x00001064 through 0x000010FFH */
91 /* Performance monitoring unit 0x00001100 through 0x000011FF*/
92 #define IOP310_PMONGTMR (volatile u32 *)IOP310_REG_ADDR(0x00001100)
93 #define IOP310_PMONESR (volatile u32 *)IOP310_REG_ADDR(0x00001104)
94 #define IOP310_PMONEMISR (volatile u32 *)IOP310_REG_ADDR(0x00001108)
95 #define IOP310_PMONGTSR (volatile u32 *)IOP310_REG_ADDR(0x00001110)
96 #define IOP310_PMONPECR1 (volatile u32 *)IOP310_REG_ADDR(0x00001114)
97 #define IOP310_PMONPECR2 (volatile u32 *)IOP310_REG_ADDR(0x00001118)
98 #define IOP310_PMONPECR3 (volatile u32 *)IOP310_REG_ADDR(0x0000111C)
99 #define IOP310_PMONPECR4 (volatile u32 *)IOP310_REG_ADDR(0x00001120)
100 #define IOP310_PMONPECR5 (volatile u32 *)IOP310_REG_ADDR(0x00001124)
101 #define IOP310_PMONPECR6 (volatile u32 *)IOP310_REG_ADDR(0x00001128)
102 #define IOP310_PMONPECR7 (volatile u32 *)IOP310_REG_ADDR(0x0000112C)
103 #define IOP310_PMONPECR8 (volatile u32 *)IOP310_REG_ADDR(0x00001130)
104 #define IOP310_PMONPECR9 (volatile u32 *)IOP310_REG_ADDR(0x00001134)
105 #define IOP310_PMONPECR10 (volatile u32 *)IOP310_REG_ADDR(0x00001138)
106 #define IOP310_PMONPECR11 (volatile u32 *)IOP310_REG_ADDR(0x0000113C)
107 #define IOP310_PMONPECR12 (volatile u32 *)IOP310_REG_ADDR(0x00001140)
108 #define IOP310_PMONPECR13 (volatile u32 *)IOP310_REG_ADDR(0x00001144)
109 #define IOP310_PMONPECR14 (volatile u32 *)IOP310_REG_ADDR(0x00001148)
111 /* Address Translation Unit 0x00001200 through 0x000012FF */
112 #define IOP310_ATUVID (volatile u16 *)IOP310_REG_ADDR(0x00001200)
113 #define IOP310_ATUDID (volatile u16 *)IOP310_REG_ADDR(0x00001202)
114 #define IOP310_PATUCMD (volatile u16 *)IOP310_REG_ADDR(0x00001204)
115 #define IOP310_PATUSR (volatile u16 *)IOP310_REG_ADDR(0x00001206)
116 #define IOP310_ATURID (volatile u8 *)IOP310_REG_ADDR(0x00001208)
117 #define IOP310_ATUCCR (volatile u32 *)IOP310_REG_ADDR(0x00001209)
118 #define IOP310_ATUCLSR (volatile u8 *)IOP310_REG_ADDR(0x0000120C)
119 #define IOP310_ATULT (volatile u8 *)IOP310_REG_ADDR(0x0000120D)
120 #define IOP310_ATUHTR (volatile u8 *)IOP310_REG_ADDR(0x0000120E)
122 #define IOP310_PIABAR (volatile u32 *)IOP310_REG_ADDR(0x00001210)
123 /* Reserved 0x00001214 through 0x0000122B */
124 #define IOP310_ASVIR (volatile u16 *)IOP310_REG_ADDR(0x0000122C)
125 #define IOP310_ASIR (volatile u16 *)IOP310_REG_ADDR(0x0000122E)
126 #define IOP310_ERBAR (volatile u32 *)IOP310_REG_ADDR(0x00001230)
127 #define IOP310_ATUCAPPTR (volatile u8 *)IOP310_REG_ADDR(0x00001234)
128 /* Reserved 0x00001235 through 0x0000123B */
129 #define IOP310_ATUILR (volatile u8 *)IOP310_REG_ADDR(0x0000123C)
130 #define IOP310_ATUIPR (volatile u8 *)IOP310_REG_ADDR(0x0000123D)
131 #define IOP310_ATUMGNT (volatile u8 *)IOP310_REG_ADDR(0x0000123E)
132 #define IOP310_ATUMLAT (volatile u8 *)IOP310_REG_ADDR(0x0000123F)
133 #define IOP310_PIALR (volatile u32 *)IOP310_REG_ADDR(0x00001240)
134 #define IOP310_PIATVR (volatile u32 *)IOP310_REG_ADDR(0x00001244)
135 #define IOP310_SIABAR (volatile u32 *)IOP310_REG_ADDR(0x00001248)
136 #define IOP310_SIALR (volatile u32 *)IOP310_REG_ADDR(0x0000124C)
137 #define IOP310_SIATVR (volatile u32 *)IOP310_REG_ADDR(0x00001250)
138 #define IOP310_POMWVR (volatile u32 *)IOP310_REG_ADDR(0x00001254)
139 /* Reserved 0x00001258 through 0x0000125B */
140 #define IOP310_POIOWVR (volatile u32 *)IOP310_REG_ADDR(0x0000125C)
141 #define IOP310_PODWVR (volatile u32 *)IOP310_REG_ADDR(0x00001260)
142 #define IOP310_POUDR (volatile u32 *)IOP310_REG_ADDR(0x00001264)
143 #define IOP310_SOMWVR (volatile u32 *)IOP310_REG_ADDR(0x00001268)
144 #define IOP310_SOIOWVR (volatile u32 *)IOP310_REG_ADDR(0x0000126C)
145 /* Reserved 0x00001270 through 0x00001273*/
146 #define IOP310_ERLR (volatile u32 *)IOP310_REG_ADDR(0x00001274)
147 #define IOP310_ERTVR (volatile u32 *)IOP310_REG_ADDR(0x00001278)
148 /* Reserved 0x00001279 through 0x0000127C*/
149 #define IOP310_ATUCAPID (volatile u8 *)IOP310_REG_ADDR(0x00001280)
150 #define IOP310_ATUNIPTR (volatile u8 *)IOP310_REG_ADDR(0x00001281)
151 #define IOP310_APMCR (volatile u16 *)IOP310_REG_ADDR(0x00001282)
152 #define IOP310_APMCSR (volatile u16 *)IOP310_REG_ADDR(0x00001284)
153 /* Reserved 0x00001286 through 0x00001287 */
154 #define IOP310_ATUCR (volatile u32 *)IOP310_REG_ADDR(0x00001288)
155 /* Reserved 0x00001289 through 0x0000128C*/
156 #define IOP310_PATUISR (volatile u32 *)IOP310_REG_ADDR(0x00001290)
157 #define IOP310_SATUISR (volatile u32 *)IOP310_REG_ADDR(0x00001294)
158 #define IOP310_SATUCMD (volatile u16 *)IOP310_REG_ADDR(0x00001298)
159 #define IOP310_SATUSR (volatile u16 *)IOP310_REG_ADDR(0x0000129A)
160 #define IOP310_SODWVR (volatile u32 *)IOP310_REG_ADDR(0x0000129C)
161 #define IOP310_SOUDR (volatile u32 *)IOP310_REG_ADDR(0x000012A0)
162 #define IOP310_POCCAR (volatile u32 *)IOP310_REG_ADDR(0x000012A4)
163 #define IOP310_SOCCAR (volatile u32 *)IOP310_REG_ADDR(0x000012A8)
164 #define IOP310_POCCDR (volatile u32 *)IOP310_REG_ADDR(0x000012AC)
165 #define IOP310_SOCCDR (volatile u32 *)IOP310_REG_ADDR(0x000012B0)
166 #define IOP310_PAQCR (volatile u32 *)IOP310_REG_ADDR(0x000012B4)
167 #define IOP310_SAQCR (volatile u32 *)IOP310_REG_ADDR(0x000012B8)
168 #define IOP310_PATUIMR (volatile u32 *)IOP310_REG_ADDR(0x000012BC)
169 #define IOP310_SATUIMR (volatile u32 *)IOP310_REG_ADDR(0x000012C0)
170 /* Reserved 0x000012C4 through 0x000012FF */
171 /* Messaging Unit 0x00001300 through 0x000013FF */
172 #define IOP310_MUIMR0 (volatile u32 *)IOP310_REG_ADDR(0x00001310)
173 #define IOP310_MUIMR1 (volatile u32 *)IOP310_REG_ADDR(0x00001314)
174 #define IOP310_MUOMR0 (volatile u32 *)IOP310_REG_ADDR(0x00001318)
175 #define IOP310_MUOMR1 (volatile u32 *)IOP310_REG_ADDR(0x0000131C)
176 #define IOP310_MUIDR (volatile u32 *)IOP310_REG_ADDR(0x00001320)
177 #define IOP310_MUIISR (volatile u32 *)IOP310_REG_ADDR(0x00001324)
178 #define IOP310_MUIIMR (volatile u32 *)IOP310_REG_ADDR(0x00001328)
179 #define IOP310_MUODR (volatile u32 *)IOP310_REG_ADDR(0x0000132C)
180 #define IOP310_MUOISR (volatile u32 *)IOP310_REG_ADDR(0x00001330)
181 #define IOP310_MUOIMR (volatile u32 *)IOP310_REG_ADDR(0x00001334)
182 #define IOP310_MUMUCR (volatile u32 *)IOP310_REG_ADDR(0x00001350)
183 #define IOP310_MUQBAR (volatile u32 *)IOP310_REG_ADDR(0x00001354)
184 #define IOP310_MUIFHPR (volatile u32 *)IOP310_REG_ADDR(0x00001360)
185 #define IOP310_MUIFTPR (volatile u32 *)IOP310_REG_ADDR(0x00001364)
186 #define IOP310_MUIPHPR (volatile u32 *)IOP310_REG_ADDR(0x00001368)
187 #define IOP310_MUIPTPR (volatile u32 *)IOP310_REG_ADDR(0x0000136C)
188 #define IOP310_MUOFHPR (volatile u32 *)IOP310_REG_ADDR(0x00001370)
189 #define IOP310_MUOFTPR (volatile u32 *)IOP310_REG_ADDR(0x00001374)
190 #define IOP310_MUOPHPR (volatile u32 *)IOP310_REG_ADDR(0x00001378)
191 #define IOP310_MUOPTPR (volatile u32 *)IOP310_REG_ADDR(0x0000137C)
192 #define IOP310_MUIAR (volatile u32 *)IOP310_REG_ADDR(0x00001380)
193 /* DMA Controller 0x00001400 through 0x000014FF */
194 #define IOP310_DMA0CCR (volatile u32 *)IOP310_REG_ADDR(0x00001400)
195 #define IOP310_DMA0CSR (volatile u32 *)IOP310_REG_ADDR(0x00001404)
196 /* Reserved 0x001408 through 0x00140B */
197 #define IOP310_DMA0DAR (volatile u32 *)IOP310_REG_ADDR(0x0000140C)
198 #define IOP310_DMA0NDAR (volatile u32 *)IOP310_REG_ADDR(0x00001410)
199 #define IOP310_DMA0PADR (volatile u32 *)IOP310_REG_ADDR(0x00001414)
200 #define IOP310_DMA0PUADR (volatile u32 *)IOP310_REG_ADDR(0x00001418)
201 #define IOP310_DMA0LADR (volatile u32 *)IOP310_REG_ADDR(0x0000141C)
202 #define IOP310_DMA0BCR (volatile u32 *)IOP310_REG_ADDR(0x00001420)
203 #define IOP310_DMA0DCR (volatile u32 *)IOP310_REG_ADDR(0x00001424)
204 /* Reserved 0x00001428 through 0x0000143F */
205 #define IOP310_DMA1CCR (volatile u32 *)IOP310_REG_ADDR(0x00001440)
206 #define IOP310_DMA1CSR (volatile u32 *)IOP310_REG_ADDR(0x00001444)
207 /* Reserved 0x00001448 through 0x0000144B */
208 #define IOP310_DMA1DAR (volatile u32 *)IOP310_REG_ADDR(0x0000144C)
209 #define IOP310_DMA1NDAR (volatile u32 *)IOP310_REG_ADDR(0x00001450)
210 #define IOP310_DMA1PADR (volatile u32 *)IOP310_REG_ADDR(0x00001454)
211 #define IOP310_DMA1PUADR (volatile u32 *)IOP310_REG_ADDR(0x00001458)
212 #define IOP310_DMA1LADR (volatile u32 *)IOP310_REG_ADDR(0x0000145C)
213 #define IOP310_DMA1BCR (volatile u32 *)IOP310_REG_ADDR(0x00001460)
214 #define IOP310_DMA1DCR (volatile u32 *)IOP310_REG_ADDR(0x00001464)
215 /* Reserved 0x00001468 through 0x0000147F */
216 #define IOP310_DMA2CCR (volatile u32 *)IOP310_REG_ADDR(0x00001480)
217 #define IOP310_DMA2CSR (volatile u32 *)IOP310_REG_ADDR(0x00001484)
218 /* Reserved 0x00001488 through 0x0000148B */
219 #define IOP310_DMA2DAR (volatile u32 *)IOP310_REG_ADDR(0x0000148C)
220 #define IOP310_DMA2NDAR (volatile u32 *)IOP310_REG_ADDR(0x00001490)
221 #define IOP310_DMA2PADR (volatile u32 *)IOP310_REG_ADDR(0x00001494)
222 #define IOP310_DMA2PUADR (volatile u32 *)IOP310_REG_ADDR(0x00001498)
223 #define IOP310_DMA2LADR (volatile u32 *)IOP310_REG_ADDR(0x0000149C)
224 #define IOP310_DMA2BCR (volatile u32 *)IOP310_REG_ADDR(0x000014A0)
225 #define IOP310_DMA2DCR (volatile u32 *)IOP310_REG_ADDR(0x000014A4)
227 /* Memory controller 0x00001500 through 0x0015FF */
229 /* core interface unit 0x00001640 - 0x0000167F */
230 #define IOP310_CIUISR (volatile u32 *)IOP310_REG_ADDR(0x00001644)
232 /* PCI and Peripheral Interrupt Controller 0x00001700 - 0x0000171B */
233 #define IOP310_IRQISR (volatile u32 *)IOP310_REG_ADDR(0x00001700)
234 #define IOP310_FIQ2ISR (volatile u32 *)IOP310_REG_ADDR(0x00001704)
235 #define IOP310_FIQ1ISR (volatile u32 *)IOP310_REG_ADDR(0x00001708)
236 #define IOP310_PDIDR (volatile u32 *)IOP310_REG_ADDR(0x00001710)
238 /* AAU registers. DJ 0x00001800 - 0x00001838 */
239 #define IOP310_AAUACR (volatile u32 *)IOP310_REG_ADDR(0x00001800)
240 #define IOP310_AAUASR (volatile u32 *)IOP310_REG_ADDR(0x00001804)
241 #define IOP310_AAUADAR (volatile u32 *)IOP310_REG_ADDR(0x00001808)
242 #define IOP310_AAUANDAR (volatile u32 *)IOP310_REG_ADDR(0x0000180C)
243 #define IOP310_AAUSAR1 (volatile u32 *)IOP310_REG_ADDR(0x00001810)
244 #define IOP310_AAUSAR2 (volatile u32 *)IOP310_REG_ADDR(0x00001814)
245 #define IOP310_AAUSAR3 (volatile u32 *)IOP310_REG_ADDR(0x00001818)
246 #define IOP310_AAUSAR4 (volatile u32 *)IOP310_REG_ADDR(0x0000181C)
247 #define IOP310_AAUDAR (volatile u32 *)IOP310_REG_ADDR(0x00001820)
248 #define IOP310_AAUABCR (volatile u32 *)IOP310_REG_ADDR(0x00001824)
249 #define IOP310_AAUADCR (volatile u32 *)IOP310_REG_ADDR(0x00001828)
250 #define IOP310_AAUSAR5 (volatile u32 *)IOP310_REG_ADDR(0x0000182C)
251 #define IOP310_AAUSAR6 (volatile u32 *)IOP310_REG_ADDR(0x00001830)
252 #define IOP310_AAUSAR7 (volatile u32 *)IOP310_REG_ADDR(0x00001834)
253 #define IOP310_AAUSAR8 (volatile u32 *)IOP310_REG_ADDR(0x00001838)
255 #endif // _IOP310_HW_H_