2 * linux/include/asm-arm/arch-omap/hardware.h
4 * Hardware definitions for TI OMAP processors and boards
6 * NOTE: Please put device driver specific defines into a separate header
7 * file for each driver.
9 * Copyright (C) 2001 RidgeRun, Inc.
10 * Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
12 * Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com>
13 * and Dirk Behme <dirk.behme@de.bosch.com>
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
20 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
21 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
23 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
26 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
27 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 * You should have received a copy of the GNU General Public License along
32 * with this program; if not, write to the Free Software Foundation, Inc.,
33 * 675 Mass Ave, Cambridge, MA 02139, USA.
36 #ifndef __ASM_ARCH_OMAP_HARDWARE_H
37 #define __ASM_ARCH_OMAP_HARDWARE_H
39 #include <asm/sizes.h>
40 #include <linux/config.h>
42 #include <asm/types.h>
44 #include <asm/arch/io.h>
47 * ---------------------------------------------------------------------------
48 * Common definitions for all OMAP processors
49 * NOTE: Put all processor or board specific parts to the special header
51 * ---------------------------------------------------------------------------
55 * ----------------------------------------------------------------------------
57 * ----------------------------------------------------------------------------
59 #define CLKGEN_REG_BASE (0xfffece00)
60 #define ARM_CKCTL (CLKGEN_REG_BASE + 0x0)
61 #define ARM_IDLECT1 (CLKGEN_REG_BASE + 0x4)
62 #define ARM_IDLECT2 (CLKGEN_REG_BASE + 0x8)
63 #define ARM_EWUPCT (CLKGEN_REG_BASE + 0xC)
64 #define ARM_RSTCT1 (CLKGEN_REG_BASE + 0x10)
65 #define ARM_RSTCT2 (CLKGEN_REG_BASE + 0x14)
66 #define ARM_SYSST (CLKGEN_REG_BASE + 0x18)
72 #define SETARM_IDLE_SHIFT
74 /* DPLL control registers */
75 #define DPLL_CTL (0xfffecf00)
77 /* DSP clock control */
78 #define DSP_CONFIG_REG_BASE (0xe1008000)
79 #define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4)
80 #define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8)
83 * ---------------------------------------------------------------------------
85 * ---------------------------------------------------------------------------
87 #define ULPD_REG_BASE (0xfffe0800)
88 #define ULPD_IT_STATUS (ULPD_REG_BASE + 0x14)
89 #define ULPD_CLOCK_CTRL (ULPD_REG_BASE + 0x30)
90 #define ULPD_SOFT_REQ (ULPD_REG_BASE + 0x34)
91 #define ULPD_DPLL_CTRL (ULPD_REG_BASE + 0x3c)
92 #define ULPD_STATUS_REQ (ULPD_REG_BASE + 0x40)
93 #define ULPD_APLL_CTRL (ULPD_REG_BASE + 0x4c)
94 #define ULPD_POWER_CTRL (ULPD_REG_BASE + 0x50)
95 #define ULPD_CAM_CLK_CTRL (ULPD_REG_BASE + 0x7c)
98 * ---------------------------------------------------------------------------
100 * ---------------------------------------------------------------------------
102 #define OMAP_32kHz_TIMER_BASE 0xfffb9000
104 /* 32k Timer Registers */
105 #define TIMER32k_CR 0x08
106 #define TIMER32k_TVR 0x00
107 #define TIMER32k_TCR 0x04
109 /* 32k Timer Control Register definition */
110 #define TIMER32k_TSS (1<<0)
111 #define TIMER32k_TRB (1<<1)
112 #define TIMER32k_INT (1<<2)
113 #define TIMER32k_ARL (1<<3)
115 /* MPU Timer base addresses */
116 #define OMAP_TIMER1_BASE (0xfffec500)
117 #define OMAP_TIMER2_BASE (0xfffec600)
118 #define OMAP_TIMER3_BASE (0xfffec700)
119 #define OMAP_MPUTIMER_BASE OMAP_TIMER1_BASE
120 #define OMAP_MPUTIMER_OFFSET 0x100
122 /* MPU Timer Registers */
123 #define OMAP_TIMER1_CNTL (OMAP_TIMER_BASE1 + 0x0)
124 #define OMAP_TIMER1_LOAD_TIM (OMAP_TIMER_BASE1 + 0x4)
125 #define OMAP_TIMER1_READ_TIM (OMAP_TIMER_BASE1 + 0x8)
127 #define OMAP_TIMER2_CNTL (OMAP_TIMER_BASE2 + 0x0)
128 #define OMAP_TIMER2_LOAD_TIM (OMAP_TIMER_BASE2 + 0x4)
129 #define OMAP_TIMER2_READ_TIM (OMAP_TIMER_BASE2 + 0x8)
131 #define OMAP_TIMER3_CNTL (OMAP_TIMER_BASE3 + 0x0)
132 #define OMAP_TIMER3_LOAD_TIM (OMAP_TIMER_BASE3 + 0x4)
133 #define OMAP_TIMER3_READ_TIM (OMAP_TIMER_BASE3 + 0x8)
135 /* CNTL_TIMER register bits */
136 #define MPUTIM_FREE (1<<6)
137 #define MPUTIM_CLOCK_ENABLE (1<<5)
138 #define MPUTIM_PTV_MASK (0x7<<PTV_BIT)
139 #define MPUTIM_PTV_BIT 2
140 #define MPUTIM_AR (1<<1)
141 #define MPUTIM_ST (1<<0)
144 #define OMAP_WATCHDOG_BASE (0xfffec800)
145 #define OMAP_WDT_TIMER (OMAP_WATCHDOG_BASE + 0x0)
146 #define OMAP_WDT_LOAD_TIM (OMAP_WATCHDOG_BASE + 0x4)
147 #define OMAP_WDT_READ_TIM (OMAP_WATCHDOG_BASE + 0x4)
148 #define OMAP_WDT_TIMER_MODE (OMAP_WATCHDOG_BASE + 0x8)
151 * ---------------------------------------------------------------------------
153 * ---------------------------------------------------------------------------
155 #define OMAP_IH1_BASE 0xfffecb00
156 #define OMAP_IH2_BASE 0xfffe0000
158 #define OMAP_IH1_ITR (OMAP_IH1_BASE + 0x00)
159 #define OMAP_IH1_MIR (OMAP_IH1_BASE + 0x04)
160 #define OMAP_IH1_SIR_IRQ (OMAP_IH1_BASE + 0x10)
161 #define OMAP_IH1_SIR_FIQ (OMAP_IH1_BASE + 0x14)
162 #define OMAP_IH1_CONTROL (OMAP_IH1_BASE + 0x18)
163 #define OMAP_IH1_ILR0 (OMAP_IH1_BASE + 0x1c)
164 #define OMAP_IH1_ISR (OMAP_IH1_BASE + 0x9c)
166 #define OMAP_IH2_ITR (OMAP_IH2_BASE + 0x00)
167 #define OMAP_IH2_MIR (OMAP_IH2_BASE + 0x04)
168 #define OMAP_IH2_SIR_IRQ (OMAP_IH2_BASE + 0x10)
169 #define OMAP_IH2_SIR_FIQ (OMAP_IH2_BASE + 0x14)
170 #define OMAP_IH2_CONTROL (OMAP_IH2_BASE + 0x18)
171 #define OMAP_IH2_ILR0 (OMAP_IH2_BASE + 0x1c)
172 #define OMAP_IH2_ISR (OMAP_IH2_BASE + 0x9c)
174 #define IRQ_ITR_REG_OFFSET 0x00
175 #define IRQ_MIR_REG_OFFSET 0x04
176 #define IRQ_SIR_IRQ_REG_OFFSET 0x10
177 #define IRQ_SIR_FIQ_REG_OFFSET 0x14
178 #define IRQ_CONTROL_REG_OFFSET 0x18
179 #define IRQ_ISR_REG_OFFSET 0x9c
180 #define IRQ_ILR0_REG_OFFSET 0x1c
183 * ---------------------------------------------------------------------------
184 * Traffic controller memory interface
185 * ---------------------------------------------------------------------------
187 #define TCMIF_BASE 0xfffecc00
188 #define IMIF_PRIO (TCMIF_BASE + 0x00)
189 #define EMIFS_PRIO (TCMIF_BASE + 0x04)
190 #define EMIFF_PRIO (TCMIF_BASE + 0x08)
191 #define EMIFS_CONFIG (TCMIF_BASE + 0x0c)
192 #define EMIFS_CS0_CONFIG (TCMIF_BASE + 0x10)
193 #define EMIFS_CS1_CONFIG (TCMIF_BASE + 0x14)
194 #define EMIFS_CS2_CONFIG (TCMIF_BASE + 0x18)
195 #define EMIFS_CS3_CONFIG (TCMIF_BASE + 0x1c)
196 #define EMIFF_SDRAM_CONFIG (TCMIF_BASE + 0x20)
197 #define EMIFF_MRS (TCMIF_BASE + 0x24)
198 #define TC_TIMEOUT1 (TCMIF_BASE + 0x28)
199 #define TC_TIMEOUT2 (TCMIF_BASE + 0x2c)
200 #define TC_TIMEOUT3 (TCMIF_BASE + 0x30)
201 #define TC_ENDIANISM (TCMIF_BASE + 0x34)
202 #define EMIFF_SDRAM_CONFIG_2 (TCMIF_BASE + 0x3c)
203 #define EMIF_CFG_DYNAMIC_WS (TCMIF_BASE + 0x40)
205 * ----------------------------------------------------------------------------
206 * System control registers
207 * ----------------------------------------------------------------------------
209 #define MOD_CONF_CTRL_0 0xfffe1080
210 #define MOD_CONF_CTRL_1 0xfffe1110
213 * ----------------------------------------------------------------------------
214 * Pin multiplexing registers
215 * ----------------------------------------------------------------------------
217 #define FUNC_MUX_CTRL_0 0xfffe1000
218 #define FUNC_MUX_CTRL_1 0xfffe1004
219 #define FUNC_MUX_CTRL_2 0xfffe1008
220 #define COMP_MODE_CTRL_0 0xfffe100c
221 #define FUNC_MUX_CTRL_3 0xfffe1010
222 #define FUNC_MUX_CTRL_4 0xfffe1014
223 #define FUNC_MUX_CTRL_5 0xfffe1018
224 #define FUNC_MUX_CTRL_6 0xfffe101C
225 #define FUNC_MUX_CTRL_7 0xfffe1020
226 #define FUNC_MUX_CTRL_8 0xfffe1024
227 #define FUNC_MUX_CTRL_9 0xfffe1028
228 #define FUNC_MUX_CTRL_A 0xfffe102C
229 #define FUNC_MUX_CTRL_B 0xfffe1030
230 #define FUNC_MUX_CTRL_C 0xfffe1034
231 #define FUNC_MUX_CTRL_D 0xfffe1038
232 #define PULL_DWN_CTRL_0 0xfffe1040
233 #define PULL_DWN_CTRL_1 0xfffe1044
234 #define PULL_DWN_CTRL_2 0xfffe1048
235 #define PULL_DWN_CTRL_3 0xfffe104c
237 /* OMAP-1610 specific multiplexing registers */
238 #define FUNC_MUX_CTRL_E 0xfffe1090
239 #define FUNC_MUX_CTRL_F 0xfffe1094
240 #define FUNC_MUX_CTRL_10 0xfffe1098
241 #define FUNC_MUX_CTRL_11 0xfffe109c
242 #define FUNC_MUX_CTRL_12 0xfffe10a0
243 #define PU_PD_SEL_0 0xfffe10b4
244 #define PU_PD_SEL_1 0xfffe10b8
245 #define PU_PD_SEL_2 0xfffe10bc
246 #define PU_PD_SEL_3 0xfffe10c0
247 #define PU_PD_SEL_4 0xfffe10c4
250 * ---------------------------------------------------------------------------
252 * ---------------------------------------------------------------------------
254 #define TIPB_PUBLIC_CNTL_BASE 0xfffed300
255 #define MPU_PUBLIC_TIPB_CNTL (TIPB_PUBLIC_CNTL_BASE + 0x8)
256 #define TIPB_PRIVATE_CNTL_BASE 0xfffeca00
257 #define MPU_PRIVATE_TIPB_CNTL (TIPB_PRIVATE_CNTL_BASE + 0x8)
260 * ----------------------------------------------------------------------------
262 * ----------------------------------------------------------------------------
264 #define MPUI_BASE (0xfffec900)
265 #define MPUI_CTRL (MPUI_BASE + 0x0)
266 #define MPUI_DEBUG_ADDR (MPUI_BASE + 0x4)
267 #define MPUI_DEBUG_DATA (MPUI_BASE + 0x8)
268 #define MPUI_DEBUG_FLAG (MPUI_BASE + 0xc)
269 #define MPUI_STATUS_REG (MPUI_BASE + 0x10)
270 #define MPUI_DSP_STATUS (MPUI_BASE + 0x14)
271 #define MPUI_DSP_BOOT_CONFIG (MPUI_BASE + 0x18)
272 #define MPUI_DSP_API_CONFIG (MPUI_BASE + 0x1c)
274 #ifndef __ASSEMBLER__
277 * ---------------------------------------------------------------------------
278 * Processor differentiation
279 * ---------------------------------------------------------------------------
281 #define OMAP_ID_BASE (0xfffed400)
282 #define OMAP_ID_REG __REG32(OMAP_ID_BASE + 0x04)
285 #define ID_MASK 0x7fff
287 /* See also uncompress.h */
288 #define OMAP_ID_730 0x355F
289 #define OMAP_ID_1510 0x3470
290 #define OMAP_ID_1610 0x3576
291 #define OMAP_ID_1710 0x35F7
292 #define OMAP_ID_5912 0x358C
294 #ifdef CONFIG_ARCH_OMAP730
296 #define cpu_is_omap730() (((OMAP_ID_REG >> ID_SHIFT) & ID_MASK) == OMAP_ID_730)
298 #define cpu_is_omap730() 0
301 #ifdef CONFIG_ARCH_OMAP1510
302 #include "omap1510.h"
303 #define cpu_is_omap1510() (((OMAP_ID_REG >> ID_SHIFT) & ID_MASK) == OMAP_ID_1510)
305 #define cpu_is_omap1510() 0
308 #ifdef CONFIG_ARCH_OMAP1610
309 #include "omap1610.h"
310 #define cpu_is_omap1710() (((OMAP_ID_REG >> ID_SHIFT) & ID_MASK) == OMAP_ID_1710)
311 /* Detect 1710 as 1610 for now */
312 #define cpu_is_omap1610() (((OMAP_ID_REG >> ID_SHIFT) & ID_MASK) == OMAP_ID_1610 \
313 || cpu_is_omap1710())
315 #define cpu_is_omap1610() 0
316 #define cpu_is_omap1710() 0
319 #ifdef CONFIG_ARCH_OMAP5912
320 #include "omap5912.h"
321 #define cpu_is_omap5912() (((OMAP_ID_REG >> ID_SHIFT) & ID_MASK) == OMAP_ID_5912)
323 #define cpu_is_omap5912() 0
327 * ---------------------------------------------------------------------------
328 * Board differentiation
329 * ---------------------------------------------------------------------------
332 #ifdef CONFIG_MACH_OMAP_INNOVATOR
333 #include "board-innovator.h"
336 #ifdef CONFIG_MACH_OMAP_H2
337 #include "board-h2.h"
340 #ifdef CONFIG_MACH_OMAP_PERSEUS2
341 #include "board-perseus2.h"
344 #ifdef CONFIG_MACH_OMAP_H3
345 #include "board-h3.h"
346 #error "Support for H3 board not yet implemented."
349 #ifdef CONFIG_MACH_OMAP_H4
350 #include "board-h4.h"
351 #error "Support for H4 board not yet implemented."
354 #ifdef CONFIG_MACH_OMAP_OSK
355 #include "board-osk.h"
358 #endif /* !__ASSEMBLER__ */
360 #endif /* __ASM_ARCH_OMAP_HARDWARE_H */