2 * linux/include/asm-arm/arch-omap/omap-perseus2.h
4 * Copyright 2003 by Texas Instruments Incorporated
5 * OMAP730 / P2-sample additions
8 * Copyright (C) 2001 RidgeRun, Inc. (http://www.ridgerun.com)
9 * Author: RidgeRun, Inc.
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
19 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
22 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
23 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 * You should have received a copy of the GNU General Public License along
28 * with this program; if not, write to the Free Software Foundation, Inc.,
29 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 #ifndef __ASM_ARCH_OMAP_P2SAMPLE_H
32 #define __ASM_ARCH_OMAP_P2SAMPLE_H
34 #if defined(CONFIG_ARCH_OMAP730) && defined (CONFIG_MACH_OMAP_PERSEUS2)
37 * NOTE: ALL DEFINITIONS IN THIS FILE NEED TO BE PREFIXED BY IDENTIFIER
38 * P2SAMPLE_ since they are specific to the EVM and not the chip.
41 /* ---------------------------------------------------------------------------
42 * OMAP730 Debug Board FPGA
43 * ---------------------------------------------------------------------------
47 /* maps in the FPGA registers and the ETHR registers */
48 #define OMAP730_FPGA_BASE 0xE8000000 /* VA */
49 #define OMAP730_FPGA_SIZE SZ_4K /* SIZE */
50 #define OMAP730_FPGA_START 0x04000000 /* PA */
52 #define OMAP730_FPGA_ETHR_START OMAP730_FPGA_START
53 #define OMAP730_FPGA_ETHR_BASE OMAP730_FPGA_BASE
54 #define OMAP730_FPGA_FPGA_REV (OMAP730_FPGA_BASE + 0x10) /* FPGA Revision */
55 #define OMAP730_FPGA_BOARD_REV (OMAP730_FPGA_BASE + 0x12) /* Board Revision */
56 #define OMAP730_FPGA_GPIO (OMAP730_FPGA_BASE + 0x14) /* GPIO outputs */
57 #define OMAP730_FPGA_LEDS (OMAP730_FPGA_BASE + 0x16) /* LEDs outputs */
58 #define OMAP730_FPGA_MISC_INPUTS (OMAP730_FPGA_BASE + 0x18) /* Misc inputs */
59 #define OMAP730_FPGA_LAN_STATUS (OMAP730_FPGA_BASE + 0x1A) /* LAN Status line */
60 #define OMAP730_FPGA_LAN_RESET (OMAP730_FPGA_BASE + 0x1C) /* LAN Reset line */
62 // LEDs definition on debug board (16 LEDs)
63 #define OMAP730_FPGA_LED_CLAIMRELEASE (1 << 15)
64 #define OMAP730_FPGA_LED_STARTSTOP (1 << 14)
65 #define OMAP730_FPGA_LED_HALTED (1 << 13)
66 #define OMAP730_FPGA_LED_IDLE (1 << 12)
67 #define OMAP730_FPGA_LED_TIMER (1 << 11)
68 // cpu0 load-meter LEDs
69 #define OMAP730_FPGA_LOAD_METER (1 << 0) // A bit of fun on our board ...
70 #define OMAP730_FPGA_LOAD_METER_SIZE 11
71 #define OMAP730_FPGA_LOAD_METER_MASK ((1 << OMAP730_FPGA_LOAD_METER_SIZE) - 1)
73 #ifndef OMAP_SDRAM_DEVICE
74 #define OMAP_SDRAM_DEVICE D256M_1X16_4B
79 * These definitions define an area of FLASH set aside
80 * for the use of MTD/JFFS2. This is the area of flash
81 * that a JFFS2 filesystem will reside which is mounted
82 * at boot with the "root=/dev/mtdblock/0 rw"
83 * command line option.
86 /* Intel flash_0, partitioned as expected by rrload */
87 #define OMAP_FLASH_0_BASE 0xD8000000 /* VA */
88 #define OMAP_FLASH_0_START 0x00000000 /* PA */
89 #define OMAP_FLASH_0_SIZE SZ_32M
91 /* 2.9.6 Traffic Controller Memory Interface Registers */
92 #define OMAP_FLASH_CFG_0 0xfffecc10
93 #define OMAP_FLASH_ACFG_0 0xfffecc50
95 #define OMAP_FLASH_CFG_1 0xfffecc14
96 #define OMAP_FLASH_ACFG_1 0xfffecc54
99 * Configuration Registers
101 #define PERSEUS2_CONFIG_BASE 0xfffe1000
102 #define PERSEUS2_IO_CONF_0 0xfffe1070
103 #define PERSEUS2_IO_CONF_1 0xfffe1074
104 #define PERSEUS2_IO_CONF_2 0xfffe1078
105 #define PERSEUS2_IO_CONF_3 0xfffe107c
106 #define PERSEUS2_IO_CONF_4 0xfffe1080
107 #define PERSEUS2_IO_CONF_5 0xfffe1084
108 #define PERSEUS2_IO_CONF_6 0xfffe1088
109 #define PERSEUS2_IO_CONF_7 0xfffe108c
110 #define PERSEUS2_IO_CONF_8 0xfffe1090
111 #define PERSEUS2_IO_CONF_9 0xfffe1094
112 #define PERSEUS2_IO_CONF_10 0xfffe1098
113 #define PERSEUS2_IO_CONF_11 0xfffe109c
114 #define PERSEUS2_IO_CONF_12 0xfffe10a0
115 #define PERSEUS2_IO_CONF_13 0xfffe10a4
117 #define PERSEUS2_MODE_1 0xfffe1010
118 #define PERSEUS2_MODE_2 0xfffe1014
120 /* CSMI specials: in terms of base + offset */
121 #define PERSEUS2_MODE2_OFFSET 0x14
123 /* DSP control: ICR registers */
124 #define ICR_BASE 0xfffbb800
126 #define DSP_M_CTL ((volatile __u16 *)0xfffbb804)
127 /* DSP control: MMU registers */
128 #define DSP_MMU_BASE ((volatile __u16 *)0xfffed200)
130 /* The Ethernet Controller IRQ is cascaded to MPU_EXT_nIRQ througb the FPGA */
131 #define INT_ETHER INT_730_MPU_EXT_NIRQ
133 #define MAXIRQNUM IH_BOARD_BASE
134 #define MAXFIQNUM MAXIRQNUM
135 #define MAXSWINUM MAXIRQNUM
137 #define NR_IRQS (MAXIRQNUM + 1)
140 void fpga_write(unsigned char val, int reg);
141 unsigned char fpga_read(int reg);
144 /* PCC_UPLD control register: OMAP730 */
145 #define PCC_UPLD_CTRL_REG_BASE (0xfffe0900)
146 #define PCC_UPLD_CTRL_REG (volatile __u16 *)(PCC_UPLD_CTRL_REG_BASE + 0x00)
149 #error "Only OMAP730 Perseus2 supported!"