include/asm-arm/arch-omap/omap1610.h

   1 /* linux/include/asm-arm/arch-omap/omap1610.h
   2  *
   3  * Hardware definitions for TI OMAP1610 processor.
   4  *
   5  * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or (at your
  10  * option) any later version.
  11  *
  12  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  13  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  14  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  15  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  16  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  17  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  18  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  19  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  20  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  21  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  22  *
  23  * You should have received a copy of the  GNU General Public License along
  24  * with this program; if not, write  to the Free Software Foundation, Inc.,
  25  * 675 Mass Ave, Cambridge, MA 02139, USA.
  26  */
  27
  28 #ifndef __ASM_ARCH_OMAP1610_H
  29 #define __ASM_ARCH_OMAP1610_H
  30
  31 /*
  32  * ----------------------------------------------------------------------------
  33  * Base addresses
  34  * ----------------------------------------------------------------------------
  35  */
  36
  37 /* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
  38
  39 #define OMAP1610_SRAM_BASE      0xD0000000
  40 #define OMAP1610_SRAM_SIZE      (SZ_16K)
  41 #define OMAP1610_SRAM_START     0x20000000
  42
  43 #define OMAP1610_DSP_BASE       0xE0000000
  44 #define OMAP1610_DSP_SIZE       0x28000
  45 #define OMAP1610_DSP_START      0xE0000000
  46
  47 #define OMAP1610_DSPREG_BASE    0xE1000000
  48 #define OMAP1610_DSPREG_SIZE    SZ_128K
  49 #define OMAP1610_DSPREG_START   0xE1000000
  50
  51 /*
  52  * ---------------------------------------------------------------------------
  53  * Interrupts
  54  * ---------------------------------------------------------------------------
  55  */
  56 #define OMAP_IH2_0_BASE         (0xfffe0000)
  57 #define OMAP_IH2_1_BASE         (0xfffe0100)
  58 #define OMAP_IH2_2_BASE         (0xfffe0200)
  59 #define OMAP_IH2_3_BASE         (0xfffe0300)
  60
  61 #define OMAP_IH2_0_ITR          (OMAP_IH2_0_BASE + 0x00)
  62 #define OMAP_IH2_0_MIR          (OMAP_IH2_0_BASE + 0x04)
  63 #define OMAP_IH2_0_SIR_IRQ      (OMAP_IH2_0_BASE + 0x10)
  64 #define OMAP_IH2_0_SIR_FIQ      (OMAP_IH2_0_BASE + 0x14)
  65 #define OMAP_IH2_0_CONTROL      (OMAP_IH2_0_BASE + 0x18)
  66 #define OMAP_IH2_0_ILR0         (OMAP_IH2_0_BASE + 0x1c)
  67 #define OMAP_IH2_0_ISR          (OMAP_IH2_0_BASE + 0x9c)
  68
  69 #define OMAP_IH2_1_ITR          (OMAP_IH2_1_BASE + 0x00)
  70 #define OMAP_IH2_1_MIR          (OMAP_IH2_1_BASE + 0x04)
  71 #define OMAP_IH2_1_SIR_IRQ      (OMAP_IH2_1_BASE + 0x10)
  72 #define OMAP_IH2_1_SIR_FIQ      (OMAP_IH2_1_BASE + 0x14)
  73 #define OMAP_IH2_1_CONTROL      (OMAP_IH2_1_BASE + 0x18)
  74 #define OMAP_IH2_1_ILR1         (OMAP_IH2_1_BASE + 0x1c)
  75 #define OMAP_IH2_1_ISR          (OMAP_IH2_1_BASE + 0x9c)
  76
  77 #define OMAP_IH2_2_ITR          (OMAP_IH2_2_BASE + 0x00)
  78 #define OMAP_IH2_2_MIR          (OMAP_IH2_2_BASE + 0x04)
  79 #define OMAP_IH2_2_SIR_IRQ      (OMAP_IH2_2_BASE + 0x10)
  80 #define OMAP_IH2_2_SIR_FIQ      (OMAP_IH2_2_BASE + 0x14)
  81 #define OMAP_IH2_2_CONTROL      (OMAP_IH2_2_BASE + 0x18)
  82 #define OMAP_IH2_2_ILR2         (OMAP_IH2_2_BASE + 0x1c)
  83 #define OMAP_IH2_2_ISR          (OMAP_IH2_2_BASE + 0x9c)
  84
  85 #define OMAP_IH2_3_ITR          (OMAP_IH2_3_BASE + 0x00)
  86 #define OMAP_IH2_3_MIR          (OMAP_IH2_3_BASE + 0x04)
  87 #define OMAP_IH2_3_SIR_IRQ      (OMAP_IH2_3_BASE + 0x10)
  88 #define OMAP_IH2_3_SIR_FIQ      (OMAP_IH2_3_BASE + 0x14)
  89 #define OMAP_IH2_3_CONTROL      (OMAP_IH2_3_BASE + 0x18)
  90 #define OMAP_IH2_3_ILR3         (OMAP_IH2_3_BASE + 0x1c)
  91 #define OMAP_IH2_3_ISR          (OMAP_IH2_3_BASE + 0x9c)
  92
  93 /*
  94  * ----------------------------------------------------------------------------
  95  * Clocks
  96  * ----------------------------------------------------------------------------
  97  */
  98 #define OMAP1610_ARM_IDLECT3    (CLKGEN_REG_BASE + 0x24)
  99
 100 /*
 101  * ----------------------------------------------------------------------------
 102  * Pin configuration registers
 103  * ----------------------------------------------------------------------------
 104  */
 105 #define OMAP1610_CONF_VOLTAGE_VDDSHV6   (1 << 8)
 106 #define OMAP1610_CONF_VOLTAGE_VDDSHV7   (1 << 9)
 107 #define OMAP1610_CONF_VOLTAGE_VDDSHV8   (1 << 10)
 108 #define OMAP1610_CONF_VOLTAGE_VDDSHV9   (1 << 11)
 109 #define OMAP1610_SUBLVDS_CONF_VALID     (1 << 13)
 110
 111 /*
 112  * ---------------------------------------------------------------------------
 113  * TIPB bus interface
 114  * ---------------------------------------------------------------------------
 115  */
 116 #define TIPB_SWITCH_BASE                 (0xfffbc800)
 117 #define OMAP1610_MMCSD2_SSW_MPU_CONF    (TIPB_SWITCH_BASE + 0x160)
 118
 119 #endif /*  __ASM_ARCH_OMAP1610_H */
 120