1 /* linux/include/asm/arch-s3c2410/regs-clock.h
3 * Copyright (c) 2003,2004 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * S3C2410 clock register definitions
13 * 18-Aug-2004 Ben Dooks Added 2440 definitions
14 * 08-Aug-2004 Herbert Pƶtzl Added CLKCON definitions
15 * 19-06-2003 Ben Dooks Created file
16 * 12-03-2004 Ben Dooks Updated include protection
17 * 29-Sep-2004 Ben Dooks Fixed usage for assembly inclusion
18 * 10-Feb-2005 Ben Dooks Fixed CAMDIVN address (Guillaume Gourat)
21 #ifndef __ASM_ARM_REGS_CLOCK
22 #define __ASM_ARM_REGS_CLOCK "$Id: clock.h,v 1.4 2003/04/30 14:50:51 ben Exp $"
24 #define S3C2410_CLKREG(x) ((x) + S3C2410_VA_CLKPWR)
26 #define S3C2410_PLLVAL(_m,_p,_s) ((_m) << 12 | ((_p) << 4) | ((_s)))
28 #define S3C2410_LOCKTIME S3C2410_CLKREG(0x00)
29 #define S3C2410_MPLLCON S3C2410_CLKREG(0x04)
30 #define S3C2410_UPLLCON S3C2410_CLKREG(0x08)
31 #define S3C2410_CLKCON S3C2410_CLKREG(0x0C)
32 #define S3C2410_CLKSLOW S3C2410_CLKREG(0x10)
33 #define S3C2410_CLKDIVN S3C2410_CLKREG(0x14)
35 #define S3C2410_CLKCON_IDLE (1<<2)
36 #define S3C2410_CLKCON_POWER (1<<3)
37 #define S3C2410_CLKCON_NAND (1<<4)
38 #define S3C2410_CLKCON_LCDC (1<<5)
39 #define S3C2410_CLKCON_USBH (1<<6)
40 #define S3C2410_CLKCON_USBD (1<<7)
41 #define S3C2410_CLKCON_PWMT (1<<8)
42 #define S3C2410_CLKCON_SDI (1<<9)
43 #define S3C2410_CLKCON_UART0 (1<<10)
44 #define S3C2410_CLKCON_UART1 (1<<11)
45 #define S3C2410_CLKCON_UART2 (1<<12)
46 #define S3C2410_CLKCON_GPIO (1<<13)
47 #define S3C2410_CLKCON_RTC (1<<14)
48 #define S3C2410_CLKCON_ADC (1<<15)
49 #define S3C2410_CLKCON_IIC (1<<16)
50 #define S3C2410_CLKCON_IIS (1<<17)
51 #define S3C2410_CLKCON_SPI (1<<18)
53 #define S3C2410_PLLCON_MDIVSHIFT 12
54 #define S3C2410_PLLCON_PDIVSHIFT 4
55 #define S3C2410_PLLCON_SDIVSHIFT 0
56 #define S3C2410_PLLCON_MDIVMASK ((1<<(1+(19-12)))-1)
57 #define S3C2410_PLLCON_PDIVMASK ((1<<5)-1)
58 #define S3C2410_PLLCON_SDIVMASK 3
60 /* DCLKCON register addresses in gpio.h */
62 #define S3C2410_DCLKCON_DCLK0EN (1<<0)
63 #define S3C2410_DCLKCON_DCLK0_PCLK (0<<1)
64 #define S3C2410_DCLKCON_DCLK0_UCLK (1<<1)
65 #define S3C2410_DCLKCON_DCLK0_DIV(x) (((x) - 1 )<<4)
66 #define S3C2410_DCLKCON_DCLK0_CMP(x) (((x) - 1 )<<8)
68 #define S3C2410_DCLKCON_DCLK1EN (1<<16)
69 #define S3C2410_DCLKCON_DCLK1_PCLK (0<<17)
70 #define S3C2410_DCLKCON_DCLK1_UCLK (1<<17)
71 #define S3C2410_DCLKCON_DCLK1_DIV(x) (((x) - 1) <<20)
73 #define S3C2410_CLKDIVN_PDIVN (1<<0)
74 #define S3C2410_CLKDIVN_HDIVN (1<<1)
78 static inline unsigned int
79 s3c2410_get_pll(int pllval, int baseclk)
83 mdiv = pllval >> S3C2410_PLLCON_MDIVSHIFT;
84 pdiv = pllval >> S3C2410_PLLCON_PDIVSHIFT;
85 sdiv = pllval >> S3C2410_PLLCON_SDIVSHIFT;
87 mdiv &= S3C2410_PLLCON_MDIVMASK;
88 pdiv &= S3C2410_PLLCON_PDIVMASK;
89 sdiv &= S3C2410_PLLCON_SDIVMASK;
91 return (baseclk * (mdiv + 8)) / ((pdiv + 2) << sdiv);
94 #endif /* __ASSEMBLY__ */
96 #ifdef CONFIG_CPU_S3C2440
99 #define S3C2440_CAMDIVN S3C2410_CLKREG(0x18)
101 #define S3C2440_CLKCON_CAMERA (1<<19)
102 #define S3C2440_CLKCON_AC97 (1<<20)
104 #define S3C2440_CLKDIVN_PDIVN (1<<0)
105 #define S3C2440_CLKDIVN_HDIVN_MASK (3<<1)
106 #define S3C2440_CLKDIVN_HDIVN_1 (0<<1)
107 #define S3C2440_CLKDIVN_HDIVN_2 (1<<1)
108 #define S3C2440_CLKDIVN_HDIVN_4_8 (2<<1)
109 #define S3C2440_CLKDIVN_HDIVN_3_6 (3<<1)
110 #define S3C2440_CLKDIVN_UCLK (1<<3)
112 #define S3C2440_CAMDIVN_CAMCLK_MASK (0xf<<0)
113 #define S3C2440_CAMDIVN_CAMCLK_SEL (1<<4)
114 #define S3C2440_CAMDIVN_HCLK3_HALF (1<<8)
115 #define S3C2440_CAMDIVN_HCLK4_HALF (1<<9)
116 #define S3C2440_CAMDIVN_DVSEN (1<<12)
118 #endif /* CONFIG_CPU_S3C2440 */
121 #endif /* __ASM_ARM_REGS_CLOCK */