include/asm-arm/system.h

   1 #ifndef __ASM_ARM_SYSTEM_H
   2 #define __ASM_ARM_SYSTEM_H
   3
   4 #ifdef __KERNEL__
   5
   6 #include <linux/config.h>
   7
   8 #define CPU_ARCH_UNKNOWN        0
   9 #define CPU_ARCH_ARMv3          1
  10 #define CPU_ARCH_ARMv4          2
  11 #define CPU_ARCH_ARMv4T         3
  12 #define CPU_ARCH_ARMv5          4
  13 #define CPU_ARCH_ARMv5T         5
  14 #define CPU_ARCH_ARMv5TE        6
  15 #define CPU_ARCH_ARMv5TEJ       7
  16 #define CPU_ARCH_ARMv6          8
  17
  18 /*
  19  * CR1 bits (CP#15 CR1)
  20  */
  21 #define CR_M    (1 << 0)        /* MMU enable                           */
  22 #define CR_A    (1 << 1)        /* Alignment abort enable               */
  23 #define CR_C    (1 << 2)        /* Dcache enable                        */
  24 #define CR_W    (1 << 3)        /* Write buffer enable                  */
  25 #define CR_P    (1 << 4)        /* 32-bit exception handler             */
  26 #define CR_D    (1 << 5)        /* 32-bit data address range            */
  27 #define CR_L    (1 << 6)        /* Implementation defined               */
  28 #define CR_B    (1 << 7)        /* Big endian                           */
  29 #define CR_S    (1 << 8)        /* System MMU protection                */
  30 #define CR_R    (1 << 9)        /* ROM MMU protection                   */
  31 #define CR_F    (1 << 10)       /* Implementation defined               */
  32 #define CR_Z    (1 << 11)       /* Implementation defined               */
  33 #define CR_I    (1 << 12)       /* Icache enable                        */
  34 #define CR_V    (1 << 13)       /* Vectors relocated to 0xffff0000      */
  35 #define CR_RR   (1 << 14)       /* Round Robin cache replacement        */
  36 #define CR_L4   (1 << 15)       /* LDR pc can set T bit                 */
  37 #define CR_DT   (1 << 16)
  38 #define CR_IT   (1 << 18)
  39 #define CR_ST   (1 << 19)
  40 #define CR_FI   (1 << 21)       /* Fast interrupt (lower latency mode)  */
  41 #define CR_U    (1 << 22)       /* Unaligned access operation           */
  42 #define CR_XP   (1 << 23)       /* Extended page tables                 */
  43 #define CR_VE   (1 << 24)       /* Vectored interrupts                  */
  44
  45 #define CPUID_ID        0
  46 #define CPUID_CACHETYPE 1
  47 #define CPUID_TCM       2
  48 #define CPUID_TLBTYPE   3
  49
  50 #define read_cpuid(reg)                                                 \
  51         ({                                                              \
  52                 unsigned int __val;                                     \
  53                 asm("mrc%? p15, 0, %0, c0, c0, " __stringify(reg)       \
  54                     : "=r" (__val));                                    \
  55                 __val;                                                  \
  56         })
  57
  58 /*
  59  * This is used to ensure the compiler did actually allocate the register we
  60  * asked it for some inline assembly sequences.  Apparently we can't trust
  61  * the compiler from one version to another so a bit of paranoia won't hurt.
  62  * This string is meant to be concatenated with the inline asm string and
  63  * will cause compilation to stop on mismatch.
  64  */
  65 #define __asmeq(x, y)  ".ifnc " x "," y " ; .err ; .endif\n\t"
  66
  67 #ifndef __ASSEMBLY__
  68
  69 #include <linux/kernel.h>
  70
  71 struct thread_info;
  72
  73 /* information about the system we're running on */
  74 extern unsigned int system_rev;
  75 extern unsigned int system_serial_low;
  76 extern unsigned int system_serial_high;
  77 extern unsigned int mem_fclk_21285;
  78
  79 struct pt_regs;
  80
  81 void die(const char *msg, struct pt_regs *regs, int err)
  82                 __attribute__((noreturn));
  83
  84 void die_if_kernel(const char *str, struct pt_regs *regs, int err);
  85
  86 void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int,
  87                                        struct pt_regs *),
  88                      int sig, const char *name);
  89
  90 #include <asm/proc-fns.h>
  91
  92 #define xchg(ptr,x) \
  93         ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
  94
  95 #define tas(ptr) (xchg((ptr),1))
  96
  97 extern asmlinkage void __backtrace(void);
  98
  99 extern int cpu_architecture(void);
 100
 101 #define set_cr(x)                                       \
 102         __asm__ __volatile__(                           \
 103         "mcr    p15, 0, %0, c1, c0, 0   @ set CR"       \
 104         : : "r" (x) : "cc")
 105
 106 #define get_cr()                                        \
 107         ({                                              \
 108         unsigned int __val;                             \
 109         __asm__ __volatile__(                           \
 110         "mrc    p15, 0, %0, c1, c0, 0   @ get CR"       \
 111         : "=r" (__val) : : "cc");                       \
 112         __val;                                          \
 113         })
 114
 115 extern unsigned long cr_no_alignment;   /* defined in entry-armv.S */
 116 extern unsigned long cr_alignment;      /* defined in entry-armv.S */
 117
 118 #define UDBG_UNDEFINED  (1 << 0)
 119 #define UDBG_SYSCALL    (1 << 1)
 120 #define UDBG_BADABORT   (1 << 2)
 121 #define UDBG_SEGV       (1 << 3)
 122 #define UDBG_BUS        (1 << 4)
 123
 124 extern unsigned int user_debug;
 125
 126 #if __LINUX_ARM_ARCH__ >= 4
 127 #define vectors_base()  ((cr_alignment & CR_V) ? 0xffff0000 : 0)
 128 #else
 129 #define vectors_base()  (0)
 130 #endif
 131
 132 #define mb() __asm__ __volatile__ ("" : : : "memory")
 133 #define rmb() mb()
 134 #define wmb() mb()
 135 #define read_barrier_depends() do { } while(0)
 136 #define set_mb(var, value)  do { var = value; mb(); } while (0)
 137 #define set_wmb(var, value) do { var = value; wmb(); } while (0)
 138 #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
 139
 140 #define prepare_to_switch()    do { } while(0)
 141
 142 /*
 143  * switch_to(prev, next) should switch from task `prev' to `next'
 144  * `prev' will never be the same as `next'.
 145  * The `mb' is to tell GCC not to cache `current' across this call.
 146  */
 147 struct thread_info;
 148 struct task_struct;
 149 extern struct task_struct *__switch_to(struct task_struct *, struct thread_info *, struct thread_info *);
 150
 151 #define switch_to(prev,next,last)                                               \
 152         do {                                                                    \
 153                 last = __switch_to(prev,prev->thread_info,next->thread_info);   \
 154                 mb();                                                           \
 155         } while (0)
 156
 157 /*
 158  * CPU interrupt mask handling.
 159  */
 160 #if __LINUX_ARM_ARCH__ >= 6
 161
 162 #define local_irq_save(x)                                       \
 163         ({                                                      \
 164         __asm__ __volatile__(                                   \
 165         "mrs    %0, cpsr                @ local_irq_save\n"     \
 166         "cpsid  i"                                              \
 167         : "=r" (x) : : "memory", "cc");                         \
 168         })
 169
 170 #define local_irq_enable()  __asm__("cpsie i    @ __sti" : : : "memory", "cc")
 171 #define local_irq_disable() __asm__("cpsid i    @ __cli" : : : "memory", "cc")
 172 #define local_fiq_enable()  __asm__("cpsie f    @ __stf" : : : "memory", "cc")
 173 #define local_fiq_disable() __asm__("cpsid f    @ __clf" : : : "memory", "cc")
 174
 175 #else
 176
 177 /*
 178  * Save the current interrupt enable state & disable IRQs
 179  */
 180 #define local_irq_save(x)                                       \
 181         ({                                                      \
 182                 unsigned long temp;                             \
 183                 (void) (&temp == &x);                           \
 184         __asm__ __volatile__(                                   \
 185         "mrs    %0, cpsr                @ local_irq_save\n"     \
 186 "       orr     %1, %0, #128\n"                                 \
 187 "       msr     cpsr_c, %1"                                     \
 188         : "=r" (x), "=r" (temp)                                 \
 189         :                                                       \
 190         : "memory", "cc");                                      \
 191         })
 192
 193 /*
 194  * Enable IRQs
 195  */
 196 #define local_irq_enable()                                      \
 197         ({                                                      \
 198                 unsigned long temp;                             \
 199         __asm__ __volatile__(                                   \
 200         "mrs    %0, cpsr                @ local_irq_enable\n"   \
 201 "       bic     %0, %0, #128\n"                                 \
 202 "       msr     cpsr_c, %0"                                     \
 203         : "=r" (temp)                                           \
 204         :                                                       \
 205         : "memory", "cc");                                      \
 206         })
 207
 208 /*
 209  * Disable IRQs
 210  */
 211 #define local_irq_disable()                                     \
 212         ({                                                      \
 213                 unsigned long temp;                             \
 214         __asm__ __volatile__(                                   \
 215         "mrs    %0, cpsr                @ local_irq_disable\n"  \
 216 "       orr     %0, %0, #128\n"                                 \
 217 "       msr     cpsr_c, %0"                                     \
 218         : "=r" (temp)                                           \
 219         :                                                       \
 220         : "memory", "cc");                                      \
 221         })
 222
 223 /*
 224  * Enable FIQs
 225  */
 226 #define __stf()                                                 \
 227         ({                                                      \
 228                 unsigned long temp;                             \
 229         __asm__ __volatile__(                                   \
 230         "mrs    %0, cpsr                @ stf\n"                \
 231 "       bic     %0, %0, #64\n"                                  \
 232 "       msr     cpsr_c, %0"                                     \
 233         : "=r" (temp)                                           \
 234         :                                                       \
 235         : "memory", "cc");                                      \
 236         })
 237
 238 /*
 239  * Disable FIQs
 240  */
 241 #define __clf()                                                 \
 242         ({                                                      \
 243                 unsigned long temp;                             \
 244         __asm__ __volatile__(                                   \
 245         "mrs    %0, cpsr                @ clf\n"                \
 246 "       orr     %0, %0, #64\n"                                  \
 247 "       msr     cpsr_c, %0"                                     \
 248         : "=r" (temp)                                           \
 249         :                                                       \
 250         : "memory", "cc");                                      \
 251         })
 252
 253 #endif
 254
 255 /*
 256  * Save the current interrupt enable state.
 257  */
 258 #define local_save_flags(x)                                     \
 259         ({                                                      \
 260         __asm__ __volatile__(                                   \
 261         "mrs    %0, cpsr                @ local_save_flags"     \
 262         : "=r" (x) : : "memory", "cc");                         \
 263         })
 264
 265 /*
 266  * restore saved IRQ & FIQ state
 267  */
 268 #define local_irq_restore(x)                                    \
 269         __asm__ __volatile__(                                   \
 270         "msr    cpsr_c, %0              @ local_irq_restore\n"  \
 271         :                                                       \
 272         : "r" (x)                                               \
 273         : "memory", "cc")
 274
 275 #ifdef CONFIG_SMP
 276 #error SMP not supported
 277
 278 #define smp_mb()                mb()
 279 #define smp_rmb()               rmb()
 280 #define smp_wmb()               wmb()
 281 #define smp_read_barrier_depends()              read_barrier_depends()
 282
 283 #else
 284
 285 #define smp_mb()                barrier()
 286 #define smp_rmb()               barrier()
 287 #define smp_wmb()               barrier()
 288 #define smp_read_barrier_depends()              do { } while(0)
 289
 290 #define clf()                   __clf()
 291 #define stf()                   __stf()
 292
 293 #define irqs_disabled()                 \
 294 ({                                      \
 295         unsigned long flags;            \
 296         local_save_flags(flags);        \
 297         flags & PSR_I_BIT;              \
 298 })
 299
 300 #if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110)
 301 /*
 302  * On the StrongARM, "swp" is terminally broken since it bypasses the
 303  * cache totally.  This means that the cache becomes inconsistent, and,
 304  * since we use normal loads/stores as well, this is really bad.
 305  * Typically, this causes oopsen in filp_close, but could have other,
 306  * more disasterous effects.  There are two work-arounds:
 307  *  1. Disable interrupts and emulate the atomic swap
 308  *  2. Clean the cache, perform atomic swap, flush the cache
 309  *
 310  * We choose (1) since its the "easiest" to achieve here and is not
 311  * dependent on the processor type.
 312  */
 313 #define swp_is_buggy
 314 #endif
 315
 316 static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
 317 {
 318         extern void __bad_xchg(volatile void *, int);
 319         unsigned long ret;
 320 #ifdef swp_is_buggy
 321         unsigned long flags;
 322 #endif
 323
 324         switch (size) {
 325 #ifdef swp_is_buggy
 326                 case 1:
 327                         local_irq_save(flags);
 328                         ret = *(volatile unsigned char *)ptr;
 329                         *(volatile unsigned char *)ptr = x;
 330                         local_irq_restore(flags);
 331                         break;
 332
 333                 case 4:
 334                         local_irq_save(flags);
 335                         ret = *(volatile unsigned long *)ptr;
 336                         *(volatile unsigned long *)ptr = x;
 337                         local_irq_restore(flags);
 338                         break;
 339 #else
 340                 case 1: __asm__ __volatile__ ("swpb %0, %1, [%2]"
 341                                         : "=&r" (ret)
 342                                         : "r" (x), "r" (ptr)
 343                                         : "memory", "cc");
 344                         break;
 345                 case 4: __asm__ __volatile__ ("swp %0, %1, [%2]"
 346                                         : "=&r" (ret)
 347                                         : "r" (x), "r" (ptr)
 348                                         : "memory", "cc");
 349                         break;
 350 #endif
 351                 default: __bad_xchg(ptr, size), ret = 0;
 352         }
 353
 354         return ret;
 355 }
 356
 357 #endif /* CONFIG_SMP */
 358
 359 #endif /* __ASSEMBLY__ */
 360
 361 #endif /* __KERNEL__ */
 362
 363 #endif